Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /* Auto-generated config file hpl_dmac_config.h */ |
| 2 | #ifndef HPL_DMAC_CONFIG_H |
| 3 | #define HPL_DMAC_CONFIG_H |
| 4 | |
| 5 | // <<< Use Configuration Wizard in Context Menu >>> |
| 6 | |
| 7 | // <e> DMAC enable |
| 8 | // <i> Indicates whether dmac is enabled or not |
| 9 | // <id> dmac_enable |
| 10 | #ifndef CONF_DMAC_ENABLE |
| 11 | #define CONF_DMAC_ENABLE 0 |
| 12 | #endif |
| 13 | |
| 14 | // <q> Priority Level 0 |
| 15 | // <i> Indicates whether Priority Level 0 is enabled or not |
| 16 | // <id> dmac_lvlen0 |
| 17 | #ifndef CONF_DMAC_LVLEN0 |
| 18 | #define CONF_DMAC_LVLEN0 1 |
| 19 | #endif |
| 20 | |
| 21 | // <o> Level 0 Round-Robin Arbitration |
| 22 | // <0=> Static arbitration scheme for channel with priority 0 |
| 23 | // <1=> Round-robin arbitration scheme for channel with priority 0 |
| 24 | // <i> Defines Level 0 Arbitration for DMA channels |
| 25 | // <id> dmac_rrlvlen0 |
| 26 | #ifndef CONF_DMAC_RRLVLEN0 |
| 27 | #define CONF_DMAC_RRLVLEN0 0 |
| 28 | #endif |
| 29 | |
| 30 | // <o> Level 0 Channel Priority Number <0x00-0xFF> |
| 31 | // <id> dmac_lvlpri0 |
| 32 | #ifndef CONF_DMAC_LVLPRI0 |
| 33 | #define CONF_DMAC_LVLPRI0 0 |
| 34 | #endif |
| 35 | // <q> Priority Level 1 |
| 36 | // <i> Indicates whether Priority Level 1 is enabled or not |
| 37 | // <id> dmac_lvlen1 |
| 38 | #ifndef CONF_DMAC_LVLEN1 |
| 39 | #define CONF_DMAC_LVLEN1 1 |
| 40 | #endif |
| 41 | |
| 42 | // <o> Level 1 Round-Robin Arbitration |
| 43 | // <0=> Static arbitration scheme for channel with priority 1 |
| 44 | // <1=> Round-robin arbitration scheme for channel with priority 1 |
| 45 | // <i> Defines Level 1 Arbitration for DMA channels |
| 46 | // <id> dmac_rrlvlen1 |
| 47 | #ifndef CONF_DMAC_RRLVLEN1 |
| 48 | #define CONF_DMAC_RRLVLEN1 0 |
| 49 | #endif |
| 50 | |
| 51 | // <o> Level 1 Channel Priority Number <0x00-0xFF> |
| 52 | // <id> dmac_lvlpri1 |
| 53 | #ifndef CONF_DMAC_LVLPRI1 |
| 54 | #define CONF_DMAC_LVLPRI1 0 |
| 55 | #endif |
| 56 | // <q> Priority Level 2 |
| 57 | // <i> Indicates whether Priority Level 2 is enabled or not |
| 58 | // <id> dmac_lvlen2 |
| 59 | #ifndef CONF_DMAC_LVLEN2 |
| 60 | #define CONF_DMAC_LVLEN2 1 |
| 61 | #endif |
| 62 | |
| 63 | // <o> Level 2 Round-Robin Arbitration |
| 64 | // <0=> Static arbitration scheme for channel with priority 2 |
| 65 | // <1=> Round-robin arbitration scheme for channel with priority 2 |
| 66 | // <i> Defines Level 2 Arbitration for DMA channels |
| 67 | // <id> dmac_rrlvlen2 |
| 68 | #ifndef CONF_DMAC_RRLVLEN2 |
| 69 | #define CONF_DMAC_RRLVLEN2 0 |
| 70 | #endif |
| 71 | |
| 72 | // <o> Level 2 Channel Priority Number <0x00-0xFF> |
| 73 | // <id> dmac_lvlpri2 |
| 74 | #ifndef CONF_DMAC_LVLPRI2 |
| 75 | #define CONF_DMAC_LVLPRI2 0 |
| 76 | #endif |
| 77 | // <q> Priority Level 3 |
| 78 | // <i> Indicates whether Priority Level 3 is enabled or not |
| 79 | // <id> dmac_lvlen3 |
| 80 | #ifndef CONF_DMAC_LVLEN3 |
| 81 | #define CONF_DMAC_LVLEN3 1 |
| 82 | #endif |
| 83 | |
| 84 | // <o> Level 3 Round-Robin Arbitration |
| 85 | // <0=> Static arbitration scheme for channel with priority 3 |
| 86 | // <1=> Round-robin arbitration scheme for channel with priority 3 |
| 87 | // <i> Defines Level 3 Arbitration for DMA channels |
| 88 | // <id> dmac_rrlvlen3 |
| 89 | #ifndef CONF_DMAC_RRLVLEN3 |
| 90 | #define CONF_DMAC_RRLVLEN3 0 |
| 91 | #endif |
| 92 | |
| 93 | // <o> Level 3 Channel Priority Number <0x00-0xFF> |
| 94 | // <id> dmac_lvlpri3 |
| 95 | #ifndef CONF_DMAC_LVLPRI3 |
| 96 | #define CONF_DMAC_LVLPRI3 0 |
| 97 | #endif |
| 98 | // <q> Debug Run |
| 99 | // <i> Indicates whether Debug Run is enabled or not |
| 100 | // <id> dmac_dbgrun |
| 101 | #ifndef CONF_DMAC_DBGRUN |
| 102 | #define CONF_DMAC_DBGRUN 0 |
| 103 | #endif |
| 104 | |
| 105 | // <e> Channel 0 settings |
| 106 | // <id> dmac_channel_0_settings |
| 107 | #ifndef CONF_DMAC_CHANNEL_0_SETTINGS |
| 108 | #define CONF_DMAC_CHANNEL_0_SETTINGS 0 |
| 109 | #endif |
| 110 | |
| 111 | // <q> Channel Run in Standby |
| 112 | // <i> Indicates whether channel 0 is running in standby mode or not |
| 113 | // <id> dmac_runstdby_0 |
| 114 | #ifndef CONF_DMAC_RUNSTDBY_0 |
| 115 | #define CONF_DMAC_RUNSTDBY_0 0 |
| 116 | #endif |
| 117 | |
| 118 | // <o> Trigger action |
| 119 | // <0=> One trigger required for each block transfer |
| 120 | // <2=> One trigger required for each beat transfer |
| 121 | // <3=> One trigger required for each transaction |
| 122 | // <i> Defines the trigger action used for a transfer |
| 123 | // <id> dmac_trigact_0 |
| 124 | #ifndef CONF_DMAC_TRIGACT_0 |
| 125 | #define CONF_DMAC_TRIGACT_0 0 |
| 126 | #endif |
| 127 | |
| 128 | // <o> Trigger source |
| 129 | // <0x00=> Only software/event triggers |
| 130 | // <0x01=> RTC Time Stamp Trigger |
| 131 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 132 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 133 | // <0x04=> SERCOM0 RX Trigger |
| 134 | // <0x05=> SERCOM0 TX Trigger |
| 135 | // <0x06=> SERCOM1 RX Trigger |
| 136 | // <0x07=> SERCOM1 TX Trigger |
| 137 | // <0x08=> SERCOM2 RX Trigger |
| 138 | // <0x09=> SERCOM2 TX Trigger |
| 139 | // <0x0A=> SERCOM3 RX Trigger |
| 140 | // <0x0B=> SERCOM3 TX Trigger |
| 141 | // <0x0C=> SERCOM4 RX Trigger |
| 142 | // <0x0D=> SERCOM4 TX Trigger |
| 143 | // <0x0E=> SERCOM5 RX Trigger |
| 144 | // <0x0F=> SERCOM5 TX Trigger |
| 145 | // <0x10=> SERCOM6 RX Trigger |
| 146 | // <0x11=> SERCOM6 TX Trigger |
| 147 | // <0x12=> SERCOM7 RX Trigger |
| 148 | // <0x13=> SERCOM7 TX Trigger |
| 149 | // <0x14=> CAN0 DEBUG Trigger |
| 150 | // <0x15=> CAN1 DEBUG Trigger |
| 151 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 152 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 153 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 154 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 155 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 156 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 157 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 158 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 159 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 160 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 161 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 162 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 163 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 164 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 165 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 166 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 167 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 168 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 169 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 170 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 171 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 172 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 173 | // <0x2C=> TC0 Overflow Trigger |
| 174 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 175 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 176 | // <0x2F=> TC1 Overflow Trigger |
| 177 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 178 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 179 | // <0x32=> TC2 Overflow Trigger |
| 180 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 181 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 182 | // <0x35=> TC3 Overflow Trigger |
| 183 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 184 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 185 | // <0x38=> TC4 Overflow Trigger |
| 186 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 187 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 188 | // <0x3B=> TC5 Overflow Trigger |
| 189 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 190 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 191 | // <0x3E=> TC6 Overflow Trigger |
| 192 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 193 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 194 | // <0x41=> TC7 Overflow Trigger |
| 195 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 196 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 197 | // <0x44=> ADC0 Result Ready Trigger |
| 198 | // <0x45=> ADC0 Sequencing Trigger |
| 199 | // <0x46=> ADC1 Result Ready Trigger |
| 200 | // <0x47=> ADC1 Sequencing Trigger |
| 201 | // <0x48=> DAC Empty 0 Trigger |
| 202 | // <0x49=> DAC Empty 1 Trigger |
| 203 | // <0x4A=> DAC Result Ready 0 Trigger |
| 204 | // <0x4B=> DAC Result Ready 1 Trigger |
| 205 | // <0x4C=> I2S Rx 0 Trigger |
| 206 | // <0x4D=> I2S Rx 1 Trigger |
| 207 | // <0x4E=> I2S Tx 0 Trigger |
| 208 | // <0x4F=> I2S Tx 1 Trigger |
| 209 | // <0x50=> PCC RX Trigger |
| 210 | // <0x51=> AES Write Trigger |
| 211 | // <0x52=> AES Read Trigger |
| 212 | // <0x53=> QSPI Rx Trigger |
| 213 | // <0x54=> QSPI Tx Trigger |
| 214 | // <i> Defines the peripheral trigger which is source of the transfer |
| 215 | // <id> dmac_trifsrc_0 |
| 216 | #ifndef CONF_DMAC_TRIGSRC_0 |
| 217 | #define CONF_DMAC_TRIGSRC_0 0 |
| 218 | #endif |
| 219 | |
| 220 | // <o> Channel Arbitration Level |
| 221 | // <0=> Channel priority 0 |
| 222 | // <1=> Channel priority 1 |
| 223 | // <2=> Channel priority 2 |
| 224 | // <3=> Channel priority 3 |
| 225 | // <i> Defines the arbitration level for this channel |
| 226 | // <id> dmac_lvl_0 |
| 227 | #ifndef CONF_DMAC_LVL_0 |
| 228 | #define CONF_DMAC_LVL_0 0 |
| 229 | #endif |
| 230 | |
| 231 | // <q> Channel Event Output |
| 232 | // <i> Indicates whether channel event generation is enabled or not |
| 233 | // <id> dmac_evoe_0 |
| 234 | #ifndef CONF_DMAC_EVOE_0 |
| 235 | #define CONF_DMAC_EVOE_0 0 |
| 236 | #endif |
| 237 | |
| 238 | // <q> Channel Event Input |
| 239 | // <i> Indicates whether channel event reception is enabled or not |
| 240 | // <id> dmac_evie_0 |
| 241 | #ifndef CONF_DMAC_EVIE_0 |
| 242 | #define CONF_DMAC_EVIE_0 0 |
| 243 | #endif |
| 244 | |
| 245 | // <o> Event Input Action |
| 246 | // <0=> No action |
| 247 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 248 | // <2=> Conditional transfer trigger |
| 249 | // <3=> Conditional block transfer |
| 250 | // <4=> Channel suspend operation |
| 251 | // <5=> Channel resume operation |
| 252 | // <6=> Skip next block suspend action |
| 253 | // <i> Defines the event input action |
| 254 | // <id> dmac_evact_0 |
| 255 | #ifndef CONF_DMAC_EVACT_0 |
| 256 | #define CONF_DMAC_EVACT_0 0 |
| 257 | #endif |
| 258 | |
| 259 | // <o> Address Increment Step Size |
| 260 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 261 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 262 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 263 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 264 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 265 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 266 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 267 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 268 | // <i> Defines the address increment step size, applies to source or destination address |
| 269 | // <id> dmac_stepsize_0 |
| 270 | #ifndef CONF_DMAC_STEPSIZE_0 |
| 271 | #define CONF_DMAC_STEPSIZE_0 0 |
| 272 | #endif |
| 273 | |
| 274 | // <o> Step Selection |
| 275 | // <0=> Step size settings apply to the destination address |
| 276 | // <1=> Step size settings apply to the source address |
| 277 | // <i> Defines whether source or destination addresses are using the step size settings |
| 278 | // <id> dmac_stepsel_0 |
| 279 | #ifndef CONF_DMAC_STEPSEL_0 |
| 280 | #define CONF_DMAC_STEPSEL_0 0 |
| 281 | #endif |
| 282 | |
| 283 | // <q> Source Address Increment |
| 284 | // <i> Indicates whether the source address incrementation is enabled or not |
| 285 | // <id> dmac_srcinc_0 |
| 286 | #ifndef CONF_DMAC_SRCINC_0 |
| 287 | #define CONF_DMAC_SRCINC_0 0 |
| 288 | #endif |
| 289 | |
| 290 | // <q> Destination Address Increment |
| 291 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 292 | // <id> dmac_dstinc_0 |
| 293 | #ifndef CONF_DMAC_DSTINC_0 |
| 294 | #define CONF_DMAC_DSTINC_0 0 |
| 295 | #endif |
| 296 | |
| 297 | // <o> Beat Size |
| 298 | // <0=> 8-bit bus transfer |
| 299 | // <1=> 16-bit bus transfer |
| 300 | // <2=> 32-bit bus transfer |
| 301 | // <i> Defines the size of one beat |
| 302 | // <id> dmac_beatsize_0 |
| 303 | #ifndef CONF_DMAC_BEATSIZE_0 |
| 304 | #define CONF_DMAC_BEATSIZE_0 0 |
| 305 | #endif |
| 306 | |
| 307 | // <o> Block Action |
| 308 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 309 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 310 | // <2=> Channel suspend operation is complete |
| 311 | // <3=> Both channel suspend operation and block interrupt |
| 312 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 313 | // <id> dmac_blockact_0 |
| 314 | #ifndef CONF_DMAC_BLOCKACT_0 |
| 315 | #define CONF_DMAC_BLOCKACT_0 0 |
| 316 | #endif |
| 317 | |
| 318 | // <o> Event Output Selection |
| 319 | // <0=> Event generation disabled |
| 320 | // <1=> Event strobe when block transfer complete |
| 321 | // <3=> Event strobe when beat transfer complete |
| 322 | // <i> Defines the event output selection |
| 323 | // <id> dmac_evosel_0 |
| 324 | #ifndef CONF_DMAC_EVOSEL_0 |
| 325 | #define CONF_DMAC_EVOSEL_0 0 |
| 326 | #endif |
| 327 | // </e> |
| 328 | |
| 329 | // <e> Channel 1 settings |
| 330 | // <id> dmac_channel_1_settings |
| 331 | #ifndef CONF_DMAC_CHANNEL_1_SETTINGS |
| 332 | #define CONF_DMAC_CHANNEL_1_SETTINGS 0 |
| 333 | #endif |
| 334 | |
| 335 | // <q> Channel Run in Standby |
| 336 | // <i> Indicates whether channel 1 is running in standby mode or not |
| 337 | // <id> dmac_runstdby_1 |
| 338 | #ifndef CONF_DMAC_RUNSTDBY_1 |
| 339 | #define CONF_DMAC_RUNSTDBY_1 0 |
| 340 | #endif |
| 341 | |
| 342 | // <o> Trigger action |
| 343 | // <0=> One trigger required for each block transfer |
| 344 | // <2=> One trigger required for each beat transfer |
| 345 | // <3=> One trigger required for each transaction |
| 346 | // <i> Defines the trigger action used for a transfer |
| 347 | // <id> dmac_trigact_1 |
| 348 | #ifndef CONF_DMAC_TRIGACT_1 |
| 349 | #define CONF_DMAC_TRIGACT_1 0 |
| 350 | #endif |
| 351 | |
| 352 | // <o> Trigger source |
| 353 | // <0x00=> Only software/event triggers |
| 354 | // <0x01=> RTC Time Stamp Trigger |
| 355 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 356 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 357 | // <0x04=> SERCOM0 RX Trigger |
| 358 | // <0x05=> SERCOM0 TX Trigger |
| 359 | // <0x06=> SERCOM1 RX Trigger |
| 360 | // <0x07=> SERCOM1 TX Trigger |
| 361 | // <0x08=> SERCOM2 RX Trigger |
| 362 | // <0x09=> SERCOM2 TX Trigger |
| 363 | // <0x0A=> SERCOM3 RX Trigger |
| 364 | // <0x0B=> SERCOM3 TX Trigger |
| 365 | // <0x0C=> SERCOM4 RX Trigger |
| 366 | // <0x0D=> SERCOM4 TX Trigger |
| 367 | // <0x0E=> SERCOM5 RX Trigger |
| 368 | // <0x0F=> SERCOM5 TX Trigger |
| 369 | // <0x10=> SERCOM6 RX Trigger |
| 370 | // <0x11=> SERCOM6 TX Trigger |
| 371 | // <0x12=> SERCOM7 RX Trigger |
| 372 | // <0x13=> SERCOM7 TX Trigger |
| 373 | // <0x14=> CAN0 DEBUG Trigger |
| 374 | // <0x15=> CAN1 DEBUG Trigger |
| 375 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 376 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 377 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 378 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 379 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 380 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 381 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 382 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 383 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 384 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 385 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 386 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 387 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 388 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 389 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 390 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 391 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 392 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 393 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 394 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 395 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 396 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 397 | // <0x2C=> TC0 Overflow Trigger |
| 398 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 399 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 400 | // <0x2F=> TC1 Overflow Trigger |
| 401 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 402 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 403 | // <0x32=> TC2 Overflow Trigger |
| 404 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 405 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 406 | // <0x35=> TC3 Overflow Trigger |
| 407 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 408 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 409 | // <0x38=> TC4 Overflow Trigger |
| 410 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 411 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 412 | // <0x3B=> TC5 Overflow Trigger |
| 413 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 414 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 415 | // <0x3E=> TC6 Overflow Trigger |
| 416 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 417 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 418 | // <0x41=> TC7 Overflow Trigger |
| 419 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 420 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 421 | // <0x44=> ADC0 Result Ready Trigger |
| 422 | // <0x45=> ADC0 Sequencing Trigger |
| 423 | // <0x46=> ADC1 Result Ready Trigger |
| 424 | // <0x47=> ADC1 Sequencing Trigger |
| 425 | // <0x48=> DAC Empty 0 Trigger |
| 426 | // <0x49=> DAC Empty 1 Trigger |
| 427 | // <0x4A=> DAC Result Ready 0 Trigger |
| 428 | // <0x4B=> DAC Result Ready 1 Trigger |
| 429 | // <0x4C=> I2S Rx 0 Trigger |
| 430 | // <0x4D=> I2S Rx 1 Trigger |
| 431 | // <0x4E=> I2S Tx 0 Trigger |
| 432 | // <0x4F=> I2S Tx 1 Trigger |
| 433 | // <0x50=> PCC RX Trigger |
| 434 | // <0x51=> AES Write Trigger |
| 435 | // <0x52=> AES Read Trigger |
| 436 | // <0x53=> QSPI Rx Trigger |
| 437 | // <0x54=> QSPI Tx Trigger |
| 438 | // <i> Defines the peripheral trigger which is source of the transfer |
| 439 | // <id> dmac_trifsrc_1 |
| 440 | #ifndef CONF_DMAC_TRIGSRC_1 |
| 441 | #define CONF_DMAC_TRIGSRC_1 0 |
| 442 | #endif |
| 443 | |
| 444 | // <o> Channel Arbitration Level |
| 445 | // <0=> Channel priority 0 |
| 446 | // <1=> Channel priority 1 |
| 447 | // <2=> Channel priority 2 |
| 448 | // <3=> Channel priority 3 |
| 449 | // <i> Defines the arbitration level for this channel |
| 450 | // <id> dmac_lvl_1 |
| 451 | #ifndef CONF_DMAC_LVL_1 |
| 452 | #define CONF_DMAC_LVL_1 0 |
| 453 | #endif |
| 454 | |
| 455 | // <q> Channel Event Output |
| 456 | // <i> Indicates whether channel event generation is enabled or not |
| 457 | // <id> dmac_evoe_1 |
| 458 | #ifndef CONF_DMAC_EVOE_1 |
| 459 | #define CONF_DMAC_EVOE_1 0 |
| 460 | #endif |
| 461 | |
| 462 | // <q> Channel Event Input |
| 463 | // <i> Indicates whether channel event reception is enabled or not |
| 464 | // <id> dmac_evie_1 |
| 465 | #ifndef CONF_DMAC_EVIE_1 |
| 466 | #define CONF_DMAC_EVIE_1 0 |
| 467 | #endif |
| 468 | |
| 469 | // <o> Event Input Action |
| 470 | // <0=> No action |
| 471 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 472 | // <2=> Conditional transfer trigger |
| 473 | // <3=> Conditional block transfer |
| 474 | // <4=> Channel suspend operation |
| 475 | // <5=> Channel resume operation |
| 476 | // <6=> Skip next block suspend action |
| 477 | // <i> Defines the event input action |
| 478 | // <id> dmac_evact_1 |
| 479 | #ifndef CONF_DMAC_EVACT_1 |
| 480 | #define CONF_DMAC_EVACT_1 0 |
| 481 | #endif |
| 482 | |
| 483 | // <o> Address Increment Step Size |
| 484 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 485 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 486 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 487 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 488 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 489 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 490 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 491 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 492 | // <i> Defines the address increment step size, applies to source or destination address |
| 493 | // <id> dmac_stepsize_1 |
| 494 | #ifndef CONF_DMAC_STEPSIZE_1 |
| 495 | #define CONF_DMAC_STEPSIZE_1 0 |
| 496 | #endif |
| 497 | |
| 498 | // <o> Step Selection |
| 499 | // <0=> Step size settings apply to the destination address |
| 500 | // <1=> Step size settings apply to the source address |
| 501 | // <i> Defines whether source or destination addresses are using the step size settings |
| 502 | // <id> dmac_stepsel_1 |
| 503 | #ifndef CONF_DMAC_STEPSEL_1 |
| 504 | #define CONF_DMAC_STEPSEL_1 0 |
| 505 | #endif |
| 506 | |
| 507 | // <q> Source Address Increment |
| 508 | // <i> Indicates whether the source address incrementation is enabled or not |
| 509 | // <id> dmac_srcinc_1 |
| 510 | #ifndef CONF_DMAC_SRCINC_1 |
| 511 | #define CONF_DMAC_SRCINC_1 0 |
| 512 | #endif |
| 513 | |
| 514 | // <q> Destination Address Increment |
| 515 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 516 | // <id> dmac_dstinc_1 |
| 517 | #ifndef CONF_DMAC_DSTINC_1 |
| 518 | #define CONF_DMAC_DSTINC_1 0 |
| 519 | #endif |
| 520 | |
| 521 | // <o> Beat Size |
| 522 | // <0=> 8-bit bus transfer |
| 523 | // <1=> 16-bit bus transfer |
| 524 | // <2=> 32-bit bus transfer |
| 525 | // <i> Defines the size of one beat |
| 526 | // <id> dmac_beatsize_1 |
| 527 | #ifndef CONF_DMAC_BEATSIZE_1 |
| 528 | #define CONF_DMAC_BEATSIZE_1 0 |
| 529 | #endif |
| 530 | |
| 531 | // <o> Block Action |
| 532 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 533 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 534 | // <2=> Channel suspend operation is complete |
| 535 | // <3=> Both channel suspend operation and block interrupt |
| 536 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 537 | // <id> dmac_blockact_1 |
| 538 | #ifndef CONF_DMAC_BLOCKACT_1 |
| 539 | #define CONF_DMAC_BLOCKACT_1 0 |
| 540 | #endif |
| 541 | |
| 542 | // <o> Event Output Selection |
| 543 | // <0=> Event generation disabled |
| 544 | // <1=> Event strobe when block transfer complete |
| 545 | // <3=> Event strobe when beat transfer complete |
| 546 | // <i> Defines the event output selection |
| 547 | // <id> dmac_evosel_1 |
| 548 | #ifndef CONF_DMAC_EVOSEL_1 |
| 549 | #define CONF_DMAC_EVOSEL_1 0 |
| 550 | #endif |
| 551 | // </e> |
| 552 | |
| 553 | // <e> Channel 2 settings |
| 554 | // <id> dmac_channel_2_settings |
| 555 | #ifndef CONF_DMAC_CHANNEL_2_SETTINGS |
| 556 | #define CONF_DMAC_CHANNEL_2_SETTINGS 0 |
| 557 | #endif |
| 558 | |
| 559 | // <q> Channel Run in Standby |
| 560 | // <i> Indicates whether channel 2 is running in standby mode or not |
| 561 | // <id> dmac_runstdby_2 |
| 562 | #ifndef CONF_DMAC_RUNSTDBY_2 |
| 563 | #define CONF_DMAC_RUNSTDBY_2 0 |
| 564 | #endif |
| 565 | |
| 566 | // <o> Trigger action |
| 567 | // <0=> One trigger required for each block transfer |
| 568 | // <2=> One trigger required for each beat transfer |
| 569 | // <3=> One trigger required for each transaction |
| 570 | // <i> Defines the trigger action used for a transfer |
| 571 | // <id> dmac_trigact_2 |
| 572 | #ifndef CONF_DMAC_TRIGACT_2 |
| 573 | #define CONF_DMAC_TRIGACT_2 0 |
| 574 | #endif |
| 575 | |
| 576 | // <o> Trigger source |
| 577 | // <0x00=> Only software/event triggers |
| 578 | // <0x01=> RTC Time Stamp Trigger |
| 579 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 580 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 581 | // <0x04=> SERCOM0 RX Trigger |
| 582 | // <0x05=> SERCOM0 TX Trigger |
| 583 | // <0x06=> SERCOM1 RX Trigger |
| 584 | // <0x07=> SERCOM1 TX Trigger |
| 585 | // <0x08=> SERCOM2 RX Trigger |
| 586 | // <0x09=> SERCOM2 TX Trigger |
| 587 | // <0x0A=> SERCOM3 RX Trigger |
| 588 | // <0x0B=> SERCOM3 TX Trigger |
| 589 | // <0x0C=> SERCOM4 RX Trigger |
| 590 | // <0x0D=> SERCOM4 TX Trigger |
| 591 | // <0x0E=> SERCOM5 RX Trigger |
| 592 | // <0x0F=> SERCOM5 TX Trigger |
| 593 | // <0x10=> SERCOM6 RX Trigger |
| 594 | // <0x11=> SERCOM6 TX Trigger |
| 595 | // <0x12=> SERCOM7 RX Trigger |
| 596 | // <0x13=> SERCOM7 TX Trigger |
| 597 | // <0x14=> CAN0 DEBUG Trigger |
| 598 | // <0x15=> CAN1 DEBUG Trigger |
| 599 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 600 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 601 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 602 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 603 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 604 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 605 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 606 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 607 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 608 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 609 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 610 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 611 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 612 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 613 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 614 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 615 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 616 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 617 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 618 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 619 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 620 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 621 | // <0x2C=> TC0 Overflow Trigger |
| 622 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 623 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 624 | // <0x2F=> TC1 Overflow Trigger |
| 625 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 626 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 627 | // <0x32=> TC2 Overflow Trigger |
| 628 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 629 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 630 | // <0x35=> TC3 Overflow Trigger |
| 631 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 632 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 633 | // <0x38=> TC4 Overflow Trigger |
| 634 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 635 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 636 | // <0x3B=> TC5 Overflow Trigger |
| 637 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 638 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 639 | // <0x3E=> TC6 Overflow Trigger |
| 640 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 641 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 642 | // <0x41=> TC7 Overflow Trigger |
| 643 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 644 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 645 | // <0x44=> ADC0 Result Ready Trigger |
| 646 | // <0x45=> ADC0 Sequencing Trigger |
| 647 | // <0x46=> ADC1 Result Ready Trigger |
| 648 | // <0x47=> ADC1 Sequencing Trigger |
| 649 | // <0x48=> DAC Empty 0 Trigger |
| 650 | // <0x49=> DAC Empty 1 Trigger |
| 651 | // <0x4A=> DAC Result Ready 0 Trigger |
| 652 | // <0x4B=> DAC Result Ready 1 Trigger |
| 653 | // <0x4C=> I2S Rx 0 Trigger |
| 654 | // <0x4D=> I2S Rx 1 Trigger |
| 655 | // <0x4E=> I2S Tx 0 Trigger |
| 656 | // <0x4F=> I2S Tx 1 Trigger |
| 657 | // <0x50=> PCC RX Trigger |
| 658 | // <0x51=> AES Write Trigger |
| 659 | // <0x52=> AES Read Trigger |
| 660 | // <0x53=> QSPI Rx Trigger |
| 661 | // <0x54=> QSPI Tx Trigger |
| 662 | // <i> Defines the peripheral trigger which is source of the transfer |
| 663 | // <id> dmac_trifsrc_2 |
| 664 | #ifndef CONF_DMAC_TRIGSRC_2 |
| 665 | #define CONF_DMAC_TRIGSRC_2 0 |
| 666 | #endif |
| 667 | |
| 668 | // <o> Channel Arbitration Level |
| 669 | // <0=> Channel priority 0 |
| 670 | // <1=> Channel priority 1 |
| 671 | // <2=> Channel priority 2 |
| 672 | // <3=> Channel priority 3 |
| 673 | // <i> Defines the arbitration level for this channel |
| 674 | // <id> dmac_lvl_2 |
| 675 | #ifndef CONF_DMAC_LVL_2 |
| 676 | #define CONF_DMAC_LVL_2 0 |
| 677 | #endif |
| 678 | |
| 679 | // <q> Channel Event Output |
| 680 | // <i> Indicates whether channel event generation is enabled or not |
| 681 | // <id> dmac_evoe_2 |
| 682 | #ifndef CONF_DMAC_EVOE_2 |
| 683 | #define CONF_DMAC_EVOE_2 0 |
| 684 | #endif |
| 685 | |
| 686 | // <q> Channel Event Input |
| 687 | // <i> Indicates whether channel event reception is enabled or not |
| 688 | // <id> dmac_evie_2 |
| 689 | #ifndef CONF_DMAC_EVIE_2 |
| 690 | #define CONF_DMAC_EVIE_2 0 |
| 691 | #endif |
| 692 | |
| 693 | // <o> Event Input Action |
| 694 | // <0=> No action |
| 695 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 696 | // <2=> Conditional transfer trigger |
| 697 | // <3=> Conditional block transfer |
| 698 | // <4=> Channel suspend operation |
| 699 | // <5=> Channel resume operation |
| 700 | // <6=> Skip next block suspend action |
| 701 | // <i> Defines the event input action |
| 702 | // <id> dmac_evact_2 |
| 703 | #ifndef CONF_DMAC_EVACT_2 |
| 704 | #define CONF_DMAC_EVACT_2 0 |
| 705 | #endif |
| 706 | |
| 707 | // <o> Address Increment Step Size |
| 708 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 709 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 710 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 711 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 712 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 713 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 714 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 715 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 716 | // <i> Defines the address increment step size, applies to source or destination address |
| 717 | // <id> dmac_stepsize_2 |
| 718 | #ifndef CONF_DMAC_STEPSIZE_2 |
| 719 | #define CONF_DMAC_STEPSIZE_2 0 |
| 720 | #endif |
| 721 | |
| 722 | // <o> Step Selection |
| 723 | // <0=> Step size settings apply to the destination address |
| 724 | // <1=> Step size settings apply to the source address |
| 725 | // <i> Defines whether source or destination addresses are using the step size settings |
| 726 | // <id> dmac_stepsel_2 |
| 727 | #ifndef CONF_DMAC_STEPSEL_2 |
| 728 | #define CONF_DMAC_STEPSEL_2 0 |
| 729 | #endif |
| 730 | |
| 731 | // <q> Source Address Increment |
| 732 | // <i> Indicates whether the source address incrementation is enabled or not |
| 733 | // <id> dmac_srcinc_2 |
| 734 | #ifndef CONF_DMAC_SRCINC_2 |
| 735 | #define CONF_DMAC_SRCINC_2 0 |
| 736 | #endif |
| 737 | |
| 738 | // <q> Destination Address Increment |
| 739 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 740 | // <id> dmac_dstinc_2 |
| 741 | #ifndef CONF_DMAC_DSTINC_2 |
| 742 | #define CONF_DMAC_DSTINC_2 0 |
| 743 | #endif |
| 744 | |
| 745 | // <o> Beat Size |
| 746 | // <0=> 8-bit bus transfer |
| 747 | // <1=> 16-bit bus transfer |
| 748 | // <2=> 32-bit bus transfer |
| 749 | // <i> Defines the size of one beat |
| 750 | // <id> dmac_beatsize_2 |
| 751 | #ifndef CONF_DMAC_BEATSIZE_2 |
| 752 | #define CONF_DMAC_BEATSIZE_2 0 |
| 753 | #endif |
| 754 | |
| 755 | // <o> Block Action |
| 756 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 757 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 758 | // <2=> Channel suspend operation is complete |
| 759 | // <3=> Both channel suspend operation and block interrupt |
| 760 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 761 | // <id> dmac_blockact_2 |
| 762 | #ifndef CONF_DMAC_BLOCKACT_2 |
| 763 | #define CONF_DMAC_BLOCKACT_2 0 |
| 764 | #endif |
| 765 | |
| 766 | // <o> Event Output Selection |
| 767 | // <0=> Event generation disabled |
| 768 | // <1=> Event strobe when block transfer complete |
| 769 | // <3=> Event strobe when beat transfer complete |
| 770 | // <i> Defines the event output selection |
| 771 | // <id> dmac_evosel_2 |
| 772 | #ifndef CONF_DMAC_EVOSEL_2 |
| 773 | #define CONF_DMAC_EVOSEL_2 0 |
| 774 | #endif |
| 775 | // </e> |
| 776 | |
| 777 | // <e> Channel 3 settings |
| 778 | // <id> dmac_channel_3_settings |
| 779 | #ifndef CONF_DMAC_CHANNEL_3_SETTINGS |
| 780 | #define CONF_DMAC_CHANNEL_3_SETTINGS 0 |
| 781 | #endif |
| 782 | |
| 783 | // <q> Channel Run in Standby |
| 784 | // <i> Indicates whether channel 3 is running in standby mode or not |
| 785 | // <id> dmac_runstdby_3 |
| 786 | #ifndef CONF_DMAC_RUNSTDBY_3 |
| 787 | #define CONF_DMAC_RUNSTDBY_3 0 |
| 788 | #endif |
| 789 | |
| 790 | // <o> Trigger action |
| 791 | // <0=> One trigger required for each block transfer |
| 792 | // <2=> One trigger required for each beat transfer |
| 793 | // <3=> One trigger required for each transaction |
| 794 | // <i> Defines the trigger action used for a transfer |
| 795 | // <id> dmac_trigact_3 |
| 796 | #ifndef CONF_DMAC_TRIGACT_3 |
| 797 | #define CONF_DMAC_TRIGACT_3 0 |
| 798 | #endif |
| 799 | |
| 800 | // <o> Trigger source |
| 801 | // <0x00=> Only software/event triggers |
| 802 | // <0x01=> RTC Time Stamp Trigger |
| 803 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 804 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 805 | // <0x04=> SERCOM0 RX Trigger |
| 806 | // <0x05=> SERCOM0 TX Trigger |
| 807 | // <0x06=> SERCOM1 RX Trigger |
| 808 | // <0x07=> SERCOM1 TX Trigger |
| 809 | // <0x08=> SERCOM2 RX Trigger |
| 810 | // <0x09=> SERCOM2 TX Trigger |
| 811 | // <0x0A=> SERCOM3 RX Trigger |
| 812 | // <0x0B=> SERCOM3 TX Trigger |
| 813 | // <0x0C=> SERCOM4 RX Trigger |
| 814 | // <0x0D=> SERCOM4 TX Trigger |
| 815 | // <0x0E=> SERCOM5 RX Trigger |
| 816 | // <0x0F=> SERCOM5 TX Trigger |
| 817 | // <0x10=> SERCOM6 RX Trigger |
| 818 | // <0x11=> SERCOM6 TX Trigger |
| 819 | // <0x12=> SERCOM7 RX Trigger |
| 820 | // <0x13=> SERCOM7 TX Trigger |
| 821 | // <0x14=> CAN0 DEBUG Trigger |
| 822 | // <0x15=> CAN1 DEBUG Trigger |
| 823 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 824 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 825 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 826 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 827 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 828 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 829 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 830 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 831 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 832 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 833 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 834 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 835 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 836 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 837 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 838 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 839 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 840 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 841 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 842 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 843 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 844 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 845 | // <0x2C=> TC0 Overflow Trigger |
| 846 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 847 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 848 | // <0x2F=> TC1 Overflow Trigger |
| 849 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 850 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 851 | // <0x32=> TC2 Overflow Trigger |
| 852 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 853 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 854 | // <0x35=> TC3 Overflow Trigger |
| 855 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 856 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 857 | // <0x38=> TC4 Overflow Trigger |
| 858 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 859 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 860 | // <0x3B=> TC5 Overflow Trigger |
| 861 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 862 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 863 | // <0x3E=> TC6 Overflow Trigger |
| 864 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 865 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 866 | // <0x41=> TC7 Overflow Trigger |
| 867 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 868 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 869 | // <0x44=> ADC0 Result Ready Trigger |
| 870 | // <0x45=> ADC0 Sequencing Trigger |
| 871 | // <0x46=> ADC1 Result Ready Trigger |
| 872 | // <0x47=> ADC1 Sequencing Trigger |
| 873 | // <0x48=> DAC Empty 0 Trigger |
| 874 | // <0x49=> DAC Empty 1 Trigger |
| 875 | // <0x4A=> DAC Result Ready 0 Trigger |
| 876 | // <0x4B=> DAC Result Ready 1 Trigger |
| 877 | // <0x4C=> I2S Rx 0 Trigger |
| 878 | // <0x4D=> I2S Rx 1 Trigger |
| 879 | // <0x4E=> I2S Tx 0 Trigger |
| 880 | // <0x4F=> I2S Tx 1 Trigger |
| 881 | // <0x50=> PCC RX Trigger |
| 882 | // <0x51=> AES Write Trigger |
| 883 | // <0x52=> AES Read Trigger |
| 884 | // <0x53=> QSPI Rx Trigger |
| 885 | // <0x54=> QSPI Tx Trigger |
| 886 | // <i> Defines the peripheral trigger which is source of the transfer |
| 887 | // <id> dmac_trifsrc_3 |
| 888 | #ifndef CONF_DMAC_TRIGSRC_3 |
| 889 | #define CONF_DMAC_TRIGSRC_3 0 |
| 890 | #endif |
| 891 | |
| 892 | // <o> Channel Arbitration Level |
| 893 | // <0=> Channel priority 0 |
| 894 | // <1=> Channel priority 1 |
| 895 | // <2=> Channel priority 2 |
| 896 | // <3=> Channel priority 3 |
| 897 | // <i> Defines the arbitration level for this channel |
| 898 | // <id> dmac_lvl_3 |
| 899 | #ifndef CONF_DMAC_LVL_3 |
| 900 | #define CONF_DMAC_LVL_3 0 |
| 901 | #endif |
| 902 | |
| 903 | // <q> Channel Event Output |
| 904 | // <i> Indicates whether channel event generation is enabled or not |
| 905 | // <id> dmac_evoe_3 |
| 906 | #ifndef CONF_DMAC_EVOE_3 |
| 907 | #define CONF_DMAC_EVOE_3 0 |
| 908 | #endif |
| 909 | |
| 910 | // <q> Channel Event Input |
| 911 | // <i> Indicates whether channel event reception is enabled or not |
| 912 | // <id> dmac_evie_3 |
| 913 | #ifndef CONF_DMAC_EVIE_3 |
| 914 | #define CONF_DMAC_EVIE_3 0 |
| 915 | #endif |
| 916 | |
| 917 | // <o> Event Input Action |
| 918 | // <0=> No action |
| 919 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 920 | // <2=> Conditional transfer trigger |
| 921 | // <3=> Conditional block transfer |
| 922 | // <4=> Channel suspend operation |
| 923 | // <5=> Channel resume operation |
| 924 | // <6=> Skip next block suspend action |
| 925 | // <i> Defines the event input action |
| 926 | // <id> dmac_evact_3 |
| 927 | #ifndef CONF_DMAC_EVACT_3 |
| 928 | #define CONF_DMAC_EVACT_3 0 |
| 929 | #endif |
| 930 | |
| 931 | // <o> Address Increment Step Size |
| 932 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 933 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 934 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 935 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 936 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 937 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 938 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 939 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 940 | // <i> Defines the address increment step size, applies to source or destination address |
| 941 | // <id> dmac_stepsize_3 |
| 942 | #ifndef CONF_DMAC_STEPSIZE_3 |
| 943 | #define CONF_DMAC_STEPSIZE_3 0 |
| 944 | #endif |
| 945 | |
| 946 | // <o> Step Selection |
| 947 | // <0=> Step size settings apply to the destination address |
| 948 | // <1=> Step size settings apply to the source address |
| 949 | // <i> Defines whether source or destination addresses are using the step size settings |
| 950 | // <id> dmac_stepsel_3 |
| 951 | #ifndef CONF_DMAC_STEPSEL_3 |
| 952 | #define CONF_DMAC_STEPSEL_3 0 |
| 953 | #endif |
| 954 | |
| 955 | // <q> Source Address Increment |
| 956 | // <i> Indicates whether the source address incrementation is enabled or not |
| 957 | // <id> dmac_srcinc_3 |
| 958 | #ifndef CONF_DMAC_SRCINC_3 |
| 959 | #define CONF_DMAC_SRCINC_3 0 |
| 960 | #endif |
| 961 | |
| 962 | // <q> Destination Address Increment |
| 963 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 964 | // <id> dmac_dstinc_3 |
| 965 | #ifndef CONF_DMAC_DSTINC_3 |
| 966 | #define CONF_DMAC_DSTINC_3 0 |
| 967 | #endif |
| 968 | |
| 969 | // <o> Beat Size |
| 970 | // <0=> 8-bit bus transfer |
| 971 | // <1=> 16-bit bus transfer |
| 972 | // <2=> 32-bit bus transfer |
| 973 | // <i> Defines the size of one beat |
| 974 | // <id> dmac_beatsize_3 |
| 975 | #ifndef CONF_DMAC_BEATSIZE_3 |
| 976 | #define CONF_DMAC_BEATSIZE_3 0 |
| 977 | #endif |
| 978 | |
| 979 | // <o> Block Action |
| 980 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 981 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 982 | // <2=> Channel suspend operation is complete |
| 983 | // <3=> Both channel suspend operation and block interrupt |
| 984 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 985 | // <id> dmac_blockact_3 |
| 986 | #ifndef CONF_DMAC_BLOCKACT_3 |
| 987 | #define CONF_DMAC_BLOCKACT_3 0 |
| 988 | #endif |
| 989 | |
| 990 | // <o> Event Output Selection |
| 991 | // <0=> Event generation disabled |
| 992 | // <1=> Event strobe when block transfer complete |
| 993 | // <3=> Event strobe when beat transfer complete |
| 994 | // <i> Defines the event output selection |
| 995 | // <id> dmac_evosel_3 |
| 996 | #ifndef CONF_DMAC_EVOSEL_3 |
| 997 | #define CONF_DMAC_EVOSEL_3 0 |
| 998 | #endif |
| 999 | // </e> |
| 1000 | |
| 1001 | // <e> Channel 4 settings |
| 1002 | // <id> dmac_channel_4_settings |
| 1003 | #ifndef CONF_DMAC_CHANNEL_4_SETTINGS |
| 1004 | #define CONF_DMAC_CHANNEL_4_SETTINGS 0 |
| 1005 | #endif |
| 1006 | |
| 1007 | // <q> Channel Run in Standby |
| 1008 | // <i> Indicates whether channel 4 is running in standby mode or not |
| 1009 | // <id> dmac_runstdby_4 |
| 1010 | #ifndef CONF_DMAC_RUNSTDBY_4 |
| 1011 | #define CONF_DMAC_RUNSTDBY_4 0 |
| 1012 | #endif |
| 1013 | |
| 1014 | // <o> Trigger action |
| 1015 | // <0=> One trigger required for each block transfer |
| 1016 | // <2=> One trigger required for each beat transfer |
| 1017 | // <3=> One trigger required for each transaction |
| 1018 | // <i> Defines the trigger action used for a transfer |
| 1019 | // <id> dmac_trigact_4 |
| 1020 | #ifndef CONF_DMAC_TRIGACT_4 |
| 1021 | #define CONF_DMAC_TRIGACT_4 0 |
| 1022 | #endif |
| 1023 | |
| 1024 | // <o> Trigger source |
| 1025 | // <0x00=> Only software/event triggers |
| 1026 | // <0x01=> RTC Time Stamp Trigger |
| 1027 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 1028 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 1029 | // <0x04=> SERCOM0 RX Trigger |
| 1030 | // <0x05=> SERCOM0 TX Trigger |
| 1031 | // <0x06=> SERCOM1 RX Trigger |
| 1032 | // <0x07=> SERCOM1 TX Trigger |
| 1033 | // <0x08=> SERCOM2 RX Trigger |
| 1034 | // <0x09=> SERCOM2 TX Trigger |
| 1035 | // <0x0A=> SERCOM3 RX Trigger |
| 1036 | // <0x0B=> SERCOM3 TX Trigger |
| 1037 | // <0x0C=> SERCOM4 RX Trigger |
| 1038 | // <0x0D=> SERCOM4 TX Trigger |
| 1039 | // <0x0E=> SERCOM5 RX Trigger |
| 1040 | // <0x0F=> SERCOM5 TX Trigger |
| 1041 | // <0x10=> SERCOM6 RX Trigger |
| 1042 | // <0x11=> SERCOM6 TX Trigger |
| 1043 | // <0x12=> SERCOM7 RX Trigger |
| 1044 | // <0x13=> SERCOM7 TX Trigger |
| 1045 | // <0x14=> CAN0 DEBUG Trigger |
| 1046 | // <0x15=> CAN1 DEBUG Trigger |
| 1047 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 1048 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 1049 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 1050 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 1051 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 1052 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 1053 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 1054 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 1055 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 1056 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 1057 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 1058 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 1059 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 1060 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 1061 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 1062 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 1063 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 1064 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 1065 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 1066 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 1067 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 1068 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 1069 | // <0x2C=> TC0 Overflow Trigger |
| 1070 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 1071 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 1072 | // <0x2F=> TC1 Overflow Trigger |
| 1073 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 1074 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 1075 | // <0x32=> TC2 Overflow Trigger |
| 1076 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 1077 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 1078 | // <0x35=> TC3 Overflow Trigger |
| 1079 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 1080 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 1081 | // <0x38=> TC4 Overflow Trigger |
| 1082 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 1083 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 1084 | // <0x3B=> TC5 Overflow Trigger |
| 1085 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 1086 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 1087 | // <0x3E=> TC6 Overflow Trigger |
| 1088 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 1089 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 1090 | // <0x41=> TC7 Overflow Trigger |
| 1091 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 1092 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 1093 | // <0x44=> ADC0 Result Ready Trigger |
| 1094 | // <0x45=> ADC0 Sequencing Trigger |
| 1095 | // <0x46=> ADC1 Result Ready Trigger |
| 1096 | // <0x47=> ADC1 Sequencing Trigger |
| 1097 | // <0x48=> DAC Empty 0 Trigger |
| 1098 | // <0x49=> DAC Empty 1 Trigger |
| 1099 | // <0x4A=> DAC Result Ready 0 Trigger |
| 1100 | // <0x4B=> DAC Result Ready 1 Trigger |
| 1101 | // <0x4C=> I2S Rx 0 Trigger |
| 1102 | // <0x4D=> I2S Rx 1 Trigger |
| 1103 | // <0x4E=> I2S Tx 0 Trigger |
| 1104 | // <0x4F=> I2S Tx 1 Trigger |
| 1105 | // <0x50=> PCC RX Trigger |
| 1106 | // <0x51=> AES Write Trigger |
| 1107 | // <0x52=> AES Read Trigger |
| 1108 | // <0x53=> QSPI Rx Trigger |
| 1109 | // <0x54=> QSPI Tx Trigger |
| 1110 | // <i> Defines the peripheral trigger which is source of the transfer |
| 1111 | // <id> dmac_trifsrc_4 |
| 1112 | #ifndef CONF_DMAC_TRIGSRC_4 |
| 1113 | #define CONF_DMAC_TRIGSRC_4 0 |
| 1114 | #endif |
| 1115 | |
| 1116 | // <o> Channel Arbitration Level |
| 1117 | // <0=> Channel priority 0 |
| 1118 | // <1=> Channel priority 1 |
| 1119 | // <2=> Channel priority 2 |
| 1120 | // <3=> Channel priority 3 |
| 1121 | // <i> Defines the arbitration level for this channel |
| 1122 | // <id> dmac_lvl_4 |
| 1123 | #ifndef CONF_DMAC_LVL_4 |
| 1124 | #define CONF_DMAC_LVL_4 0 |
| 1125 | #endif |
| 1126 | |
| 1127 | // <q> Channel Event Output |
| 1128 | // <i> Indicates whether channel event generation is enabled or not |
| 1129 | // <id> dmac_evoe_4 |
| 1130 | #ifndef CONF_DMAC_EVOE_4 |
| 1131 | #define CONF_DMAC_EVOE_4 0 |
| 1132 | #endif |
| 1133 | |
| 1134 | // <q> Channel Event Input |
| 1135 | // <i> Indicates whether channel event reception is enabled or not |
| 1136 | // <id> dmac_evie_4 |
| 1137 | #ifndef CONF_DMAC_EVIE_4 |
| 1138 | #define CONF_DMAC_EVIE_4 0 |
| 1139 | #endif |
| 1140 | |
| 1141 | // <o> Event Input Action |
| 1142 | // <0=> No action |
| 1143 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 1144 | // <2=> Conditional transfer trigger |
| 1145 | // <3=> Conditional block transfer |
| 1146 | // <4=> Channel suspend operation |
| 1147 | // <5=> Channel resume operation |
| 1148 | // <6=> Skip next block suspend action |
| 1149 | // <i> Defines the event input action |
| 1150 | // <id> dmac_evact_4 |
| 1151 | #ifndef CONF_DMAC_EVACT_4 |
| 1152 | #define CONF_DMAC_EVACT_4 0 |
| 1153 | #endif |
| 1154 | |
| 1155 | // <o> Address Increment Step Size |
| 1156 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 1157 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 1158 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 1159 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 1160 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 1161 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 1162 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 1163 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 1164 | // <i> Defines the address increment step size, applies to source or destination address |
| 1165 | // <id> dmac_stepsize_4 |
| 1166 | #ifndef CONF_DMAC_STEPSIZE_4 |
| 1167 | #define CONF_DMAC_STEPSIZE_4 0 |
| 1168 | #endif |
| 1169 | |
| 1170 | // <o> Step Selection |
| 1171 | // <0=> Step size settings apply to the destination address |
| 1172 | // <1=> Step size settings apply to the source address |
| 1173 | // <i> Defines whether source or destination addresses are using the step size settings |
| 1174 | // <id> dmac_stepsel_4 |
| 1175 | #ifndef CONF_DMAC_STEPSEL_4 |
| 1176 | #define CONF_DMAC_STEPSEL_4 0 |
| 1177 | #endif |
| 1178 | |
| 1179 | // <q> Source Address Increment |
| 1180 | // <i> Indicates whether the source address incrementation is enabled or not |
| 1181 | // <id> dmac_srcinc_4 |
| 1182 | #ifndef CONF_DMAC_SRCINC_4 |
| 1183 | #define CONF_DMAC_SRCINC_4 0 |
| 1184 | #endif |
| 1185 | |
| 1186 | // <q> Destination Address Increment |
| 1187 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 1188 | // <id> dmac_dstinc_4 |
| 1189 | #ifndef CONF_DMAC_DSTINC_4 |
| 1190 | #define CONF_DMAC_DSTINC_4 0 |
| 1191 | #endif |
| 1192 | |
| 1193 | // <o> Beat Size |
| 1194 | // <0=> 8-bit bus transfer |
| 1195 | // <1=> 16-bit bus transfer |
| 1196 | // <2=> 32-bit bus transfer |
| 1197 | // <i> Defines the size of one beat |
| 1198 | // <id> dmac_beatsize_4 |
| 1199 | #ifndef CONF_DMAC_BEATSIZE_4 |
| 1200 | #define CONF_DMAC_BEATSIZE_4 0 |
| 1201 | #endif |
| 1202 | |
| 1203 | // <o> Block Action |
| 1204 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 1205 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 1206 | // <2=> Channel suspend operation is complete |
| 1207 | // <3=> Both channel suspend operation and block interrupt |
| 1208 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 1209 | // <id> dmac_blockact_4 |
| 1210 | #ifndef CONF_DMAC_BLOCKACT_4 |
| 1211 | #define CONF_DMAC_BLOCKACT_4 0 |
| 1212 | #endif |
| 1213 | |
| 1214 | // <o> Event Output Selection |
| 1215 | // <0=> Event generation disabled |
| 1216 | // <1=> Event strobe when block transfer complete |
| 1217 | // <3=> Event strobe when beat transfer complete |
| 1218 | // <i> Defines the event output selection |
| 1219 | // <id> dmac_evosel_4 |
| 1220 | #ifndef CONF_DMAC_EVOSEL_4 |
| 1221 | #define CONF_DMAC_EVOSEL_4 0 |
| 1222 | #endif |
| 1223 | // </e> |
| 1224 | |
| 1225 | // <e> Channel 5 settings |
| 1226 | // <id> dmac_channel_5_settings |
| 1227 | #ifndef CONF_DMAC_CHANNEL_5_SETTINGS |
| 1228 | #define CONF_DMAC_CHANNEL_5_SETTINGS 0 |
| 1229 | #endif |
| 1230 | |
| 1231 | // <q> Channel Run in Standby |
| 1232 | // <i> Indicates whether channel 5 is running in standby mode or not |
| 1233 | // <id> dmac_runstdby_5 |
| 1234 | #ifndef CONF_DMAC_RUNSTDBY_5 |
| 1235 | #define CONF_DMAC_RUNSTDBY_5 0 |
| 1236 | #endif |
| 1237 | |
| 1238 | // <o> Trigger action |
| 1239 | // <0=> One trigger required for each block transfer |
| 1240 | // <2=> One trigger required for each beat transfer |
| 1241 | // <3=> One trigger required for each transaction |
| 1242 | // <i> Defines the trigger action used for a transfer |
| 1243 | // <id> dmac_trigact_5 |
| 1244 | #ifndef CONF_DMAC_TRIGACT_5 |
| 1245 | #define CONF_DMAC_TRIGACT_5 0 |
| 1246 | #endif |
| 1247 | |
| 1248 | // <o> Trigger source |
| 1249 | // <0x00=> Only software/event triggers |
| 1250 | // <0x01=> RTC Time Stamp Trigger |
| 1251 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 1252 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 1253 | // <0x04=> SERCOM0 RX Trigger |
| 1254 | // <0x05=> SERCOM0 TX Trigger |
| 1255 | // <0x06=> SERCOM1 RX Trigger |
| 1256 | // <0x07=> SERCOM1 TX Trigger |
| 1257 | // <0x08=> SERCOM2 RX Trigger |
| 1258 | // <0x09=> SERCOM2 TX Trigger |
| 1259 | // <0x0A=> SERCOM3 RX Trigger |
| 1260 | // <0x0B=> SERCOM3 TX Trigger |
| 1261 | // <0x0C=> SERCOM4 RX Trigger |
| 1262 | // <0x0D=> SERCOM4 TX Trigger |
| 1263 | // <0x0E=> SERCOM5 RX Trigger |
| 1264 | // <0x0F=> SERCOM5 TX Trigger |
| 1265 | // <0x10=> SERCOM6 RX Trigger |
| 1266 | // <0x11=> SERCOM6 TX Trigger |
| 1267 | // <0x12=> SERCOM7 RX Trigger |
| 1268 | // <0x13=> SERCOM7 TX Trigger |
| 1269 | // <0x14=> CAN0 DEBUG Trigger |
| 1270 | // <0x15=> CAN1 DEBUG Trigger |
| 1271 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 1272 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 1273 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 1274 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 1275 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 1276 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 1277 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 1278 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 1279 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 1280 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 1281 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 1282 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 1283 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 1284 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 1285 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 1286 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 1287 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 1288 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 1289 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 1290 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 1291 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 1292 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 1293 | // <0x2C=> TC0 Overflow Trigger |
| 1294 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 1295 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 1296 | // <0x2F=> TC1 Overflow Trigger |
| 1297 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 1298 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 1299 | // <0x32=> TC2 Overflow Trigger |
| 1300 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 1301 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 1302 | // <0x35=> TC3 Overflow Trigger |
| 1303 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 1304 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 1305 | // <0x38=> TC4 Overflow Trigger |
| 1306 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 1307 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 1308 | // <0x3B=> TC5 Overflow Trigger |
| 1309 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 1310 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 1311 | // <0x3E=> TC6 Overflow Trigger |
| 1312 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 1313 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 1314 | // <0x41=> TC7 Overflow Trigger |
| 1315 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 1316 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 1317 | // <0x44=> ADC0 Result Ready Trigger |
| 1318 | // <0x45=> ADC0 Sequencing Trigger |
| 1319 | // <0x46=> ADC1 Result Ready Trigger |
| 1320 | // <0x47=> ADC1 Sequencing Trigger |
| 1321 | // <0x48=> DAC Empty 0 Trigger |
| 1322 | // <0x49=> DAC Empty 1 Trigger |
| 1323 | // <0x4A=> DAC Result Ready 0 Trigger |
| 1324 | // <0x4B=> DAC Result Ready 1 Trigger |
| 1325 | // <0x4C=> I2S Rx 0 Trigger |
| 1326 | // <0x4D=> I2S Rx 1 Trigger |
| 1327 | // <0x4E=> I2S Tx 0 Trigger |
| 1328 | // <0x4F=> I2S Tx 1 Trigger |
| 1329 | // <0x50=> PCC RX Trigger |
| 1330 | // <0x51=> AES Write Trigger |
| 1331 | // <0x52=> AES Read Trigger |
| 1332 | // <0x53=> QSPI Rx Trigger |
| 1333 | // <0x54=> QSPI Tx Trigger |
| 1334 | // <i> Defines the peripheral trigger which is source of the transfer |
| 1335 | // <id> dmac_trifsrc_5 |
| 1336 | #ifndef CONF_DMAC_TRIGSRC_5 |
| 1337 | #define CONF_DMAC_TRIGSRC_5 0 |
| 1338 | #endif |
| 1339 | |
| 1340 | // <o> Channel Arbitration Level |
| 1341 | // <0=> Channel priority 0 |
| 1342 | // <1=> Channel priority 1 |
| 1343 | // <2=> Channel priority 2 |
| 1344 | // <3=> Channel priority 3 |
| 1345 | // <i> Defines the arbitration level for this channel |
| 1346 | // <id> dmac_lvl_5 |
| 1347 | #ifndef CONF_DMAC_LVL_5 |
| 1348 | #define CONF_DMAC_LVL_5 0 |
| 1349 | #endif |
| 1350 | |
| 1351 | // <q> Channel Event Output |
| 1352 | // <i> Indicates whether channel event generation is enabled or not |
| 1353 | // <id> dmac_evoe_5 |
| 1354 | #ifndef CONF_DMAC_EVOE_5 |
| 1355 | #define CONF_DMAC_EVOE_5 0 |
| 1356 | #endif |
| 1357 | |
| 1358 | // <q> Channel Event Input |
| 1359 | // <i> Indicates whether channel event reception is enabled or not |
| 1360 | // <id> dmac_evie_5 |
| 1361 | #ifndef CONF_DMAC_EVIE_5 |
| 1362 | #define CONF_DMAC_EVIE_5 0 |
| 1363 | #endif |
| 1364 | |
| 1365 | // <o> Event Input Action |
| 1366 | // <0=> No action |
| 1367 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 1368 | // <2=> Conditional transfer trigger |
| 1369 | // <3=> Conditional block transfer |
| 1370 | // <4=> Channel suspend operation |
| 1371 | // <5=> Channel resume operation |
| 1372 | // <6=> Skip next block suspend action |
| 1373 | // <i> Defines the event input action |
| 1374 | // <id> dmac_evact_5 |
| 1375 | #ifndef CONF_DMAC_EVACT_5 |
| 1376 | #define CONF_DMAC_EVACT_5 0 |
| 1377 | #endif |
| 1378 | |
| 1379 | // <o> Address Increment Step Size |
| 1380 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 1381 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 1382 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 1383 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 1384 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 1385 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 1386 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 1387 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 1388 | // <i> Defines the address increment step size, applies to source or destination address |
| 1389 | // <id> dmac_stepsize_5 |
| 1390 | #ifndef CONF_DMAC_STEPSIZE_5 |
| 1391 | #define CONF_DMAC_STEPSIZE_5 0 |
| 1392 | #endif |
| 1393 | |
| 1394 | // <o> Step Selection |
| 1395 | // <0=> Step size settings apply to the destination address |
| 1396 | // <1=> Step size settings apply to the source address |
| 1397 | // <i> Defines whether source or destination addresses are using the step size settings |
| 1398 | // <id> dmac_stepsel_5 |
| 1399 | #ifndef CONF_DMAC_STEPSEL_5 |
| 1400 | #define CONF_DMAC_STEPSEL_5 0 |
| 1401 | #endif |
| 1402 | |
| 1403 | // <q> Source Address Increment |
| 1404 | // <i> Indicates whether the source address incrementation is enabled or not |
| 1405 | // <id> dmac_srcinc_5 |
| 1406 | #ifndef CONF_DMAC_SRCINC_5 |
| 1407 | #define CONF_DMAC_SRCINC_5 0 |
| 1408 | #endif |
| 1409 | |
| 1410 | // <q> Destination Address Increment |
| 1411 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 1412 | // <id> dmac_dstinc_5 |
| 1413 | #ifndef CONF_DMAC_DSTINC_5 |
| 1414 | #define CONF_DMAC_DSTINC_5 0 |
| 1415 | #endif |
| 1416 | |
| 1417 | // <o> Beat Size |
| 1418 | // <0=> 8-bit bus transfer |
| 1419 | // <1=> 16-bit bus transfer |
| 1420 | // <2=> 32-bit bus transfer |
| 1421 | // <i> Defines the size of one beat |
| 1422 | // <id> dmac_beatsize_5 |
| 1423 | #ifndef CONF_DMAC_BEATSIZE_5 |
| 1424 | #define CONF_DMAC_BEATSIZE_5 0 |
| 1425 | #endif |
| 1426 | |
| 1427 | // <o> Block Action |
| 1428 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 1429 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 1430 | // <2=> Channel suspend operation is complete |
| 1431 | // <3=> Both channel suspend operation and block interrupt |
| 1432 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 1433 | // <id> dmac_blockact_5 |
| 1434 | #ifndef CONF_DMAC_BLOCKACT_5 |
| 1435 | #define CONF_DMAC_BLOCKACT_5 0 |
| 1436 | #endif |
| 1437 | |
| 1438 | // <o> Event Output Selection |
| 1439 | // <0=> Event generation disabled |
| 1440 | // <1=> Event strobe when block transfer complete |
| 1441 | // <3=> Event strobe when beat transfer complete |
| 1442 | // <i> Defines the event output selection |
| 1443 | // <id> dmac_evosel_5 |
| 1444 | #ifndef CONF_DMAC_EVOSEL_5 |
| 1445 | #define CONF_DMAC_EVOSEL_5 0 |
| 1446 | #endif |
| 1447 | // </e> |
| 1448 | |
| 1449 | // <e> Channel 6 settings |
| 1450 | // <id> dmac_channel_6_settings |
| 1451 | #ifndef CONF_DMAC_CHANNEL_6_SETTINGS |
| 1452 | #define CONF_DMAC_CHANNEL_6_SETTINGS 0 |
| 1453 | #endif |
| 1454 | |
| 1455 | // <q> Channel Run in Standby |
| 1456 | // <i> Indicates whether channel 6 is running in standby mode or not |
| 1457 | // <id> dmac_runstdby_6 |
| 1458 | #ifndef CONF_DMAC_RUNSTDBY_6 |
| 1459 | #define CONF_DMAC_RUNSTDBY_6 0 |
| 1460 | #endif |
| 1461 | |
| 1462 | // <o> Trigger action |
| 1463 | // <0=> One trigger required for each block transfer |
| 1464 | // <2=> One trigger required for each beat transfer |
| 1465 | // <3=> One trigger required for each transaction |
| 1466 | // <i> Defines the trigger action used for a transfer |
| 1467 | // <id> dmac_trigact_6 |
| 1468 | #ifndef CONF_DMAC_TRIGACT_6 |
| 1469 | #define CONF_DMAC_TRIGACT_6 0 |
| 1470 | #endif |
| 1471 | |
| 1472 | // <o> Trigger source |
| 1473 | // <0x00=> Only software/event triggers |
| 1474 | // <0x01=> RTC Time Stamp Trigger |
| 1475 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 1476 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 1477 | // <0x04=> SERCOM0 RX Trigger |
| 1478 | // <0x05=> SERCOM0 TX Trigger |
| 1479 | // <0x06=> SERCOM1 RX Trigger |
| 1480 | // <0x07=> SERCOM1 TX Trigger |
| 1481 | // <0x08=> SERCOM2 RX Trigger |
| 1482 | // <0x09=> SERCOM2 TX Trigger |
| 1483 | // <0x0A=> SERCOM3 RX Trigger |
| 1484 | // <0x0B=> SERCOM3 TX Trigger |
| 1485 | // <0x0C=> SERCOM4 RX Trigger |
| 1486 | // <0x0D=> SERCOM4 TX Trigger |
| 1487 | // <0x0E=> SERCOM5 RX Trigger |
| 1488 | // <0x0F=> SERCOM5 TX Trigger |
| 1489 | // <0x10=> SERCOM6 RX Trigger |
| 1490 | // <0x11=> SERCOM6 TX Trigger |
| 1491 | // <0x12=> SERCOM7 RX Trigger |
| 1492 | // <0x13=> SERCOM7 TX Trigger |
| 1493 | // <0x14=> CAN0 DEBUG Trigger |
| 1494 | // <0x15=> CAN1 DEBUG Trigger |
| 1495 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 1496 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 1497 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 1498 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 1499 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 1500 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 1501 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 1502 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 1503 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 1504 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 1505 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 1506 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 1507 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 1508 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 1509 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 1510 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 1511 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 1512 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 1513 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 1514 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 1515 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 1516 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 1517 | // <0x2C=> TC0 Overflow Trigger |
| 1518 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 1519 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 1520 | // <0x2F=> TC1 Overflow Trigger |
| 1521 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 1522 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 1523 | // <0x32=> TC2 Overflow Trigger |
| 1524 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 1525 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 1526 | // <0x35=> TC3 Overflow Trigger |
| 1527 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 1528 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 1529 | // <0x38=> TC4 Overflow Trigger |
| 1530 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 1531 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 1532 | // <0x3B=> TC5 Overflow Trigger |
| 1533 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 1534 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 1535 | // <0x3E=> TC6 Overflow Trigger |
| 1536 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 1537 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 1538 | // <0x41=> TC7 Overflow Trigger |
| 1539 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 1540 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 1541 | // <0x44=> ADC0 Result Ready Trigger |
| 1542 | // <0x45=> ADC0 Sequencing Trigger |
| 1543 | // <0x46=> ADC1 Result Ready Trigger |
| 1544 | // <0x47=> ADC1 Sequencing Trigger |
| 1545 | // <0x48=> DAC Empty 0 Trigger |
| 1546 | // <0x49=> DAC Empty 1 Trigger |
| 1547 | // <0x4A=> DAC Result Ready 0 Trigger |
| 1548 | // <0x4B=> DAC Result Ready 1 Trigger |
| 1549 | // <0x4C=> I2S Rx 0 Trigger |
| 1550 | // <0x4D=> I2S Rx 1 Trigger |
| 1551 | // <0x4E=> I2S Tx 0 Trigger |
| 1552 | // <0x4F=> I2S Tx 1 Trigger |
| 1553 | // <0x50=> PCC RX Trigger |
| 1554 | // <0x51=> AES Write Trigger |
| 1555 | // <0x52=> AES Read Trigger |
| 1556 | // <0x53=> QSPI Rx Trigger |
| 1557 | // <0x54=> QSPI Tx Trigger |
| 1558 | // <i> Defines the peripheral trigger which is source of the transfer |
| 1559 | // <id> dmac_trifsrc_6 |
| 1560 | #ifndef CONF_DMAC_TRIGSRC_6 |
| 1561 | #define CONF_DMAC_TRIGSRC_6 0 |
| 1562 | #endif |
| 1563 | |
| 1564 | // <o> Channel Arbitration Level |
| 1565 | // <0=> Channel priority 0 |
| 1566 | // <1=> Channel priority 1 |
| 1567 | // <2=> Channel priority 2 |
| 1568 | // <3=> Channel priority 3 |
| 1569 | // <i> Defines the arbitration level for this channel |
| 1570 | // <id> dmac_lvl_6 |
| 1571 | #ifndef CONF_DMAC_LVL_6 |
| 1572 | #define CONF_DMAC_LVL_6 0 |
| 1573 | #endif |
| 1574 | |
| 1575 | // <q> Channel Event Output |
| 1576 | // <i> Indicates whether channel event generation is enabled or not |
| 1577 | // <id> dmac_evoe_6 |
| 1578 | #ifndef CONF_DMAC_EVOE_6 |
| 1579 | #define CONF_DMAC_EVOE_6 0 |
| 1580 | #endif |
| 1581 | |
| 1582 | // <q> Channel Event Input |
| 1583 | // <i> Indicates whether channel event reception is enabled or not |
| 1584 | // <id> dmac_evie_6 |
| 1585 | #ifndef CONF_DMAC_EVIE_6 |
| 1586 | #define CONF_DMAC_EVIE_6 0 |
| 1587 | #endif |
| 1588 | |
| 1589 | // <o> Event Input Action |
| 1590 | // <0=> No action |
| 1591 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 1592 | // <2=> Conditional transfer trigger |
| 1593 | // <3=> Conditional block transfer |
| 1594 | // <4=> Channel suspend operation |
| 1595 | // <5=> Channel resume operation |
| 1596 | // <6=> Skip next block suspend action |
| 1597 | // <i> Defines the event input action |
| 1598 | // <id> dmac_evact_6 |
| 1599 | #ifndef CONF_DMAC_EVACT_6 |
| 1600 | #define CONF_DMAC_EVACT_6 0 |
| 1601 | #endif |
| 1602 | |
| 1603 | // <o> Address Increment Step Size |
| 1604 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 1605 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 1606 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 1607 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 1608 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 1609 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 1610 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 1611 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 1612 | // <i> Defines the address increment step size, applies to source or destination address |
| 1613 | // <id> dmac_stepsize_6 |
| 1614 | #ifndef CONF_DMAC_STEPSIZE_6 |
| 1615 | #define CONF_DMAC_STEPSIZE_6 0 |
| 1616 | #endif |
| 1617 | |
| 1618 | // <o> Step Selection |
| 1619 | // <0=> Step size settings apply to the destination address |
| 1620 | // <1=> Step size settings apply to the source address |
| 1621 | // <i> Defines whether source or destination addresses are using the step size settings |
| 1622 | // <id> dmac_stepsel_6 |
| 1623 | #ifndef CONF_DMAC_STEPSEL_6 |
| 1624 | #define CONF_DMAC_STEPSEL_6 0 |
| 1625 | #endif |
| 1626 | |
| 1627 | // <q> Source Address Increment |
| 1628 | // <i> Indicates whether the source address incrementation is enabled or not |
| 1629 | // <id> dmac_srcinc_6 |
| 1630 | #ifndef CONF_DMAC_SRCINC_6 |
| 1631 | #define CONF_DMAC_SRCINC_6 0 |
| 1632 | #endif |
| 1633 | |
| 1634 | // <q> Destination Address Increment |
| 1635 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 1636 | // <id> dmac_dstinc_6 |
| 1637 | #ifndef CONF_DMAC_DSTINC_6 |
| 1638 | #define CONF_DMAC_DSTINC_6 0 |
| 1639 | #endif |
| 1640 | |
| 1641 | // <o> Beat Size |
| 1642 | // <0=> 8-bit bus transfer |
| 1643 | // <1=> 16-bit bus transfer |
| 1644 | // <2=> 32-bit bus transfer |
| 1645 | // <i> Defines the size of one beat |
| 1646 | // <id> dmac_beatsize_6 |
| 1647 | #ifndef CONF_DMAC_BEATSIZE_6 |
| 1648 | #define CONF_DMAC_BEATSIZE_6 0 |
| 1649 | #endif |
| 1650 | |
| 1651 | // <o> Block Action |
| 1652 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 1653 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 1654 | // <2=> Channel suspend operation is complete |
| 1655 | // <3=> Both channel suspend operation and block interrupt |
| 1656 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 1657 | // <id> dmac_blockact_6 |
| 1658 | #ifndef CONF_DMAC_BLOCKACT_6 |
| 1659 | #define CONF_DMAC_BLOCKACT_6 0 |
| 1660 | #endif |
| 1661 | |
| 1662 | // <o> Event Output Selection |
| 1663 | // <0=> Event generation disabled |
| 1664 | // <1=> Event strobe when block transfer complete |
| 1665 | // <3=> Event strobe when beat transfer complete |
| 1666 | // <i> Defines the event output selection |
| 1667 | // <id> dmac_evosel_6 |
| 1668 | #ifndef CONF_DMAC_EVOSEL_6 |
| 1669 | #define CONF_DMAC_EVOSEL_6 0 |
| 1670 | #endif |
| 1671 | // </e> |
| 1672 | |
| 1673 | // <e> Channel 7 settings |
| 1674 | // <id> dmac_channel_7_settings |
| 1675 | #ifndef CONF_DMAC_CHANNEL_7_SETTINGS |
| 1676 | #define CONF_DMAC_CHANNEL_7_SETTINGS 0 |
| 1677 | #endif |
| 1678 | |
| 1679 | // <q> Channel Run in Standby |
| 1680 | // <i> Indicates whether channel 7 is running in standby mode or not |
| 1681 | // <id> dmac_runstdby_7 |
| 1682 | #ifndef CONF_DMAC_RUNSTDBY_7 |
| 1683 | #define CONF_DMAC_RUNSTDBY_7 0 |
| 1684 | #endif |
| 1685 | |
| 1686 | // <o> Trigger action |
| 1687 | // <0=> One trigger required for each block transfer |
| 1688 | // <2=> One trigger required for each beat transfer |
| 1689 | // <3=> One trigger required for each transaction |
| 1690 | // <i> Defines the trigger action used for a transfer |
| 1691 | // <id> dmac_trigact_7 |
| 1692 | #ifndef CONF_DMAC_TRIGACT_7 |
| 1693 | #define CONF_DMAC_TRIGACT_7 0 |
| 1694 | #endif |
| 1695 | |
| 1696 | // <o> Trigger source |
| 1697 | // <0x00=> Only software/event triggers |
| 1698 | // <0x01=> RTC Time Stamp Trigger |
| 1699 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 1700 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 1701 | // <0x04=> SERCOM0 RX Trigger |
| 1702 | // <0x05=> SERCOM0 TX Trigger |
| 1703 | // <0x06=> SERCOM1 RX Trigger |
| 1704 | // <0x07=> SERCOM1 TX Trigger |
| 1705 | // <0x08=> SERCOM2 RX Trigger |
| 1706 | // <0x09=> SERCOM2 TX Trigger |
| 1707 | // <0x0A=> SERCOM3 RX Trigger |
| 1708 | // <0x0B=> SERCOM3 TX Trigger |
| 1709 | // <0x0C=> SERCOM4 RX Trigger |
| 1710 | // <0x0D=> SERCOM4 TX Trigger |
| 1711 | // <0x0E=> SERCOM5 RX Trigger |
| 1712 | // <0x0F=> SERCOM5 TX Trigger |
| 1713 | // <0x10=> SERCOM6 RX Trigger |
| 1714 | // <0x11=> SERCOM6 TX Trigger |
| 1715 | // <0x12=> SERCOM7 RX Trigger |
| 1716 | // <0x13=> SERCOM7 TX Trigger |
| 1717 | // <0x14=> CAN0 DEBUG Trigger |
| 1718 | // <0x15=> CAN1 DEBUG Trigger |
| 1719 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 1720 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 1721 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 1722 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 1723 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 1724 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 1725 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 1726 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 1727 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 1728 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 1729 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 1730 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 1731 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 1732 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 1733 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 1734 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 1735 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 1736 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 1737 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 1738 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 1739 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 1740 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 1741 | // <0x2C=> TC0 Overflow Trigger |
| 1742 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 1743 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 1744 | // <0x2F=> TC1 Overflow Trigger |
| 1745 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 1746 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 1747 | // <0x32=> TC2 Overflow Trigger |
| 1748 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 1749 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 1750 | // <0x35=> TC3 Overflow Trigger |
| 1751 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 1752 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 1753 | // <0x38=> TC4 Overflow Trigger |
| 1754 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 1755 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 1756 | // <0x3B=> TC5 Overflow Trigger |
| 1757 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 1758 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 1759 | // <0x3E=> TC6 Overflow Trigger |
| 1760 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 1761 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 1762 | // <0x41=> TC7 Overflow Trigger |
| 1763 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 1764 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 1765 | // <0x44=> ADC0 Result Ready Trigger |
| 1766 | // <0x45=> ADC0 Sequencing Trigger |
| 1767 | // <0x46=> ADC1 Result Ready Trigger |
| 1768 | // <0x47=> ADC1 Sequencing Trigger |
| 1769 | // <0x48=> DAC Empty 0 Trigger |
| 1770 | // <0x49=> DAC Empty 1 Trigger |
| 1771 | // <0x4A=> DAC Result Ready 0 Trigger |
| 1772 | // <0x4B=> DAC Result Ready 1 Trigger |
| 1773 | // <0x4C=> I2S Rx 0 Trigger |
| 1774 | // <0x4D=> I2S Rx 1 Trigger |
| 1775 | // <0x4E=> I2S Tx 0 Trigger |
| 1776 | // <0x4F=> I2S Tx 1 Trigger |
| 1777 | // <0x50=> PCC RX Trigger |
| 1778 | // <0x51=> AES Write Trigger |
| 1779 | // <0x52=> AES Read Trigger |
| 1780 | // <0x53=> QSPI Rx Trigger |
| 1781 | // <0x54=> QSPI Tx Trigger |
| 1782 | // <i> Defines the peripheral trigger which is source of the transfer |
| 1783 | // <id> dmac_trifsrc_7 |
| 1784 | #ifndef CONF_DMAC_TRIGSRC_7 |
| 1785 | #define CONF_DMAC_TRIGSRC_7 0 |
| 1786 | #endif |
| 1787 | |
| 1788 | // <o> Channel Arbitration Level |
| 1789 | // <0=> Channel priority 0 |
| 1790 | // <1=> Channel priority 1 |
| 1791 | // <2=> Channel priority 2 |
| 1792 | // <3=> Channel priority 3 |
| 1793 | // <i> Defines the arbitration level for this channel |
| 1794 | // <id> dmac_lvl_7 |
| 1795 | #ifndef CONF_DMAC_LVL_7 |
| 1796 | #define CONF_DMAC_LVL_7 0 |
| 1797 | #endif |
| 1798 | |
| 1799 | // <q> Channel Event Output |
| 1800 | // <i> Indicates whether channel event generation is enabled or not |
| 1801 | // <id> dmac_evoe_7 |
| 1802 | #ifndef CONF_DMAC_EVOE_7 |
| 1803 | #define CONF_DMAC_EVOE_7 0 |
| 1804 | #endif |
| 1805 | |
| 1806 | // <q> Channel Event Input |
| 1807 | // <i> Indicates whether channel event reception is enabled or not |
| 1808 | // <id> dmac_evie_7 |
| 1809 | #ifndef CONF_DMAC_EVIE_7 |
| 1810 | #define CONF_DMAC_EVIE_7 0 |
| 1811 | #endif |
| 1812 | |
| 1813 | // <o> Event Input Action |
| 1814 | // <0=> No action |
| 1815 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 1816 | // <2=> Conditional transfer trigger |
| 1817 | // <3=> Conditional block transfer |
| 1818 | // <4=> Channel suspend operation |
| 1819 | // <5=> Channel resume operation |
| 1820 | // <6=> Skip next block suspend action |
| 1821 | // <i> Defines the event input action |
| 1822 | // <id> dmac_evact_7 |
| 1823 | #ifndef CONF_DMAC_EVACT_7 |
| 1824 | #define CONF_DMAC_EVACT_7 0 |
| 1825 | #endif |
| 1826 | |
| 1827 | // <o> Address Increment Step Size |
| 1828 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 1829 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 1830 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 1831 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 1832 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 1833 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 1834 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 1835 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 1836 | // <i> Defines the address increment step size, applies to source or destination address |
| 1837 | // <id> dmac_stepsize_7 |
| 1838 | #ifndef CONF_DMAC_STEPSIZE_7 |
| 1839 | #define CONF_DMAC_STEPSIZE_7 0 |
| 1840 | #endif |
| 1841 | |
| 1842 | // <o> Step Selection |
| 1843 | // <0=> Step size settings apply to the destination address |
| 1844 | // <1=> Step size settings apply to the source address |
| 1845 | // <i> Defines whether source or destination addresses are using the step size settings |
| 1846 | // <id> dmac_stepsel_7 |
| 1847 | #ifndef CONF_DMAC_STEPSEL_7 |
| 1848 | #define CONF_DMAC_STEPSEL_7 0 |
| 1849 | #endif |
| 1850 | |
| 1851 | // <q> Source Address Increment |
| 1852 | // <i> Indicates whether the source address incrementation is enabled or not |
| 1853 | // <id> dmac_srcinc_7 |
| 1854 | #ifndef CONF_DMAC_SRCINC_7 |
| 1855 | #define CONF_DMAC_SRCINC_7 0 |
| 1856 | #endif |
| 1857 | |
| 1858 | // <q> Destination Address Increment |
| 1859 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 1860 | // <id> dmac_dstinc_7 |
| 1861 | #ifndef CONF_DMAC_DSTINC_7 |
| 1862 | #define CONF_DMAC_DSTINC_7 0 |
| 1863 | #endif |
| 1864 | |
| 1865 | // <o> Beat Size |
| 1866 | // <0=> 8-bit bus transfer |
| 1867 | // <1=> 16-bit bus transfer |
| 1868 | // <2=> 32-bit bus transfer |
| 1869 | // <i> Defines the size of one beat |
| 1870 | // <id> dmac_beatsize_7 |
| 1871 | #ifndef CONF_DMAC_BEATSIZE_7 |
| 1872 | #define CONF_DMAC_BEATSIZE_7 0 |
| 1873 | #endif |
| 1874 | |
| 1875 | // <o> Block Action |
| 1876 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 1877 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 1878 | // <2=> Channel suspend operation is complete |
| 1879 | // <3=> Both channel suspend operation and block interrupt |
| 1880 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 1881 | // <id> dmac_blockact_7 |
| 1882 | #ifndef CONF_DMAC_BLOCKACT_7 |
| 1883 | #define CONF_DMAC_BLOCKACT_7 0 |
| 1884 | #endif |
| 1885 | |
| 1886 | // <o> Event Output Selection |
| 1887 | // <0=> Event generation disabled |
| 1888 | // <1=> Event strobe when block transfer complete |
| 1889 | // <3=> Event strobe when beat transfer complete |
| 1890 | // <i> Defines the event output selection |
| 1891 | // <id> dmac_evosel_7 |
| 1892 | #ifndef CONF_DMAC_EVOSEL_7 |
| 1893 | #define CONF_DMAC_EVOSEL_7 0 |
| 1894 | #endif |
| 1895 | // </e> |
| 1896 | |
| 1897 | // <e> Channel 8 settings |
| 1898 | // <id> dmac_channel_8_settings |
| 1899 | #ifndef CONF_DMAC_CHANNEL_8_SETTINGS |
| 1900 | #define CONF_DMAC_CHANNEL_8_SETTINGS 0 |
| 1901 | #endif |
| 1902 | |
| 1903 | // <q> Channel Run in Standby |
| 1904 | // <i> Indicates whether channel 8 is running in standby mode or not |
| 1905 | // <id> dmac_runstdby_8 |
| 1906 | #ifndef CONF_DMAC_RUNSTDBY_8 |
| 1907 | #define CONF_DMAC_RUNSTDBY_8 0 |
| 1908 | #endif |
| 1909 | |
| 1910 | // <o> Trigger action |
| 1911 | // <0=> One trigger required for each block transfer |
| 1912 | // <2=> One trigger required for each beat transfer |
| 1913 | // <3=> One trigger required for each transaction |
| 1914 | // <i> Defines the trigger action used for a transfer |
| 1915 | // <id> dmac_trigact_8 |
| 1916 | #ifndef CONF_DMAC_TRIGACT_8 |
| 1917 | #define CONF_DMAC_TRIGACT_8 0 |
| 1918 | #endif |
| 1919 | |
| 1920 | // <o> Trigger source |
| 1921 | // <0x00=> Only software/event triggers |
| 1922 | // <0x01=> RTC Time Stamp Trigger |
| 1923 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 1924 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 1925 | // <0x04=> SERCOM0 RX Trigger |
| 1926 | // <0x05=> SERCOM0 TX Trigger |
| 1927 | // <0x06=> SERCOM1 RX Trigger |
| 1928 | // <0x07=> SERCOM1 TX Trigger |
| 1929 | // <0x08=> SERCOM2 RX Trigger |
| 1930 | // <0x09=> SERCOM2 TX Trigger |
| 1931 | // <0x0A=> SERCOM3 RX Trigger |
| 1932 | // <0x0B=> SERCOM3 TX Trigger |
| 1933 | // <0x0C=> SERCOM4 RX Trigger |
| 1934 | // <0x0D=> SERCOM4 TX Trigger |
| 1935 | // <0x0E=> SERCOM5 RX Trigger |
| 1936 | // <0x0F=> SERCOM5 TX Trigger |
| 1937 | // <0x10=> SERCOM6 RX Trigger |
| 1938 | // <0x11=> SERCOM6 TX Trigger |
| 1939 | // <0x12=> SERCOM7 RX Trigger |
| 1940 | // <0x13=> SERCOM7 TX Trigger |
| 1941 | // <0x14=> CAN0 DEBUG Trigger |
| 1942 | // <0x15=> CAN1 DEBUG Trigger |
| 1943 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 1944 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 1945 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 1946 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 1947 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 1948 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 1949 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 1950 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 1951 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 1952 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 1953 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 1954 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 1955 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 1956 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 1957 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 1958 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 1959 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 1960 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 1961 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 1962 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 1963 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 1964 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 1965 | // <0x2C=> TC0 Overflow Trigger |
| 1966 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 1967 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 1968 | // <0x2F=> TC1 Overflow Trigger |
| 1969 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 1970 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 1971 | // <0x32=> TC2 Overflow Trigger |
| 1972 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 1973 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 1974 | // <0x35=> TC3 Overflow Trigger |
| 1975 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 1976 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 1977 | // <0x38=> TC4 Overflow Trigger |
| 1978 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 1979 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 1980 | // <0x3B=> TC5 Overflow Trigger |
| 1981 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 1982 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 1983 | // <0x3E=> TC6 Overflow Trigger |
| 1984 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 1985 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 1986 | // <0x41=> TC7 Overflow Trigger |
| 1987 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 1988 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 1989 | // <0x44=> ADC0 Result Ready Trigger |
| 1990 | // <0x45=> ADC0 Sequencing Trigger |
| 1991 | // <0x46=> ADC1 Result Ready Trigger |
| 1992 | // <0x47=> ADC1 Sequencing Trigger |
| 1993 | // <0x48=> DAC Empty 0 Trigger |
| 1994 | // <0x49=> DAC Empty 1 Trigger |
| 1995 | // <0x4A=> DAC Result Ready 0 Trigger |
| 1996 | // <0x4B=> DAC Result Ready 1 Trigger |
| 1997 | // <0x4C=> I2S Rx 0 Trigger |
| 1998 | // <0x4D=> I2S Rx 1 Trigger |
| 1999 | // <0x4E=> I2S Tx 0 Trigger |
| 2000 | // <0x4F=> I2S Tx 1 Trigger |
| 2001 | // <0x50=> PCC RX Trigger |
| 2002 | // <0x51=> AES Write Trigger |
| 2003 | // <0x52=> AES Read Trigger |
| 2004 | // <0x53=> QSPI Rx Trigger |
| 2005 | // <0x54=> QSPI Tx Trigger |
| 2006 | // <i> Defines the peripheral trigger which is source of the transfer |
| 2007 | // <id> dmac_trifsrc_8 |
| 2008 | #ifndef CONF_DMAC_TRIGSRC_8 |
| 2009 | #define CONF_DMAC_TRIGSRC_8 0 |
| 2010 | #endif |
| 2011 | |
| 2012 | // <o> Channel Arbitration Level |
| 2013 | // <0=> Channel priority 0 |
| 2014 | // <1=> Channel priority 1 |
| 2015 | // <2=> Channel priority 2 |
| 2016 | // <3=> Channel priority 3 |
| 2017 | // <i> Defines the arbitration level for this channel |
| 2018 | // <id> dmac_lvl_8 |
| 2019 | #ifndef CONF_DMAC_LVL_8 |
| 2020 | #define CONF_DMAC_LVL_8 0 |
| 2021 | #endif |
| 2022 | |
| 2023 | // <q> Channel Event Output |
| 2024 | // <i> Indicates whether channel event generation is enabled or not |
| 2025 | // <id> dmac_evoe_8 |
| 2026 | #ifndef CONF_DMAC_EVOE_8 |
| 2027 | #define CONF_DMAC_EVOE_8 0 |
| 2028 | #endif |
| 2029 | |
| 2030 | // <q> Channel Event Input |
| 2031 | // <i> Indicates whether channel event reception is enabled or not |
| 2032 | // <id> dmac_evie_8 |
| 2033 | #ifndef CONF_DMAC_EVIE_8 |
| 2034 | #define CONF_DMAC_EVIE_8 0 |
| 2035 | #endif |
| 2036 | |
| 2037 | // <o> Event Input Action |
| 2038 | // <0=> No action |
| 2039 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 2040 | // <2=> Conditional transfer trigger |
| 2041 | // <3=> Conditional block transfer |
| 2042 | // <4=> Channel suspend operation |
| 2043 | // <5=> Channel resume operation |
| 2044 | // <6=> Skip next block suspend action |
| 2045 | // <i> Defines the event input action |
| 2046 | // <id> dmac_evact_8 |
| 2047 | #ifndef CONF_DMAC_EVACT_8 |
| 2048 | #define CONF_DMAC_EVACT_8 0 |
| 2049 | #endif |
| 2050 | |
| 2051 | // <o> Address Increment Step Size |
| 2052 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 2053 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 2054 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 2055 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 2056 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 2057 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 2058 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 2059 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 2060 | // <i> Defines the address increment step size, applies to source or destination address |
| 2061 | // <id> dmac_stepsize_8 |
| 2062 | #ifndef CONF_DMAC_STEPSIZE_8 |
| 2063 | #define CONF_DMAC_STEPSIZE_8 0 |
| 2064 | #endif |
| 2065 | |
| 2066 | // <o> Step Selection |
| 2067 | // <0=> Step size settings apply to the destination address |
| 2068 | // <1=> Step size settings apply to the source address |
| 2069 | // <i> Defines whether source or destination addresses are using the step size settings |
| 2070 | // <id> dmac_stepsel_8 |
| 2071 | #ifndef CONF_DMAC_STEPSEL_8 |
| 2072 | #define CONF_DMAC_STEPSEL_8 0 |
| 2073 | #endif |
| 2074 | |
| 2075 | // <q> Source Address Increment |
| 2076 | // <i> Indicates whether the source address incrementation is enabled or not |
| 2077 | // <id> dmac_srcinc_8 |
| 2078 | #ifndef CONF_DMAC_SRCINC_8 |
| 2079 | #define CONF_DMAC_SRCINC_8 0 |
| 2080 | #endif |
| 2081 | |
| 2082 | // <q> Destination Address Increment |
| 2083 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 2084 | // <id> dmac_dstinc_8 |
| 2085 | #ifndef CONF_DMAC_DSTINC_8 |
| 2086 | #define CONF_DMAC_DSTINC_8 0 |
| 2087 | #endif |
| 2088 | |
| 2089 | // <o> Beat Size |
| 2090 | // <0=> 8-bit bus transfer |
| 2091 | // <1=> 16-bit bus transfer |
| 2092 | // <2=> 32-bit bus transfer |
| 2093 | // <i> Defines the size of one beat |
| 2094 | // <id> dmac_beatsize_8 |
| 2095 | #ifndef CONF_DMAC_BEATSIZE_8 |
| 2096 | #define CONF_DMAC_BEATSIZE_8 0 |
| 2097 | #endif |
| 2098 | |
| 2099 | // <o> Block Action |
| 2100 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 2101 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 2102 | // <2=> Channel suspend operation is complete |
| 2103 | // <3=> Both channel suspend operation and block interrupt |
| 2104 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 2105 | // <id> dmac_blockact_8 |
| 2106 | #ifndef CONF_DMAC_BLOCKACT_8 |
| 2107 | #define CONF_DMAC_BLOCKACT_8 0 |
| 2108 | #endif |
| 2109 | |
| 2110 | // <o> Event Output Selection |
| 2111 | // <0=> Event generation disabled |
| 2112 | // <1=> Event strobe when block transfer complete |
| 2113 | // <3=> Event strobe when beat transfer complete |
| 2114 | // <i> Defines the event output selection |
| 2115 | // <id> dmac_evosel_8 |
| 2116 | #ifndef CONF_DMAC_EVOSEL_8 |
| 2117 | #define CONF_DMAC_EVOSEL_8 0 |
| 2118 | #endif |
| 2119 | // </e> |
| 2120 | |
| 2121 | // <e> Channel 9 settings |
| 2122 | // <id> dmac_channel_9_settings |
| 2123 | #ifndef CONF_DMAC_CHANNEL_9_SETTINGS |
| 2124 | #define CONF_DMAC_CHANNEL_9_SETTINGS 0 |
| 2125 | #endif |
| 2126 | |
| 2127 | // <q> Channel Run in Standby |
| 2128 | // <i> Indicates whether channel 9 is running in standby mode or not |
| 2129 | // <id> dmac_runstdby_9 |
| 2130 | #ifndef CONF_DMAC_RUNSTDBY_9 |
| 2131 | #define CONF_DMAC_RUNSTDBY_9 0 |
| 2132 | #endif |
| 2133 | |
| 2134 | // <o> Trigger action |
| 2135 | // <0=> One trigger required for each block transfer |
| 2136 | // <2=> One trigger required for each beat transfer |
| 2137 | // <3=> One trigger required for each transaction |
| 2138 | // <i> Defines the trigger action used for a transfer |
| 2139 | // <id> dmac_trigact_9 |
| 2140 | #ifndef CONF_DMAC_TRIGACT_9 |
| 2141 | #define CONF_DMAC_TRIGACT_9 0 |
| 2142 | #endif |
| 2143 | |
| 2144 | // <o> Trigger source |
| 2145 | // <0x00=> Only software/event triggers |
| 2146 | // <0x01=> RTC Time Stamp Trigger |
| 2147 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 2148 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 2149 | // <0x04=> SERCOM0 RX Trigger |
| 2150 | // <0x05=> SERCOM0 TX Trigger |
| 2151 | // <0x06=> SERCOM1 RX Trigger |
| 2152 | // <0x07=> SERCOM1 TX Trigger |
| 2153 | // <0x08=> SERCOM2 RX Trigger |
| 2154 | // <0x09=> SERCOM2 TX Trigger |
| 2155 | // <0x0A=> SERCOM3 RX Trigger |
| 2156 | // <0x0B=> SERCOM3 TX Trigger |
| 2157 | // <0x0C=> SERCOM4 RX Trigger |
| 2158 | // <0x0D=> SERCOM4 TX Trigger |
| 2159 | // <0x0E=> SERCOM5 RX Trigger |
| 2160 | // <0x0F=> SERCOM5 TX Trigger |
| 2161 | // <0x10=> SERCOM6 RX Trigger |
| 2162 | // <0x11=> SERCOM6 TX Trigger |
| 2163 | // <0x12=> SERCOM7 RX Trigger |
| 2164 | // <0x13=> SERCOM7 TX Trigger |
| 2165 | // <0x14=> CAN0 DEBUG Trigger |
| 2166 | // <0x15=> CAN1 DEBUG Trigger |
| 2167 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 2168 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 2169 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 2170 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 2171 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 2172 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 2173 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 2174 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 2175 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 2176 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 2177 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 2178 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 2179 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 2180 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 2181 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 2182 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 2183 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 2184 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 2185 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 2186 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 2187 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 2188 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 2189 | // <0x2C=> TC0 Overflow Trigger |
| 2190 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 2191 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 2192 | // <0x2F=> TC1 Overflow Trigger |
| 2193 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 2194 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 2195 | // <0x32=> TC2 Overflow Trigger |
| 2196 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 2197 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 2198 | // <0x35=> TC3 Overflow Trigger |
| 2199 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 2200 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 2201 | // <0x38=> TC4 Overflow Trigger |
| 2202 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 2203 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 2204 | // <0x3B=> TC5 Overflow Trigger |
| 2205 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 2206 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 2207 | // <0x3E=> TC6 Overflow Trigger |
| 2208 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 2209 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 2210 | // <0x41=> TC7 Overflow Trigger |
| 2211 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 2212 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 2213 | // <0x44=> ADC0 Result Ready Trigger |
| 2214 | // <0x45=> ADC0 Sequencing Trigger |
| 2215 | // <0x46=> ADC1 Result Ready Trigger |
| 2216 | // <0x47=> ADC1 Sequencing Trigger |
| 2217 | // <0x48=> DAC Empty 0 Trigger |
| 2218 | // <0x49=> DAC Empty 1 Trigger |
| 2219 | // <0x4A=> DAC Result Ready 0 Trigger |
| 2220 | // <0x4B=> DAC Result Ready 1 Trigger |
| 2221 | // <0x4C=> I2S Rx 0 Trigger |
| 2222 | // <0x4D=> I2S Rx 1 Trigger |
| 2223 | // <0x4E=> I2S Tx 0 Trigger |
| 2224 | // <0x4F=> I2S Tx 1 Trigger |
| 2225 | // <0x50=> PCC RX Trigger |
| 2226 | // <0x51=> AES Write Trigger |
| 2227 | // <0x52=> AES Read Trigger |
| 2228 | // <0x53=> QSPI Rx Trigger |
| 2229 | // <0x54=> QSPI Tx Trigger |
| 2230 | // <i> Defines the peripheral trigger which is source of the transfer |
| 2231 | // <id> dmac_trifsrc_9 |
| 2232 | #ifndef CONF_DMAC_TRIGSRC_9 |
| 2233 | #define CONF_DMAC_TRIGSRC_9 0 |
| 2234 | #endif |
| 2235 | |
| 2236 | // <o> Channel Arbitration Level |
| 2237 | // <0=> Channel priority 0 |
| 2238 | // <1=> Channel priority 1 |
| 2239 | // <2=> Channel priority 2 |
| 2240 | // <3=> Channel priority 3 |
| 2241 | // <i> Defines the arbitration level for this channel |
| 2242 | // <id> dmac_lvl_9 |
| 2243 | #ifndef CONF_DMAC_LVL_9 |
| 2244 | #define CONF_DMAC_LVL_9 0 |
| 2245 | #endif |
| 2246 | |
| 2247 | // <q> Channel Event Output |
| 2248 | // <i> Indicates whether channel event generation is enabled or not |
| 2249 | // <id> dmac_evoe_9 |
| 2250 | #ifndef CONF_DMAC_EVOE_9 |
| 2251 | #define CONF_DMAC_EVOE_9 0 |
| 2252 | #endif |
| 2253 | |
| 2254 | // <q> Channel Event Input |
| 2255 | // <i> Indicates whether channel event reception is enabled or not |
| 2256 | // <id> dmac_evie_9 |
| 2257 | #ifndef CONF_DMAC_EVIE_9 |
| 2258 | #define CONF_DMAC_EVIE_9 0 |
| 2259 | #endif |
| 2260 | |
| 2261 | // <o> Event Input Action |
| 2262 | // <0=> No action |
| 2263 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 2264 | // <2=> Conditional transfer trigger |
| 2265 | // <3=> Conditional block transfer |
| 2266 | // <4=> Channel suspend operation |
| 2267 | // <5=> Channel resume operation |
| 2268 | // <6=> Skip next block suspend action |
| 2269 | // <i> Defines the event input action |
| 2270 | // <id> dmac_evact_9 |
| 2271 | #ifndef CONF_DMAC_EVACT_9 |
| 2272 | #define CONF_DMAC_EVACT_9 0 |
| 2273 | #endif |
| 2274 | |
| 2275 | // <o> Address Increment Step Size |
| 2276 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 2277 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 2278 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 2279 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 2280 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 2281 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 2282 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 2283 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 2284 | // <i> Defines the address increment step size, applies to source or destination address |
| 2285 | // <id> dmac_stepsize_9 |
| 2286 | #ifndef CONF_DMAC_STEPSIZE_9 |
| 2287 | #define CONF_DMAC_STEPSIZE_9 0 |
| 2288 | #endif |
| 2289 | |
| 2290 | // <o> Step Selection |
| 2291 | // <0=> Step size settings apply to the destination address |
| 2292 | // <1=> Step size settings apply to the source address |
| 2293 | // <i> Defines whether source or destination addresses are using the step size settings |
| 2294 | // <id> dmac_stepsel_9 |
| 2295 | #ifndef CONF_DMAC_STEPSEL_9 |
| 2296 | #define CONF_DMAC_STEPSEL_9 0 |
| 2297 | #endif |
| 2298 | |
| 2299 | // <q> Source Address Increment |
| 2300 | // <i> Indicates whether the source address incrementation is enabled or not |
| 2301 | // <id> dmac_srcinc_9 |
| 2302 | #ifndef CONF_DMAC_SRCINC_9 |
| 2303 | #define CONF_DMAC_SRCINC_9 0 |
| 2304 | #endif |
| 2305 | |
| 2306 | // <q> Destination Address Increment |
| 2307 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 2308 | // <id> dmac_dstinc_9 |
| 2309 | #ifndef CONF_DMAC_DSTINC_9 |
| 2310 | #define CONF_DMAC_DSTINC_9 0 |
| 2311 | #endif |
| 2312 | |
| 2313 | // <o> Beat Size |
| 2314 | // <0=> 8-bit bus transfer |
| 2315 | // <1=> 16-bit bus transfer |
| 2316 | // <2=> 32-bit bus transfer |
| 2317 | // <i> Defines the size of one beat |
| 2318 | // <id> dmac_beatsize_9 |
| 2319 | #ifndef CONF_DMAC_BEATSIZE_9 |
| 2320 | #define CONF_DMAC_BEATSIZE_9 0 |
| 2321 | #endif |
| 2322 | |
| 2323 | // <o> Block Action |
| 2324 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 2325 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 2326 | // <2=> Channel suspend operation is complete |
| 2327 | // <3=> Both channel suspend operation and block interrupt |
| 2328 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 2329 | // <id> dmac_blockact_9 |
| 2330 | #ifndef CONF_DMAC_BLOCKACT_9 |
| 2331 | #define CONF_DMAC_BLOCKACT_9 0 |
| 2332 | #endif |
| 2333 | |
| 2334 | // <o> Event Output Selection |
| 2335 | // <0=> Event generation disabled |
| 2336 | // <1=> Event strobe when block transfer complete |
| 2337 | // <3=> Event strobe when beat transfer complete |
| 2338 | // <i> Defines the event output selection |
| 2339 | // <id> dmac_evosel_9 |
| 2340 | #ifndef CONF_DMAC_EVOSEL_9 |
| 2341 | #define CONF_DMAC_EVOSEL_9 0 |
| 2342 | #endif |
| 2343 | // </e> |
| 2344 | |
| 2345 | // <e> Channel 10 settings |
| 2346 | // <id> dmac_channel_10_settings |
| 2347 | #ifndef CONF_DMAC_CHANNEL_10_SETTINGS |
| 2348 | #define CONF_DMAC_CHANNEL_10_SETTINGS 0 |
| 2349 | #endif |
| 2350 | |
| 2351 | // <q> Channel Run in Standby |
| 2352 | // <i> Indicates whether channel 10 is running in standby mode or not |
| 2353 | // <id> dmac_runstdby_10 |
| 2354 | #ifndef CONF_DMAC_RUNSTDBY_10 |
| 2355 | #define CONF_DMAC_RUNSTDBY_10 0 |
| 2356 | #endif |
| 2357 | |
| 2358 | // <o> Trigger action |
| 2359 | // <0=> One trigger required for each block transfer |
| 2360 | // <2=> One trigger required for each beat transfer |
| 2361 | // <3=> One trigger required for each transaction |
| 2362 | // <i> Defines the trigger action used for a transfer |
| 2363 | // <id> dmac_trigact_10 |
| 2364 | #ifndef CONF_DMAC_TRIGACT_10 |
| 2365 | #define CONF_DMAC_TRIGACT_10 0 |
| 2366 | #endif |
| 2367 | |
| 2368 | // <o> Trigger source |
| 2369 | // <0x00=> Only software/event triggers |
| 2370 | // <0x01=> RTC Time Stamp Trigger |
| 2371 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 2372 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 2373 | // <0x04=> SERCOM0 RX Trigger |
| 2374 | // <0x05=> SERCOM0 TX Trigger |
| 2375 | // <0x06=> SERCOM1 RX Trigger |
| 2376 | // <0x07=> SERCOM1 TX Trigger |
| 2377 | // <0x08=> SERCOM2 RX Trigger |
| 2378 | // <0x09=> SERCOM2 TX Trigger |
| 2379 | // <0x0A=> SERCOM3 RX Trigger |
| 2380 | // <0x0B=> SERCOM3 TX Trigger |
| 2381 | // <0x0C=> SERCOM4 RX Trigger |
| 2382 | // <0x0D=> SERCOM4 TX Trigger |
| 2383 | // <0x0E=> SERCOM5 RX Trigger |
| 2384 | // <0x0F=> SERCOM5 TX Trigger |
| 2385 | // <0x10=> SERCOM6 RX Trigger |
| 2386 | // <0x11=> SERCOM6 TX Trigger |
| 2387 | // <0x12=> SERCOM7 RX Trigger |
| 2388 | // <0x13=> SERCOM7 TX Trigger |
| 2389 | // <0x14=> CAN0 DEBUG Trigger |
| 2390 | // <0x15=> CAN1 DEBUG Trigger |
| 2391 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 2392 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 2393 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 2394 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 2395 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 2396 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 2397 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 2398 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 2399 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 2400 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 2401 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 2402 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 2403 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 2404 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 2405 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 2406 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 2407 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 2408 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 2409 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 2410 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 2411 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 2412 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 2413 | // <0x2C=> TC0 Overflow Trigger |
| 2414 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 2415 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 2416 | // <0x2F=> TC1 Overflow Trigger |
| 2417 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 2418 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 2419 | // <0x32=> TC2 Overflow Trigger |
| 2420 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 2421 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 2422 | // <0x35=> TC3 Overflow Trigger |
| 2423 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 2424 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 2425 | // <0x38=> TC4 Overflow Trigger |
| 2426 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 2427 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 2428 | // <0x3B=> TC5 Overflow Trigger |
| 2429 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 2430 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 2431 | // <0x3E=> TC6 Overflow Trigger |
| 2432 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 2433 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 2434 | // <0x41=> TC7 Overflow Trigger |
| 2435 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 2436 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 2437 | // <0x44=> ADC0 Result Ready Trigger |
| 2438 | // <0x45=> ADC0 Sequencing Trigger |
| 2439 | // <0x46=> ADC1 Result Ready Trigger |
| 2440 | // <0x47=> ADC1 Sequencing Trigger |
| 2441 | // <0x48=> DAC Empty 0 Trigger |
| 2442 | // <0x49=> DAC Empty 1 Trigger |
| 2443 | // <0x4A=> DAC Result Ready 0 Trigger |
| 2444 | // <0x4B=> DAC Result Ready 1 Trigger |
| 2445 | // <0x4C=> I2S Rx 0 Trigger |
| 2446 | // <0x4D=> I2S Rx 1 Trigger |
| 2447 | // <0x4E=> I2S Tx 0 Trigger |
| 2448 | // <0x4F=> I2S Tx 1 Trigger |
| 2449 | // <0x50=> PCC RX Trigger |
| 2450 | // <0x51=> AES Write Trigger |
| 2451 | // <0x52=> AES Read Trigger |
| 2452 | // <0x53=> QSPI Rx Trigger |
| 2453 | // <0x54=> QSPI Tx Trigger |
| 2454 | // <i> Defines the peripheral trigger which is source of the transfer |
| 2455 | // <id> dmac_trifsrc_10 |
| 2456 | #ifndef CONF_DMAC_TRIGSRC_10 |
| 2457 | #define CONF_DMAC_TRIGSRC_10 0 |
| 2458 | #endif |
| 2459 | |
| 2460 | // <o> Channel Arbitration Level |
| 2461 | // <0=> Channel priority 0 |
| 2462 | // <1=> Channel priority 1 |
| 2463 | // <2=> Channel priority 2 |
| 2464 | // <3=> Channel priority 3 |
| 2465 | // <i> Defines the arbitration level for this channel |
| 2466 | // <id> dmac_lvl_10 |
| 2467 | #ifndef CONF_DMAC_LVL_10 |
| 2468 | #define CONF_DMAC_LVL_10 0 |
| 2469 | #endif |
| 2470 | |
| 2471 | // <q> Channel Event Output |
| 2472 | // <i> Indicates whether channel event generation is enabled or not |
| 2473 | // <id> dmac_evoe_10 |
| 2474 | #ifndef CONF_DMAC_EVOE_10 |
| 2475 | #define CONF_DMAC_EVOE_10 0 |
| 2476 | #endif |
| 2477 | |
| 2478 | // <q> Channel Event Input |
| 2479 | // <i> Indicates whether channel event reception is enabled or not |
| 2480 | // <id> dmac_evie_10 |
| 2481 | #ifndef CONF_DMAC_EVIE_10 |
| 2482 | #define CONF_DMAC_EVIE_10 0 |
| 2483 | #endif |
| 2484 | |
| 2485 | // <o> Event Input Action |
| 2486 | // <0=> No action |
| 2487 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 2488 | // <2=> Conditional transfer trigger |
| 2489 | // <3=> Conditional block transfer |
| 2490 | // <4=> Channel suspend operation |
| 2491 | // <5=> Channel resume operation |
| 2492 | // <6=> Skip next block suspend action |
| 2493 | // <i> Defines the event input action |
| 2494 | // <id> dmac_evact_10 |
| 2495 | #ifndef CONF_DMAC_EVACT_10 |
| 2496 | #define CONF_DMAC_EVACT_10 0 |
| 2497 | #endif |
| 2498 | |
| 2499 | // <o> Address Increment Step Size |
| 2500 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 2501 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 2502 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 2503 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 2504 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 2505 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 2506 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 2507 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 2508 | // <i> Defines the address increment step size, applies to source or destination address |
| 2509 | // <id> dmac_stepsize_10 |
| 2510 | #ifndef CONF_DMAC_STEPSIZE_10 |
| 2511 | #define CONF_DMAC_STEPSIZE_10 0 |
| 2512 | #endif |
| 2513 | |
| 2514 | // <o> Step Selection |
| 2515 | // <0=> Step size settings apply to the destination address |
| 2516 | // <1=> Step size settings apply to the source address |
| 2517 | // <i> Defines whether source or destination addresses are using the step size settings |
| 2518 | // <id> dmac_stepsel_10 |
| 2519 | #ifndef CONF_DMAC_STEPSEL_10 |
| 2520 | #define CONF_DMAC_STEPSEL_10 0 |
| 2521 | #endif |
| 2522 | |
| 2523 | // <q> Source Address Increment |
| 2524 | // <i> Indicates whether the source address incrementation is enabled or not |
| 2525 | // <id> dmac_srcinc_10 |
| 2526 | #ifndef CONF_DMAC_SRCINC_10 |
| 2527 | #define CONF_DMAC_SRCINC_10 0 |
| 2528 | #endif |
| 2529 | |
| 2530 | // <q> Destination Address Increment |
| 2531 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 2532 | // <id> dmac_dstinc_10 |
| 2533 | #ifndef CONF_DMAC_DSTINC_10 |
| 2534 | #define CONF_DMAC_DSTINC_10 0 |
| 2535 | #endif |
| 2536 | |
| 2537 | // <o> Beat Size |
| 2538 | // <0=> 8-bit bus transfer |
| 2539 | // <1=> 16-bit bus transfer |
| 2540 | // <2=> 32-bit bus transfer |
| 2541 | // <i> Defines the size of one beat |
| 2542 | // <id> dmac_beatsize_10 |
| 2543 | #ifndef CONF_DMAC_BEATSIZE_10 |
| 2544 | #define CONF_DMAC_BEATSIZE_10 0 |
| 2545 | #endif |
| 2546 | |
| 2547 | // <o> Block Action |
| 2548 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 2549 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 2550 | // <2=> Channel suspend operation is complete |
| 2551 | // <3=> Both channel suspend operation and block interrupt |
| 2552 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 2553 | // <id> dmac_blockact_10 |
| 2554 | #ifndef CONF_DMAC_BLOCKACT_10 |
| 2555 | #define CONF_DMAC_BLOCKACT_10 0 |
| 2556 | #endif |
| 2557 | |
| 2558 | // <o> Event Output Selection |
| 2559 | // <0=> Event generation disabled |
| 2560 | // <1=> Event strobe when block transfer complete |
| 2561 | // <3=> Event strobe when beat transfer complete |
| 2562 | // <i> Defines the event output selection |
| 2563 | // <id> dmac_evosel_10 |
| 2564 | #ifndef CONF_DMAC_EVOSEL_10 |
| 2565 | #define CONF_DMAC_EVOSEL_10 0 |
| 2566 | #endif |
| 2567 | // </e> |
| 2568 | |
| 2569 | // <e> Channel 11 settings |
| 2570 | // <id> dmac_channel_11_settings |
| 2571 | #ifndef CONF_DMAC_CHANNEL_11_SETTINGS |
| 2572 | #define CONF_DMAC_CHANNEL_11_SETTINGS 0 |
| 2573 | #endif |
| 2574 | |
| 2575 | // <q> Channel Run in Standby |
| 2576 | // <i> Indicates whether channel 11 is running in standby mode or not |
| 2577 | // <id> dmac_runstdby_11 |
| 2578 | #ifndef CONF_DMAC_RUNSTDBY_11 |
| 2579 | #define CONF_DMAC_RUNSTDBY_11 0 |
| 2580 | #endif |
| 2581 | |
| 2582 | // <o> Trigger action |
| 2583 | // <0=> One trigger required for each block transfer |
| 2584 | // <2=> One trigger required for each beat transfer |
| 2585 | // <3=> One trigger required for each transaction |
| 2586 | // <i> Defines the trigger action used for a transfer |
| 2587 | // <id> dmac_trigact_11 |
| 2588 | #ifndef CONF_DMAC_TRIGACT_11 |
| 2589 | #define CONF_DMAC_TRIGACT_11 0 |
| 2590 | #endif |
| 2591 | |
| 2592 | // <o> Trigger source |
| 2593 | // <0x00=> Only software/event triggers |
| 2594 | // <0x01=> RTC Time Stamp Trigger |
| 2595 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 2596 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 2597 | // <0x04=> SERCOM0 RX Trigger |
| 2598 | // <0x05=> SERCOM0 TX Trigger |
| 2599 | // <0x06=> SERCOM1 RX Trigger |
| 2600 | // <0x07=> SERCOM1 TX Trigger |
| 2601 | // <0x08=> SERCOM2 RX Trigger |
| 2602 | // <0x09=> SERCOM2 TX Trigger |
| 2603 | // <0x0A=> SERCOM3 RX Trigger |
| 2604 | // <0x0B=> SERCOM3 TX Trigger |
| 2605 | // <0x0C=> SERCOM4 RX Trigger |
| 2606 | // <0x0D=> SERCOM4 TX Trigger |
| 2607 | // <0x0E=> SERCOM5 RX Trigger |
| 2608 | // <0x0F=> SERCOM5 TX Trigger |
| 2609 | // <0x10=> SERCOM6 RX Trigger |
| 2610 | // <0x11=> SERCOM6 TX Trigger |
| 2611 | // <0x12=> SERCOM7 RX Trigger |
| 2612 | // <0x13=> SERCOM7 TX Trigger |
| 2613 | // <0x14=> CAN0 DEBUG Trigger |
| 2614 | // <0x15=> CAN1 DEBUG Trigger |
| 2615 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 2616 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 2617 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 2618 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 2619 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 2620 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 2621 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 2622 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 2623 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 2624 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 2625 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 2626 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 2627 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 2628 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 2629 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 2630 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 2631 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 2632 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 2633 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 2634 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 2635 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 2636 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 2637 | // <0x2C=> TC0 Overflow Trigger |
| 2638 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 2639 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 2640 | // <0x2F=> TC1 Overflow Trigger |
| 2641 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 2642 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 2643 | // <0x32=> TC2 Overflow Trigger |
| 2644 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 2645 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 2646 | // <0x35=> TC3 Overflow Trigger |
| 2647 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 2648 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 2649 | // <0x38=> TC4 Overflow Trigger |
| 2650 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 2651 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 2652 | // <0x3B=> TC5 Overflow Trigger |
| 2653 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 2654 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 2655 | // <0x3E=> TC6 Overflow Trigger |
| 2656 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 2657 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 2658 | // <0x41=> TC7 Overflow Trigger |
| 2659 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 2660 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 2661 | // <0x44=> ADC0 Result Ready Trigger |
| 2662 | // <0x45=> ADC0 Sequencing Trigger |
| 2663 | // <0x46=> ADC1 Result Ready Trigger |
| 2664 | // <0x47=> ADC1 Sequencing Trigger |
| 2665 | // <0x48=> DAC Empty 0 Trigger |
| 2666 | // <0x49=> DAC Empty 1 Trigger |
| 2667 | // <0x4A=> DAC Result Ready 0 Trigger |
| 2668 | // <0x4B=> DAC Result Ready 1 Trigger |
| 2669 | // <0x4C=> I2S Rx 0 Trigger |
| 2670 | // <0x4D=> I2S Rx 1 Trigger |
| 2671 | // <0x4E=> I2S Tx 0 Trigger |
| 2672 | // <0x4F=> I2S Tx 1 Trigger |
| 2673 | // <0x50=> PCC RX Trigger |
| 2674 | // <0x51=> AES Write Trigger |
| 2675 | // <0x52=> AES Read Trigger |
| 2676 | // <0x53=> QSPI Rx Trigger |
| 2677 | // <0x54=> QSPI Tx Trigger |
| 2678 | // <i> Defines the peripheral trigger which is source of the transfer |
| 2679 | // <id> dmac_trifsrc_11 |
| 2680 | #ifndef CONF_DMAC_TRIGSRC_11 |
| 2681 | #define CONF_DMAC_TRIGSRC_11 0 |
| 2682 | #endif |
| 2683 | |
| 2684 | // <o> Channel Arbitration Level |
| 2685 | // <0=> Channel priority 0 |
| 2686 | // <1=> Channel priority 1 |
| 2687 | // <2=> Channel priority 2 |
| 2688 | // <3=> Channel priority 3 |
| 2689 | // <i> Defines the arbitration level for this channel |
| 2690 | // <id> dmac_lvl_11 |
| 2691 | #ifndef CONF_DMAC_LVL_11 |
| 2692 | #define CONF_DMAC_LVL_11 0 |
| 2693 | #endif |
| 2694 | |
| 2695 | // <q> Channel Event Output |
| 2696 | // <i> Indicates whether channel event generation is enabled or not |
| 2697 | // <id> dmac_evoe_11 |
| 2698 | #ifndef CONF_DMAC_EVOE_11 |
| 2699 | #define CONF_DMAC_EVOE_11 0 |
| 2700 | #endif |
| 2701 | |
| 2702 | // <q> Channel Event Input |
| 2703 | // <i> Indicates whether channel event reception is enabled or not |
| 2704 | // <id> dmac_evie_11 |
| 2705 | #ifndef CONF_DMAC_EVIE_11 |
| 2706 | #define CONF_DMAC_EVIE_11 0 |
| 2707 | #endif |
| 2708 | |
| 2709 | // <o> Event Input Action |
| 2710 | // <0=> No action |
| 2711 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 2712 | // <2=> Conditional transfer trigger |
| 2713 | // <3=> Conditional block transfer |
| 2714 | // <4=> Channel suspend operation |
| 2715 | // <5=> Channel resume operation |
| 2716 | // <6=> Skip next block suspend action |
| 2717 | // <i> Defines the event input action |
| 2718 | // <id> dmac_evact_11 |
| 2719 | #ifndef CONF_DMAC_EVACT_11 |
| 2720 | #define CONF_DMAC_EVACT_11 0 |
| 2721 | #endif |
| 2722 | |
| 2723 | // <o> Address Increment Step Size |
| 2724 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 2725 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 2726 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 2727 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 2728 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 2729 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 2730 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 2731 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 2732 | // <i> Defines the address increment step size, applies to source or destination address |
| 2733 | // <id> dmac_stepsize_11 |
| 2734 | #ifndef CONF_DMAC_STEPSIZE_11 |
| 2735 | #define CONF_DMAC_STEPSIZE_11 0 |
| 2736 | #endif |
| 2737 | |
| 2738 | // <o> Step Selection |
| 2739 | // <0=> Step size settings apply to the destination address |
| 2740 | // <1=> Step size settings apply to the source address |
| 2741 | // <i> Defines whether source or destination addresses are using the step size settings |
| 2742 | // <id> dmac_stepsel_11 |
| 2743 | #ifndef CONF_DMAC_STEPSEL_11 |
| 2744 | #define CONF_DMAC_STEPSEL_11 0 |
| 2745 | #endif |
| 2746 | |
| 2747 | // <q> Source Address Increment |
| 2748 | // <i> Indicates whether the source address incrementation is enabled or not |
| 2749 | // <id> dmac_srcinc_11 |
| 2750 | #ifndef CONF_DMAC_SRCINC_11 |
| 2751 | #define CONF_DMAC_SRCINC_11 0 |
| 2752 | #endif |
| 2753 | |
| 2754 | // <q> Destination Address Increment |
| 2755 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 2756 | // <id> dmac_dstinc_11 |
| 2757 | #ifndef CONF_DMAC_DSTINC_11 |
| 2758 | #define CONF_DMAC_DSTINC_11 0 |
| 2759 | #endif |
| 2760 | |
| 2761 | // <o> Beat Size |
| 2762 | // <0=> 8-bit bus transfer |
| 2763 | // <1=> 16-bit bus transfer |
| 2764 | // <2=> 32-bit bus transfer |
| 2765 | // <i> Defines the size of one beat |
| 2766 | // <id> dmac_beatsize_11 |
| 2767 | #ifndef CONF_DMAC_BEATSIZE_11 |
| 2768 | #define CONF_DMAC_BEATSIZE_11 0 |
| 2769 | #endif |
| 2770 | |
| 2771 | // <o> Block Action |
| 2772 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 2773 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 2774 | // <2=> Channel suspend operation is complete |
| 2775 | // <3=> Both channel suspend operation and block interrupt |
| 2776 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 2777 | // <id> dmac_blockact_11 |
| 2778 | #ifndef CONF_DMAC_BLOCKACT_11 |
| 2779 | #define CONF_DMAC_BLOCKACT_11 0 |
| 2780 | #endif |
| 2781 | |
| 2782 | // <o> Event Output Selection |
| 2783 | // <0=> Event generation disabled |
| 2784 | // <1=> Event strobe when block transfer complete |
| 2785 | // <3=> Event strobe when beat transfer complete |
| 2786 | // <i> Defines the event output selection |
| 2787 | // <id> dmac_evosel_11 |
| 2788 | #ifndef CONF_DMAC_EVOSEL_11 |
| 2789 | #define CONF_DMAC_EVOSEL_11 0 |
| 2790 | #endif |
| 2791 | // </e> |
| 2792 | |
| 2793 | // <e> Channel 12 settings |
| 2794 | // <id> dmac_channel_12_settings |
| 2795 | #ifndef CONF_DMAC_CHANNEL_12_SETTINGS |
| 2796 | #define CONF_DMAC_CHANNEL_12_SETTINGS 0 |
| 2797 | #endif |
| 2798 | |
| 2799 | // <q> Channel Run in Standby |
| 2800 | // <i> Indicates whether channel 12 is running in standby mode or not |
| 2801 | // <id> dmac_runstdby_12 |
| 2802 | #ifndef CONF_DMAC_RUNSTDBY_12 |
| 2803 | #define CONF_DMAC_RUNSTDBY_12 0 |
| 2804 | #endif |
| 2805 | |
| 2806 | // <o> Trigger action |
| 2807 | // <0=> One trigger required for each block transfer |
| 2808 | // <2=> One trigger required for each beat transfer |
| 2809 | // <3=> One trigger required for each transaction |
| 2810 | // <i> Defines the trigger action used for a transfer |
| 2811 | // <id> dmac_trigact_12 |
| 2812 | #ifndef CONF_DMAC_TRIGACT_12 |
| 2813 | #define CONF_DMAC_TRIGACT_12 0 |
| 2814 | #endif |
| 2815 | |
| 2816 | // <o> Trigger source |
| 2817 | // <0x00=> Only software/event triggers |
| 2818 | // <0x01=> RTC Time Stamp Trigger |
| 2819 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 2820 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 2821 | // <0x04=> SERCOM0 RX Trigger |
| 2822 | // <0x05=> SERCOM0 TX Trigger |
| 2823 | // <0x06=> SERCOM1 RX Trigger |
| 2824 | // <0x07=> SERCOM1 TX Trigger |
| 2825 | // <0x08=> SERCOM2 RX Trigger |
| 2826 | // <0x09=> SERCOM2 TX Trigger |
| 2827 | // <0x0A=> SERCOM3 RX Trigger |
| 2828 | // <0x0B=> SERCOM3 TX Trigger |
| 2829 | // <0x0C=> SERCOM4 RX Trigger |
| 2830 | // <0x0D=> SERCOM4 TX Trigger |
| 2831 | // <0x0E=> SERCOM5 RX Trigger |
| 2832 | // <0x0F=> SERCOM5 TX Trigger |
| 2833 | // <0x10=> SERCOM6 RX Trigger |
| 2834 | // <0x11=> SERCOM6 TX Trigger |
| 2835 | // <0x12=> SERCOM7 RX Trigger |
| 2836 | // <0x13=> SERCOM7 TX Trigger |
| 2837 | // <0x14=> CAN0 DEBUG Trigger |
| 2838 | // <0x15=> CAN1 DEBUG Trigger |
| 2839 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 2840 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 2841 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 2842 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 2843 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 2844 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 2845 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 2846 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 2847 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 2848 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 2849 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 2850 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 2851 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 2852 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 2853 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 2854 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 2855 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 2856 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 2857 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 2858 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 2859 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 2860 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 2861 | // <0x2C=> TC0 Overflow Trigger |
| 2862 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 2863 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 2864 | // <0x2F=> TC1 Overflow Trigger |
| 2865 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 2866 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 2867 | // <0x32=> TC2 Overflow Trigger |
| 2868 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 2869 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 2870 | // <0x35=> TC3 Overflow Trigger |
| 2871 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 2872 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 2873 | // <0x38=> TC4 Overflow Trigger |
| 2874 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 2875 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 2876 | // <0x3B=> TC5 Overflow Trigger |
| 2877 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 2878 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 2879 | // <0x3E=> TC6 Overflow Trigger |
| 2880 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 2881 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 2882 | // <0x41=> TC7 Overflow Trigger |
| 2883 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 2884 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 2885 | // <0x44=> ADC0 Result Ready Trigger |
| 2886 | // <0x45=> ADC0 Sequencing Trigger |
| 2887 | // <0x46=> ADC1 Result Ready Trigger |
| 2888 | // <0x47=> ADC1 Sequencing Trigger |
| 2889 | // <0x48=> DAC Empty 0 Trigger |
| 2890 | // <0x49=> DAC Empty 1 Trigger |
| 2891 | // <0x4A=> DAC Result Ready 0 Trigger |
| 2892 | // <0x4B=> DAC Result Ready 1 Trigger |
| 2893 | // <0x4C=> I2S Rx 0 Trigger |
| 2894 | // <0x4D=> I2S Rx 1 Trigger |
| 2895 | // <0x4E=> I2S Tx 0 Trigger |
| 2896 | // <0x4F=> I2S Tx 1 Trigger |
| 2897 | // <0x50=> PCC RX Trigger |
| 2898 | // <0x51=> AES Write Trigger |
| 2899 | // <0x52=> AES Read Trigger |
| 2900 | // <0x53=> QSPI Rx Trigger |
| 2901 | // <0x54=> QSPI Tx Trigger |
| 2902 | // <i> Defines the peripheral trigger which is source of the transfer |
| 2903 | // <id> dmac_trifsrc_12 |
| 2904 | #ifndef CONF_DMAC_TRIGSRC_12 |
| 2905 | #define CONF_DMAC_TRIGSRC_12 0 |
| 2906 | #endif |
| 2907 | |
| 2908 | // <o> Channel Arbitration Level |
| 2909 | // <0=> Channel priority 0 |
| 2910 | // <1=> Channel priority 1 |
| 2911 | // <2=> Channel priority 2 |
| 2912 | // <3=> Channel priority 3 |
| 2913 | // <i> Defines the arbitration level for this channel |
| 2914 | // <id> dmac_lvl_12 |
| 2915 | #ifndef CONF_DMAC_LVL_12 |
| 2916 | #define CONF_DMAC_LVL_12 0 |
| 2917 | #endif |
| 2918 | |
| 2919 | // <q> Channel Event Output |
| 2920 | // <i> Indicates whether channel event generation is enabled or not |
| 2921 | // <id> dmac_evoe_12 |
| 2922 | #ifndef CONF_DMAC_EVOE_12 |
| 2923 | #define CONF_DMAC_EVOE_12 0 |
| 2924 | #endif |
| 2925 | |
| 2926 | // <q> Channel Event Input |
| 2927 | // <i> Indicates whether channel event reception is enabled or not |
| 2928 | // <id> dmac_evie_12 |
| 2929 | #ifndef CONF_DMAC_EVIE_12 |
| 2930 | #define CONF_DMAC_EVIE_12 0 |
| 2931 | #endif |
| 2932 | |
| 2933 | // <o> Event Input Action |
| 2934 | // <0=> No action |
| 2935 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 2936 | // <2=> Conditional transfer trigger |
| 2937 | // <3=> Conditional block transfer |
| 2938 | // <4=> Channel suspend operation |
| 2939 | // <5=> Channel resume operation |
| 2940 | // <6=> Skip next block suspend action |
| 2941 | // <i> Defines the event input action |
| 2942 | // <id> dmac_evact_12 |
| 2943 | #ifndef CONF_DMAC_EVACT_12 |
| 2944 | #define CONF_DMAC_EVACT_12 0 |
| 2945 | #endif |
| 2946 | |
| 2947 | // <o> Address Increment Step Size |
| 2948 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 2949 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 2950 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 2951 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 2952 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 2953 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 2954 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 2955 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 2956 | // <i> Defines the address increment step size, applies to source or destination address |
| 2957 | // <id> dmac_stepsize_12 |
| 2958 | #ifndef CONF_DMAC_STEPSIZE_12 |
| 2959 | #define CONF_DMAC_STEPSIZE_12 0 |
| 2960 | #endif |
| 2961 | |
| 2962 | // <o> Step Selection |
| 2963 | // <0=> Step size settings apply to the destination address |
| 2964 | // <1=> Step size settings apply to the source address |
| 2965 | // <i> Defines whether source or destination addresses are using the step size settings |
| 2966 | // <id> dmac_stepsel_12 |
| 2967 | #ifndef CONF_DMAC_STEPSEL_12 |
| 2968 | #define CONF_DMAC_STEPSEL_12 0 |
| 2969 | #endif |
| 2970 | |
| 2971 | // <q> Source Address Increment |
| 2972 | // <i> Indicates whether the source address incrementation is enabled or not |
| 2973 | // <id> dmac_srcinc_12 |
| 2974 | #ifndef CONF_DMAC_SRCINC_12 |
| 2975 | #define CONF_DMAC_SRCINC_12 0 |
| 2976 | #endif |
| 2977 | |
| 2978 | // <q> Destination Address Increment |
| 2979 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 2980 | // <id> dmac_dstinc_12 |
| 2981 | #ifndef CONF_DMAC_DSTINC_12 |
| 2982 | #define CONF_DMAC_DSTINC_12 0 |
| 2983 | #endif |
| 2984 | |
| 2985 | // <o> Beat Size |
| 2986 | // <0=> 8-bit bus transfer |
| 2987 | // <1=> 16-bit bus transfer |
| 2988 | // <2=> 32-bit bus transfer |
| 2989 | // <i> Defines the size of one beat |
| 2990 | // <id> dmac_beatsize_12 |
| 2991 | #ifndef CONF_DMAC_BEATSIZE_12 |
| 2992 | #define CONF_DMAC_BEATSIZE_12 0 |
| 2993 | #endif |
| 2994 | |
| 2995 | // <o> Block Action |
| 2996 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 2997 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 2998 | // <2=> Channel suspend operation is complete |
| 2999 | // <3=> Both channel suspend operation and block interrupt |
| 3000 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 3001 | // <id> dmac_blockact_12 |
| 3002 | #ifndef CONF_DMAC_BLOCKACT_12 |
| 3003 | #define CONF_DMAC_BLOCKACT_12 0 |
| 3004 | #endif |
| 3005 | |
| 3006 | // <o> Event Output Selection |
| 3007 | // <0=> Event generation disabled |
| 3008 | // <1=> Event strobe when block transfer complete |
| 3009 | // <3=> Event strobe when beat transfer complete |
| 3010 | // <i> Defines the event output selection |
| 3011 | // <id> dmac_evosel_12 |
| 3012 | #ifndef CONF_DMAC_EVOSEL_12 |
| 3013 | #define CONF_DMAC_EVOSEL_12 0 |
| 3014 | #endif |
| 3015 | // </e> |
| 3016 | |
| 3017 | // <e> Channel 13 settings |
| 3018 | // <id> dmac_channel_13_settings |
| 3019 | #ifndef CONF_DMAC_CHANNEL_13_SETTINGS |
| 3020 | #define CONF_DMAC_CHANNEL_13_SETTINGS 0 |
| 3021 | #endif |
| 3022 | |
| 3023 | // <q> Channel Run in Standby |
| 3024 | // <i> Indicates whether channel 13 is running in standby mode or not |
| 3025 | // <id> dmac_runstdby_13 |
| 3026 | #ifndef CONF_DMAC_RUNSTDBY_13 |
| 3027 | #define CONF_DMAC_RUNSTDBY_13 0 |
| 3028 | #endif |
| 3029 | |
| 3030 | // <o> Trigger action |
| 3031 | // <0=> One trigger required for each block transfer |
| 3032 | // <2=> One trigger required for each beat transfer |
| 3033 | // <3=> One trigger required for each transaction |
| 3034 | // <i> Defines the trigger action used for a transfer |
| 3035 | // <id> dmac_trigact_13 |
| 3036 | #ifndef CONF_DMAC_TRIGACT_13 |
| 3037 | #define CONF_DMAC_TRIGACT_13 0 |
| 3038 | #endif |
| 3039 | |
| 3040 | // <o> Trigger source |
| 3041 | // <0x00=> Only software/event triggers |
| 3042 | // <0x01=> RTC Time Stamp Trigger |
| 3043 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 3044 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 3045 | // <0x04=> SERCOM0 RX Trigger |
| 3046 | // <0x05=> SERCOM0 TX Trigger |
| 3047 | // <0x06=> SERCOM1 RX Trigger |
| 3048 | // <0x07=> SERCOM1 TX Trigger |
| 3049 | // <0x08=> SERCOM2 RX Trigger |
| 3050 | // <0x09=> SERCOM2 TX Trigger |
| 3051 | // <0x0A=> SERCOM3 RX Trigger |
| 3052 | // <0x0B=> SERCOM3 TX Trigger |
| 3053 | // <0x0C=> SERCOM4 RX Trigger |
| 3054 | // <0x0D=> SERCOM4 TX Trigger |
| 3055 | // <0x0E=> SERCOM5 RX Trigger |
| 3056 | // <0x0F=> SERCOM5 TX Trigger |
| 3057 | // <0x10=> SERCOM6 RX Trigger |
| 3058 | // <0x11=> SERCOM6 TX Trigger |
| 3059 | // <0x12=> SERCOM7 RX Trigger |
| 3060 | // <0x13=> SERCOM7 TX Trigger |
| 3061 | // <0x14=> CAN0 DEBUG Trigger |
| 3062 | // <0x15=> CAN1 DEBUG Trigger |
| 3063 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 3064 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 3065 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 3066 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 3067 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 3068 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 3069 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 3070 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 3071 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 3072 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 3073 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 3074 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 3075 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 3076 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 3077 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 3078 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 3079 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 3080 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 3081 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 3082 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 3083 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 3084 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 3085 | // <0x2C=> TC0 Overflow Trigger |
| 3086 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 3087 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 3088 | // <0x2F=> TC1 Overflow Trigger |
| 3089 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 3090 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 3091 | // <0x32=> TC2 Overflow Trigger |
| 3092 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 3093 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 3094 | // <0x35=> TC3 Overflow Trigger |
| 3095 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 3096 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 3097 | // <0x38=> TC4 Overflow Trigger |
| 3098 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 3099 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 3100 | // <0x3B=> TC5 Overflow Trigger |
| 3101 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 3102 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 3103 | // <0x3E=> TC6 Overflow Trigger |
| 3104 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 3105 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 3106 | // <0x41=> TC7 Overflow Trigger |
| 3107 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 3108 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 3109 | // <0x44=> ADC0 Result Ready Trigger |
| 3110 | // <0x45=> ADC0 Sequencing Trigger |
| 3111 | // <0x46=> ADC1 Result Ready Trigger |
| 3112 | // <0x47=> ADC1 Sequencing Trigger |
| 3113 | // <0x48=> DAC Empty 0 Trigger |
| 3114 | // <0x49=> DAC Empty 1 Trigger |
| 3115 | // <0x4A=> DAC Result Ready 0 Trigger |
| 3116 | // <0x4B=> DAC Result Ready 1 Trigger |
| 3117 | // <0x4C=> I2S Rx 0 Trigger |
| 3118 | // <0x4D=> I2S Rx 1 Trigger |
| 3119 | // <0x4E=> I2S Tx 0 Trigger |
| 3120 | // <0x4F=> I2S Tx 1 Trigger |
| 3121 | // <0x50=> PCC RX Trigger |
| 3122 | // <0x51=> AES Write Trigger |
| 3123 | // <0x52=> AES Read Trigger |
| 3124 | // <0x53=> QSPI Rx Trigger |
| 3125 | // <0x54=> QSPI Tx Trigger |
| 3126 | // <i> Defines the peripheral trigger which is source of the transfer |
| 3127 | // <id> dmac_trifsrc_13 |
| 3128 | #ifndef CONF_DMAC_TRIGSRC_13 |
| 3129 | #define CONF_DMAC_TRIGSRC_13 0 |
| 3130 | #endif |
| 3131 | |
| 3132 | // <o> Channel Arbitration Level |
| 3133 | // <0=> Channel priority 0 |
| 3134 | // <1=> Channel priority 1 |
| 3135 | // <2=> Channel priority 2 |
| 3136 | // <3=> Channel priority 3 |
| 3137 | // <i> Defines the arbitration level for this channel |
| 3138 | // <id> dmac_lvl_13 |
| 3139 | #ifndef CONF_DMAC_LVL_13 |
| 3140 | #define CONF_DMAC_LVL_13 0 |
| 3141 | #endif |
| 3142 | |
| 3143 | // <q> Channel Event Output |
| 3144 | // <i> Indicates whether channel event generation is enabled or not |
| 3145 | // <id> dmac_evoe_13 |
| 3146 | #ifndef CONF_DMAC_EVOE_13 |
| 3147 | #define CONF_DMAC_EVOE_13 0 |
| 3148 | #endif |
| 3149 | |
| 3150 | // <q> Channel Event Input |
| 3151 | // <i> Indicates whether channel event reception is enabled or not |
| 3152 | // <id> dmac_evie_13 |
| 3153 | #ifndef CONF_DMAC_EVIE_13 |
| 3154 | #define CONF_DMAC_EVIE_13 0 |
| 3155 | #endif |
| 3156 | |
| 3157 | // <o> Event Input Action |
| 3158 | // <0=> No action |
| 3159 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 3160 | // <2=> Conditional transfer trigger |
| 3161 | // <3=> Conditional block transfer |
| 3162 | // <4=> Channel suspend operation |
| 3163 | // <5=> Channel resume operation |
| 3164 | // <6=> Skip next block suspend action |
| 3165 | // <i> Defines the event input action |
| 3166 | // <id> dmac_evact_13 |
| 3167 | #ifndef CONF_DMAC_EVACT_13 |
| 3168 | #define CONF_DMAC_EVACT_13 0 |
| 3169 | #endif |
| 3170 | |
| 3171 | // <o> Address Increment Step Size |
| 3172 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 3173 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 3174 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 3175 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 3176 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 3177 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 3178 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 3179 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 3180 | // <i> Defines the address increment step size, applies to source or destination address |
| 3181 | // <id> dmac_stepsize_13 |
| 3182 | #ifndef CONF_DMAC_STEPSIZE_13 |
| 3183 | #define CONF_DMAC_STEPSIZE_13 0 |
| 3184 | #endif |
| 3185 | |
| 3186 | // <o> Step Selection |
| 3187 | // <0=> Step size settings apply to the destination address |
| 3188 | // <1=> Step size settings apply to the source address |
| 3189 | // <i> Defines whether source or destination addresses are using the step size settings |
| 3190 | // <id> dmac_stepsel_13 |
| 3191 | #ifndef CONF_DMAC_STEPSEL_13 |
| 3192 | #define CONF_DMAC_STEPSEL_13 0 |
| 3193 | #endif |
| 3194 | |
| 3195 | // <q> Source Address Increment |
| 3196 | // <i> Indicates whether the source address incrementation is enabled or not |
| 3197 | // <id> dmac_srcinc_13 |
| 3198 | #ifndef CONF_DMAC_SRCINC_13 |
| 3199 | #define CONF_DMAC_SRCINC_13 0 |
| 3200 | #endif |
| 3201 | |
| 3202 | // <q> Destination Address Increment |
| 3203 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 3204 | // <id> dmac_dstinc_13 |
| 3205 | #ifndef CONF_DMAC_DSTINC_13 |
| 3206 | #define CONF_DMAC_DSTINC_13 0 |
| 3207 | #endif |
| 3208 | |
| 3209 | // <o> Beat Size |
| 3210 | // <0=> 8-bit bus transfer |
| 3211 | // <1=> 16-bit bus transfer |
| 3212 | // <2=> 32-bit bus transfer |
| 3213 | // <i> Defines the size of one beat |
| 3214 | // <id> dmac_beatsize_13 |
| 3215 | #ifndef CONF_DMAC_BEATSIZE_13 |
| 3216 | #define CONF_DMAC_BEATSIZE_13 0 |
| 3217 | #endif |
| 3218 | |
| 3219 | // <o> Block Action |
| 3220 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 3221 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 3222 | // <2=> Channel suspend operation is complete |
| 3223 | // <3=> Both channel suspend operation and block interrupt |
| 3224 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 3225 | // <id> dmac_blockact_13 |
| 3226 | #ifndef CONF_DMAC_BLOCKACT_13 |
| 3227 | #define CONF_DMAC_BLOCKACT_13 0 |
| 3228 | #endif |
| 3229 | |
| 3230 | // <o> Event Output Selection |
| 3231 | // <0=> Event generation disabled |
| 3232 | // <1=> Event strobe when block transfer complete |
| 3233 | // <3=> Event strobe when beat transfer complete |
| 3234 | // <i> Defines the event output selection |
| 3235 | // <id> dmac_evosel_13 |
| 3236 | #ifndef CONF_DMAC_EVOSEL_13 |
| 3237 | #define CONF_DMAC_EVOSEL_13 0 |
| 3238 | #endif |
| 3239 | // </e> |
| 3240 | |
| 3241 | // <e> Channel 14 settings |
| 3242 | // <id> dmac_channel_14_settings |
| 3243 | #ifndef CONF_DMAC_CHANNEL_14_SETTINGS |
| 3244 | #define CONF_DMAC_CHANNEL_14_SETTINGS 0 |
| 3245 | #endif |
| 3246 | |
| 3247 | // <q> Channel Run in Standby |
| 3248 | // <i> Indicates whether channel 14 is running in standby mode or not |
| 3249 | // <id> dmac_runstdby_14 |
| 3250 | #ifndef CONF_DMAC_RUNSTDBY_14 |
| 3251 | #define CONF_DMAC_RUNSTDBY_14 0 |
| 3252 | #endif |
| 3253 | |
| 3254 | // <o> Trigger action |
| 3255 | // <0=> One trigger required for each block transfer |
| 3256 | // <2=> One trigger required for each beat transfer |
| 3257 | // <3=> One trigger required for each transaction |
| 3258 | // <i> Defines the trigger action used for a transfer |
| 3259 | // <id> dmac_trigact_14 |
| 3260 | #ifndef CONF_DMAC_TRIGACT_14 |
| 3261 | #define CONF_DMAC_TRIGACT_14 0 |
| 3262 | #endif |
| 3263 | |
| 3264 | // <o> Trigger source |
| 3265 | // <0x00=> Only software/event triggers |
| 3266 | // <0x01=> RTC Time Stamp Trigger |
| 3267 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 3268 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 3269 | // <0x04=> SERCOM0 RX Trigger |
| 3270 | // <0x05=> SERCOM0 TX Trigger |
| 3271 | // <0x06=> SERCOM1 RX Trigger |
| 3272 | // <0x07=> SERCOM1 TX Trigger |
| 3273 | // <0x08=> SERCOM2 RX Trigger |
| 3274 | // <0x09=> SERCOM2 TX Trigger |
| 3275 | // <0x0A=> SERCOM3 RX Trigger |
| 3276 | // <0x0B=> SERCOM3 TX Trigger |
| 3277 | // <0x0C=> SERCOM4 RX Trigger |
| 3278 | // <0x0D=> SERCOM4 TX Trigger |
| 3279 | // <0x0E=> SERCOM5 RX Trigger |
| 3280 | // <0x0F=> SERCOM5 TX Trigger |
| 3281 | // <0x10=> SERCOM6 RX Trigger |
| 3282 | // <0x11=> SERCOM6 TX Trigger |
| 3283 | // <0x12=> SERCOM7 RX Trigger |
| 3284 | // <0x13=> SERCOM7 TX Trigger |
| 3285 | // <0x14=> CAN0 DEBUG Trigger |
| 3286 | // <0x15=> CAN1 DEBUG Trigger |
| 3287 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 3288 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 3289 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 3290 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 3291 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 3292 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 3293 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 3294 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 3295 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 3296 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 3297 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 3298 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 3299 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 3300 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 3301 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 3302 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 3303 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 3304 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 3305 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 3306 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 3307 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 3308 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 3309 | // <0x2C=> TC0 Overflow Trigger |
| 3310 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 3311 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 3312 | // <0x2F=> TC1 Overflow Trigger |
| 3313 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 3314 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 3315 | // <0x32=> TC2 Overflow Trigger |
| 3316 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 3317 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 3318 | // <0x35=> TC3 Overflow Trigger |
| 3319 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 3320 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 3321 | // <0x38=> TC4 Overflow Trigger |
| 3322 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 3323 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 3324 | // <0x3B=> TC5 Overflow Trigger |
| 3325 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 3326 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 3327 | // <0x3E=> TC6 Overflow Trigger |
| 3328 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 3329 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 3330 | // <0x41=> TC7 Overflow Trigger |
| 3331 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 3332 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 3333 | // <0x44=> ADC0 Result Ready Trigger |
| 3334 | // <0x45=> ADC0 Sequencing Trigger |
| 3335 | // <0x46=> ADC1 Result Ready Trigger |
| 3336 | // <0x47=> ADC1 Sequencing Trigger |
| 3337 | // <0x48=> DAC Empty 0 Trigger |
| 3338 | // <0x49=> DAC Empty 1 Trigger |
| 3339 | // <0x4A=> DAC Result Ready 0 Trigger |
| 3340 | // <0x4B=> DAC Result Ready 1 Trigger |
| 3341 | // <0x4C=> I2S Rx 0 Trigger |
| 3342 | // <0x4D=> I2S Rx 1 Trigger |
| 3343 | // <0x4E=> I2S Tx 0 Trigger |
| 3344 | // <0x4F=> I2S Tx 1 Trigger |
| 3345 | // <0x50=> PCC RX Trigger |
| 3346 | // <0x51=> AES Write Trigger |
| 3347 | // <0x52=> AES Read Trigger |
| 3348 | // <0x53=> QSPI Rx Trigger |
| 3349 | // <0x54=> QSPI Tx Trigger |
| 3350 | // <i> Defines the peripheral trigger which is source of the transfer |
| 3351 | // <id> dmac_trifsrc_14 |
| 3352 | #ifndef CONF_DMAC_TRIGSRC_14 |
| 3353 | #define CONF_DMAC_TRIGSRC_14 0 |
| 3354 | #endif |
| 3355 | |
| 3356 | // <o> Channel Arbitration Level |
| 3357 | // <0=> Channel priority 0 |
| 3358 | // <1=> Channel priority 1 |
| 3359 | // <2=> Channel priority 2 |
| 3360 | // <3=> Channel priority 3 |
| 3361 | // <i> Defines the arbitration level for this channel |
| 3362 | // <id> dmac_lvl_14 |
| 3363 | #ifndef CONF_DMAC_LVL_14 |
| 3364 | #define CONF_DMAC_LVL_14 0 |
| 3365 | #endif |
| 3366 | |
| 3367 | // <q> Channel Event Output |
| 3368 | // <i> Indicates whether channel event generation is enabled or not |
| 3369 | // <id> dmac_evoe_14 |
| 3370 | #ifndef CONF_DMAC_EVOE_14 |
| 3371 | #define CONF_DMAC_EVOE_14 0 |
| 3372 | #endif |
| 3373 | |
| 3374 | // <q> Channel Event Input |
| 3375 | // <i> Indicates whether channel event reception is enabled or not |
| 3376 | // <id> dmac_evie_14 |
| 3377 | #ifndef CONF_DMAC_EVIE_14 |
| 3378 | #define CONF_DMAC_EVIE_14 0 |
| 3379 | #endif |
| 3380 | |
| 3381 | // <o> Event Input Action |
| 3382 | // <0=> No action |
| 3383 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 3384 | // <2=> Conditional transfer trigger |
| 3385 | // <3=> Conditional block transfer |
| 3386 | // <4=> Channel suspend operation |
| 3387 | // <5=> Channel resume operation |
| 3388 | // <6=> Skip next block suspend action |
| 3389 | // <i> Defines the event input action |
| 3390 | // <id> dmac_evact_14 |
| 3391 | #ifndef CONF_DMAC_EVACT_14 |
| 3392 | #define CONF_DMAC_EVACT_14 0 |
| 3393 | #endif |
| 3394 | |
| 3395 | // <o> Address Increment Step Size |
| 3396 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 3397 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 3398 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 3399 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 3400 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 3401 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 3402 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 3403 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 3404 | // <i> Defines the address increment step size, applies to source or destination address |
| 3405 | // <id> dmac_stepsize_14 |
| 3406 | #ifndef CONF_DMAC_STEPSIZE_14 |
| 3407 | #define CONF_DMAC_STEPSIZE_14 0 |
| 3408 | #endif |
| 3409 | |
| 3410 | // <o> Step Selection |
| 3411 | // <0=> Step size settings apply to the destination address |
| 3412 | // <1=> Step size settings apply to the source address |
| 3413 | // <i> Defines whether source or destination addresses are using the step size settings |
| 3414 | // <id> dmac_stepsel_14 |
| 3415 | #ifndef CONF_DMAC_STEPSEL_14 |
| 3416 | #define CONF_DMAC_STEPSEL_14 0 |
| 3417 | #endif |
| 3418 | |
| 3419 | // <q> Source Address Increment |
| 3420 | // <i> Indicates whether the source address incrementation is enabled or not |
| 3421 | // <id> dmac_srcinc_14 |
| 3422 | #ifndef CONF_DMAC_SRCINC_14 |
| 3423 | #define CONF_DMAC_SRCINC_14 0 |
| 3424 | #endif |
| 3425 | |
| 3426 | // <q> Destination Address Increment |
| 3427 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 3428 | // <id> dmac_dstinc_14 |
| 3429 | #ifndef CONF_DMAC_DSTINC_14 |
| 3430 | #define CONF_DMAC_DSTINC_14 0 |
| 3431 | #endif |
| 3432 | |
| 3433 | // <o> Beat Size |
| 3434 | // <0=> 8-bit bus transfer |
| 3435 | // <1=> 16-bit bus transfer |
| 3436 | // <2=> 32-bit bus transfer |
| 3437 | // <i> Defines the size of one beat |
| 3438 | // <id> dmac_beatsize_14 |
| 3439 | #ifndef CONF_DMAC_BEATSIZE_14 |
| 3440 | #define CONF_DMAC_BEATSIZE_14 0 |
| 3441 | #endif |
| 3442 | |
| 3443 | // <o> Block Action |
| 3444 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 3445 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 3446 | // <2=> Channel suspend operation is complete |
| 3447 | // <3=> Both channel suspend operation and block interrupt |
| 3448 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 3449 | // <id> dmac_blockact_14 |
| 3450 | #ifndef CONF_DMAC_BLOCKACT_14 |
| 3451 | #define CONF_DMAC_BLOCKACT_14 0 |
| 3452 | #endif |
| 3453 | |
| 3454 | // <o> Event Output Selection |
| 3455 | // <0=> Event generation disabled |
| 3456 | // <1=> Event strobe when block transfer complete |
| 3457 | // <3=> Event strobe when beat transfer complete |
| 3458 | // <i> Defines the event output selection |
| 3459 | // <id> dmac_evosel_14 |
| 3460 | #ifndef CONF_DMAC_EVOSEL_14 |
| 3461 | #define CONF_DMAC_EVOSEL_14 0 |
| 3462 | #endif |
| 3463 | // </e> |
| 3464 | |
| 3465 | // <e> Channel 15 settings |
| 3466 | // <id> dmac_channel_15_settings |
| 3467 | #ifndef CONF_DMAC_CHANNEL_15_SETTINGS |
| 3468 | #define CONF_DMAC_CHANNEL_15_SETTINGS 0 |
| 3469 | #endif |
| 3470 | |
| 3471 | // <q> Channel Run in Standby |
| 3472 | // <i> Indicates whether channel 15 is running in standby mode or not |
| 3473 | // <id> dmac_runstdby_15 |
| 3474 | #ifndef CONF_DMAC_RUNSTDBY_15 |
| 3475 | #define CONF_DMAC_RUNSTDBY_15 0 |
| 3476 | #endif |
| 3477 | |
| 3478 | // <o> Trigger action |
| 3479 | // <0=> One trigger required for each block transfer |
| 3480 | // <2=> One trigger required for each beat transfer |
| 3481 | // <3=> One trigger required for each transaction |
| 3482 | // <i> Defines the trigger action used for a transfer |
| 3483 | // <id> dmac_trigact_15 |
| 3484 | #ifndef CONF_DMAC_TRIGACT_15 |
| 3485 | #define CONF_DMAC_TRIGACT_15 0 |
| 3486 | #endif |
| 3487 | |
| 3488 | // <o> Trigger source |
| 3489 | // <0x00=> Only software/event triggers |
| 3490 | // <0x01=> RTC Time Stamp Trigger |
| 3491 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 3492 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 3493 | // <0x04=> SERCOM0 RX Trigger |
| 3494 | // <0x05=> SERCOM0 TX Trigger |
| 3495 | // <0x06=> SERCOM1 RX Trigger |
| 3496 | // <0x07=> SERCOM1 TX Trigger |
| 3497 | // <0x08=> SERCOM2 RX Trigger |
| 3498 | // <0x09=> SERCOM2 TX Trigger |
| 3499 | // <0x0A=> SERCOM3 RX Trigger |
| 3500 | // <0x0B=> SERCOM3 TX Trigger |
| 3501 | // <0x0C=> SERCOM4 RX Trigger |
| 3502 | // <0x0D=> SERCOM4 TX Trigger |
| 3503 | // <0x0E=> SERCOM5 RX Trigger |
| 3504 | // <0x0F=> SERCOM5 TX Trigger |
| 3505 | // <0x10=> SERCOM6 RX Trigger |
| 3506 | // <0x11=> SERCOM6 TX Trigger |
| 3507 | // <0x12=> SERCOM7 RX Trigger |
| 3508 | // <0x13=> SERCOM7 TX Trigger |
| 3509 | // <0x14=> CAN0 DEBUG Trigger |
| 3510 | // <0x15=> CAN1 DEBUG Trigger |
| 3511 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 3512 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 3513 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 3514 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 3515 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 3516 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 3517 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 3518 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 3519 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 3520 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 3521 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 3522 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 3523 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 3524 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 3525 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 3526 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 3527 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 3528 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 3529 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 3530 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 3531 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 3532 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 3533 | // <0x2C=> TC0 Overflow Trigger |
| 3534 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 3535 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 3536 | // <0x2F=> TC1 Overflow Trigger |
| 3537 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 3538 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 3539 | // <0x32=> TC2 Overflow Trigger |
| 3540 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 3541 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 3542 | // <0x35=> TC3 Overflow Trigger |
| 3543 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 3544 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 3545 | // <0x38=> TC4 Overflow Trigger |
| 3546 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 3547 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 3548 | // <0x3B=> TC5 Overflow Trigger |
| 3549 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 3550 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 3551 | // <0x3E=> TC6 Overflow Trigger |
| 3552 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 3553 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 3554 | // <0x41=> TC7 Overflow Trigger |
| 3555 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 3556 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 3557 | // <0x44=> ADC0 Result Ready Trigger |
| 3558 | // <0x45=> ADC0 Sequencing Trigger |
| 3559 | // <0x46=> ADC1 Result Ready Trigger |
| 3560 | // <0x47=> ADC1 Sequencing Trigger |
| 3561 | // <0x48=> DAC Empty 0 Trigger |
| 3562 | // <0x49=> DAC Empty 1 Trigger |
| 3563 | // <0x4A=> DAC Result Ready 0 Trigger |
| 3564 | // <0x4B=> DAC Result Ready 1 Trigger |
| 3565 | // <0x4C=> I2S Rx 0 Trigger |
| 3566 | // <0x4D=> I2S Rx 1 Trigger |
| 3567 | // <0x4E=> I2S Tx 0 Trigger |
| 3568 | // <0x4F=> I2S Tx 1 Trigger |
| 3569 | // <0x50=> PCC RX Trigger |
| 3570 | // <0x51=> AES Write Trigger |
| 3571 | // <0x52=> AES Read Trigger |
| 3572 | // <0x53=> QSPI Rx Trigger |
| 3573 | // <0x54=> QSPI Tx Trigger |
| 3574 | // <i> Defines the peripheral trigger which is source of the transfer |
| 3575 | // <id> dmac_trifsrc_15 |
| 3576 | #ifndef CONF_DMAC_TRIGSRC_15 |
| 3577 | #define CONF_DMAC_TRIGSRC_15 0 |
| 3578 | #endif |
| 3579 | |
| 3580 | // <o> Channel Arbitration Level |
| 3581 | // <0=> Channel priority 0 |
| 3582 | // <1=> Channel priority 1 |
| 3583 | // <2=> Channel priority 2 |
| 3584 | // <3=> Channel priority 3 |
| 3585 | // <i> Defines the arbitration level for this channel |
| 3586 | // <id> dmac_lvl_15 |
| 3587 | #ifndef CONF_DMAC_LVL_15 |
| 3588 | #define CONF_DMAC_LVL_15 0 |
| 3589 | #endif |
| 3590 | |
| 3591 | // <q> Channel Event Output |
| 3592 | // <i> Indicates whether channel event generation is enabled or not |
| 3593 | // <id> dmac_evoe_15 |
| 3594 | #ifndef CONF_DMAC_EVOE_15 |
| 3595 | #define CONF_DMAC_EVOE_15 0 |
| 3596 | #endif |
| 3597 | |
| 3598 | // <q> Channel Event Input |
| 3599 | // <i> Indicates whether channel event reception is enabled or not |
| 3600 | // <id> dmac_evie_15 |
| 3601 | #ifndef CONF_DMAC_EVIE_15 |
| 3602 | #define CONF_DMAC_EVIE_15 0 |
| 3603 | #endif |
| 3604 | |
| 3605 | // <o> Event Input Action |
| 3606 | // <0=> No action |
| 3607 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 3608 | // <2=> Conditional transfer trigger |
| 3609 | // <3=> Conditional block transfer |
| 3610 | // <4=> Channel suspend operation |
| 3611 | // <5=> Channel resume operation |
| 3612 | // <6=> Skip next block suspend action |
| 3613 | // <i> Defines the event input action |
| 3614 | // <id> dmac_evact_15 |
| 3615 | #ifndef CONF_DMAC_EVACT_15 |
| 3616 | #define CONF_DMAC_EVACT_15 0 |
| 3617 | #endif |
| 3618 | |
| 3619 | // <o> Address Increment Step Size |
| 3620 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 3621 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 3622 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 3623 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 3624 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 3625 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 3626 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 3627 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 3628 | // <i> Defines the address increment step size, applies to source or destination address |
| 3629 | // <id> dmac_stepsize_15 |
| 3630 | #ifndef CONF_DMAC_STEPSIZE_15 |
| 3631 | #define CONF_DMAC_STEPSIZE_15 0 |
| 3632 | #endif |
| 3633 | |
| 3634 | // <o> Step Selection |
| 3635 | // <0=> Step size settings apply to the destination address |
| 3636 | // <1=> Step size settings apply to the source address |
| 3637 | // <i> Defines whether source or destination addresses are using the step size settings |
| 3638 | // <id> dmac_stepsel_15 |
| 3639 | #ifndef CONF_DMAC_STEPSEL_15 |
| 3640 | #define CONF_DMAC_STEPSEL_15 0 |
| 3641 | #endif |
| 3642 | |
| 3643 | // <q> Source Address Increment |
| 3644 | // <i> Indicates whether the source address incrementation is enabled or not |
| 3645 | // <id> dmac_srcinc_15 |
| 3646 | #ifndef CONF_DMAC_SRCINC_15 |
| 3647 | #define CONF_DMAC_SRCINC_15 0 |
| 3648 | #endif |
| 3649 | |
| 3650 | // <q> Destination Address Increment |
| 3651 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 3652 | // <id> dmac_dstinc_15 |
| 3653 | #ifndef CONF_DMAC_DSTINC_15 |
| 3654 | #define CONF_DMAC_DSTINC_15 0 |
| 3655 | #endif |
| 3656 | |
| 3657 | // <o> Beat Size |
| 3658 | // <0=> 8-bit bus transfer |
| 3659 | // <1=> 16-bit bus transfer |
| 3660 | // <2=> 32-bit bus transfer |
| 3661 | // <i> Defines the size of one beat |
| 3662 | // <id> dmac_beatsize_15 |
| 3663 | #ifndef CONF_DMAC_BEATSIZE_15 |
| 3664 | #define CONF_DMAC_BEATSIZE_15 0 |
| 3665 | #endif |
| 3666 | |
| 3667 | // <o> Block Action |
| 3668 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 3669 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 3670 | // <2=> Channel suspend operation is complete |
| 3671 | // <3=> Both channel suspend operation and block interrupt |
| 3672 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 3673 | // <id> dmac_blockact_15 |
| 3674 | #ifndef CONF_DMAC_BLOCKACT_15 |
| 3675 | #define CONF_DMAC_BLOCKACT_15 0 |
| 3676 | #endif |
| 3677 | |
| 3678 | // <o> Event Output Selection |
| 3679 | // <0=> Event generation disabled |
| 3680 | // <1=> Event strobe when block transfer complete |
| 3681 | // <3=> Event strobe when beat transfer complete |
| 3682 | // <i> Defines the event output selection |
| 3683 | // <id> dmac_evosel_15 |
| 3684 | #ifndef CONF_DMAC_EVOSEL_15 |
| 3685 | #define CONF_DMAC_EVOSEL_15 0 |
| 3686 | #endif |
| 3687 | // </e> |
| 3688 | |
| 3689 | // <e> Channel 16 settings |
| 3690 | // <id> dmac_channel_16_settings |
| 3691 | #ifndef CONF_DMAC_CHANNEL_16_SETTINGS |
| 3692 | #define CONF_DMAC_CHANNEL_16_SETTINGS 0 |
| 3693 | #endif |
| 3694 | |
| 3695 | // <q> Channel Run in Standby |
| 3696 | // <i> Indicates whether channel 16 is running in standby mode or not |
| 3697 | // <id> dmac_runstdby_16 |
| 3698 | #ifndef CONF_DMAC_RUNSTDBY_16 |
| 3699 | #define CONF_DMAC_RUNSTDBY_16 0 |
| 3700 | #endif |
| 3701 | |
| 3702 | // <o> Trigger action |
| 3703 | // <0=> One trigger required for each block transfer |
| 3704 | // <2=> One trigger required for each beat transfer |
| 3705 | // <3=> One trigger required for each transaction |
| 3706 | // <i> Defines the trigger action used for a transfer |
| 3707 | // <id> dmac_trigact_16 |
| 3708 | #ifndef CONF_DMAC_TRIGACT_16 |
| 3709 | #define CONF_DMAC_TRIGACT_16 0 |
| 3710 | #endif |
| 3711 | |
| 3712 | // <o> Trigger source |
| 3713 | // <0x00=> Only software/event triggers |
| 3714 | // <0x01=> RTC Time Stamp Trigger |
| 3715 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 3716 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 3717 | // <0x04=> SERCOM0 RX Trigger |
| 3718 | // <0x05=> SERCOM0 TX Trigger |
| 3719 | // <0x06=> SERCOM1 RX Trigger |
| 3720 | // <0x07=> SERCOM1 TX Trigger |
| 3721 | // <0x08=> SERCOM2 RX Trigger |
| 3722 | // <0x09=> SERCOM2 TX Trigger |
| 3723 | // <0x0A=> SERCOM3 RX Trigger |
| 3724 | // <0x0B=> SERCOM3 TX Trigger |
| 3725 | // <0x0C=> SERCOM4 RX Trigger |
| 3726 | // <0x0D=> SERCOM4 TX Trigger |
| 3727 | // <0x0E=> SERCOM5 RX Trigger |
| 3728 | // <0x0F=> SERCOM5 TX Trigger |
| 3729 | // <0x10=> SERCOM6 RX Trigger |
| 3730 | // <0x11=> SERCOM6 TX Trigger |
| 3731 | // <0x12=> SERCOM7 RX Trigger |
| 3732 | // <0x13=> SERCOM7 TX Trigger |
| 3733 | // <0x14=> CAN0 DEBUG Trigger |
| 3734 | // <0x15=> CAN1 DEBUG Trigger |
| 3735 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 3736 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 3737 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 3738 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 3739 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 3740 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 3741 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 3742 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 3743 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 3744 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 3745 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 3746 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 3747 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 3748 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 3749 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 3750 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 3751 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 3752 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 3753 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 3754 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 3755 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 3756 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 3757 | // <0x2C=> TC0 Overflow Trigger |
| 3758 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 3759 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 3760 | // <0x2F=> TC1 Overflow Trigger |
| 3761 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 3762 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 3763 | // <0x32=> TC2 Overflow Trigger |
| 3764 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 3765 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 3766 | // <0x35=> TC3 Overflow Trigger |
| 3767 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 3768 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 3769 | // <0x38=> TC4 Overflow Trigger |
| 3770 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 3771 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 3772 | // <0x3B=> TC5 Overflow Trigger |
| 3773 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 3774 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 3775 | // <0x3E=> TC6 Overflow Trigger |
| 3776 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 3777 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 3778 | // <0x41=> TC7 Overflow Trigger |
| 3779 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 3780 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 3781 | // <0x44=> ADC0 Result Ready Trigger |
| 3782 | // <0x45=> ADC0 Sequencing Trigger |
| 3783 | // <0x46=> ADC1 Result Ready Trigger |
| 3784 | // <0x47=> ADC1 Sequencing Trigger |
| 3785 | // <0x48=> DAC Empty 0 Trigger |
| 3786 | // <0x49=> DAC Empty 1 Trigger |
| 3787 | // <0x4A=> DAC Result Ready 0 Trigger |
| 3788 | // <0x4B=> DAC Result Ready 1 Trigger |
| 3789 | // <0x4C=> I2S Rx 0 Trigger |
| 3790 | // <0x4D=> I2S Rx 1 Trigger |
| 3791 | // <0x4E=> I2S Tx 0 Trigger |
| 3792 | // <0x4F=> I2S Tx 1 Trigger |
| 3793 | // <0x50=> PCC RX Trigger |
| 3794 | // <0x51=> AES Write Trigger |
| 3795 | // <0x52=> AES Read Trigger |
| 3796 | // <0x53=> QSPI Rx Trigger |
| 3797 | // <0x54=> QSPI Tx Trigger |
| 3798 | // <i> Defines the peripheral trigger which is source of the transfer |
| 3799 | // <id> dmac_trifsrc_16 |
| 3800 | #ifndef CONF_DMAC_TRIGSRC_16 |
| 3801 | #define CONF_DMAC_TRIGSRC_16 0 |
| 3802 | #endif |
| 3803 | |
| 3804 | // <o> Channel Arbitration Level |
| 3805 | // <0=> Channel priority 0 |
| 3806 | // <1=> Channel priority 1 |
| 3807 | // <2=> Channel priority 2 |
| 3808 | // <3=> Channel priority 3 |
| 3809 | // <i> Defines the arbitration level for this channel |
| 3810 | // <id> dmac_lvl_16 |
| 3811 | #ifndef CONF_DMAC_LVL_16 |
| 3812 | #define CONF_DMAC_LVL_16 0 |
| 3813 | #endif |
| 3814 | |
| 3815 | // <q> Channel Event Output |
| 3816 | // <i> Indicates whether channel event generation is enabled or not |
| 3817 | // <id> dmac_evoe_16 |
| 3818 | #ifndef CONF_DMAC_EVOE_16 |
| 3819 | #define CONF_DMAC_EVOE_16 0 |
| 3820 | #endif |
| 3821 | |
| 3822 | // <q> Channel Event Input |
| 3823 | // <i> Indicates whether channel event reception is enabled or not |
| 3824 | // <id> dmac_evie_16 |
| 3825 | #ifndef CONF_DMAC_EVIE_16 |
| 3826 | #define CONF_DMAC_EVIE_16 0 |
| 3827 | #endif |
| 3828 | |
| 3829 | // <o> Event Input Action |
| 3830 | // <0=> No action |
| 3831 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 3832 | // <2=> Conditional transfer trigger |
| 3833 | // <3=> Conditional block transfer |
| 3834 | // <4=> Channel suspend operation |
| 3835 | // <5=> Channel resume operation |
| 3836 | // <6=> Skip next block suspend action |
| 3837 | // <i> Defines the event input action |
| 3838 | // <id> dmac_evact_16 |
| 3839 | #ifndef CONF_DMAC_EVACT_16 |
| 3840 | #define CONF_DMAC_EVACT_16 0 |
| 3841 | #endif |
| 3842 | |
| 3843 | // <o> Address Increment Step Size |
| 3844 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 3845 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 3846 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 3847 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 3848 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 3849 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 3850 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 3851 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 3852 | // <i> Defines the address increment step size, applies to source or destination address |
| 3853 | // <id> dmac_stepsize_16 |
| 3854 | #ifndef CONF_DMAC_STEPSIZE_16 |
| 3855 | #define CONF_DMAC_STEPSIZE_16 0 |
| 3856 | #endif |
| 3857 | |
| 3858 | // <o> Step Selection |
| 3859 | // <0=> Step size settings apply to the destination address |
| 3860 | // <1=> Step size settings apply to the source address |
| 3861 | // <i> Defines whether source or destination addresses are using the step size settings |
| 3862 | // <id> dmac_stepsel_16 |
| 3863 | #ifndef CONF_DMAC_STEPSEL_16 |
| 3864 | #define CONF_DMAC_STEPSEL_16 0 |
| 3865 | #endif |
| 3866 | |
| 3867 | // <q> Source Address Increment |
| 3868 | // <i> Indicates whether the source address incrementation is enabled or not |
| 3869 | // <id> dmac_srcinc_16 |
| 3870 | #ifndef CONF_DMAC_SRCINC_16 |
| 3871 | #define CONF_DMAC_SRCINC_16 0 |
| 3872 | #endif |
| 3873 | |
| 3874 | // <q> Destination Address Increment |
| 3875 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 3876 | // <id> dmac_dstinc_16 |
| 3877 | #ifndef CONF_DMAC_DSTINC_16 |
| 3878 | #define CONF_DMAC_DSTINC_16 0 |
| 3879 | #endif |
| 3880 | |
| 3881 | // <o> Beat Size |
| 3882 | // <0=> 8-bit bus transfer |
| 3883 | // <1=> 16-bit bus transfer |
| 3884 | // <2=> 32-bit bus transfer |
| 3885 | // <i> Defines the size of one beat |
| 3886 | // <id> dmac_beatsize_16 |
| 3887 | #ifndef CONF_DMAC_BEATSIZE_16 |
| 3888 | #define CONF_DMAC_BEATSIZE_16 0 |
| 3889 | #endif |
| 3890 | |
| 3891 | // <o> Block Action |
| 3892 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 3893 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 3894 | // <2=> Channel suspend operation is complete |
| 3895 | // <3=> Both channel suspend operation and block interrupt |
| 3896 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 3897 | // <id> dmac_blockact_16 |
| 3898 | #ifndef CONF_DMAC_BLOCKACT_16 |
| 3899 | #define CONF_DMAC_BLOCKACT_16 0 |
| 3900 | #endif |
| 3901 | |
| 3902 | // <o> Event Output Selection |
| 3903 | // <0=> Event generation disabled |
| 3904 | // <1=> Event strobe when block transfer complete |
| 3905 | // <3=> Event strobe when beat transfer complete |
| 3906 | // <i> Defines the event output selection |
| 3907 | // <id> dmac_evosel_16 |
| 3908 | #ifndef CONF_DMAC_EVOSEL_16 |
| 3909 | #define CONF_DMAC_EVOSEL_16 0 |
| 3910 | #endif |
| 3911 | // </e> |
| 3912 | |
| 3913 | // <e> Channel 17 settings |
| 3914 | // <id> dmac_channel_17_settings |
| 3915 | #ifndef CONF_DMAC_CHANNEL_17_SETTINGS |
| 3916 | #define CONF_DMAC_CHANNEL_17_SETTINGS 0 |
| 3917 | #endif |
| 3918 | |
| 3919 | // <q> Channel Run in Standby |
| 3920 | // <i> Indicates whether channel 17 is running in standby mode or not |
| 3921 | // <id> dmac_runstdby_17 |
| 3922 | #ifndef CONF_DMAC_RUNSTDBY_17 |
| 3923 | #define CONF_DMAC_RUNSTDBY_17 0 |
| 3924 | #endif |
| 3925 | |
| 3926 | // <o> Trigger action |
| 3927 | // <0=> One trigger required for each block transfer |
| 3928 | // <2=> One trigger required for each beat transfer |
| 3929 | // <3=> One trigger required for each transaction |
| 3930 | // <i> Defines the trigger action used for a transfer |
| 3931 | // <id> dmac_trigact_17 |
| 3932 | #ifndef CONF_DMAC_TRIGACT_17 |
| 3933 | #define CONF_DMAC_TRIGACT_17 0 |
| 3934 | #endif |
| 3935 | |
| 3936 | // <o> Trigger source |
| 3937 | // <0x00=> Only software/event triggers |
| 3938 | // <0x01=> RTC Time Stamp Trigger |
| 3939 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 3940 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 3941 | // <0x04=> SERCOM0 RX Trigger |
| 3942 | // <0x05=> SERCOM0 TX Trigger |
| 3943 | // <0x06=> SERCOM1 RX Trigger |
| 3944 | // <0x07=> SERCOM1 TX Trigger |
| 3945 | // <0x08=> SERCOM2 RX Trigger |
| 3946 | // <0x09=> SERCOM2 TX Trigger |
| 3947 | // <0x0A=> SERCOM3 RX Trigger |
| 3948 | // <0x0B=> SERCOM3 TX Trigger |
| 3949 | // <0x0C=> SERCOM4 RX Trigger |
| 3950 | // <0x0D=> SERCOM4 TX Trigger |
| 3951 | // <0x0E=> SERCOM5 RX Trigger |
| 3952 | // <0x0F=> SERCOM5 TX Trigger |
| 3953 | // <0x10=> SERCOM6 RX Trigger |
| 3954 | // <0x11=> SERCOM6 TX Trigger |
| 3955 | // <0x12=> SERCOM7 RX Trigger |
| 3956 | // <0x13=> SERCOM7 TX Trigger |
| 3957 | // <0x14=> CAN0 DEBUG Trigger |
| 3958 | // <0x15=> CAN1 DEBUG Trigger |
| 3959 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 3960 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 3961 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 3962 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 3963 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 3964 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 3965 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 3966 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 3967 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 3968 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 3969 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 3970 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 3971 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 3972 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 3973 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 3974 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 3975 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 3976 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 3977 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 3978 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 3979 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 3980 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 3981 | // <0x2C=> TC0 Overflow Trigger |
| 3982 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 3983 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 3984 | // <0x2F=> TC1 Overflow Trigger |
| 3985 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 3986 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 3987 | // <0x32=> TC2 Overflow Trigger |
| 3988 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 3989 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 3990 | // <0x35=> TC3 Overflow Trigger |
| 3991 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 3992 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 3993 | // <0x38=> TC4 Overflow Trigger |
| 3994 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 3995 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 3996 | // <0x3B=> TC5 Overflow Trigger |
| 3997 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 3998 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 3999 | // <0x3E=> TC6 Overflow Trigger |
| 4000 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 4001 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 4002 | // <0x41=> TC7 Overflow Trigger |
| 4003 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 4004 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 4005 | // <0x44=> ADC0 Result Ready Trigger |
| 4006 | // <0x45=> ADC0 Sequencing Trigger |
| 4007 | // <0x46=> ADC1 Result Ready Trigger |
| 4008 | // <0x47=> ADC1 Sequencing Trigger |
| 4009 | // <0x48=> DAC Empty 0 Trigger |
| 4010 | // <0x49=> DAC Empty 1 Trigger |
| 4011 | // <0x4A=> DAC Result Ready 0 Trigger |
| 4012 | // <0x4B=> DAC Result Ready 1 Trigger |
| 4013 | // <0x4C=> I2S Rx 0 Trigger |
| 4014 | // <0x4D=> I2S Rx 1 Trigger |
| 4015 | // <0x4E=> I2S Tx 0 Trigger |
| 4016 | // <0x4F=> I2S Tx 1 Trigger |
| 4017 | // <0x50=> PCC RX Trigger |
| 4018 | // <0x51=> AES Write Trigger |
| 4019 | // <0x52=> AES Read Trigger |
| 4020 | // <0x53=> QSPI Rx Trigger |
| 4021 | // <0x54=> QSPI Tx Trigger |
| 4022 | // <i> Defines the peripheral trigger which is source of the transfer |
| 4023 | // <id> dmac_trifsrc_17 |
| 4024 | #ifndef CONF_DMAC_TRIGSRC_17 |
| 4025 | #define CONF_DMAC_TRIGSRC_17 0 |
| 4026 | #endif |
| 4027 | |
| 4028 | // <o> Channel Arbitration Level |
| 4029 | // <0=> Channel priority 0 |
| 4030 | // <1=> Channel priority 1 |
| 4031 | // <2=> Channel priority 2 |
| 4032 | // <3=> Channel priority 3 |
| 4033 | // <i> Defines the arbitration level for this channel |
| 4034 | // <id> dmac_lvl_17 |
| 4035 | #ifndef CONF_DMAC_LVL_17 |
| 4036 | #define CONF_DMAC_LVL_17 0 |
| 4037 | #endif |
| 4038 | |
| 4039 | // <q> Channel Event Output |
| 4040 | // <i> Indicates whether channel event generation is enabled or not |
| 4041 | // <id> dmac_evoe_17 |
| 4042 | #ifndef CONF_DMAC_EVOE_17 |
| 4043 | #define CONF_DMAC_EVOE_17 0 |
| 4044 | #endif |
| 4045 | |
| 4046 | // <q> Channel Event Input |
| 4047 | // <i> Indicates whether channel event reception is enabled or not |
| 4048 | // <id> dmac_evie_17 |
| 4049 | #ifndef CONF_DMAC_EVIE_17 |
| 4050 | #define CONF_DMAC_EVIE_17 0 |
| 4051 | #endif |
| 4052 | |
| 4053 | // <o> Event Input Action |
| 4054 | // <0=> No action |
| 4055 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 4056 | // <2=> Conditional transfer trigger |
| 4057 | // <3=> Conditional block transfer |
| 4058 | // <4=> Channel suspend operation |
| 4059 | // <5=> Channel resume operation |
| 4060 | // <6=> Skip next block suspend action |
| 4061 | // <i> Defines the event input action |
| 4062 | // <id> dmac_evact_17 |
| 4063 | #ifndef CONF_DMAC_EVACT_17 |
| 4064 | #define CONF_DMAC_EVACT_17 0 |
| 4065 | #endif |
| 4066 | |
| 4067 | // <o> Address Increment Step Size |
| 4068 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 4069 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 4070 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 4071 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 4072 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 4073 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 4074 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 4075 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 4076 | // <i> Defines the address increment step size, applies to source or destination address |
| 4077 | // <id> dmac_stepsize_17 |
| 4078 | #ifndef CONF_DMAC_STEPSIZE_17 |
| 4079 | #define CONF_DMAC_STEPSIZE_17 0 |
| 4080 | #endif |
| 4081 | |
| 4082 | // <o> Step Selection |
| 4083 | // <0=> Step size settings apply to the destination address |
| 4084 | // <1=> Step size settings apply to the source address |
| 4085 | // <i> Defines whether source or destination addresses are using the step size settings |
| 4086 | // <id> dmac_stepsel_17 |
| 4087 | #ifndef CONF_DMAC_STEPSEL_17 |
| 4088 | #define CONF_DMAC_STEPSEL_17 0 |
| 4089 | #endif |
| 4090 | |
| 4091 | // <q> Source Address Increment |
| 4092 | // <i> Indicates whether the source address incrementation is enabled or not |
| 4093 | // <id> dmac_srcinc_17 |
| 4094 | #ifndef CONF_DMAC_SRCINC_17 |
| 4095 | #define CONF_DMAC_SRCINC_17 0 |
| 4096 | #endif |
| 4097 | |
| 4098 | // <q> Destination Address Increment |
| 4099 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 4100 | // <id> dmac_dstinc_17 |
| 4101 | #ifndef CONF_DMAC_DSTINC_17 |
| 4102 | #define CONF_DMAC_DSTINC_17 0 |
| 4103 | #endif |
| 4104 | |
| 4105 | // <o> Beat Size |
| 4106 | // <0=> 8-bit bus transfer |
| 4107 | // <1=> 16-bit bus transfer |
| 4108 | // <2=> 32-bit bus transfer |
| 4109 | // <i> Defines the size of one beat |
| 4110 | // <id> dmac_beatsize_17 |
| 4111 | #ifndef CONF_DMAC_BEATSIZE_17 |
| 4112 | #define CONF_DMAC_BEATSIZE_17 0 |
| 4113 | #endif |
| 4114 | |
| 4115 | // <o> Block Action |
| 4116 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 4117 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 4118 | // <2=> Channel suspend operation is complete |
| 4119 | // <3=> Both channel suspend operation and block interrupt |
| 4120 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 4121 | // <id> dmac_blockact_17 |
| 4122 | #ifndef CONF_DMAC_BLOCKACT_17 |
| 4123 | #define CONF_DMAC_BLOCKACT_17 0 |
| 4124 | #endif |
| 4125 | |
| 4126 | // <o> Event Output Selection |
| 4127 | // <0=> Event generation disabled |
| 4128 | // <1=> Event strobe when block transfer complete |
| 4129 | // <3=> Event strobe when beat transfer complete |
| 4130 | // <i> Defines the event output selection |
| 4131 | // <id> dmac_evosel_17 |
| 4132 | #ifndef CONF_DMAC_EVOSEL_17 |
| 4133 | #define CONF_DMAC_EVOSEL_17 0 |
| 4134 | #endif |
| 4135 | // </e> |
| 4136 | |
| 4137 | // <e> Channel 18 settings |
| 4138 | // <id> dmac_channel_18_settings |
| 4139 | #ifndef CONF_DMAC_CHANNEL_18_SETTINGS |
| 4140 | #define CONF_DMAC_CHANNEL_18_SETTINGS 0 |
| 4141 | #endif |
| 4142 | |
| 4143 | // <q> Channel Run in Standby |
| 4144 | // <i> Indicates whether channel 18 is running in standby mode or not |
| 4145 | // <id> dmac_runstdby_18 |
| 4146 | #ifndef CONF_DMAC_RUNSTDBY_18 |
| 4147 | #define CONF_DMAC_RUNSTDBY_18 0 |
| 4148 | #endif |
| 4149 | |
| 4150 | // <o> Trigger action |
| 4151 | // <0=> One trigger required for each block transfer |
| 4152 | // <2=> One trigger required for each beat transfer |
| 4153 | // <3=> One trigger required for each transaction |
| 4154 | // <i> Defines the trigger action used for a transfer |
| 4155 | // <id> dmac_trigact_18 |
| 4156 | #ifndef CONF_DMAC_TRIGACT_18 |
| 4157 | #define CONF_DMAC_TRIGACT_18 0 |
| 4158 | #endif |
| 4159 | |
| 4160 | // <o> Trigger source |
| 4161 | // <0x00=> Only software/event triggers |
| 4162 | // <0x01=> RTC Time Stamp Trigger |
| 4163 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 4164 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 4165 | // <0x04=> SERCOM0 RX Trigger |
| 4166 | // <0x05=> SERCOM0 TX Trigger |
| 4167 | // <0x06=> SERCOM1 RX Trigger |
| 4168 | // <0x07=> SERCOM1 TX Trigger |
| 4169 | // <0x08=> SERCOM2 RX Trigger |
| 4170 | // <0x09=> SERCOM2 TX Trigger |
| 4171 | // <0x0A=> SERCOM3 RX Trigger |
| 4172 | // <0x0B=> SERCOM3 TX Trigger |
| 4173 | // <0x0C=> SERCOM4 RX Trigger |
| 4174 | // <0x0D=> SERCOM4 TX Trigger |
| 4175 | // <0x0E=> SERCOM5 RX Trigger |
| 4176 | // <0x0F=> SERCOM5 TX Trigger |
| 4177 | // <0x10=> SERCOM6 RX Trigger |
| 4178 | // <0x11=> SERCOM6 TX Trigger |
| 4179 | // <0x12=> SERCOM7 RX Trigger |
| 4180 | // <0x13=> SERCOM7 TX Trigger |
| 4181 | // <0x14=> CAN0 DEBUG Trigger |
| 4182 | // <0x15=> CAN1 DEBUG Trigger |
| 4183 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 4184 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 4185 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 4186 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 4187 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 4188 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 4189 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 4190 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 4191 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 4192 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 4193 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 4194 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 4195 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 4196 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 4197 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 4198 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 4199 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 4200 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 4201 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 4202 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 4203 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 4204 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 4205 | // <0x2C=> TC0 Overflow Trigger |
| 4206 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 4207 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 4208 | // <0x2F=> TC1 Overflow Trigger |
| 4209 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 4210 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 4211 | // <0x32=> TC2 Overflow Trigger |
| 4212 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 4213 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 4214 | // <0x35=> TC3 Overflow Trigger |
| 4215 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 4216 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 4217 | // <0x38=> TC4 Overflow Trigger |
| 4218 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 4219 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 4220 | // <0x3B=> TC5 Overflow Trigger |
| 4221 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 4222 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 4223 | // <0x3E=> TC6 Overflow Trigger |
| 4224 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 4225 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 4226 | // <0x41=> TC7 Overflow Trigger |
| 4227 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 4228 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 4229 | // <0x44=> ADC0 Result Ready Trigger |
| 4230 | // <0x45=> ADC0 Sequencing Trigger |
| 4231 | // <0x46=> ADC1 Result Ready Trigger |
| 4232 | // <0x47=> ADC1 Sequencing Trigger |
| 4233 | // <0x48=> DAC Empty 0 Trigger |
| 4234 | // <0x49=> DAC Empty 1 Trigger |
| 4235 | // <0x4A=> DAC Result Ready 0 Trigger |
| 4236 | // <0x4B=> DAC Result Ready 1 Trigger |
| 4237 | // <0x4C=> I2S Rx 0 Trigger |
| 4238 | // <0x4D=> I2S Rx 1 Trigger |
| 4239 | // <0x4E=> I2S Tx 0 Trigger |
| 4240 | // <0x4F=> I2S Tx 1 Trigger |
| 4241 | // <0x50=> PCC RX Trigger |
| 4242 | // <0x51=> AES Write Trigger |
| 4243 | // <0x52=> AES Read Trigger |
| 4244 | // <0x53=> QSPI Rx Trigger |
| 4245 | // <0x54=> QSPI Tx Trigger |
| 4246 | // <i> Defines the peripheral trigger which is source of the transfer |
| 4247 | // <id> dmac_trifsrc_18 |
| 4248 | #ifndef CONF_DMAC_TRIGSRC_18 |
| 4249 | #define CONF_DMAC_TRIGSRC_18 0 |
| 4250 | #endif |
| 4251 | |
| 4252 | // <o> Channel Arbitration Level |
| 4253 | // <0=> Channel priority 0 |
| 4254 | // <1=> Channel priority 1 |
| 4255 | // <2=> Channel priority 2 |
| 4256 | // <3=> Channel priority 3 |
| 4257 | // <i> Defines the arbitration level for this channel |
| 4258 | // <id> dmac_lvl_18 |
| 4259 | #ifndef CONF_DMAC_LVL_18 |
| 4260 | #define CONF_DMAC_LVL_18 0 |
| 4261 | #endif |
| 4262 | |
| 4263 | // <q> Channel Event Output |
| 4264 | // <i> Indicates whether channel event generation is enabled or not |
| 4265 | // <id> dmac_evoe_18 |
| 4266 | #ifndef CONF_DMAC_EVOE_18 |
| 4267 | #define CONF_DMAC_EVOE_18 0 |
| 4268 | #endif |
| 4269 | |
| 4270 | // <q> Channel Event Input |
| 4271 | // <i> Indicates whether channel event reception is enabled or not |
| 4272 | // <id> dmac_evie_18 |
| 4273 | #ifndef CONF_DMAC_EVIE_18 |
| 4274 | #define CONF_DMAC_EVIE_18 0 |
| 4275 | #endif |
| 4276 | |
| 4277 | // <o> Event Input Action |
| 4278 | // <0=> No action |
| 4279 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 4280 | // <2=> Conditional transfer trigger |
| 4281 | // <3=> Conditional block transfer |
| 4282 | // <4=> Channel suspend operation |
| 4283 | // <5=> Channel resume operation |
| 4284 | // <6=> Skip next block suspend action |
| 4285 | // <i> Defines the event input action |
| 4286 | // <id> dmac_evact_18 |
| 4287 | #ifndef CONF_DMAC_EVACT_18 |
| 4288 | #define CONF_DMAC_EVACT_18 0 |
| 4289 | #endif |
| 4290 | |
| 4291 | // <o> Address Increment Step Size |
| 4292 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 4293 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 4294 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 4295 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 4296 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 4297 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 4298 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 4299 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 4300 | // <i> Defines the address increment step size, applies to source or destination address |
| 4301 | // <id> dmac_stepsize_18 |
| 4302 | #ifndef CONF_DMAC_STEPSIZE_18 |
| 4303 | #define CONF_DMAC_STEPSIZE_18 0 |
| 4304 | #endif |
| 4305 | |
| 4306 | // <o> Step Selection |
| 4307 | // <0=> Step size settings apply to the destination address |
| 4308 | // <1=> Step size settings apply to the source address |
| 4309 | // <i> Defines whether source or destination addresses are using the step size settings |
| 4310 | // <id> dmac_stepsel_18 |
| 4311 | #ifndef CONF_DMAC_STEPSEL_18 |
| 4312 | #define CONF_DMAC_STEPSEL_18 0 |
| 4313 | #endif |
| 4314 | |
| 4315 | // <q> Source Address Increment |
| 4316 | // <i> Indicates whether the source address incrementation is enabled or not |
| 4317 | // <id> dmac_srcinc_18 |
| 4318 | #ifndef CONF_DMAC_SRCINC_18 |
| 4319 | #define CONF_DMAC_SRCINC_18 0 |
| 4320 | #endif |
| 4321 | |
| 4322 | // <q> Destination Address Increment |
| 4323 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 4324 | // <id> dmac_dstinc_18 |
| 4325 | #ifndef CONF_DMAC_DSTINC_18 |
| 4326 | #define CONF_DMAC_DSTINC_18 0 |
| 4327 | #endif |
| 4328 | |
| 4329 | // <o> Beat Size |
| 4330 | // <0=> 8-bit bus transfer |
| 4331 | // <1=> 16-bit bus transfer |
| 4332 | // <2=> 32-bit bus transfer |
| 4333 | // <i> Defines the size of one beat |
| 4334 | // <id> dmac_beatsize_18 |
| 4335 | #ifndef CONF_DMAC_BEATSIZE_18 |
| 4336 | #define CONF_DMAC_BEATSIZE_18 0 |
| 4337 | #endif |
| 4338 | |
| 4339 | // <o> Block Action |
| 4340 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 4341 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 4342 | // <2=> Channel suspend operation is complete |
| 4343 | // <3=> Both channel suspend operation and block interrupt |
| 4344 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 4345 | // <id> dmac_blockact_18 |
| 4346 | #ifndef CONF_DMAC_BLOCKACT_18 |
| 4347 | #define CONF_DMAC_BLOCKACT_18 0 |
| 4348 | #endif |
| 4349 | |
| 4350 | // <o> Event Output Selection |
| 4351 | // <0=> Event generation disabled |
| 4352 | // <1=> Event strobe when block transfer complete |
| 4353 | // <3=> Event strobe when beat transfer complete |
| 4354 | // <i> Defines the event output selection |
| 4355 | // <id> dmac_evosel_18 |
| 4356 | #ifndef CONF_DMAC_EVOSEL_18 |
| 4357 | #define CONF_DMAC_EVOSEL_18 0 |
| 4358 | #endif |
| 4359 | // </e> |
| 4360 | |
| 4361 | // <e> Channel 19 settings |
| 4362 | // <id> dmac_channel_19_settings |
| 4363 | #ifndef CONF_DMAC_CHANNEL_19_SETTINGS |
| 4364 | #define CONF_DMAC_CHANNEL_19_SETTINGS 0 |
| 4365 | #endif |
| 4366 | |
| 4367 | // <q> Channel Run in Standby |
| 4368 | // <i> Indicates whether channel 19 is running in standby mode or not |
| 4369 | // <id> dmac_runstdby_19 |
| 4370 | #ifndef CONF_DMAC_RUNSTDBY_19 |
| 4371 | #define CONF_DMAC_RUNSTDBY_19 0 |
| 4372 | #endif |
| 4373 | |
| 4374 | // <o> Trigger action |
| 4375 | // <0=> One trigger required for each block transfer |
| 4376 | // <2=> One trigger required for each beat transfer |
| 4377 | // <3=> One trigger required for each transaction |
| 4378 | // <i> Defines the trigger action used for a transfer |
| 4379 | // <id> dmac_trigact_19 |
| 4380 | #ifndef CONF_DMAC_TRIGACT_19 |
| 4381 | #define CONF_DMAC_TRIGACT_19 0 |
| 4382 | #endif |
| 4383 | |
| 4384 | // <o> Trigger source |
| 4385 | // <0x00=> Only software/event triggers |
| 4386 | // <0x01=> RTC Time Stamp Trigger |
| 4387 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 4388 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 4389 | // <0x04=> SERCOM0 RX Trigger |
| 4390 | // <0x05=> SERCOM0 TX Trigger |
| 4391 | // <0x06=> SERCOM1 RX Trigger |
| 4392 | // <0x07=> SERCOM1 TX Trigger |
| 4393 | // <0x08=> SERCOM2 RX Trigger |
| 4394 | // <0x09=> SERCOM2 TX Trigger |
| 4395 | // <0x0A=> SERCOM3 RX Trigger |
| 4396 | // <0x0B=> SERCOM3 TX Trigger |
| 4397 | // <0x0C=> SERCOM4 RX Trigger |
| 4398 | // <0x0D=> SERCOM4 TX Trigger |
| 4399 | // <0x0E=> SERCOM5 RX Trigger |
| 4400 | // <0x0F=> SERCOM5 TX Trigger |
| 4401 | // <0x10=> SERCOM6 RX Trigger |
| 4402 | // <0x11=> SERCOM6 TX Trigger |
| 4403 | // <0x12=> SERCOM7 RX Trigger |
| 4404 | // <0x13=> SERCOM7 TX Trigger |
| 4405 | // <0x14=> CAN0 DEBUG Trigger |
| 4406 | // <0x15=> CAN1 DEBUG Trigger |
| 4407 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 4408 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 4409 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 4410 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 4411 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 4412 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 4413 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 4414 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 4415 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 4416 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 4417 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 4418 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 4419 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 4420 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 4421 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 4422 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 4423 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 4424 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 4425 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 4426 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 4427 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 4428 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 4429 | // <0x2C=> TC0 Overflow Trigger |
| 4430 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 4431 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 4432 | // <0x2F=> TC1 Overflow Trigger |
| 4433 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 4434 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 4435 | // <0x32=> TC2 Overflow Trigger |
| 4436 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 4437 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 4438 | // <0x35=> TC3 Overflow Trigger |
| 4439 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 4440 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 4441 | // <0x38=> TC4 Overflow Trigger |
| 4442 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 4443 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 4444 | // <0x3B=> TC5 Overflow Trigger |
| 4445 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 4446 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 4447 | // <0x3E=> TC6 Overflow Trigger |
| 4448 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 4449 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 4450 | // <0x41=> TC7 Overflow Trigger |
| 4451 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 4452 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 4453 | // <0x44=> ADC0 Result Ready Trigger |
| 4454 | // <0x45=> ADC0 Sequencing Trigger |
| 4455 | // <0x46=> ADC1 Result Ready Trigger |
| 4456 | // <0x47=> ADC1 Sequencing Trigger |
| 4457 | // <0x48=> DAC Empty 0 Trigger |
| 4458 | // <0x49=> DAC Empty 1 Trigger |
| 4459 | // <0x4A=> DAC Result Ready 0 Trigger |
| 4460 | // <0x4B=> DAC Result Ready 1 Trigger |
| 4461 | // <0x4C=> I2S Rx 0 Trigger |
| 4462 | // <0x4D=> I2S Rx 1 Trigger |
| 4463 | // <0x4E=> I2S Tx 0 Trigger |
| 4464 | // <0x4F=> I2S Tx 1 Trigger |
| 4465 | // <0x50=> PCC RX Trigger |
| 4466 | // <0x51=> AES Write Trigger |
| 4467 | // <0x52=> AES Read Trigger |
| 4468 | // <0x53=> QSPI Rx Trigger |
| 4469 | // <0x54=> QSPI Tx Trigger |
| 4470 | // <i> Defines the peripheral trigger which is source of the transfer |
| 4471 | // <id> dmac_trifsrc_19 |
| 4472 | #ifndef CONF_DMAC_TRIGSRC_19 |
| 4473 | #define CONF_DMAC_TRIGSRC_19 0 |
| 4474 | #endif |
| 4475 | |
| 4476 | // <o> Channel Arbitration Level |
| 4477 | // <0=> Channel priority 0 |
| 4478 | // <1=> Channel priority 1 |
| 4479 | // <2=> Channel priority 2 |
| 4480 | // <3=> Channel priority 3 |
| 4481 | // <i> Defines the arbitration level for this channel |
| 4482 | // <id> dmac_lvl_19 |
| 4483 | #ifndef CONF_DMAC_LVL_19 |
| 4484 | #define CONF_DMAC_LVL_19 0 |
| 4485 | #endif |
| 4486 | |
| 4487 | // <q> Channel Event Output |
| 4488 | // <i> Indicates whether channel event generation is enabled or not |
| 4489 | // <id> dmac_evoe_19 |
| 4490 | #ifndef CONF_DMAC_EVOE_19 |
| 4491 | #define CONF_DMAC_EVOE_19 0 |
| 4492 | #endif |
| 4493 | |
| 4494 | // <q> Channel Event Input |
| 4495 | // <i> Indicates whether channel event reception is enabled or not |
| 4496 | // <id> dmac_evie_19 |
| 4497 | #ifndef CONF_DMAC_EVIE_19 |
| 4498 | #define CONF_DMAC_EVIE_19 0 |
| 4499 | #endif |
| 4500 | |
| 4501 | // <o> Event Input Action |
| 4502 | // <0=> No action |
| 4503 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 4504 | // <2=> Conditional transfer trigger |
| 4505 | // <3=> Conditional block transfer |
| 4506 | // <4=> Channel suspend operation |
| 4507 | // <5=> Channel resume operation |
| 4508 | // <6=> Skip next block suspend action |
| 4509 | // <i> Defines the event input action |
| 4510 | // <id> dmac_evact_19 |
| 4511 | #ifndef CONF_DMAC_EVACT_19 |
| 4512 | #define CONF_DMAC_EVACT_19 0 |
| 4513 | #endif |
| 4514 | |
| 4515 | // <o> Address Increment Step Size |
| 4516 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 4517 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 4518 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 4519 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 4520 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 4521 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 4522 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 4523 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 4524 | // <i> Defines the address increment step size, applies to source or destination address |
| 4525 | // <id> dmac_stepsize_19 |
| 4526 | #ifndef CONF_DMAC_STEPSIZE_19 |
| 4527 | #define CONF_DMAC_STEPSIZE_19 0 |
| 4528 | #endif |
| 4529 | |
| 4530 | // <o> Step Selection |
| 4531 | // <0=> Step size settings apply to the destination address |
| 4532 | // <1=> Step size settings apply to the source address |
| 4533 | // <i> Defines whether source or destination addresses are using the step size settings |
| 4534 | // <id> dmac_stepsel_19 |
| 4535 | #ifndef CONF_DMAC_STEPSEL_19 |
| 4536 | #define CONF_DMAC_STEPSEL_19 0 |
| 4537 | #endif |
| 4538 | |
| 4539 | // <q> Source Address Increment |
| 4540 | // <i> Indicates whether the source address incrementation is enabled or not |
| 4541 | // <id> dmac_srcinc_19 |
| 4542 | #ifndef CONF_DMAC_SRCINC_19 |
| 4543 | #define CONF_DMAC_SRCINC_19 0 |
| 4544 | #endif |
| 4545 | |
| 4546 | // <q> Destination Address Increment |
| 4547 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 4548 | // <id> dmac_dstinc_19 |
| 4549 | #ifndef CONF_DMAC_DSTINC_19 |
| 4550 | #define CONF_DMAC_DSTINC_19 0 |
| 4551 | #endif |
| 4552 | |
| 4553 | // <o> Beat Size |
| 4554 | // <0=> 8-bit bus transfer |
| 4555 | // <1=> 16-bit bus transfer |
| 4556 | // <2=> 32-bit bus transfer |
| 4557 | // <i> Defines the size of one beat |
| 4558 | // <id> dmac_beatsize_19 |
| 4559 | #ifndef CONF_DMAC_BEATSIZE_19 |
| 4560 | #define CONF_DMAC_BEATSIZE_19 0 |
| 4561 | #endif |
| 4562 | |
| 4563 | // <o> Block Action |
| 4564 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 4565 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 4566 | // <2=> Channel suspend operation is complete |
| 4567 | // <3=> Both channel suspend operation and block interrupt |
| 4568 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 4569 | // <id> dmac_blockact_19 |
| 4570 | #ifndef CONF_DMAC_BLOCKACT_19 |
| 4571 | #define CONF_DMAC_BLOCKACT_19 0 |
| 4572 | #endif |
| 4573 | |
| 4574 | // <o> Event Output Selection |
| 4575 | // <0=> Event generation disabled |
| 4576 | // <1=> Event strobe when block transfer complete |
| 4577 | // <3=> Event strobe when beat transfer complete |
| 4578 | // <i> Defines the event output selection |
| 4579 | // <id> dmac_evosel_19 |
| 4580 | #ifndef CONF_DMAC_EVOSEL_19 |
| 4581 | #define CONF_DMAC_EVOSEL_19 0 |
| 4582 | #endif |
| 4583 | // </e> |
| 4584 | |
| 4585 | // <e> Channel 20 settings |
| 4586 | // <id> dmac_channel_20_settings |
| 4587 | #ifndef CONF_DMAC_CHANNEL_20_SETTINGS |
| 4588 | #define CONF_DMAC_CHANNEL_20_SETTINGS 0 |
| 4589 | #endif |
| 4590 | |
| 4591 | // <q> Channel Run in Standby |
| 4592 | // <i> Indicates whether channel 20 is running in standby mode or not |
| 4593 | // <id> dmac_runstdby_20 |
| 4594 | #ifndef CONF_DMAC_RUNSTDBY_20 |
| 4595 | #define CONF_DMAC_RUNSTDBY_20 0 |
| 4596 | #endif |
| 4597 | |
| 4598 | // <o> Trigger action |
| 4599 | // <0=> One trigger required for each block transfer |
| 4600 | // <2=> One trigger required for each beat transfer |
| 4601 | // <3=> One trigger required for each transaction |
| 4602 | // <i> Defines the trigger action used for a transfer |
| 4603 | // <id> dmac_trigact_20 |
| 4604 | #ifndef CONF_DMAC_TRIGACT_20 |
| 4605 | #define CONF_DMAC_TRIGACT_20 0 |
| 4606 | #endif |
| 4607 | |
| 4608 | // <o> Trigger source |
| 4609 | // <0x00=> Only software/event triggers |
| 4610 | // <0x01=> RTC Time Stamp Trigger |
| 4611 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 4612 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 4613 | // <0x04=> SERCOM0 RX Trigger |
| 4614 | // <0x05=> SERCOM0 TX Trigger |
| 4615 | // <0x06=> SERCOM1 RX Trigger |
| 4616 | // <0x07=> SERCOM1 TX Trigger |
| 4617 | // <0x08=> SERCOM2 RX Trigger |
| 4618 | // <0x09=> SERCOM2 TX Trigger |
| 4619 | // <0x0A=> SERCOM3 RX Trigger |
| 4620 | // <0x0B=> SERCOM3 TX Trigger |
| 4621 | // <0x0C=> SERCOM4 RX Trigger |
| 4622 | // <0x0D=> SERCOM4 TX Trigger |
| 4623 | // <0x0E=> SERCOM5 RX Trigger |
| 4624 | // <0x0F=> SERCOM5 TX Trigger |
| 4625 | // <0x10=> SERCOM6 RX Trigger |
| 4626 | // <0x11=> SERCOM6 TX Trigger |
| 4627 | // <0x12=> SERCOM7 RX Trigger |
| 4628 | // <0x13=> SERCOM7 TX Trigger |
| 4629 | // <0x14=> CAN0 DEBUG Trigger |
| 4630 | // <0x15=> CAN1 DEBUG Trigger |
| 4631 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 4632 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 4633 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 4634 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 4635 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 4636 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 4637 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 4638 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 4639 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 4640 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 4641 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 4642 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 4643 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 4644 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 4645 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 4646 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 4647 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 4648 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 4649 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 4650 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 4651 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 4652 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 4653 | // <0x2C=> TC0 Overflow Trigger |
| 4654 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 4655 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 4656 | // <0x2F=> TC1 Overflow Trigger |
| 4657 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 4658 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 4659 | // <0x32=> TC2 Overflow Trigger |
| 4660 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 4661 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 4662 | // <0x35=> TC3 Overflow Trigger |
| 4663 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 4664 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 4665 | // <0x38=> TC4 Overflow Trigger |
| 4666 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 4667 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 4668 | // <0x3B=> TC5 Overflow Trigger |
| 4669 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 4670 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 4671 | // <0x3E=> TC6 Overflow Trigger |
| 4672 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 4673 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 4674 | // <0x41=> TC7 Overflow Trigger |
| 4675 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 4676 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 4677 | // <0x44=> ADC0 Result Ready Trigger |
| 4678 | // <0x45=> ADC0 Sequencing Trigger |
| 4679 | // <0x46=> ADC1 Result Ready Trigger |
| 4680 | // <0x47=> ADC1 Sequencing Trigger |
| 4681 | // <0x48=> DAC Empty 0 Trigger |
| 4682 | // <0x49=> DAC Empty 1 Trigger |
| 4683 | // <0x4A=> DAC Result Ready 0 Trigger |
| 4684 | // <0x4B=> DAC Result Ready 1 Trigger |
| 4685 | // <0x4C=> I2S Rx 0 Trigger |
| 4686 | // <0x4D=> I2S Rx 1 Trigger |
| 4687 | // <0x4E=> I2S Tx 0 Trigger |
| 4688 | // <0x4F=> I2S Tx 1 Trigger |
| 4689 | // <0x50=> PCC RX Trigger |
| 4690 | // <0x51=> AES Write Trigger |
| 4691 | // <0x52=> AES Read Trigger |
| 4692 | // <0x53=> QSPI Rx Trigger |
| 4693 | // <0x54=> QSPI Tx Trigger |
| 4694 | // <i> Defines the peripheral trigger which is source of the transfer |
| 4695 | // <id> dmac_trifsrc_20 |
| 4696 | #ifndef CONF_DMAC_TRIGSRC_20 |
| 4697 | #define CONF_DMAC_TRIGSRC_20 0 |
| 4698 | #endif |
| 4699 | |
| 4700 | // <o> Channel Arbitration Level |
| 4701 | // <0=> Channel priority 0 |
| 4702 | // <1=> Channel priority 1 |
| 4703 | // <2=> Channel priority 2 |
| 4704 | // <3=> Channel priority 3 |
| 4705 | // <i> Defines the arbitration level for this channel |
| 4706 | // <id> dmac_lvl_20 |
| 4707 | #ifndef CONF_DMAC_LVL_20 |
| 4708 | #define CONF_DMAC_LVL_20 0 |
| 4709 | #endif |
| 4710 | |
| 4711 | // <q> Channel Event Output |
| 4712 | // <i> Indicates whether channel event generation is enabled or not |
| 4713 | // <id> dmac_evoe_20 |
| 4714 | #ifndef CONF_DMAC_EVOE_20 |
| 4715 | #define CONF_DMAC_EVOE_20 0 |
| 4716 | #endif |
| 4717 | |
| 4718 | // <q> Channel Event Input |
| 4719 | // <i> Indicates whether channel event reception is enabled or not |
| 4720 | // <id> dmac_evie_20 |
| 4721 | #ifndef CONF_DMAC_EVIE_20 |
| 4722 | #define CONF_DMAC_EVIE_20 0 |
| 4723 | #endif |
| 4724 | |
| 4725 | // <o> Event Input Action |
| 4726 | // <0=> No action |
| 4727 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 4728 | // <2=> Conditional transfer trigger |
| 4729 | // <3=> Conditional block transfer |
| 4730 | // <4=> Channel suspend operation |
| 4731 | // <5=> Channel resume operation |
| 4732 | // <6=> Skip next block suspend action |
| 4733 | // <i> Defines the event input action |
| 4734 | // <id> dmac_evact_20 |
| 4735 | #ifndef CONF_DMAC_EVACT_20 |
| 4736 | #define CONF_DMAC_EVACT_20 0 |
| 4737 | #endif |
| 4738 | |
| 4739 | // <o> Address Increment Step Size |
| 4740 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 4741 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 4742 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 4743 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 4744 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 4745 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 4746 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 4747 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 4748 | // <i> Defines the address increment step size, applies to source or destination address |
| 4749 | // <id> dmac_stepsize_20 |
| 4750 | #ifndef CONF_DMAC_STEPSIZE_20 |
| 4751 | #define CONF_DMAC_STEPSIZE_20 0 |
| 4752 | #endif |
| 4753 | |
| 4754 | // <o> Step Selection |
| 4755 | // <0=> Step size settings apply to the destination address |
| 4756 | // <1=> Step size settings apply to the source address |
| 4757 | // <i> Defines whether source or destination addresses are using the step size settings |
| 4758 | // <id> dmac_stepsel_20 |
| 4759 | #ifndef CONF_DMAC_STEPSEL_20 |
| 4760 | #define CONF_DMAC_STEPSEL_20 0 |
| 4761 | #endif |
| 4762 | |
| 4763 | // <q> Source Address Increment |
| 4764 | // <i> Indicates whether the source address incrementation is enabled or not |
| 4765 | // <id> dmac_srcinc_20 |
| 4766 | #ifndef CONF_DMAC_SRCINC_20 |
| 4767 | #define CONF_DMAC_SRCINC_20 0 |
| 4768 | #endif |
| 4769 | |
| 4770 | // <q> Destination Address Increment |
| 4771 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 4772 | // <id> dmac_dstinc_20 |
| 4773 | #ifndef CONF_DMAC_DSTINC_20 |
| 4774 | #define CONF_DMAC_DSTINC_20 0 |
| 4775 | #endif |
| 4776 | |
| 4777 | // <o> Beat Size |
| 4778 | // <0=> 8-bit bus transfer |
| 4779 | // <1=> 16-bit bus transfer |
| 4780 | // <2=> 32-bit bus transfer |
| 4781 | // <i> Defines the size of one beat |
| 4782 | // <id> dmac_beatsize_20 |
| 4783 | #ifndef CONF_DMAC_BEATSIZE_20 |
| 4784 | #define CONF_DMAC_BEATSIZE_20 0 |
| 4785 | #endif |
| 4786 | |
| 4787 | // <o> Block Action |
| 4788 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 4789 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 4790 | // <2=> Channel suspend operation is complete |
| 4791 | // <3=> Both channel suspend operation and block interrupt |
| 4792 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 4793 | // <id> dmac_blockact_20 |
| 4794 | #ifndef CONF_DMAC_BLOCKACT_20 |
| 4795 | #define CONF_DMAC_BLOCKACT_20 0 |
| 4796 | #endif |
| 4797 | |
| 4798 | // <o> Event Output Selection |
| 4799 | // <0=> Event generation disabled |
| 4800 | // <1=> Event strobe when block transfer complete |
| 4801 | // <3=> Event strobe when beat transfer complete |
| 4802 | // <i> Defines the event output selection |
| 4803 | // <id> dmac_evosel_20 |
| 4804 | #ifndef CONF_DMAC_EVOSEL_20 |
| 4805 | #define CONF_DMAC_EVOSEL_20 0 |
| 4806 | #endif |
| 4807 | // </e> |
| 4808 | |
| 4809 | // <e> Channel 21 settings |
| 4810 | // <id> dmac_channel_21_settings |
| 4811 | #ifndef CONF_DMAC_CHANNEL_21_SETTINGS |
| 4812 | #define CONF_DMAC_CHANNEL_21_SETTINGS 0 |
| 4813 | #endif |
| 4814 | |
| 4815 | // <q> Channel Run in Standby |
| 4816 | // <i> Indicates whether channel 21 is running in standby mode or not |
| 4817 | // <id> dmac_runstdby_21 |
| 4818 | #ifndef CONF_DMAC_RUNSTDBY_21 |
| 4819 | #define CONF_DMAC_RUNSTDBY_21 0 |
| 4820 | #endif |
| 4821 | |
| 4822 | // <o> Trigger action |
| 4823 | // <0=> One trigger required for each block transfer |
| 4824 | // <2=> One trigger required for each beat transfer |
| 4825 | // <3=> One trigger required for each transaction |
| 4826 | // <i> Defines the trigger action used for a transfer |
| 4827 | // <id> dmac_trigact_21 |
| 4828 | #ifndef CONF_DMAC_TRIGACT_21 |
| 4829 | #define CONF_DMAC_TRIGACT_21 0 |
| 4830 | #endif |
| 4831 | |
| 4832 | // <o> Trigger source |
| 4833 | // <0x00=> Only software/event triggers |
| 4834 | // <0x01=> RTC Time Stamp Trigger |
| 4835 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 4836 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 4837 | // <0x04=> SERCOM0 RX Trigger |
| 4838 | // <0x05=> SERCOM0 TX Trigger |
| 4839 | // <0x06=> SERCOM1 RX Trigger |
| 4840 | // <0x07=> SERCOM1 TX Trigger |
| 4841 | // <0x08=> SERCOM2 RX Trigger |
| 4842 | // <0x09=> SERCOM2 TX Trigger |
| 4843 | // <0x0A=> SERCOM3 RX Trigger |
| 4844 | // <0x0B=> SERCOM3 TX Trigger |
| 4845 | // <0x0C=> SERCOM4 RX Trigger |
| 4846 | // <0x0D=> SERCOM4 TX Trigger |
| 4847 | // <0x0E=> SERCOM5 RX Trigger |
| 4848 | // <0x0F=> SERCOM5 TX Trigger |
| 4849 | // <0x10=> SERCOM6 RX Trigger |
| 4850 | // <0x11=> SERCOM6 TX Trigger |
| 4851 | // <0x12=> SERCOM7 RX Trigger |
| 4852 | // <0x13=> SERCOM7 TX Trigger |
| 4853 | // <0x14=> CAN0 DEBUG Trigger |
| 4854 | // <0x15=> CAN1 DEBUG Trigger |
| 4855 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 4856 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 4857 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 4858 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 4859 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 4860 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 4861 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 4862 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 4863 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 4864 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 4865 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 4866 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 4867 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 4868 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 4869 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 4870 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 4871 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 4872 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 4873 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 4874 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 4875 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 4876 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 4877 | // <0x2C=> TC0 Overflow Trigger |
| 4878 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 4879 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 4880 | // <0x2F=> TC1 Overflow Trigger |
| 4881 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 4882 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 4883 | // <0x32=> TC2 Overflow Trigger |
| 4884 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 4885 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 4886 | // <0x35=> TC3 Overflow Trigger |
| 4887 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 4888 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 4889 | // <0x38=> TC4 Overflow Trigger |
| 4890 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 4891 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 4892 | // <0x3B=> TC5 Overflow Trigger |
| 4893 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 4894 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 4895 | // <0x3E=> TC6 Overflow Trigger |
| 4896 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 4897 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 4898 | // <0x41=> TC7 Overflow Trigger |
| 4899 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 4900 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 4901 | // <0x44=> ADC0 Result Ready Trigger |
| 4902 | // <0x45=> ADC0 Sequencing Trigger |
| 4903 | // <0x46=> ADC1 Result Ready Trigger |
| 4904 | // <0x47=> ADC1 Sequencing Trigger |
| 4905 | // <0x48=> DAC Empty 0 Trigger |
| 4906 | // <0x49=> DAC Empty 1 Trigger |
| 4907 | // <0x4A=> DAC Result Ready 0 Trigger |
| 4908 | // <0x4B=> DAC Result Ready 1 Trigger |
| 4909 | // <0x4C=> I2S Rx 0 Trigger |
| 4910 | // <0x4D=> I2S Rx 1 Trigger |
| 4911 | // <0x4E=> I2S Tx 0 Trigger |
| 4912 | // <0x4F=> I2S Tx 1 Trigger |
| 4913 | // <0x50=> PCC RX Trigger |
| 4914 | // <0x51=> AES Write Trigger |
| 4915 | // <0x52=> AES Read Trigger |
| 4916 | // <0x53=> QSPI Rx Trigger |
| 4917 | // <0x54=> QSPI Tx Trigger |
| 4918 | // <i> Defines the peripheral trigger which is source of the transfer |
| 4919 | // <id> dmac_trifsrc_21 |
| 4920 | #ifndef CONF_DMAC_TRIGSRC_21 |
| 4921 | #define CONF_DMAC_TRIGSRC_21 0 |
| 4922 | #endif |
| 4923 | |
| 4924 | // <o> Channel Arbitration Level |
| 4925 | // <0=> Channel priority 0 |
| 4926 | // <1=> Channel priority 1 |
| 4927 | // <2=> Channel priority 2 |
| 4928 | // <3=> Channel priority 3 |
| 4929 | // <i> Defines the arbitration level for this channel |
| 4930 | // <id> dmac_lvl_21 |
| 4931 | #ifndef CONF_DMAC_LVL_21 |
| 4932 | #define CONF_DMAC_LVL_21 0 |
| 4933 | #endif |
| 4934 | |
| 4935 | // <q> Channel Event Output |
| 4936 | // <i> Indicates whether channel event generation is enabled or not |
| 4937 | // <id> dmac_evoe_21 |
| 4938 | #ifndef CONF_DMAC_EVOE_21 |
| 4939 | #define CONF_DMAC_EVOE_21 0 |
| 4940 | #endif |
| 4941 | |
| 4942 | // <q> Channel Event Input |
| 4943 | // <i> Indicates whether channel event reception is enabled or not |
| 4944 | // <id> dmac_evie_21 |
| 4945 | #ifndef CONF_DMAC_EVIE_21 |
| 4946 | #define CONF_DMAC_EVIE_21 0 |
| 4947 | #endif |
| 4948 | |
| 4949 | // <o> Event Input Action |
| 4950 | // <0=> No action |
| 4951 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 4952 | // <2=> Conditional transfer trigger |
| 4953 | // <3=> Conditional block transfer |
| 4954 | // <4=> Channel suspend operation |
| 4955 | // <5=> Channel resume operation |
| 4956 | // <6=> Skip next block suspend action |
| 4957 | // <i> Defines the event input action |
| 4958 | // <id> dmac_evact_21 |
| 4959 | #ifndef CONF_DMAC_EVACT_21 |
| 4960 | #define CONF_DMAC_EVACT_21 0 |
| 4961 | #endif |
| 4962 | |
| 4963 | // <o> Address Increment Step Size |
| 4964 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 4965 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 4966 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 4967 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 4968 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 4969 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 4970 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 4971 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 4972 | // <i> Defines the address increment step size, applies to source or destination address |
| 4973 | // <id> dmac_stepsize_21 |
| 4974 | #ifndef CONF_DMAC_STEPSIZE_21 |
| 4975 | #define CONF_DMAC_STEPSIZE_21 0 |
| 4976 | #endif |
| 4977 | |
| 4978 | // <o> Step Selection |
| 4979 | // <0=> Step size settings apply to the destination address |
| 4980 | // <1=> Step size settings apply to the source address |
| 4981 | // <i> Defines whether source or destination addresses are using the step size settings |
| 4982 | // <id> dmac_stepsel_21 |
| 4983 | #ifndef CONF_DMAC_STEPSEL_21 |
| 4984 | #define CONF_DMAC_STEPSEL_21 0 |
| 4985 | #endif |
| 4986 | |
| 4987 | // <q> Source Address Increment |
| 4988 | // <i> Indicates whether the source address incrementation is enabled or not |
| 4989 | // <id> dmac_srcinc_21 |
| 4990 | #ifndef CONF_DMAC_SRCINC_21 |
| 4991 | #define CONF_DMAC_SRCINC_21 0 |
| 4992 | #endif |
| 4993 | |
| 4994 | // <q> Destination Address Increment |
| 4995 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 4996 | // <id> dmac_dstinc_21 |
| 4997 | #ifndef CONF_DMAC_DSTINC_21 |
| 4998 | #define CONF_DMAC_DSTINC_21 0 |
| 4999 | #endif |
| 5000 | |
| 5001 | // <o> Beat Size |
| 5002 | // <0=> 8-bit bus transfer |
| 5003 | // <1=> 16-bit bus transfer |
| 5004 | // <2=> 32-bit bus transfer |
| 5005 | // <i> Defines the size of one beat |
| 5006 | // <id> dmac_beatsize_21 |
| 5007 | #ifndef CONF_DMAC_BEATSIZE_21 |
| 5008 | #define CONF_DMAC_BEATSIZE_21 0 |
| 5009 | #endif |
| 5010 | |
| 5011 | // <o> Block Action |
| 5012 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 5013 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 5014 | // <2=> Channel suspend operation is complete |
| 5015 | // <3=> Both channel suspend operation and block interrupt |
| 5016 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 5017 | // <id> dmac_blockact_21 |
| 5018 | #ifndef CONF_DMAC_BLOCKACT_21 |
| 5019 | #define CONF_DMAC_BLOCKACT_21 0 |
| 5020 | #endif |
| 5021 | |
| 5022 | // <o> Event Output Selection |
| 5023 | // <0=> Event generation disabled |
| 5024 | // <1=> Event strobe when block transfer complete |
| 5025 | // <3=> Event strobe when beat transfer complete |
| 5026 | // <i> Defines the event output selection |
| 5027 | // <id> dmac_evosel_21 |
| 5028 | #ifndef CONF_DMAC_EVOSEL_21 |
| 5029 | #define CONF_DMAC_EVOSEL_21 0 |
| 5030 | #endif |
| 5031 | // </e> |
| 5032 | |
| 5033 | // <e> Channel 22 settings |
| 5034 | // <id> dmac_channel_22_settings |
| 5035 | #ifndef CONF_DMAC_CHANNEL_22_SETTINGS |
| 5036 | #define CONF_DMAC_CHANNEL_22_SETTINGS 0 |
| 5037 | #endif |
| 5038 | |
| 5039 | // <q> Channel Run in Standby |
| 5040 | // <i> Indicates whether channel 22 is running in standby mode or not |
| 5041 | // <id> dmac_runstdby_22 |
| 5042 | #ifndef CONF_DMAC_RUNSTDBY_22 |
| 5043 | #define CONF_DMAC_RUNSTDBY_22 0 |
| 5044 | #endif |
| 5045 | |
| 5046 | // <o> Trigger action |
| 5047 | // <0=> One trigger required for each block transfer |
| 5048 | // <2=> One trigger required for each beat transfer |
| 5049 | // <3=> One trigger required for each transaction |
| 5050 | // <i> Defines the trigger action used for a transfer |
| 5051 | // <id> dmac_trigact_22 |
| 5052 | #ifndef CONF_DMAC_TRIGACT_22 |
| 5053 | #define CONF_DMAC_TRIGACT_22 0 |
| 5054 | #endif |
| 5055 | |
| 5056 | // <o> Trigger source |
| 5057 | // <0x00=> Only software/event triggers |
| 5058 | // <0x01=> RTC Time Stamp Trigger |
| 5059 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 5060 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 5061 | // <0x04=> SERCOM0 RX Trigger |
| 5062 | // <0x05=> SERCOM0 TX Trigger |
| 5063 | // <0x06=> SERCOM1 RX Trigger |
| 5064 | // <0x07=> SERCOM1 TX Trigger |
| 5065 | // <0x08=> SERCOM2 RX Trigger |
| 5066 | // <0x09=> SERCOM2 TX Trigger |
| 5067 | // <0x0A=> SERCOM3 RX Trigger |
| 5068 | // <0x0B=> SERCOM3 TX Trigger |
| 5069 | // <0x0C=> SERCOM4 RX Trigger |
| 5070 | // <0x0D=> SERCOM4 TX Trigger |
| 5071 | // <0x0E=> SERCOM5 RX Trigger |
| 5072 | // <0x0F=> SERCOM5 TX Trigger |
| 5073 | // <0x10=> SERCOM6 RX Trigger |
| 5074 | // <0x11=> SERCOM6 TX Trigger |
| 5075 | // <0x12=> SERCOM7 RX Trigger |
| 5076 | // <0x13=> SERCOM7 TX Trigger |
| 5077 | // <0x14=> CAN0 DEBUG Trigger |
| 5078 | // <0x15=> CAN1 DEBUG Trigger |
| 5079 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 5080 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 5081 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 5082 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 5083 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 5084 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 5085 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 5086 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 5087 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 5088 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 5089 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 5090 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 5091 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 5092 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 5093 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 5094 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 5095 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 5096 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 5097 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 5098 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 5099 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 5100 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 5101 | // <0x2C=> TC0 Overflow Trigger |
| 5102 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 5103 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 5104 | // <0x2F=> TC1 Overflow Trigger |
| 5105 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 5106 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 5107 | // <0x32=> TC2 Overflow Trigger |
| 5108 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 5109 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 5110 | // <0x35=> TC3 Overflow Trigger |
| 5111 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 5112 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 5113 | // <0x38=> TC4 Overflow Trigger |
| 5114 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 5115 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 5116 | // <0x3B=> TC5 Overflow Trigger |
| 5117 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 5118 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 5119 | // <0x3E=> TC6 Overflow Trigger |
| 5120 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 5121 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 5122 | // <0x41=> TC7 Overflow Trigger |
| 5123 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 5124 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 5125 | // <0x44=> ADC0 Result Ready Trigger |
| 5126 | // <0x45=> ADC0 Sequencing Trigger |
| 5127 | // <0x46=> ADC1 Result Ready Trigger |
| 5128 | // <0x47=> ADC1 Sequencing Trigger |
| 5129 | // <0x48=> DAC Empty 0 Trigger |
| 5130 | // <0x49=> DAC Empty 1 Trigger |
| 5131 | // <0x4A=> DAC Result Ready 0 Trigger |
| 5132 | // <0x4B=> DAC Result Ready 1 Trigger |
| 5133 | // <0x4C=> I2S Rx 0 Trigger |
| 5134 | // <0x4D=> I2S Rx 1 Trigger |
| 5135 | // <0x4E=> I2S Tx 0 Trigger |
| 5136 | // <0x4F=> I2S Tx 1 Trigger |
| 5137 | // <0x50=> PCC RX Trigger |
| 5138 | // <0x51=> AES Write Trigger |
| 5139 | // <0x52=> AES Read Trigger |
| 5140 | // <0x53=> QSPI Rx Trigger |
| 5141 | // <0x54=> QSPI Tx Trigger |
| 5142 | // <i> Defines the peripheral trigger which is source of the transfer |
| 5143 | // <id> dmac_trifsrc_22 |
| 5144 | #ifndef CONF_DMAC_TRIGSRC_22 |
| 5145 | #define CONF_DMAC_TRIGSRC_22 0 |
| 5146 | #endif |
| 5147 | |
| 5148 | // <o> Channel Arbitration Level |
| 5149 | // <0=> Channel priority 0 |
| 5150 | // <1=> Channel priority 1 |
| 5151 | // <2=> Channel priority 2 |
| 5152 | // <3=> Channel priority 3 |
| 5153 | // <i> Defines the arbitration level for this channel |
| 5154 | // <id> dmac_lvl_22 |
| 5155 | #ifndef CONF_DMAC_LVL_22 |
| 5156 | #define CONF_DMAC_LVL_22 0 |
| 5157 | #endif |
| 5158 | |
| 5159 | // <q> Channel Event Output |
| 5160 | // <i> Indicates whether channel event generation is enabled or not |
| 5161 | // <id> dmac_evoe_22 |
| 5162 | #ifndef CONF_DMAC_EVOE_22 |
| 5163 | #define CONF_DMAC_EVOE_22 0 |
| 5164 | #endif |
| 5165 | |
| 5166 | // <q> Channel Event Input |
| 5167 | // <i> Indicates whether channel event reception is enabled or not |
| 5168 | // <id> dmac_evie_22 |
| 5169 | #ifndef CONF_DMAC_EVIE_22 |
| 5170 | #define CONF_DMAC_EVIE_22 0 |
| 5171 | #endif |
| 5172 | |
| 5173 | // <o> Event Input Action |
| 5174 | // <0=> No action |
| 5175 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 5176 | // <2=> Conditional transfer trigger |
| 5177 | // <3=> Conditional block transfer |
| 5178 | // <4=> Channel suspend operation |
| 5179 | // <5=> Channel resume operation |
| 5180 | // <6=> Skip next block suspend action |
| 5181 | // <i> Defines the event input action |
| 5182 | // <id> dmac_evact_22 |
| 5183 | #ifndef CONF_DMAC_EVACT_22 |
| 5184 | #define CONF_DMAC_EVACT_22 0 |
| 5185 | #endif |
| 5186 | |
| 5187 | // <o> Address Increment Step Size |
| 5188 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 5189 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 5190 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 5191 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 5192 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 5193 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 5194 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 5195 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 5196 | // <i> Defines the address increment step size, applies to source or destination address |
| 5197 | // <id> dmac_stepsize_22 |
| 5198 | #ifndef CONF_DMAC_STEPSIZE_22 |
| 5199 | #define CONF_DMAC_STEPSIZE_22 0 |
| 5200 | #endif |
| 5201 | |
| 5202 | // <o> Step Selection |
| 5203 | // <0=> Step size settings apply to the destination address |
| 5204 | // <1=> Step size settings apply to the source address |
| 5205 | // <i> Defines whether source or destination addresses are using the step size settings |
| 5206 | // <id> dmac_stepsel_22 |
| 5207 | #ifndef CONF_DMAC_STEPSEL_22 |
| 5208 | #define CONF_DMAC_STEPSEL_22 0 |
| 5209 | #endif |
| 5210 | |
| 5211 | // <q> Source Address Increment |
| 5212 | // <i> Indicates whether the source address incrementation is enabled or not |
| 5213 | // <id> dmac_srcinc_22 |
| 5214 | #ifndef CONF_DMAC_SRCINC_22 |
| 5215 | #define CONF_DMAC_SRCINC_22 0 |
| 5216 | #endif |
| 5217 | |
| 5218 | // <q> Destination Address Increment |
| 5219 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 5220 | // <id> dmac_dstinc_22 |
| 5221 | #ifndef CONF_DMAC_DSTINC_22 |
| 5222 | #define CONF_DMAC_DSTINC_22 0 |
| 5223 | #endif |
| 5224 | |
| 5225 | // <o> Beat Size |
| 5226 | // <0=> 8-bit bus transfer |
| 5227 | // <1=> 16-bit bus transfer |
| 5228 | // <2=> 32-bit bus transfer |
| 5229 | // <i> Defines the size of one beat |
| 5230 | // <id> dmac_beatsize_22 |
| 5231 | #ifndef CONF_DMAC_BEATSIZE_22 |
| 5232 | #define CONF_DMAC_BEATSIZE_22 0 |
| 5233 | #endif |
| 5234 | |
| 5235 | // <o> Block Action |
| 5236 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 5237 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 5238 | // <2=> Channel suspend operation is complete |
| 5239 | // <3=> Both channel suspend operation and block interrupt |
| 5240 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 5241 | // <id> dmac_blockact_22 |
| 5242 | #ifndef CONF_DMAC_BLOCKACT_22 |
| 5243 | #define CONF_DMAC_BLOCKACT_22 0 |
| 5244 | #endif |
| 5245 | |
| 5246 | // <o> Event Output Selection |
| 5247 | // <0=> Event generation disabled |
| 5248 | // <1=> Event strobe when block transfer complete |
| 5249 | // <3=> Event strobe when beat transfer complete |
| 5250 | // <i> Defines the event output selection |
| 5251 | // <id> dmac_evosel_22 |
| 5252 | #ifndef CONF_DMAC_EVOSEL_22 |
| 5253 | #define CONF_DMAC_EVOSEL_22 0 |
| 5254 | #endif |
| 5255 | // </e> |
| 5256 | |
| 5257 | // <e> Channel 23 settings |
| 5258 | // <id> dmac_channel_23_settings |
| 5259 | #ifndef CONF_DMAC_CHANNEL_23_SETTINGS |
| 5260 | #define CONF_DMAC_CHANNEL_23_SETTINGS 0 |
| 5261 | #endif |
| 5262 | |
| 5263 | // <q> Channel Run in Standby |
| 5264 | // <i> Indicates whether channel 23 is running in standby mode or not |
| 5265 | // <id> dmac_runstdby_23 |
| 5266 | #ifndef CONF_DMAC_RUNSTDBY_23 |
| 5267 | #define CONF_DMAC_RUNSTDBY_23 0 |
| 5268 | #endif |
| 5269 | |
| 5270 | // <o> Trigger action |
| 5271 | // <0=> One trigger required for each block transfer |
| 5272 | // <2=> One trigger required for each beat transfer |
| 5273 | // <3=> One trigger required for each transaction |
| 5274 | // <i> Defines the trigger action used for a transfer |
| 5275 | // <id> dmac_trigact_23 |
| 5276 | #ifndef CONF_DMAC_TRIGACT_23 |
| 5277 | #define CONF_DMAC_TRIGACT_23 0 |
| 5278 | #endif |
| 5279 | |
| 5280 | // <o> Trigger source |
| 5281 | // <0x00=> Only software/event triggers |
| 5282 | // <0x01=> RTC Time Stamp Trigger |
| 5283 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 5284 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 5285 | // <0x04=> SERCOM0 RX Trigger |
| 5286 | // <0x05=> SERCOM0 TX Trigger |
| 5287 | // <0x06=> SERCOM1 RX Trigger |
| 5288 | // <0x07=> SERCOM1 TX Trigger |
| 5289 | // <0x08=> SERCOM2 RX Trigger |
| 5290 | // <0x09=> SERCOM2 TX Trigger |
| 5291 | // <0x0A=> SERCOM3 RX Trigger |
| 5292 | // <0x0B=> SERCOM3 TX Trigger |
| 5293 | // <0x0C=> SERCOM4 RX Trigger |
| 5294 | // <0x0D=> SERCOM4 TX Trigger |
| 5295 | // <0x0E=> SERCOM5 RX Trigger |
| 5296 | // <0x0F=> SERCOM5 TX Trigger |
| 5297 | // <0x10=> SERCOM6 RX Trigger |
| 5298 | // <0x11=> SERCOM6 TX Trigger |
| 5299 | // <0x12=> SERCOM7 RX Trigger |
| 5300 | // <0x13=> SERCOM7 TX Trigger |
| 5301 | // <0x14=> CAN0 DEBUG Trigger |
| 5302 | // <0x15=> CAN1 DEBUG Trigger |
| 5303 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 5304 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 5305 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 5306 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 5307 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 5308 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 5309 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 5310 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 5311 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 5312 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 5313 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 5314 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 5315 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 5316 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 5317 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 5318 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 5319 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 5320 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 5321 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 5322 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 5323 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 5324 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 5325 | // <0x2C=> TC0 Overflow Trigger |
| 5326 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 5327 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 5328 | // <0x2F=> TC1 Overflow Trigger |
| 5329 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 5330 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 5331 | // <0x32=> TC2 Overflow Trigger |
| 5332 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 5333 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 5334 | // <0x35=> TC3 Overflow Trigger |
| 5335 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 5336 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 5337 | // <0x38=> TC4 Overflow Trigger |
| 5338 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 5339 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 5340 | // <0x3B=> TC5 Overflow Trigger |
| 5341 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 5342 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 5343 | // <0x3E=> TC6 Overflow Trigger |
| 5344 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 5345 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 5346 | // <0x41=> TC7 Overflow Trigger |
| 5347 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 5348 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 5349 | // <0x44=> ADC0 Result Ready Trigger |
| 5350 | // <0x45=> ADC0 Sequencing Trigger |
| 5351 | // <0x46=> ADC1 Result Ready Trigger |
| 5352 | // <0x47=> ADC1 Sequencing Trigger |
| 5353 | // <0x48=> DAC Empty 0 Trigger |
| 5354 | // <0x49=> DAC Empty 1 Trigger |
| 5355 | // <0x4A=> DAC Result Ready 0 Trigger |
| 5356 | // <0x4B=> DAC Result Ready 1 Trigger |
| 5357 | // <0x4C=> I2S Rx 0 Trigger |
| 5358 | // <0x4D=> I2S Rx 1 Trigger |
| 5359 | // <0x4E=> I2S Tx 0 Trigger |
| 5360 | // <0x4F=> I2S Tx 1 Trigger |
| 5361 | // <0x50=> PCC RX Trigger |
| 5362 | // <0x51=> AES Write Trigger |
| 5363 | // <0x52=> AES Read Trigger |
| 5364 | // <0x53=> QSPI Rx Trigger |
| 5365 | // <0x54=> QSPI Tx Trigger |
| 5366 | // <i> Defines the peripheral trigger which is source of the transfer |
| 5367 | // <id> dmac_trifsrc_23 |
| 5368 | #ifndef CONF_DMAC_TRIGSRC_23 |
| 5369 | #define CONF_DMAC_TRIGSRC_23 0 |
| 5370 | #endif |
| 5371 | |
| 5372 | // <o> Channel Arbitration Level |
| 5373 | // <0=> Channel priority 0 |
| 5374 | // <1=> Channel priority 1 |
| 5375 | // <2=> Channel priority 2 |
| 5376 | // <3=> Channel priority 3 |
| 5377 | // <i> Defines the arbitration level for this channel |
| 5378 | // <id> dmac_lvl_23 |
| 5379 | #ifndef CONF_DMAC_LVL_23 |
| 5380 | #define CONF_DMAC_LVL_23 0 |
| 5381 | #endif |
| 5382 | |
| 5383 | // <q> Channel Event Output |
| 5384 | // <i> Indicates whether channel event generation is enabled or not |
| 5385 | // <id> dmac_evoe_23 |
| 5386 | #ifndef CONF_DMAC_EVOE_23 |
| 5387 | #define CONF_DMAC_EVOE_23 0 |
| 5388 | #endif |
| 5389 | |
| 5390 | // <q> Channel Event Input |
| 5391 | // <i> Indicates whether channel event reception is enabled or not |
| 5392 | // <id> dmac_evie_23 |
| 5393 | #ifndef CONF_DMAC_EVIE_23 |
| 5394 | #define CONF_DMAC_EVIE_23 0 |
| 5395 | #endif |
| 5396 | |
| 5397 | // <o> Event Input Action |
| 5398 | // <0=> No action |
| 5399 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 5400 | // <2=> Conditional transfer trigger |
| 5401 | // <3=> Conditional block transfer |
| 5402 | // <4=> Channel suspend operation |
| 5403 | // <5=> Channel resume operation |
| 5404 | // <6=> Skip next block suspend action |
| 5405 | // <i> Defines the event input action |
| 5406 | // <id> dmac_evact_23 |
| 5407 | #ifndef CONF_DMAC_EVACT_23 |
| 5408 | #define CONF_DMAC_EVACT_23 0 |
| 5409 | #endif |
| 5410 | |
| 5411 | // <o> Address Increment Step Size |
| 5412 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 5413 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 5414 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 5415 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 5416 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 5417 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 5418 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 5419 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 5420 | // <i> Defines the address increment step size, applies to source or destination address |
| 5421 | // <id> dmac_stepsize_23 |
| 5422 | #ifndef CONF_DMAC_STEPSIZE_23 |
| 5423 | #define CONF_DMAC_STEPSIZE_23 0 |
| 5424 | #endif |
| 5425 | |
| 5426 | // <o> Step Selection |
| 5427 | // <0=> Step size settings apply to the destination address |
| 5428 | // <1=> Step size settings apply to the source address |
| 5429 | // <i> Defines whether source or destination addresses are using the step size settings |
| 5430 | // <id> dmac_stepsel_23 |
| 5431 | #ifndef CONF_DMAC_STEPSEL_23 |
| 5432 | #define CONF_DMAC_STEPSEL_23 0 |
| 5433 | #endif |
| 5434 | |
| 5435 | // <q> Source Address Increment |
| 5436 | // <i> Indicates whether the source address incrementation is enabled or not |
| 5437 | // <id> dmac_srcinc_23 |
| 5438 | #ifndef CONF_DMAC_SRCINC_23 |
| 5439 | #define CONF_DMAC_SRCINC_23 0 |
| 5440 | #endif |
| 5441 | |
| 5442 | // <q> Destination Address Increment |
| 5443 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 5444 | // <id> dmac_dstinc_23 |
| 5445 | #ifndef CONF_DMAC_DSTINC_23 |
| 5446 | #define CONF_DMAC_DSTINC_23 0 |
| 5447 | #endif |
| 5448 | |
| 5449 | // <o> Beat Size |
| 5450 | // <0=> 8-bit bus transfer |
| 5451 | // <1=> 16-bit bus transfer |
| 5452 | // <2=> 32-bit bus transfer |
| 5453 | // <i> Defines the size of one beat |
| 5454 | // <id> dmac_beatsize_23 |
| 5455 | #ifndef CONF_DMAC_BEATSIZE_23 |
| 5456 | #define CONF_DMAC_BEATSIZE_23 0 |
| 5457 | #endif |
| 5458 | |
| 5459 | // <o> Block Action |
| 5460 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 5461 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 5462 | // <2=> Channel suspend operation is complete |
| 5463 | // <3=> Both channel suspend operation and block interrupt |
| 5464 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 5465 | // <id> dmac_blockact_23 |
| 5466 | #ifndef CONF_DMAC_BLOCKACT_23 |
| 5467 | #define CONF_DMAC_BLOCKACT_23 0 |
| 5468 | #endif |
| 5469 | |
| 5470 | // <o> Event Output Selection |
| 5471 | // <0=> Event generation disabled |
| 5472 | // <1=> Event strobe when block transfer complete |
| 5473 | // <3=> Event strobe when beat transfer complete |
| 5474 | // <i> Defines the event output selection |
| 5475 | // <id> dmac_evosel_23 |
| 5476 | #ifndef CONF_DMAC_EVOSEL_23 |
| 5477 | #define CONF_DMAC_EVOSEL_23 0 |
| 5478 | #endif |
| 5479 | // </e> |
| 5480 | |
| 5481 | // <e> Channel 24 settings |
| 5482 | // <id> dmac_channel_24_settings |
| 5483 | #ifndef CONF_DMAC_CHANNEL_24_SETTINGS |
| 5484 | #define CONF_DMAC_CHANNEL_24_SETTINGS 0 |
| 5485 | #endif |
| 5486 | |
| 5487 | // <q> Channel Run in Standby |
| 5488 | // <i> Indicates whether channel 24 is running in standby mode or not |
| 5489 | // <id> dmac_runstdby_24 |
| 5490 | #ifndef CONF_DMAC_RUNSTDBY_24 |
| 5491 | #define CONF_DMAC_RUNSTDBY_24 0 |
| 5492 | #endif |
| 5493 | |
| 5494 | // <o> Trigger action |
| 5495 | // <0=> One trigger required for each block transfer |
| 5496 | // <2=> One trigger required for each beat transfer |
| 5497 | // <3=> One trigger required for each transaction |
| 5498 | // <i> Defines the trigger action used for a transfer |
| 5499 | // <id> dmac_trigact_24 |
| 5500 | #ifndef CONF_DMAC_TRIGACT_24 |
| 5501 | #define CONF_DMAC_TRIGACT_24 0 |
| 5502 | #endif |
| 5503 | |
| 5504 | // <o> Trigger source |
| 5505 | // <0x00=> Only software/event triggers |
| 5506 | // <0x01=> RTC Time Stamp Trigger |
| 5507 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 5508 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 5509 | // <0x04=> SERCOM0 RX Trigger |
| 5510 | // <0x05=> SERCOM0 TX Trigger |
| 5511 | // <0x06=> SERCOM1 RX Trigger |
| 5512 | // <0x07=> SERCOM1 TX Trigger |
| 5513 | // <0x08=> SERCOM2 RX Trigger |
| 5514 | // <0x09=> SERCOM2 TX Trigger |
| 5515 | // <0x0A=> SERCOM3 RX Trigger |
| 5516 | // <0x0B=> SERCOM3 TX Trigger |
| 5517 | // <0x0C=> SERCOM4 RX Trigger |
| 5518 | // <0x0D=> SERCOM4 TX Trigger |
| 5519 | // <0x0E=> SERCOM5 RX Trigger |
| 5520 | // <0x0F=> SERCOM5 TX Trigger |
| 5521 | // <0x10=> SERCOM6 RX Trigger |
| 5522 | // <0x11=> SERCOM6 TX Trigger |
| 5523 | // <0x12=> SERCOM7 RX Trigger |
| 5524 | // <0x13=> SERCOM7 TX Trigger |
| 5525 | // <0x14=> CAN0 DEBUG Trigger |
| 5526 | // <0x15=> CAN1 DEBUG Trigger |
| 5527 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 5528 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 5529 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 5530 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 5531 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 5532 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 5533 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 5534 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 5535 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 5536 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 5537 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 5538 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 5539 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 5540 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 5541 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 5542 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 5543 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 5544 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 5545 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 5546 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 5547 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 5548 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 5549 | // <0x2C=> TC0 Overflow Trigger |
| 5550 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 5551 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 5552 | // <0x2F=> TC1 Overflow Trigger |
| 5553 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 5554 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 5555 | // <0x32=> TC2 Overflow Trigger |
| 5556 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 5557 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 5558 | // <0x35=> TC3 Overflow Trigger |
| 5559 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 5560 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 5561 | // <0x38=> TC4 Overflow Trigger |
| 5562 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 5563 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 5564 | // <0x3B=> TC5 Overflow Trigger |
| 5565 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 5566 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 5567 | // <0x3E=> TC6 Overflow Trigger |
| 5568 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 5569 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 5570 | // <0x41=> TC7 Overflow Trigger |
| 5571 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 5572 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 5573 | // <0x44=> ADC0 Result Ready Trigger |
| 5574 | // <0x45=> ADC0 Sequencing Trigger |
| 5575 | // <0x46=> ADC1 Result Ready Trigger |
| 5576 | // <0x47=> ADC1 Sequencing Trigger |
| 5577 | // <0x48=> DAC Empty 0 Trigger |
| 5578 | // <0x49=> DAC Empty 1 Trigger |
| 5579 | // <0x4A=> DAC Result Ready 0 Trigger |
| 5580 | // <0x4B=> DAC Result Ready 1 Trigger |
| 5581 | // <0x4C=> I2S Rx 0 Trigger |
| 5582 | // <0x4D=> I2S Rx 1 Trigger |
| 5583 | // <0x4E=> I2S Tx 0 Trigger |
| 5584 | // <0x4F=> I2S Tx 1 Trigger |
| 5585 | // <0x50=> PCC RX Trigger |
| 5586 | // <0x51=> AES Write Trigger |
| 5587 | // <0x52=> AES Read Trigger |
| 5588 | // <0x53=> QSPI Rx Trigger |
| 5589 | // <0x54=> QSPI Tx Trigger |
| 5590 | // <i> Defines the peripheral trigger which is source of the transfer |
| 5591 | // <id> dmac_trifsrc_24 |
| 5592 | #ifndef CONF_DMAC_TRIGSRC_24 |
| 5593 | #define CONF_DMAC_TRIGSRC_24 0 |
| 5594 | #endif |
| 5595 | |
| 5596 | // <o> Channel Arbitration Level |
| 5597 | // <0=> Channel priority 0 |
| 5598 | // <1=> Channel priority 1 |
| 5599 | // <2=> Channel priority 2 |
| 5600 | // <3=> Channel priority 3 |
| 5601 | // <i> Defines the arbitration level for this channel |
| 5602 | // <id> dmac_lvl_24 |
| 5603 | #ifndef CONF_DMAC_LVL_24 |
| 5604 | #define CONF_DMAC_LVL_24 0 |
| 5605 | #endif |
| 5606 | |
| 5607 | // <q> Channel Event Output |
| 5608 | // <i> Indicates whether channel event generation is enabled or not |
| 5609 | // <id> dmac_evoe_24 |
| 5610 | #ifndef CONF_DMAC_EVOE_24 |
| 5611 | #define CONF_DMAC_EVOE_24 0 |
| 5612 | #endif |
| 5613 | |
| 5614 | // <q> Channel Event Input |
| 5615 | // <i> Indicates whether channel event reception is enabled or not |
| 5616 | // <id> dmac_evie_24 |
| 5617 | #ifndef CONF_DMAC_EVIE_24 |
| 5618 | #define CONF_DMAC_EVIE_24 0 |
| 5619 | #endif |
| 5620 | |
| 5621 | // <o> Event Input Action |
| 5622 | // <0=> No action |
| 5623 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 5624 | // <2=> Conditional transfer trigger |
| 5625 | // <3=> Conditional block transfer |
| 5626 | // <4=> Channel suspend operation |
| 5627 | // <5=> Channel resume operation |
| 5628 | // <6=> Skip next block suspend action |
| 5629 | // <i> Defines the event input action |
| 5630 | // <id> dmac_evact_24 |
| 5631 | #ifndef CONF_DMAC_EVACT_24 |
| 5632 | #define CONF_DMAC_EVACT_24 0 |
| 5633 | #endif |
| 5634 | |
| 5635 | // <o> Address Increment Step Size |
| 5636 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 5637 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 5638 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 5639 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 5640 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 5641 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 5642 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 5643 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 5644 | // <i> Defines the address increment step size, applies to source or destination address |
| 5645 | // <id> dmac_stepsize_24 |
| 5646 | #ifndef CONF_DMAC_STEPSIZE_24 |
| 5647 | #define CONF_DMAC_STEPSIZE_24 0 |
| 5648 | #endif |
| 5649 | |
| 5650 | // <o> Step Selection |
| 5651 | // <0=> Step size settings apply to the destination address |
| 5652 | // <1=> Step size settings apply to the source address |
| 5653 | // <i> Defines whether source or destination addresses are using the step size settings |
| 5654 | // <id> dmac_stepsel_24 |
| 5655 | #ifndef CONF_DMAC_STEPSEL_24 |
| 5656 | #define CONF_DMAC_STEPSEL_24 0 |
| 5657 | #endif |
| 5658 | |
| 5659 | // <q> Source Address Increment |
| 5660 | // <i> Indicates whether the source address incrementation is enabled or not |
| 5661 | // <id> dmac_srcinc_24 |
| 5662 | #ifndef CONF_DMAC_SRCINC_24 |
| 5663 | #define CONF_DMAC_SRCINC_24 0 |
| 5664 | #endif |
| 5665 | |
| 5666 | // <q> Destination Address Increment |
| 5667 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 5668 | // <id> dmac_dstinc_24 |
| 5669 | #ifndef CONF_DMAC_DSTINC_24 |
| 5670 | #define CONF_DMAC_DSTINC_24 0 |
| 5671 | #endif |
| 5672 | |
| 5673 | // <o> Beat Size |
| 5674 | // <0=> 8-bit bus transfer |
| 5675 | // <1=> 16-bit bus transfer |
| 5676 | // <2=> 32-bit bus transfer |
| 5677 | // <i> Defines the size of one beat |
| 5678 | // <id> dmac_beatsize_24 |
| 5679 | #ifndef CONF_DMAC_BEATSIZE_24 |
| 5680 | #define CONF_DMAC_BEATSIZE_24 0 |
| 5681 | #endif |
| 5682 | |
| 5683 | // <o> Block Action |
| 5684 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 5685 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 5686 | // <2=> Channel suspend operation is complete |
| 5687 | // <3=> Both channel suspend operation and block interrupt |
| 5688 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 5689 | // <id> dmac_blockact_24 |
| 5690 | #ifndef CONF_DMAC_BLOCKACT_24 |
| 5691 | #define CONF_DMAC_BLOCKACT_24 0 |
| 5692 | #endif |
| 5693 | |
| 5694 | // <o> Event Output Selection |
| 5695 | // <0=> Event generation disabled |
| 5696 | // <1=> Event strobe when block transfer complete |
| 5697 | // <3=> Event strobe when beat transfer complete |
| 5698 | // <i> Defines the event output selection |
| 5699 | // <id> dmac_evosel_24 |
| 5700 | #ifndef CONF_DMAC_EVOSEL_24 |
| 5701 | #define CONF_DMAC_EVOSEL_24 0 |
| 5702 | #endif |
| 5703 | // </e> |
| 5704 | |
| 5705 | // <e> Channel 25 settings |
| 5706 | // <id> dmac_channel_25_settings |
| 5707 | #ifndef CONF_DMAC_CHANNEL_25_SETTINGS |
| 5708 | #define CONF_DMAC_CHANNEL_25_SETTINGS 0 |
| 5709 | #endif |
| 5710 | |
| 5711 | // <q> Channel Run in Standby |
| 5712 | // <i> Indicates whether channel 25 is running in standby mode or not |
| 5713 | // <id> dmac_runstdby_25 |
| 5714 | #ifndef CONF_DMAC_RUNSTDBY_25 |
| 5715 | #define CONF_DMAC_RUNSTDBY_25 0 |
| 5716 | #endif |
| 5717 | |
| 5718 | // <o> Trigger action |
| 5719 | // <0=> One trigger required for each block transfer |
| 5720 | // <2=> One trigger required for each beat transfer |
| 5721 | // <3=> One trigger required for each transaction |
| 5722 | // <i> Defines the trigger action used for a transfer |
| 5723 | // <id> dmac_trigact_25 |
| 5724 | #ifndef CONF_DMAC_TRIGACT_25 |
| 5725 | #define CONF_DMAC_TRIGACT_25 0 |
| 5726 | #endif |
| 5727 | |
| 5728 | // <o> Trigger source |
| 5729 | // <0x00=> Only software/event triggers |
| 5730 | // <0x01=> RTC Time Stamp Trigger |
| 5731 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 5732 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 5733 | // <0x04=> SERCOM0 RX Trigger |
| 5734 | // <0x05=> SERCOM0 TX Trigger |
| 5735 | // <0x06=> SERCOM1 RX Trigger |
| 5736 | // <0x07=> SERCOM1 TX Trigger |
| 5737 | // <0x08=> SERCOM2 RX Trigger |
| 5738 | // <0x09=> SERCOM2 TX Trigger |
| 5739 | // <0x0A=> SERCOM3 RX Trigger |
| 5740 | // <0x0B=> SERCOM3 TX Trigger |
| 5741 | // <0x0C=> SERCOM4 RX Trigger |
| 5742 | // <0x0D=> SERCOM4 TX Trigger |
| 5743 | // <0x0E=> SERCOM5 RX Trigger |
| 5744 | // <0x0F=> SERCOM5 TX Trigger |
| 5745 | // <0x10=> SERCOM6 RX Trigger |
| 5746 | // <0x11=> SERCOM6 TX Trigger |
| 5747 | // <0x12=> SERCOM7 RX Trigger |
| 5748 | // <0x13=> SERCOM7 TX Trigger |
| 5749 | // <0x14=> CAN0 DEBUG Trigger |
| 5750 | // <0x15=> CAN1 DEBUG Trigger |
| 5751 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 5752 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 5753 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 5754 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 5755 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 5756 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 5757 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 5758 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 5759 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 5760 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 5761 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 5762 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 5763 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 5764 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 5765 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 5766 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 5767 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 5768 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 5769 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 5770 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 5771 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 5772 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 5773 | // <0x2C=> TC0 Overflow Trigger |
| 5774 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 5775 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 5776 | // <0x2F=> TC1 Overflow Trigger |
| 5777 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 5778 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 5779 | // <0x32=> TC2 Overflow Trigger |
| 5780 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 5781 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 5782 | // <0x35=> TC3 Overflow Trigger |
| 5783 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 5784 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 5785 | // <0x38=> TC4 Overflow Trigger |
| 5786 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 5787 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 5788 | // <0x3B=> TC5 Overflow Trigger |
| 5789 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 5790 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 5791 | // <0x3E=> TC6 Overflow Trigger |
| 5792 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 5793 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 5794 | // <0x41=> TC7 Overflow Trigger |
| 5795 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 5796 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 5797 | // <0x44=> ADC0 Result Ready Trigger |
| 5798 | // <0x45=> ADC0 Sequencing Trigger |
| 5799 | // <0x46=> ADC1 Result Ready Trigger |
| 5800 | // <0x47=> ADC1 Sequencing Trigger |
| 5801 | // <0x48=> DAC Empty 0 Trigger |
| 5802 | // <0x49=> DAC Empty 1 Trigger |
| 5803 | // <0x4A=> DAC Result Ready 0 Trigger |
| 5804 | // <0x4B=> DAC Result Ready 1 Trigger |
| 5805 | // <0x4C=> I2S Rx 0 Trigger |
| 5806 | // <0x4D=> I2S Rx 1 Trigger |
| 5807 | // <0x4E=> I2S Tx 0 Trigger |
| 5808 | // <0x4F=> I2S Tx 1 Trigger |
| 5809 | // <0x50=> PCC RX Trigger |
| 5810 | // <0x51=> AES Write Trigger |
| 5811 | // <0x52=> AES Read Trigger |
| 5812 | // <0x53=> QSPI Rx Trigger |
| 5813 | // <0x54=> QSPI Tx Trigger |
| 5814 | // <i> Defines the peripheral trigger which is source of the transfer |
| 5815 | // <id> dmac_trifsrc_25 |
| 5816 | #ifndef CONF_DMAC_TRIGSRC_25 |
| 5817 | #define CONF_DMAC_TRIGSRC_25 0 |
| 5818 | #endif |
| 5819 | |
| 5820 | // <o> Channel Arbitration Level |
| 5821 | // <0=> Channel priority 0 |
| 5822 | // <1=> Channel priority 1 |
| 5823 | // <2=> Channel priority 2 |
| 5824 | // <3=> Channel priority 3 |
| 5825 | // <i> Defines the arbitration level for this channel |
| 5826 | // <id> dmac_lvl_25 |
| 5827 | #ifndef CONF_DMAC_LVL_25 |
| 5828 | #define CONF_DMAC_LVL_25 0 |
| 5829 | #endif |
| 5830 | |
| 5831 | // <q> Channel Event Output |
| 5832 | // <i> Indicates whether channel event generation is enabled or not |
| 5833 | // <id> dmac_evoe_25 |
| 5834 | #ifndef CONF_DMAC_EVOE_25 |
| 5835 | #define CONF_DMAC_EVOE_25 0 |
| 5836 | #endif |
| 5837 | |
| 5838 | // <q> Channel Event Input |
| 5839 | // <i> Indicates whether channel event reception is enabled or not |
| 5840 | // <id> dmac_evie_25 |
| 5841 | #ifndef CONF_DMAC_EVIE_25 |
| 5842 | #define CONF_DMAC_EVIE_25 0 |
| 5843 | #endif |
| 5844 | |
| 5845 | // <o> Event Input Action |
| 5846 | // <0=> No action |
| 5847 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 5848 | // <2=> Conditional transfer trigger |
| 5849 | // <3=> Conditional block transfer |
| 5850 | // <4=> Channel suspend operation |
| 5851 | // <5=> Channel resume operation |
| 5852 | // <6=> Skip next block suspend action |
| 5853 | // <i> Defines the event input action |
| 5854 | // <id> dmac_evact_25 |
| 5855 | #ifndef CONF_DMAC_EVACT_25 |
| 5856 | #define CONF_DMAC_EVACT_25 0 |
| 5857 | #endif |
| 5858 | |
| 5859 | // <o> Address Increment Step Size |
| 5860 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 5861 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 5862 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 5863 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 5864 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 5865 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 5866 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 5867 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 5868 | // <i> Defines the address increment step size, applies to source or destination address |
| 5869 | // <id> dmac_stepsize_25 |
| 5870 | #ifndef CONF_DMAC_STEPSIZE_25 |
| 5871 | #define CONF_DMAC_STEPSIZE_25 0 |
| 5872 | #endif |
| 5873 | |
| 5874 | // <o> Step Selection |
| 5875 | // <0=> Step size settings apply to the destination address |
| 5876 | // <1=> Step size settings apply to the source address |
| 5877 | // <i> Defines whether source or destination addresses are using the step size settings |
| 5878 | // <id> dmac_stepsel_25 |
| 5879 | #ifndef CONF_DMAC_STEPSEL_25 |
| 5880 | #define CONF_DMAC_STEPSEL_25 0 |
| 5881 | #endif |
| 5882 | |
| 5883 | // <q> Source Address Increment |
| 5884 | // <i> Indicates whether the source address incrementation is enabled or not |
| 5885 | // <id> dmac_srcinc_25 |
| 5886 | #ifndef CONF_DMAC_SRCINC_25 |
| 5887 | #define CONF_DMAC_SRCINC_25 0 |
| 5888 | #endif |
| 5889 | |
| 5890 | // <q> Destination Address Increment |
| 5891 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 5892 | // <id> dmac_dstinc_25 |
| 5893 | #ifndef CONF_DMAC_DSTINC_25 |
| 5894 | #define CONF_DMAC_DSTINC_25 0 |
| 5895 | #endif |
| 5896 | |
| 5897 | // <o> Beat Size |
| 5898 | // <0=> 8-bit bus transfer |
| 5899 | // <1=> 16-bit bus transfer |
| 5900 | // <2=> 32-bit bus transfer |
| 5901 | // <i> Defines the size of one beat |
| 5902 | // <id> dmac_beatsize_25 |
| 5903 | #ifndef CONF_DMAC_BEATSIZE_25 |
| 5904 | #define CONF_DMAC_BEATSIZE_25 0 |
| 5905 | #endif |
| 5906 | |
| 5907 | // <o> Block Action |
| 5908 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 5909 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 5910 | // <2=> Channel suspend operation is complete |
| 5911 | // <3=> Both channel suspend operation and block interrupt |
| 5912 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 5913 | // <id> dmac_blockact_25 |
| 5914 | #ifndef CONF_DMAC_BLOCKACT_25 |
| 5915 | #define CONF_DMAC_BLOCKACT_25 0 |
| 5916 | #endif |
| 5917 | |
| 5918 | // <o> Event Output Selection |
| 5919 | // <0=> Event generation disabled |
| 5920 | // <1=> Event strobe when block transfer complete |
| 5921 | // <3=> Event strobe when beat transfer complete |
| 5922 | // <i> Defines the event output selection |
| 5923 | // <id> dmac_evosel_25 |
| 5924 | #ifndef CONF_DMAC_EVOSEL_25 |
| 5925 | #define CONF_DMAC_EVOSEL_25 0 |
| 5926 | #endif |
| 5927 | // </e> |
| 5928 | |
| 5929 | // <e> Channel 26 settings |
| 5930 | // <id> dmac_channel_26_settings |
| 5931 | #ifndef CONF_DMAC_CHANNEL_26_SETTINGS |
| 5932 | #define CONF_DMAC_CHANNEL_26_SETTINGS 0 |
| 5933 | #endif |
| 5934 | |
| 5935 | // <q> Channel Run in Standby |
| 5936 | // <i> Indicates whether channel 26 is running in standby mode or not |
| 5937 | // <id> dmac_runstdby_26 |
| 5938 | #ifndef CONF_DMAC_RUNSTDBY_26 |
| 5939 | #define CONF_DMAC_RUNSTDBY_26 0 |
| 5940 | #endif |
| 5941 | |
| 5942 | // <o> Trigger action |
| 5943 | // <0=> One trigger required for each block transfer |
| 5944 | // <2=> One trigger required for each beat transfer |
| 5945 | // <3=> One trigger required for each transaction |
| 5946 | // <i> Defines the trigger action used for a transfer |
| 5947 | // <id> dmac_trigact_26 |
| 5948 | #ifndef CONF_DMAC_TRIGACT_26 |
| 5949 | #define CONF_DMAC_TRIGACT_26 0 |
| 5950 | #endif |
| 5951 | |
| 5952 | // <o> Trigger source |
| 5953 | // <0x00=> Only software/event triggers |
| 5954 | // <0x01=> RTC Time Stamp Trigger |
| 5955 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 5956 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 5957 | // <0x04=> SERCOM0 RX Trigger |
| 5958 | // <0x05=> SERCOM0 TX Trigger |
| 5959 | // <0x06=> SERCOM1 RX Trigger |
| 5960 | // <0x07=> SERCOM1 TX Trigger |
| 5961 | // <0x08=> SERCOM2 RX Trigger |
| 5962 | // <0x09=> SERCOM2 TX Trigger |
| 5963 | // <0x0A=> SERCOM3 RX Trigger |
| 5964 | // <0x0B=> SERCOM3 TX Trigger |
| 5965 | // <0x0C=> SERCOM4 RX Trigger |
| 5966 | // <0x0D=> SERCOM4 TX Trigger |
| 5967 | // <0x0E=> SERCOM5 RX Trigger |
| 5968 | // <0x0F=> SERCOM5 TX Trigger |
| 5969 | // <0x10=> SERCOM6 RX Trigger |
| 5970 | // <0x11=> SERCOM6 TX Trigger |
| 5971 | // <0x12=> SERCOM7 RX Trigger |
| 5972 | // <0x13=> SERCOM7 TX Trigger |
| 5973 | // <0x14=> CAN0 DEBUG Trigger |
| 5974 | // <0x15=> CAN1 DEBUG Trigger |
| 5975 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 5976 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 5977 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 5978 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 5979 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 5980 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 5981 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 5982 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 5983 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 5984 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 5985 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 5986 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 5987 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 5988 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 5989 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 5990 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 5991 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 5992 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 5993 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 5994 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 5995 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 5996 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 5997 | // <0x2C=> TC0 Overflow Trigger |
| 5998 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 5999 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 6000 | // <0x2F=> TC1 Overflow Trigger |
| 6001 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 6002 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 6003 | // <0x32=> TC2 Overflow Trigger |
| 6004 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 6005 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 6006 | // <0x35=> TC3 Overflow Trigger |
| 6007 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 6008 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 6009 | // <0x38=> TC4 Overflow Trigger |
| 6010 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 6011 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 6012 | // <0x3B=> TC5 Overflow Trigger |
| 6013 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 6014 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 6015 | // <0x3E=> TC6 Overflow Trigger |
| 6016 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 6017 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 6018 | // <0x41=> TC7 Overflow Trigger |
| 6019 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 6020 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 6021 | // <0x44=> ADC0 Result Ready Trigger |
| 6022 | // <0x45=> ADC0 Sequencing Trigger |
| 6023 | // <0x46=> ADC1 Result Ready Trigger |
| 6024 | // <0x47=> ADC1 Sequencing Trigger |
| 6025 | // <0x48=> DAC Empty 0 Trigger |
| 6026 | // <0x49=> DAC Empty 1 Trigger |
| 6027 | // <0x4A=> DAC Result Ready 0 Trigger |
| 6028 | // <0x4B=> DAC Result Ready 1 Trigger |
| 6029 | // <0x4C=> I2S Rx 0 Trigger |
| 6030 | // <0x4D=> I2S Rx 1 Trigger |
| 6031 | // <0x4E=> I2S Tx 0 Trigger |
| 6032 | // <0x4F=> I2S Tx 1 Trigger |
| 6033 | // <0x50=> PCC RX Trigger |
| 6034 | // <0x51=> AES Write Trigger |
| 6035 | // <0x52=> AES Read Trigger |
| 6036 | // <0x53=> QSPI Rx Trigger |
| 6037 | // <0x54=> QSPI Tx Trigger |
| 6038 | // <i> Defines the peripheral trigger which is source of the transfer |
| 6039 | // <id> dmac_trifsrc_26 |
| 6040 | #ifndef CONF_DMAC_TRIGSRC_26 |
| 6041 | #define CONF_DMAC_TRIGSRC_26 0 |
| 6042 | #endif |
| 6043 | |
| 6044 | // <o> Channel Arbitration Level |
| 6045 | // <0=> Channel priority 0 |
| 6046 | // <1=> Channel priority 1 |
| 6047 | // <2=> Channel priority 2 |
| 6048 | // <3=> Channel priority 3 |
| 6049 | // <i> Defines the arbitration level for this channel |
| 6050 | // <id> dmac_lvl_26 |
| 6051 | #ifndef CONF_DMAC_LVL_26 |
| 6052 | #define CONF_DMAC_LVL_26 0 |
| 6053 | #endif |
| 6054 | |
| 6055 | // <q> Channel Event Output |
| 6056 | // <i> Indicates whether channel event generation is enabled or not |
| 6057 | // <id> dmac_evoe_26 |
| 6058 | #ifndef CONF_DMAC_EVOE_26 |
| 6059 | #define CONF_DMAC_EVOE_26 0 |
| 6060 | #endif |
| 6061 | |
| 6062 | // <q> Channel Event Input |
| 6063 | // <i> Indicates whether channel event reception is enabled or not |
| 6064 | // <id> dmac_evie_26 |
| 6065 | #ifndef CONF_DMAC_EVIE_26 |
| 6066 | #define CONF_DMAC_EVIE_26 0 |
| 6067 | #endif |
| 6068 | |
| 6069 | // <o> Event Input Action |
| 6070 | // <0=> No action |
| 6071 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 6072 | // <2=> Conditional transfer trigger |
| 6073 | // <3=> Conditional block transfer |
| 6074 | // <4=> Channel suspend operation |
| 6075 | // <5=> Channel resume operation |
| 6076 | // <6=> Skip next block suspend action |
| 6077 | // <i> Defines the event input action |
| 6078 | // <id> dmac_evact_26 |
| 6079 | #ifndef CONF_DMAC_EVACT_26 |
| 6080 | #define CONF_DMAC_EVACT_26 0 |
| 6081 | #endif |
| 6082 | |
| 6083 | // <o> Address Increment Step Size |
| 6084 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 6085 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 6086 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 6087 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 6088 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 6089 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 6090 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 6091 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 6092 | // <i> Defines the address increment step size, applies to source or destination address |
| 6093 | // <id> dmac_stepsize_26 |
| 6094 | #ifndef CONF_DMAC_STEPSIZE_26 |
| 6095 | #define CONF_DMAC_STEPSIZE_26 0 |
| 6096 | #endif |
| 6097 | |
| 6098 | // <o> Step Selection |
| 6099 | // <0=> Step size settings apply to the destination address |
| 6100 | // <1=> Step size settings apply to the source address |
| 6101 | // <i> Defines whether source or destination addresses are using the step size settings |
| 6102 | // <id> dmac_stepsel_26 |
| 6103 | #ifndef CONF_DMAC_STEPSEL_26 |
| 6104 | #define CONF_DMAC_STEPSEL_26 0 |
| 6105 | #endif |
| 6106 | |
| 6107 | // <q> Source Address Increment |
| 6108 | // <i> Indicates whether the source address incrementation is enabled or not |
| 6109 | // <id> dmac_srcinc_26 |
| 6110 | #ifndef CONF_DMAC_SRCINC_26 |
| 6111 | #define CONF_DMAC_SRCINC_26 0 |
| 6112 | #endif |
| 6113 | |
| 6114 | // <q> Destination Address Increment |
| 6115 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 6116 | // <id> dmac_dstinc_26 |
| 6117 | #ifndef CONF_DMAC_DSTINC_26 |
| 6118 | #define CONF_DMAC_DSTINC_26 0 |
| 6119 | #endif |
| 6120 | |
| 6121 | // <o> Beat Size |
| 6122 | // <0=> 8-bit bus transfer |
| 6123 | // <1=> 16-bit bus transfer |
| 6124 | // <2=> 32-bit bus transfer |
| 6125 | // <i> Defines the size of one beat |
| 6126 | // <id> dmac_beatsize_26 |
| 6127 | #ifndef CONF_DMAC_BEATSIZE_26 |
| 6128 | #define CONF_DMAC_BEATSIZE_26 0 |
| 6129 | #endif |
| 6130 | |
| 6131 | // <o> Block Action |
| 6132 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 6133 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 6134 | // <2=> Channel suspend operation is complete |
| 6135 | // <3=> Both channel suspend operation and block interrupt |
| 6136 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 6137 | // <id> dmac_blockact_26 |
| 6138 | #ifndef CONF_DMAC_BLOCKACT_26 |
| 6139 | #define CONF_DMAC_BLOCKACT_26 0 |
| 6140 | #endif |
| 6141 | |
| 6142 | // <o> Event Output Selection |
| 6143 | // <0=> Event generation disabled |
| 6144 | // <1=> Event strobe when block transfer complete |
| 6145 | // <3=> Event strobe when beat transfer complete |
| 6146 | // <i> Defines the event output selection |
| 6147 | // <id> dmac_evosel_26 |
| 6148 | #ifndef CONF_DMAC_EVOSEL_26 |
| 6149 | #define CONF_DMAC_EVOSEL_26 0 |
| 6150 | #endif |
| 6151 | // </e> |
| 6152 | |
| 6153 | // <e> Channel 27 settings |
| 6154 | // <id> dmac_channel_27_settings |
| 6155 | #ifndef CONF_DMAC_CHANNEL_27_SETTINGS |
| 6156 | #define CONF_DMAC_CHANNEL_27_SETTINGS 0 |
| 6157 | #endif |
| 6158 | |
| 6159 | // <q> Channel Run in Standby |
| 6160 | // <i> Indicates whether channel 27 is running in standby mode or not |
| 6161 | // <id> dmac_runstdby_27 |
| 6162 | #ifndef CONF_DMAC_RUNSTDBY_27 |
| 6163 | #define CONF_DMAC_RUNSTDBY_27 0 |
| 6164 | #endif |
| 6165 | |
| 6166 | // <o> Trigger action |
| 6167 | // <0=> One trigger required for each block transfer |
| 6168 | // <2=> One trigger required for each beat transfer |
| 6169 | // <3=> One trigger required for each transaction |
| 6170 | // <i> Defines the trigger action used for a transfer |
| 6171 | // <id> dmac_trigact_27 |
| 6172 | #ifndef CONF_DMAC_TRIGACT_27 |
| 6173 | #define CONF_DMAC_TRIGACT_27 0 |
| 6174 | #endif |
| 6175 | |
| 6176 | // <o> Trigger source |
| 6177 | // <0x00=> Only software/event triggers |
| 6178 | // <0x01=> RTC Time Stamp Trigger |
| 6179 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 6180 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 6181 | // <0x04=> SERCOM0 RX Trigger |
| 6182 | // <0x05=> SERCOM0 TX Trigger |
| 6183 | // <0x06=> SERCOM1 RX Trigger |
| 6184 | // <0x07=> SERCOM1 TX Trigger |
| 6185 | // <0x08=> SERCOM2 RX Trigger |
| 6186 | // <0x09=> SERCOM2 TX Trigger |
| 6187 | // <0x0A=> SERCOM3 RX Trigger |
| 6188 | // <0x0B=> SERCOM3 TX Trigger |
| 6189 | // <0x0C=> SERCOM4 RX Trigger |
| 6190 | // <0x0D=> SERCOM4 TX Trigger |
| 6191 | // <0x0E=> SERCOM5 RX Trigger |
| 6192 | // <0x0F=> SERCOM5 TX Trigger |
| 6193 | // <0x10=> SERCOM6 RX Trigger |
| 6194 | // <0x11=> SERCOM6 TX Trigger |
| 6195 | // <0x12=> SERCOM7 RX Trigger |
| 6196 | // <0x13=> SERCOM7 TX Trigger |
| 6197 | // <0x14=> CAN0 DEBUG Trigger |
| 6198 | // <0x15=> CAN1 DEBUG Trigger |
| 6199 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 6200 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 6201 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 6202 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 6203 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 6204 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 6205 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 6206 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 6207 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 6208 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 6209 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 6210 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 6211 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 6212 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 6213 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 6214 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 6215 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 6216 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 6217 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 6218 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 6219 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 6220 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 6221 | // <0x2C=> TC0 Overflow Trigger |
| 6222 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 6223 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 6224 | // <0x2F=> TC1 Overflow Trigger |
| 6225 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 6226 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 6227 | // <0x32=> TC2 Overflow Trigger |
| 6228 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 6229 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 6230 | // <0x35=> TC3 Overflow Trigger |
| 6231 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 6232 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 6233 | // <0x38=> TC4 Overflow Trigger |
| 6234 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 6235 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 6236 | // <0x3B=> TC5 Overflow Trigger |
| 6237 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 6238 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 6239 | // <0x3E=> TC6 Overflow Trigger |
| 6240 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 6241 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 6242 | // <0x41=> TC7 Overflow Trigger |
| 6243 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 6244 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 6245 | // <0x44=> ADC0 Result Ready Trigger |
| 6246 | // <0x45=> ADC0 Sequencing Trigger |
| 6247 | // <0x46=> ADC1 Result Ready Trigger |
| 6248 | // <0x47=> ADC1 Sequencing Trigger |
| 6249 | // <0x48=> DAC Empty 0 Trigger |
| 6250 | // <0x49=> DAC Empty 1 Trigger |
| 6251 | // <0x4A=> DAC Result Ready 0 Trigger |
| 6252 | // <0x4B=> DAC Result Ready 1 Trigger |
| 6253 | // <0x4C=> I2S Rx 0 Trigger |
| 6254 | // <0x4D=> I2S Rx 1 Trigger |
| 6255 | // <0x4E=> I2S Tx 0 Trigger |
| 6256 | // <0x4F=> I2S Tx 1 Trigger |
| 6257 | // <0x50=> PCC RX Trigger |
| 6258 | // <0x51=> AES Write Trigger |
| 6259 | // <0x52=> AES Read Trigger |
| 6260 | // <0x53=> QSPI Rx Trigger |
| 6261 | // <0x54=> QSPI Tx Trigger |
| 6262 | // <i> Defines the peripheral trigger which is source of the transfer |
| 6263 | // <id> dmac_trifsrc_27 |
| 6264 | #ifndef CONF_DMAC_TRIGSRC_27 |
| 6265 | #define CONF_DMAC_TRIGSRC_27 0 |
| 6266 | #endif |
| 6267 | |
| 6268 | // <o> Channel Arbitration Level |
| 6269 | // <0=> Channel priority 0 |
| 6270 | // <1=> Channel priority 1 |
| 6271 | // <2=> Channel priority 2 |
| 6272 | // <3=> Channel priority 3 |
| 6273 | // <i> Defines the arbitration level for this channel |
| 6274 | // <id> dmac_lvl_27 |
| 6275 | #ifndef CONF_DMAC_LVL_27 |
| 6276 | #define CONF_DMAC_LVL_27 0 |
| 6277 | #endif |
| 6278 | |
| 6279 | // <q> Channel Event Output |
| 6280 | // <i> Indicates whether channel event generation is enabled or not |
| 6281 | // <id> dmac_evoe_27 |
| 6282 | #ifndef CONF_DMAC_EVOE_27 |
| 6283 | #define CONF_DMAC_EVOE_27 0 |
| 6284 | #endif |
| 6285 | |
| 6286 | // <q> Channel Event Input |
| 6287 | // <i> Indicates whether channel event reception is enabled or not |
| 6288 | // <id> dmac_evie_27 |
| 6289 | #ifndef CONF_DMAC_EVIE_27 |
| 6290 | #define CONF_DMAC_EVIE_27 0 |
| 6291 | #endif |
| 6292 | |
| 6293 | // <o> Event Input Action |
| 6294 | // <0=> No action |
| 6295 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 6296 | // <2=> Conditional transfer trigger |
| 6297 | // <3=> Conditional block transfer |
| 6298 | // <4=> Channel suspend operation |
| 6299 | // <5=> Channel resume operation |
| 6300 | // <6=> Skip next block suspend action |
| 6301 | // <i> Defines the event input action |
| 6302 | // <id> dmac_evact_27 |
| 6303 | #ifndef CONF_DMAC_EVACT_27 |
| 6304 | #define CONF_DMAC_EVACT_27 0 |
| 6305 | #endif |
| 6306 | |
| 6307 | // <o> Address Increment Step Size |
| 6308 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 6309 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 6310 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 6311 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 6312 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 6313 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 6314 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 6315 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 6316 | // <i> Defines the address increment step size, applies to source or destination address |
| 6317 | // <id> dmac_stepsize_27 |
| 6318 | #ifndef CONF_DMAC_STEPSIZE_27 |
| 6319 | #define CONF_DMAC_STEPSIZE_27 0 |
| 6320 | #endif |
| 6321 | |
| 6322 | // <o> Step Selection |
| 6323 | // <0=> Step size settings apply to the destination address |
| 6324 | // <1=> Step size settings apply to the source address |
| 6325 | // <i> Defines whether source or destination addresses are using the step size settings |
| 6326 | // <id> dmac_stepsel_27 |
| 6327 | #ifndef CONF_DMAC_STEPSEL_27 |
| 6328 | #define CONF_DMAC_STEPSEL_27 0 |
| 6329 | #endif |
| 6330 | |
| 6331 | // <q> Source Address Increment |
| 6332 | // <i> Indicates whether the source address incrementation is enabled or not |
| 6333 | // <id> dmac_srcinc_27 |
| 6334 | #ifndef CONF_DMAC_SRCINC_27 |
| 6335 | #define CONF_DMAC_SRCINC_27 0 |
| 6336 | #endif |
| 6337 | |
| 6338 | // <q> Destination Address Increment |
| 6339 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 6340 | // <id> dmac_dstinc_27 |
| 6341 | #ifndef CONF_DMAC_DSTINC_27 |
| 6342 | #define CONF_DMAC_DSTINC_27 0 |
| 6343 | #endif |
| 6344 | |
| 6345 | // <o> Beat Size |
| 6346 | // <0=> 8-bit bus transfer |
| 6347 | // <1=> 16-bit bus transfer |
| 6348 | // <2=> 32-bit bus transfer |
| 6349 | // <i> Defines the size of one beat |
| 6350 | // <id> dmac_beatsize_27 |
| 6351 | #ifndef CONF_DMAC_BEATSIZE_27 |
| 6352 | #define CONF_DMAC_BEATSIZE_27 0 |
| 6353 | #endif |
| 6354 | |
| 6355 | // <o> Block Action |
| 6356 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 6357 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 6358 | // <2=> Channel suspend operation is complete |
| 6359 | // <3=> Both channel suspend operation and block interrupt |
| 6360 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 6361 | // <id> dmac_blockact_27 |
| 6362 | #ifndef CONF_DMAC_BLOCKACT_27 |
| 6363 | #define CONF_DMAC_BLOCKACT_27 0 |
| 6364 | #endif |
| 6365 | |
| 6366 | // <o> Event Output Selection |
| 6367 | // <0=> Event generation disabled |
| 6368 | // <1=> Event strobe when block transfer complete |
| 6369 | // <3=> Event strobe when beat transfer complete |
| 6370 | // <i> Defines the event output selection |
| 6371 | // <id> dmac_evosel_27 |
| 6372 | #ifndef CONF_DMAC_EVOSEL_27 |
| 6373 | #define CONF_DMAC_EVOSEL_27 0 |
| 6374 | #endif |
| 6375 | // </e> |
| 6376 | |
| 6377 | // <e> Channel 28 settings |
| 6378 | // <id> dmac_channel_28_settings |
| 6379 | #ifndef CONF_DMAC_CHANNEL_28_SETTINGS |
| 6380 | #define CONF_DMAC_CHANNEL_28_SETTINGS 0 |
| 6381 | #endif |
| 6382 | |
| 6383 | // <q> Channel Run in Standby |
| 6384 | // <i> Indicates whether channel 28 is running in standby mode or not |
| 6385 | // <id> dmac_runstdby_28 |
| 6386 | #ifndef CONF_DMAC_RUNSTDBY_28 |
| 6387 | #define CONF_DMAC_RUNSTDBY_28 0 |
| 6388 | #endif |
| 6389 | |
| 6390 | // <o> Trigger action |
| 6391 | // <0=> One trigger required for each block transfer |
| 6392 | // <2=> One trigger required for each beat transfer |
| 6393 | // <3=> One trigger required for each transaction |
| 6394 | // <i> Defines the trigger action used for a transfer |
| 6395 | // <id> dmac_trigact_28 |
| 6396 | #ifndef CONF_DMAC_TRIGACT_28 |
| 6397 | #define CONF_DMAC_TRIGACT_28 0 |
| 6398 | #endif |
| 6399 | |
| 6400 | // <o> Trigger source |
| 6401 | // <0x00=> Only software/event triggers |
| 6402 | // <0x01=> RTC Time Stamp Trigger |
| 6403 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 6404 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 6405 | // <0x04=> SERCOM0 RX Trigger |
| 6406 | // <0x05=> SERCOM0 TX Trigger |
| 6407 | // <0x06=> SERCOM1 RX Trigger |
| 6408 | // <0x07=> SERCOM1 TX Trigger |
| 6409 | // <0x08=> SERCOM2 RX Trigger |
| 6410 | // <0x09=> SERCOM2 TX Trigger |
| 6411 | // <0x0A=> SERCOM3 RX Trigger |
| 6412 | // <0x0B=> SERCOM3 TX Trigger |
| 6413 | // <0x0C=> SERCOM4 RX Trigger |
| 6414 | // <0x0D=> SERCOM4 TX Trigger |
| 6415 | // <0x0E=> SERCOM5 RX Trigger |
| 6416 | // <0x0F=> SERCOM5 TX Trigger |
| 6417 | // <0x10=> SERCOM6 RX Trigger |
| 6418 | // <0x11=> SERCOM6 TX Trigger |
| 6419 | // <0x12=> SERCOM7 RX Trigger |
| 6420 | // <0x13=> SERCOM7 TX Trigger |
| 6421 | // <0x14=> CAN0 DEBUG Trigger |
| 6422 | // <0x15=> CAN1 DEBUG Trigger |
| 6423 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 6424 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 6425 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 6426 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 6427 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 6428 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 6429 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 6430 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 6431 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 6432 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 6433 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 6434 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 6435 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 6436 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 6437 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 6438 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 6439 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 6440 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 6441 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 6442 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 6443 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 6444 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 6445 | // <0x2C=> TC0 Overflow Trigger |
| 6446 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 6447 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 6448 | // <0x2F=> TC1 Overflow Trigger |
| 6449 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 6450 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 6451 | // <0x32=> TC2 Overflow Trigger |
| 6452 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 6453 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 6454 | // <0x35=> TC3 Overflow Trigger |
| 6455 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 6456 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 6457 | // <0x38=> TC4 Overflow Trigger |
| 6458 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 6459 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 6460 | // <0x3B=> TC5 Overflow Trigger |
| 6461 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 6462 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 6463 | // <0x3E=> TC6 Overflow Trigger |
| 6464 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 6465 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 6466 | // <0x41=> TC7 Overflow Trigger |
| 6467 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 6468 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 6469 | // <0x44=> ADC0 Result Ready Trigger |
| 6470 | // <0x45=> ADC0 Sequencing Trigger |
| 6471 | // <0x46=> ADC1 Result Ready Trigger |
| 6472 | // <0x47=> ADC1 Sequencing Trigger |
| 6473 | // <0x48=> DAC Empty 0 Trigger |
| 6474 | // <0x49=> DAC Empty 1 Trigger |
| 6475 | // <0x4A=> DAC Result Ready 0 Trigger |
| 6476 | // <0x4B=> DAC Result Ready 1 Trigger |
| 6477 | // <0x4C=> I2S Rx 0 Trigger |
| 6478 | // <0x4D=> I2S Rx 1 Trigger |
| 6479 | // <0x4E=> I2S Tx 0 Trigger |
| 6480 | // <0x4F=> I2S Tx 1 Trigger |
| 6481 | // <0x50=> PCC RX Trigger |
| 6482 | // <0x51=> AES Write Trigger |
| 6483 | // <0x52=> AES Read Trigger |
| 6484 | // <0x53=> QSPI Rx Trigger |
| 6485 | // <0x54=> QSPI Tx Trigger |
| 6486 | // <i> Defines the peripheral trigger which is source of the transfer |
| 6487 | // <id> dmac_trifsrc_28 |
| 6488 | #ifndef CONF_DMAC_TRIGSRC_28 |
| 6489 | #define CONF_DMAC_TRIGSRC_28 0 |
| 6490 | #endif |
| 6491 | |
| 6492 | // <o> Channel Arbitration Level |
| 6493 | // <0=> Channel priority 0 |
| 6494 | // <1=> Channel priority 1 |
| 6495 | // <2=> Channel priority 2 |
| 6496 | // <3=> Channel priority 3 |
| 6497 | // <i> Defines the arbitration level for this channel |
| 6498 | // <id> dmac_lvl_28 |
| 6499 | #ifndef CONF_DMAC_LVL_28 |
| 6500 | #define CONF_DMAC_LVL_28 0 |
| 6501 | #endif |
| 6502 | |
| 6503 | // <q> Channel Event Output |
| 6504 | // <i> Indicates whether channel event generation is enabled or not |
| 6505 | // <id> dmac_evoe_28 |
| 6506 | #ifndef CONF_DMAC_EVOE_28 |
| 6507 | #define CONF_DMAC_EVOE_28 0 |
| 6508 | #endif |
| 6509 | |
| 6510 | // <q> Channel Event Input |
| 6511 | // <i> Indicates whether channel event reception is enabled or not |
| 6512 | // <id> dmac_evie_28 |
| 6513 | #ifndef CONF_DMAC_EVIE_28 |
| 6514 | #define CONF_DMAC_EVIE_28 0 |
| 6515 | #endif |
| 6516 | |
| 6517 | // <o> Event Input Action |
| 6518 | // <0=> No action |
| 6519 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 6520 | // <2=> Conditional transfer trigger |
| 6521 | // <3=> Conditional block transfer |
| 6522 | // <4=> Channel suspend operation |
| 6523 | // <5=> Channel resume operation |
| 6524 | // <6=> Skip next block suspend action |
| 6525 | // <i> Defines the event input action |
| 6526 | // <id> dmac_evact_28 |
| 6527 | #ifndef CONF_DMAC_EVACT_28 |
| 6528 | #define CONF_DMAC_EVACT_28 0 |
| 6529 | #endif |
| 6530 | |
| 6531 | // <o> Address Increment Step Size |
| 6532 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 6533 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 6534 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 6535 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 6536 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 6537 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 6538 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 6539 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 6540 | // <i> Defines the address increment step size, applies to source or destination address |
| 6541 | // <id> dmac_stepsize_28 |
| 6542 | #ifndef CONF_DMAC_STEPSIZE_28 |
| 6543 | #define CONF_DMAC_STEPSIZE_28 0 |
| 6544 | #endif |
| 6545 | |
| 6546 | // <o> Step Selection |
| 6547 | // <0=> Step size settings apply to the destination address |
| 6548 | // <1=> Step size settings apply to the source address |
| 6549 | // <i> Defines whether source or destination addresses are using the step size settings |
| 6550 | // <id> dmac_stepsel_28 |
| 6551 | #ifndef CONF_DMAC_STEPSEL_28 |
| 6552 | #define CONF_DMAC_STEPSEL_28 0 |
| 6553 | #endif |
| 6554 | |
| 6555 | // <q> Source Address Increment |
| 6556 | // <i> Indicates whether the source address incrementation is enabled or not |
| 6557 | // <id> dmac_srcinc_28 |
| 6558 | #ifndef CONF_DMAC_SRCINC_28 |
| 6559 | #define CONF_DMAC_SRCINC_28 0 |
| 6560 | #endif |
| 6561 | |
| 6562 | // <q> Destination Address Increment |
| 6563 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 6564 | // <id> dmac_dstinc_28 |
| 6565 | #ifndef CONF_DMAC_DSTINC_28 |
| 6566 | #define CONF_DMAC_DSTINC_28 0 |
| 6567 | #endif |
| 6568 | |
| 6569 | // <o> Beat Size |
| 6570 | // <0=> 8-bit bus transfer |
| 6571 | // <1=> 16-bit bus transfer |
| 6572 | // <2=> 32-bit bus transfer |
| 6573 | // <i> Defines the size of one beat |
| 6574 | // <id> dmac_beatsize_28 |
| 6575 | #ifndef CONF_DMAC_BEATSIZE_28 |
| 6576 | #define CONF_DMAC_BEATSIZE_28 0 |
| 6577 | #endif |
| 6578 | |
| 6579 | // <o> Block Action |
| 6580 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 6581 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 6582 | // <2=> Channel suspend operation is complete |
| 6583 | // <3=> Both channel suspend operation and block interrupt |
| 6584 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 6585 | // <id> dmac_blockact_28 |
| 6586 | #ifndef CONF_DMAC_BLOCKACT_28 |
| 6587 | #define CONF_DMAC_BLOCKACT_28 0 |
| 6588 | #endif |
| 6589 | |
| 6590 | // <o> Event Output Selection |
| 6591 | // <0=> Event generation disabled |
| 6592 | // <1=> Event strobe when block transfer complete |
| 6593 | // <3=> Event strobe when beat transfer complete |
| 6594 | // <i> Defines the event output selection |
| 6595 | // <id> dmac_evosel_28 |
| 6596 | #ifndef CONF_DMAC_EVOSEL_28 |
| 6597 | #define CONF_DMAC_EVOSEL_28 0 |
| 6598 | #endif |
| 6599 | // </e> |
| 6600 | |
| 6601 | // <e> Channel 29 settings |
| 6602 | // <id> dmac_channel_29_settings |
| 6603 | #ifndef CONF_DMAC_CHANNEL_29_SETTINGS |
| 6604 | #define CONF_DMAC_CHANNEL_29_SETTINGS 0 |
| 6605 | #endif |
| 6606 | |
| 6607 | // <q> Channel Run in Standby |
| 6608 | // <i> Indicates whether channel 29 is running in standby mode or not |
| 6609 | // <id> dmac_runstdby_29 |
| 6610 | #ifndef CONF_DMAC_RUNSTDBY_29 |
| 6611 | #define CONF_DMAC_RUNSTDBY_29 0 |
| 6612 | #endif |
| 6613 | |
| 6614 | // <o> Trigger action |
| 6615 | // <0=> One trigger required for each block transfer |
| 6616 | // <2=> One trigger required for each beat transfer |
| 6617 | // <3=> One trigger required for each transaction |
| 6618 | // <i> Defines the trigger action used for a transfer |
| 6619 | // <id> dmac_trigact_29 |
| 6620 | #ifndef CONF_DMAC_TRIGACT_29 |
| 6621 | #define CONF_DMAC_TRIGACT_29 0 |
| 6622 | #endif |
| 6623 | |
| 6624 | // <o> Trigger source |
| 6625 | // <0x00=> Only software/event triggers |
| 6626 | // <0x01=> RTC Time Stamp Trigger |
| 6627 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 6628 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 6629 | // <0x04=> SERCOM0 RX Trigger |
| 6630 | // <0x05=> SERCOM0 TX Trigger |
| 6631 | // <0x06=> SERCOM1 RX Trigger |
| 6632 | // <0x07=> SERCOM1 TX Trigger |
| 6633 | // <0x08=> SERCOM2 RX Trigger |
| 6634 | // <0x09=> SERCOM2 TX Trigger |
| 6635 | // <0x0A=> SERCOM3 RX Trigger |
| 6636 | // <0x0B=> SERCOM3 TX Trigger |
| 6637 | // <0x0C=> SERCOM4 RX Trigger |
| 6638 | // <0x0D=> SERCOM4 TX Trigger |
| 6639 | // <0x0E=> SERCOM5 RX Trigger |
| 6640 | // <0x0F=> SERCOM5 TX Trigger |
| 6641 | // <0x10=> SERCOM6 RX Trigger |
| 6642 | // <0x11=> SERCOM6 TX Trigger |
| 6643 | // <0x12=> SERCOM7 RX Trigger |
| 6644 | // <0x13=> SERCOM7 TX Trigger |
| 6645 | // <0x14=> CAN0 DEBUG Trigger |
| 6646 | // <0x15=> CAN1 DEBUG Trigger |
| 6647 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 6648 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 6649 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 6650 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 6651 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 6652 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 6653 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 6654 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 6655 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 6656 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 6657 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 6658 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 6659 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 6660 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 6661 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 6662 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 6663 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 6664 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 6665 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 6666 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 6667 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 6668 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 6669 | // <0x2C=> TC0 Overflow Trigger |
| 6670 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 6671 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 6672 | // <0x2F=> TC1 Overflow Trigger |
| 6673 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 6674 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 6675 | // <0x32=> TC2 Overflow Trigger |
| 6676 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 6677 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 6678 | // <0x35=> TC3 Overflow Trigger |
| 6679 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 6680 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 6681 | // <0x38=> TC4 Overflow Trigger |
| 6682 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 6683 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 6684 | // <0x3B=> TC5 Overflow Trigger |
| 6685 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 6686 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 6687 | // <0x3E=> TC6 Overflow Trigger |
| 6688 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 6689 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 6690 | // <0x41=> TC7 Overflow Trigger |
| 6691 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 6692 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 6693 | // <0x44=> ADC0 Result Ready Trigger |
| 6694 | // <0x45=> ADC0 Sequencing Trigger |
| 6695 | // <0x46=> ADC1 Result Ready Trigger |
| 6696 | // <0x47=> ADC1 Sequencing Trigger |
| 6697 | // <0x48=> DAC Empty 0 Trigger |
| 6698 | // <0x49=> DAC Empty 1 Trigger |
| 6699 | // <0x4A=> DAC Result Ready 0 Trigger |
| 6700 | // <0x4B=> DAC Result Ready 1 Trigger |
| 6701 | // <0x4C=> I2S Rx 0 Trigger |
| 6702 | // <0x4D=> I2S Rx 1 Trigger |
| 6703 | // <0x4E=> I2S Tx 0 Trigger |
| 6704 | // <0x4F=> I2S Tx 1 Trigger |
| 6705 | // <0x50=> PCC RX Trigger |
| 6706 | // <0x51=> AES Write Trigger |
| 6707 | // <0x52=> AES Read Trigger |
| 6708 | // <0x53=> QSPI Rx Trigger |
| 6709 | // <0x54=> QSPI Tx Trigger |
| 6710 | // <i> Defines the peripheral trigger which is source of the transfer |
| 6711 | // <id> dmac_trifsrc_29 |
| 6712 | #ifndef CONF_DMAC_TRIGSRC_29 |
| 6713 | #define CONF_DMAC_TRIGSRC_29 0 |
| 6714 | #endif |
| 6715 | |
| 6716 | // <o> Channel Arbitration Level |
| 6717 | // <0=> Channel priority 0 |
| 6718 | // <1=> Channel priority 1 |
| 6719 | // <2=> Channel priority 2 |
| 6720 | // <3=> Channel priority 3 |
| 6721 | // <i> Defines the arbitration level for this channel |
| 6722 | // <id> dmac_lvl_29 |
| 6723 | #ifndef CONF_DMAC_LVL_29 |
| 6724 | #define CONF_DMAC_LVL_29 0 |
| 6725 | #endif |
| 6726 | |
| 6727 | // <q> Channel Event Output |
| 6728 | // <i> Indicates whether channel event generation is enabled or not |
| 6729 | // <id> dmac_evoe_29 |
| 6730 | #ifndef CONF_DMAC_EVOE_29 |
| 6731 | #define CONF_DMAC_EVOE_29 0 |
| 6732 | #endif |
| 6733 | |
| 6734 | // <q> Channel Event Input |
| 6735 | // <i> Indicates whether channel event reception is enabled or not |
| 6736 | // <id> dmac_evie_29 |
| 6737 | #ifndef CONF_DMAC_EVIE_29 |
| 6738 | #define CONF_DMAC_EVIE_29 0 |
| 6739 | #endif |
| 6740 | |
| 6741 | // <o> Event Input Action |
| 6742 | // <0=> No action |
| 6743 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 6744 | // <2=> Conditional transfer trigger |
| 6745 | // <3=> Conditional block transfer |
| 6746 | // <4=> Channel suspend operation |
| 6747 | // <5=> Channel resume operation |
| 6748 | // <6=> Skip next block suspend action |
| 6749 | // <i> Defines the event input action |
| 6750 | // <id> dmac_evact_29 |
| 6751 | #ifndef CONF_DMAC_EVACT_29 |
| 6752 | #define CONF_DMAC_EVACT_29 0 |
| 6753 | #endif |
| 6754 | |
| 6755 | // <o> Address Increment Step Size |
| 6756 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 6757 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 6758 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 6759 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 6760 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 6761 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 6762 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 6763 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 6764 | // <i> Defines the address increment step size, applies to source or destination address |
| 6765 | // <id> dmac_stepsize_29 |
| 6766 | #ifndef CONF_DMAC_STEPSIZE_29 |
| 6767 | #define CONF_DMAC_STEPSIZE_29 0 |
| 6768 | #endif |
| 6769 | |
| 6770 | // <o> Step Selection |
| 6771 | // <0=> Step size settings apply to the destination address |
| 6772 | // <1=> Step size settings apply to the source address |
| 6773 | // <i> Defines whether source or destination addresses are using the step size settings |
| 6774 | // <id> dmac_stepsel_29 |
| 6775 | #ifndef CONF_DMAC_STEPSEL_29 |
| 6776 | #define CONF_DMAC_STEPSEL_29 0 |
| 6777 | #endif |
| 6778 | |
| 6779 | // <q> Source Address Increment |
| 6780 | // <i> Indicates whether the source address incrementation is enabled or not |
| 6781 | // <id> dmac_srcinc_29 |
| 6782 | #ifndef CONF_DMAC_SRCINC_29 |
| 6783 | #define CONF_DMAC_SRCINC_29 0 |
| 6784 | #endif |
| 6785 | |
| 6786 | // <q> Destination Address Increment |
| 6787 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 6788 | // <id> dmac_dstinc_29 |
| 6789 | #ifndef CONF_DMAC_DSTINC_29 |
| 6790 | #define CONF_DMAC_DSTINC_29 0 |
| 6791 | #endif |
| 6792 | |
| 6793 | // <o> Beat Size |
| 6794 | // <0=> 8-bit bus transfer |
| 6795 | // <1=> 16-bit bus transfer |
| 6796 | // <2=> 32-bit bus transfer |
| 6797 | // <i> Defines the size of one beat |
| 6798 | // <id> dmac_beatsize_29 |
| 6799 | #ifndef CONF_DMAC_BEATSIZE_29 |
| 6800 | #define CONF_DMAC_BEATSIZE_29 0 |
| 6801 | #endif |
| 6802 | |
| 6803 | // <o> Block Action |
| 6804 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 6805 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 6806 | // <2=> Channel suspend operation is complete |
| 6807 | // <3=> Both channel suspend operation and block interrupt |
| 6808 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 6809 | // <id> dmac_blockact_29 |
| 6810 | #ifndef CONF_DMAC_BLOCKACT_29 |
| 6811 | #define CONF_DMAC_BLOCKACT_29 0 |
| 6812 | #endif |
| 6813 | |
| 6814 | // <o> Event Output Selection |
| 6815 | // <0=> Event generation disabled |
| 6816 | // <1=> Event strobe when block transfer complete |
| 6817 | // <3=> Event strobe when beat transfer complete |
| 6818 | // <i> Defines the event output selection |
| 6819 | // <id> dmac_evosel_29 |
| 6820 | #ifndef CONF_DMAC_EVOSEL_29 |
| 6821 | #define CONF_DMAC_EVOSEL_29 0 |
| 6822 | #endif |
| 6823 | // </e> |
| 6824 | |
| 6825 | // <e> Channel 30 settings |
| 6826 | // <id> dmac_channel_30_settings |
| 6827 | #ifndef CONF_DMAC_CHANNEL_30_SETTINGS |
| 6828 | #define CONF_DMAC_CHANNEL_30_SETTINGS 0 |
| 6829 | #endif |
| 6830 | |
| 6831 | // <q> Channel Run in Standby |
| 6832 | // <i> Indicates whether channel 30 is running in standby mode or not |
| 6833 | // <id> dmac_runstdby_30 |
| 6834 | #ifndef CONF_DMAC_RUNSTDBY_30 |
| 6835 | #define CONF_DMAC_RUNSTDBY_30 0 |
| 6836 | #endif |
| 6837 | |
| 6838 | // <o> Trigger action |
| 6839 | // <0=> One trigger required for each block transfer |
| 6840 | // <2=> One trigger required for each beat transfer |
| 6841 | // <3=> One trigger required for each transaction |
| 6842 | // <i> Defines the trigger action used for a transfer |
| 6843 | // <id> dmac_trigact_30 |
| 6844 | #ifndef CONF_DMAC_TRIGACT_30 |
| 6845 | #define CONF_DMAC_TRIGACT_30 0 |
| 6846 | #endif |
| 6847 | |
| 6848 | // <o> Trigger source |
| 6849 | // <0x00=> Only software/event triggers |
| 6850 | // <0x01=> RTC Time Stamp Trigger |
| 6851 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 6852 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 6853 | // <0x04=> SERCOM0 RX Trigger |
| 6854 | // <0x05=> SERCOM0 TX Trigger |
| 6855 | // <0x06=> SERCOM1 RX Trigger |
| 6856 | // <0x07=> SERCOM1 TX Trigger |
| 6857 | // <0x08=> SERCOM2 RX Trigger |
| 6858 | // <0x09=> SERCOM2 TX Trigger |
| 6859 | // <0x0A=> SERCOM3 RX Trigger |
| 6860 | // <0x0B=> SERCOM3 TX Trigger |
| 6861 | // <0x0C=> SERCOM4 RX Trigger |
| 6862 | // <0x0D=> SERCOM4 TX Trigger |
| 6863 | // <0x0E=> SERCOM5 RX Trigger |
| 6864 | // <0x0F=> SERCOM5 TX Trigger |
| 6865 | // <0x10=> SERCOM6 RX Trigger |
| 6866 | // <0x11=> SERCOM6 TX Trigger |
| 6867 | // <0x12=> SERCOM7 RX Trigger |
| 6868 | // <0x13=> SERCOM7 TX Trigger |
| 6869 | // <0x14=> CAN0 DEBUG Trigger |
| 6870 | // <0x15=> CAN1 DEBUG Trigger |
| 6871 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 6872 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 6873 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 6874 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 6875 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 6876 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 6877 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 6878 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 6879 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 6880 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 6881 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 6882 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 6883 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 6884 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 6885 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 6886 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 6887 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 6888 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 6889 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 6890 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 6891 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 6892 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 6893 | // <0x2C=> TC0 Overflow Trigger |
| 6894 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 6895 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 6896 | // <0x2F=> TC1 Overflow Trigger |
| 6897 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 6898 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 6899 | // <0x32=> TC2 Overflow Trigger |
| 6900 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 6901 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 6902 | // <0x35=> TC3 Overflow Trigger |
| 6903 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 6904 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 6905 | // <0x38=> TC4 Overflow Trigger |
| 6906 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 6907 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 6908 | // <0x3B=> TC5 Overflow Trigger |
| 6909 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 6910 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 6911 | // <0x3E=> TC6 Overflow Trigger |
| 6912 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 6913 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 6914 | // <0x41=> TC7 Overflow Trigger |
| 6915 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 6916 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 6917 | // <0x44=> ADC0 Result Ready Trigger |
| 6918 | // <0x45=> ADC0 Sequencing Trigger |
| 6919 | // <0x46=> ADC1 Result Ready Trigger |
| 6920 | // <0x47=> ADC1 Sequencing Trigger |
| 6921 | // <0x48=> DAC Empty 0 Trigger |
| 6922 | // <0x49=> DAC Empty 1 Trigger |
| 6923 | // <0x4A=> DAC Result Ready 0 Trigger |
| 6924 | // <0x4B=> DAC Result Ready 1 Trigger |
| 6925 | // <0x4C=> I2S Rx 0 Trigger |
| 6926 | // <0x4D=> I2S Rx 1 Trigger |
| 6927 | // <0x4E=> I2S Tx 0 Trigger |
| 6928 | // <0x4F=> I2S Tx 1 Trigger |
| 6929 | // <0x50=> PCC RX Trigger |
| 6930 | // <0x51=> AES Write Trigger |
| 6931 | // <0x52=> AES Read Trigger |
| 6932 | // <0x53=> QSPI Rx Trigger |
| 6933 | // <0x54=> QSPI Tx Trigger |
| 6934 | // <i> Defines the peripheral trigger which is source of the transfer |
| 6935 | // <id> dmac_trifsrc_30 |
| 6936 | #ifndef CONF_DMAC_TRIGSRC_30 |
| 6937 | #define CONF_DMAC_TRIGSRC_30 0 |
| 6938 | #endif |
| 6939 | |
| 6940 | // <o> Channel Arbitration Level |
| 6941 | // <0=> Channel priority 0 |
| 6942 | // <1=> Channel priority 1 |
| 6943 | // <2=> Channel priority 2 |
| 6944 | // <3=> Channel priority 3 |
| 6945 | // <i> Defines the arbitration level for this channel |
| 6946 | // <id> dmac_lvl_30 |
| 6947 | #ifndef CONF_DMAC_LVL_30 |
| 6948 | #define CONF_DMAC_LVL_30 0 |
| 6949 | #endif |
| 6950 | |
| 6951 | // <q> Channel Event Output |
| 6952 | // <i> Indicates whether channel event generation is enabled or not |
| 6953 | // <id> dmac_evoe_30 |
| 6954 | #ifndef CONF_DMAC_EVOE_30 |
| 6955 | #define CONF_DMAC_EVOE_30 0 |
| 6956 | #endif |
| 6957 | |
| 6958 | // <q> Channel Event Input |
| 6959 | // <i> Indicates whether channel event reception is enabled or not |
| 6960 | // <id> dmac_evie_30 |
| 6961 | #ifndef CONF_DMAC_EVIE_30 |
| 6962 | #define CONF_DMAC_EVIE_30 0 |
| 6963 | #endif |
| 6964 | |
| 6965 | // <o> Event Input Action |
| 6966 | // <0=> No action |
| 6967 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 6968 | // <2=> Conditional transfer trigger |
| 6969 | // <3=> Conditional block transfer |
| 6970 | // <4=> Channel suspend operation |
| 6971 | // <5=> Channel resume operation |
| 6972 | // <6=> Skip next block suspend action |
| 6973 | // <i> Defines the event input action |
| 6974 | // <id> dmac_evact_30 |
| 6975 | #ifndef CONF_DMAC_EVACT_30 |
| 6976 | #define CONF_DMAC_EVACT_30 0 |
| 6977 | #endif |
| 6978 | |
| 6979 | // <o> Address Increment Step Size |
| 6980 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 6981 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 6982 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 6983 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 6984 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 6985 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 6986 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 6987 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 6988 | // <i> Defines the address increment step size, applies to source or destination address |
| 6989 | // <id> dmac_stepsize_30 |
| 6990 | #ifndef CONF_DMAC_STEPSIZE_30 |
| 6991 | #define CONF_DMAC_STEPSIZE_30 0 |
| 6992 | #endif |
| 6993 | |
| 6994 | // <o> Step Selection |
| 6995 | // <0=> Step size settings apply to the destination address |
| 6996 | // <1=> Step size settings apply to the source address |
| 6997 | // <i> Defines whether source or destination addresses are using the step size settings |
| 6998 | // <id> dmac_stepsel_30 |
| 6999 | #ifndef CONF_DMAC_STEPSEL_30 |
| 7000 | #define CONF_DMAC_STEPSEL_30 0 |
| 7001 | #endif |
| 7002 | |
| 7003 | // <q> Source Address Increment |
| 7004 | // <i> Indicates whether the source address incrementation is enabled or not |
| 7005 | // <id> dmac_srcinc_30 |
| 7006 | #ifndef CONF_DMAC_SRCINC_30 |
| 7007 | #define CONF_DMAC_SRCINC_30 0 |
| 7008 | #endif |
| 7009 | |
| 7010 | // <q> Destination Address Increment |
| 7011 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 7012 | // <id> dmac_dstinc_30 |
| 7013 | #ifndef CONF_DMAC_DSTINC_30 |
| 7014 | #define CONF_DMAC_DSTINC_30 0 |
| 7015 | #endif |
| 7016 | |
| 7017 | // <o> Beat Size |
| 7018 | // <0=> 8-bit bus transfer |
| 7019 | // <1=> 16-bit bus transfer |
| 7020 | // <2=> 32-bit bus transfer |
| 7021 | // <i> Defines the size of one beat |
| 7022 | // <id> dmac_beatsize_30 |
| 7023 | #ifndef CONF_DMAC_BEATSIZE_30 |
| 7024 | #define CONF_DMAC_BEATSIZE_30 0 |
| 7025 | #endif |
| 7026 | |
| 7027 | // <o> Block Action |
| 7028 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 7029 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 7030 | // <2=> Channel suspend operation is complete |
| 7031 | // <3=> Both channel suspend operation and block interrupt |
| 7032 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 7033 | // <id> dmac_blockact_30 |
| 7034 | #ifndef CONF_DMAC_BLOCKACT_30 |
| 7035 | #define CONF_DMAC_BLOCKACT_30 0 |
| 7036 | #endif |
| 7037 | |
| 7038 | // <o> Event Output Selection |
| 7039 | // <0=> Event generation disabled |
| 7040 | // <1=> Event strobe when block transfer complete |
| 7041 | // <3=> Event strobe when beat transfer complete |
| 7042 | // <i> Defines the event output selection |
| 7043 | // <id> dmac_evosel_30 |
| 7044 | #ifndef CONF_DMAC_EVOSEL_30 |
| 7045 | #define CONF_DMAC_EVOSEL_30 0 |
| 7046 | #endif |
| 7047 | // </e> |
| 7048 | |
| 7049 | // <e> Channel 31 settings |
| 7050 | // <id> dmac_channel_31_settings |
| 7051 | #ifndef CONF_DMAC_CHANNEL_31_SETTINGS |
| 7052 | #define CONF_DMAC_CHANNEL_31_SETTINGS 0 |
| 7053 | #endif |
| 7054 | |
| 7055 | // <q> Channel Run in Standby |
| 7056 | // <i> Indicates whether channel 31 is running in standby mode or not |
| 7057 | // <id> dmac_runstdby_31 |
| 7058 | #ifndef CONF_DMAC_RUNSTDBY_31 |
| 7059 | #define CONF_DMAC_RUNSTDBY_31 0 |
| 7060 | #endif |
| 7061 | |
| 7062 | // <o> Trigger action |
| 7063 | // <0=> One trigger required for each block transfer |
| 7064 | // <2=> One trigger required for each beat transfer |
| 7065 | // <3=> One trigger required for each transaction |
| 7066 | // <i> Defines the trigger action used for a transfer |
| 7067 | // <id> dmac_trigact_31 |
| 7068 | #ifndef CONF_DMAC_TRIGACT_31 |
| 7069 | #define CONF_DMAC_TRIGACT_31 0 |
| 7070 | #endif |
| 7071 | |
| 7072 | // <o> Trigger source |
| 7073 | // <0x00=> Only software/event triggers |
| 7074 | // <0x01=> RTC Time Stamp Trigger |
| 7075 | // <0x02=> DSU Debug Communication Channel 0 Trigger |
| 7076 | // <0x03=> DSU Debug Communication Channel 1 Trigger |
| 7077 | // <0x04=> SERCOM0 RX Trigger |
| 7078 | // <0x05=> SERCOM0 TX Trigger |
| 7079 | // <0x06=> SERCOM1 RX Trigger |
| 7080 | // <0x07=> SERCOM1 TX Trigger |
| 7081 | // <0x08=> SERCOM2 RX Trigger |
| 7082 | // <0x09=> SERCOM2 TX Trigger |
| 7083 | // <0x0A=> SERCOM3 RX Trigger |
| 7084 | // <0x0B=> SERCOM3 TX Trigger |
| 7085 | // <0x0C=> SERCOM4 RX Trigger |
| 7086 | // <0x0D=> SERCOM4 TX Trigger |
| 7087 | // <0x0E=> SERCOM5 RX Trigger |
| 7088 | // <0x0F=> SERCOM5 TX Trigger |
| 7089 | // <0x10=> SERCOM6 RX Trigger |
| 7090 | // <0x11=> SERCOM6 TX Trigger |
| 7091 | // <0x12=> SERCOM7 RX Trigger |
| 7092 | // <0x13=> SERCOM7 TX Trigger |
| 7093 | // <0x14=> CAN0 DEBUG Trigger |
| 7094 | // <0x15=> CAN1 DEBUG Trigger |
| 7095 | // <0x16=> TCC0 Overflow Trigger Trigger |
| 7096 | // <0x17=> TCC0 Match/Compare 0 Trigger Trigger |
| 7097 | // <0x18=> TCC0 Match/Compare 1 Trigger Trigger |
| 7098 | // <0x19=> TCC0 Match/Compare 2 Trigger Trigger |
| 7099 | // <0x1A=> TCC0 Match/Compare 3 Trigger Trigger |
| 7100 | // <0x1B=> TCC0 Match/Compare 4 Trigger Trigger |
| 7101 | // <0x1C=> TCC0 Match/Compare 5 Trigger Trigger |
| 7102 | // <0x1D=> TCC1 Overflow Trigger Trigger |
| 7103 | // <0x1E=> TCC1 Match/Compare 0 Trigger Trigger |
| 7104 | // <0x1F=> TCC1 Match/Compare 1 Trigger Trigger |
| 7105 | // <0x20=> TCC1 Match/Compare 2 Trigger Trigger |
| 7106 | // <0x21=> TCC1 Match/Compare 3 Trigger Trigger |
| 7107 | // <0x22=> TCC2 Overflow Trigger Trigger |
| 7108 | // <0x23=> TCC2 Match/Compare 0 Trigger Trigger |
| 7109 | // <0x24=> TCC2 Match/Compare 1 Trigger Trigger |
| 7110 | // <0x25=> TCC2 Match/Compare 2 Trigger Trigger |
| 7111 | // <0x26=> TCC3 Overflow Trigger Trigger |
| 7112 | // <0x27=> TCC3 Match/Compare 0 Trigger Trigger |
| 7113 | // <0x28=> TCC3 Match/Compare 1 Trigger Trigger |
| 7114 | // <0x29=> TCC4 Overflow Trigger Trigger |
| 7115 | // <0x2A=> TCC4 Match/Compare 0 Trigger Trigger |
| 7116 | // <0x2B=> TCC4 Match/Compare 1 Trigger Trigger |
| 7117 | // <0x2C=> TC0 Overflow Trigger |
| 7118 | // <0x2D=> TC0 Match/Compare 0 Trigger |
| 7119 | // <0x2E=> TC0 Match/Compare 1 Trigger |
| 7120 | // <0x2F=> TC1 Overflow Trigger |
| 7121 | // <0x30=> TC1 Match/Compare 0 Trigger |
| 7122 | // <0x31=> TC1 Match/Compare 1 Trigger |
| 7123 | // <0x32=> TC2 Overflow Trigger |
| 7124 | // <0x33=> TC2 Match/Compare 0 Trigger |
| 7125 | // <0x34=> TC2 Match/Compare 1 Trigger |
| 7126 | // <0x35=> TC3 Overflow Trigger |
| 7127 | // <0x36=> TC3 Match/Compare 0 Trigger |
| 7128 | // <0x37=> TC3 Match/Compare 1 Trigger |
| 7129 | // <0x38=> TC4 Overflow Trigger |
| 7130 | // <0x39=> TC4 Match/Compare 0 Trigger |
| 7131 | // <0x3A=> TC4 Match/Compare 1 Trigger |
| 7132 | // <0x3B=> TC5 Overflow Trigger |
| 7133 | // <0x3C=> TC5 Match/Compare 0 Trigger |
| 7134 | // <0x3D=> TC5 Match/Compare 1 Trigger |
| 7135 | // <0x3E=> TC6 Overflow Trigger |
| 7136 | // <0x3F=> TC6 Match/Compare 0 Trigger |
| 7137 | // <0x40=> TC6 Match/Compare 1 Trigger |
| 7138 | // <0x41=> TC7 Overflow Trigger |
| 7139 | // <0x42=> TC7 Match/Compare 0 Trigger |
| 7140 | // <0x43=> TC7 Match/Compare 1 Trigger |
| 7141 | // <0x44=> ADC0 Result Ready Trigger |
| 7142 | // <0x45=> ADC0 Sequencing Trigger |
| 7143 | // <0x46=> ADC1 Result Ready Trigger |
| 7144 | // <0x47=> ADC1 Sequencing Trigger |
| 7145 | // <0x48=> DAC Empty 0 Trigger |
| 7146 | // <0x49=> DAC Empty 1 Trigger |
| 7147 | // <0x4A=> DAC Result Ready 0 Trigger |
| 7148 | // <0x4B=> DAC Result Ready 1 Trigger |
| 7149 | // <0x4C=> I2S Rx 0 Trigger |
| 7150 | // <0x4D=> I2S Rx 1 Trigger |
| 7151 | // <0x4E=> I2S Tx 0 Trigger |
| 7152 | // <0x4F=> I2S Tx 1 Trigger |
| 7153 | // <0x50=> PCC RX Trigger |
| 7154 | // <0x51=> AES Write Trigger |
| 7155 | // <0x52=> AES Read Trigger |
| 7156 | // <0x53=> QSPI Rx Trigger |
| 7157 | // <0x54=> QSPI Tx Trigger |
| 7158 | // <i> Defines the peripheral trigger which is source of the transfer |
| 7159 | // <id> dmac_trifsrc_31 |
| 7160 | #ifndef CONF_DMAC_TRIGSRC_31 |
| 7161 | #define CONF_DMAC_TRIGSRC_31 0 |
| 7162 | #endif |
| 7163 | |
| 7164 | // <o> Channel Arbitration Level |
| 7165 | // <0=> Channel priority 0 |
| 7166 | // <1=> Channel priority 1 |
| 7167 | // <2=> Channel priority 2 |
| 7168 | // <3=> Channel priority 3 |
| 7169 | // <i> Defines the arbitration level for this channel |
| 7170 | // <id> dmac_lvl_31 |
| 7171 | #ifndef CONF_DMAC_LVL_31 |
| 7172 | #define CONF_DMAC_LVL_31 0 |
| 7173 | #endif |
| 7174 | |
| 7175 | // <q> Channel Event Output |
| 7176 | // <i> Indicates whether channel event generation is enabled or not |
| 7177 | // <id> dmac_evoe_31 |
| 7178 | #ifndef CONF_DMAC_EVOE_31 |
| 7179 | #define CONF_DMAC_EVOE_31 0 |
| 7180 | #endif |
| 7181 | |
| 7182 | // <q> Channel Event Input |
| 7183 | // <i> Indicates whether channel event reception is enabled or not |
| 7184 | // <id> dmac_evie_31 |
| 7185 | #ifndef CONF_DMAC_EVIE_31 |
| 7186 | #define CONF_DMAC_EVIE_31 0 |
| 7187 | #endif |
| 7188 | |
| 7189 | // <o> Event Input Action |
| 7190 | // <0=> No action |
| 7191 | // <1=> Normal transfer and conditional transfer on strobe trigger |
| 7192 | // <2=> Conditional transfer trigger |
| 7193 | // <3=> Conditional block transfer |
| 7194 | // <4=> Channel suspend operation |
| 7195 | // <5=> Channel resume operation |
| 7196 | // <6=> Skip next block suspend action |
| 7197 | // <i> Defines the event input action |
| 7198 | // <id> dmac_evact_31 |
| 7199 | #ifndef CONF_DMAC_EVACT_31 |
| 7200 | #define CONF_DMAC_EVACT_31 0 |
| 7201 | #endif |
| 7202 | |
| 7203 | // <o> Address Increment Step Size |
| 7204 | // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| 7205 | // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 |
| 7206 | // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 |
| 7207 | // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 |
| 7208 | // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 |
| 7209 | // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 |
| 7210 | // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 |
| 7211 | // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 |
| 7212 | // <i> Defines the address increment step size, applies to source or destination address |
| 7213 | // <id> dmac_stepsize_31 |
| 7214 | #ifndef CONF_DMAC_STEPSIZE_31 |
| 7215 | #define CONF_DMAC_STEPSIZE_31 0 |
| 7216 | #endif |
| 7217 | |
| 7218 | // <o> Step Selection |
| 7219 | // <0=> Step size settings apply to the destination address |
| 7220 | // <1=> Step size settings apply to the source address |
| 7221 | // <i> Defines whether source or destination addresses are using the step size settings |
| 7222 | // <id> dmac_stepsel_31 |
| 7223 | #ifndef CONF_DMAC_STEPSEL_31 |
| 7224 | #define CONF_DMAC_STEPSEL_31 0 |
| 7225 | #endif |
| 7226 | |
| 7227 | // <q> Source Address Increment |
| 7228 | // <i> Indicates whether the source address incrementation is enabled or not |
| 7229 | // <id> dmac_srcinc_31 |
| 7230 | #ifndef CONF_DMAC_SRCINC_31 |
| 7231 | #define CONF_DMAC_SRCINC_31 0 |
| 7232 | #endif |
| 7233 | |
| 7234 | // <q> Destination Address Increment |
| 7235 | // <i> Indicates whether the destination address incrementation is enabled or not |
| 7236 | // <id> dmac_dstinc_31 |
| 7237 | #ifndef CONF_DMAC_DSTINC_31 |
| 7238 | #define CONF_DMAC_DSTINC_31 0 |
| 7239 | #endif |
| 7240 | |
| 7241 | // <o> Beat Size |
| 7242 | // <0=> 8-bit bus transfer |
| 7243 | // <1=> 16-bit bus transfer |
| 7244 | // <2=> 32-bit bus transfer |
| 7245 | // <i> Defines the size of one beat |
| 7246 | // <id> dmac_beatsize_31 |
| 7247 | #ifndef CONF_DMAC_BEATSIZE_31 |
| 7248 | #define CONF_DMAC_BEATSIZE_31 0 |
| 7249 | #endif |
| 7250 | |
| 7251 | // <o> Block Action |
| 7252 | // <0=> Channel will be disabled if it is the last block transfer in the transaction |
| 7253 | // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
| 7254 | // <2=> Channel suspend operation is complete |
| 7255 | // <3=> Both channel suspend operation and block interrupt |
| 7256 | // <i> Defines the the DMAC should take after a block transfer has completed |
| 7257 | // <id> dmac_blockact_31 |
| 7258 | #ifndef CONF_DMAC_BLOCKACT_31 |
| 7259 | #define CONF_DMAC_BLOCKACT_31 0 |
| 7260 | #endif |
| 7261 | |
| 7262 | // <o> Event Output Selection |
| 7263 | // <0=> Event generation disabled |
| 7264 | // <1=> Event strobe when block transfer complete |
| 7265 | // <3=> Event strobe when beat transfer complete |
| 7266 | // <i> Defines the event output selection |
| 7267 | // <id> dmac_evosel_31 |
| 7268 | #ifndef CONF_DMAC_EVOSEL_31 |
| 7269 | #define CONF_DMAC_EVOSEL_31 0 |
| 7270 | #endif |
| 7271 | // </e> |
| 7272 | |
| 7273 | // </e> |
| 7274 | |
| 7275 | // <<< end of configuration section >>> |
| 7276 | |
| 7277 | #endif // HPL_DMAC_CONFIG_H |