Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for TC7 |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_TC7_INSTANCE_ |
| 31 | #define _SAME54_TC7_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for TC7 peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_TC7_CTRLA (0x43001800) /**< \brief (TC7) Control A */ |
| 36 | #define REG_TC7_CTRLBCLR (0x43001804) /**< \brief (TC7) Control B Clear */ |
| 37 | #define REG_TC7_CTRLBSET (0x43001805) /**< \brief (TC7) Control B Set */ |
| 38 | #define REG_TC7_EVCTRL (0x43001806) /**< \brief (TC7) Event Control */ |
| 39 | #define REG_TC7_INTENCLR (0x43001808) /**< \brief (TC7) Interrupt Enable Clear */ |
| 40 | #define REG_TC7_INTENSET (0x43001809) /**< \brief (TC7) Interrupt Enable Set */ |
| 41 | #define REG_TC7_INTFLAG (0x4300180A) /**< \brief (TC7) Interrupt Flag Status and Clear */ |
| 42 | #define REG_TC7_STATUS (0x4300180B) /**< \brief (TC7) Status */ |
| 43 | #define REG_TC7_WAVE (0x4300180C) /**< \brief (TC7) Waveform Generation Control */ |
| 44 | #define REG_TC7_DRVCTRL (0x4300180D) /**< \brief (TC7) Control C */ |
| 45 | #define REG_TC7_DBGCTRL (0x4300180F) /**< \brief (TC7) Debug Control */ |
| 46 | #define REG_TC7_SYNCBUSY (0x43001810) /**< \brief (TC7) Synchronization Status */ |
| 47 | #define REG_TC7_COUNT16_COUNT (0x43001814) /**< \brief (TC7) COUNT16 Count */ |
| 48 | #define REG_TC7_COUNT16_CC0 (0x4300181C) /**< \brief (TC7) COUNT16 Compare and Capture 0 */ |
| 49 | #define REG_TC7_COUNT16_CC1 (0x4300181E) /**< \brief (TC7) COUNT16 Compare and Capture 1 */ |
| 50 | #define REG_TC7_COUNT16_CCBUF0 (0x43001830) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */ |
| 51 | #define REG_TC7_COUNT16_CCBUF1 (0x43001832) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */ |
| 52 | #define REG_TC7_COUNT32_COUNT (0x43001814) /**< \brief (TC7) COUNT32 Count */ |
| 53 | #define REG_TC7_COUNT32_CC0 (0x4300181C) /**< \brief (TC7) COUNT32 Compare and Capture 0 */ |
| 54 | #define REG_TC7_COUNT32_CC1 (0x43001820) /**< \brief (TC7) COUNT32 Compare and Capture 1 */ |
| 55 | #define REG_TC7_COUNT32_CCBUF0 (0x43001830) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */ |
| 56 | #define REG_TC7_COUNT32_CCBUF1 (0x43001834) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */ |
| 57 | #define REG_TC7_COUNT8_COUNT (0x43001814) /**< \brief (TC7) COUNT8 Count */ |
| 58 | #define REG_TC7_COUNT8_PER (0x4300181B) /**< \brief (TC7) COUNT8 Period */ |
| 59 | #define REG_TC7_COUNT8_CC0 (0x4300181C) /**< \brief (TC7) COUNT8 Compare and Capture 0 */ |
| 60 | #define REG_TC7_COUNT8_CC1 (0x4300181D) /**< \brief (TC7) COUNT8 Compare and Capture 1 */ |
| 61 | #define REG_TC7_COUNT8_PERBUF (0x4300182F) /**< \brief (TC7) COUNT8 Period Buffer */ |
| 62 | #define REG_TC7_COUNT8_CCBUF0 (0x43001830) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */ |
| 63 | #define REG_TC7_COUNT8_CCBUF1 (0x43001831) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */ |
| 64 | #else |
| 65 | #define REG_TC7_CTRLA (*(RwReg *)0x43001800UL) /**< \brief (TC7) Control A */ |
| 66 | #define REG_TC7_CTRLBCLR (*(RwReg8 *)0x43001804UL) /**< \brief (TC7) Control B Clear */ |
| 67 | #define REG_TC7_CTRLBSET (*(RwReg8 *)0x43001805UL) /**< \brief (TC7) Control B Set */ |
| 68 | #define REG_TC7_EVCTRL (*(RwReg16*)0x43001806UL) /**< \brief (TC7) Event Control */ |
| 69 | #define REG_TC7_INTENCLR (*(RwReg8 *)0x43001808UL) /**< \brief (TC7) Interrupt Enable Clear */ |
| 70 | #define REG_TC7_INTENSET (*(RwReg8 *)0x43001809UL) /**< \brief (TC7) Interrupt Enable Set */ |
| 71 | #define REG_TC7_INTFLAG (*(RwReg8 *)0x4300180AUL) /**< \brief (TC7) Interrupt Flag Status and Clear */ |
| 72 | #define REG_TC7_STATUS (*(RwReg8 *)0x4300180BUL) /**< \brief (TC7) Status */ |
| 73 | #define REG_TC7_WAVE (*(RwReg8 *)0x4300180CUL) /**< \brief (TC7) Waveform Generation Control */ |
| 74 | #define REG_TC7_DRVCTRL (*(RwReg8 *)0x4300180DUL) /**< \brief (TC7) Control C */ |
| 75 | #define REG_TC7_DBGCTRL (*(RwReg8 *)0x4300180FUL) /**< \brief (TC7) Debug Control */ |
| 76 | #define REG_TC7_SYNCBUSY (*(RoReg *)0x43001810UL) /**< \brief (TC7) Synchronization Status */ |
| 77 | #define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x43001814UL) /**< \brief (TC7) COUNT16 Count */ |
| 78 | #define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x4300181CUL) /**< \brief (TC7) COUNT16 Compare and Capture 0 */ |
| 79 | #define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x4300181EUL) /**< \brief (TC7) COUNT16 Compare and Capture 1 */ |
| 80 | #define REG_TC7_COUNT16_CCBUF0 (*(RwReg16*)0x43001830UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */ |
| 81 | #define REG_TC7_COUNT16_CCBUF1 (*(RwReg16*)0x43001832UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */ |
| 82 | #define REG_TC7_COUNT32_COUNT (*(RwReg *)0x43001814UL) /**< \brief (TC7) COUNT32 Count */ |
| 83 | #define REG_TC7_COUNT32_CC0 (*(RwReg *)0x4300181CUL) /**< \brief (TC7) COUNT32 Compare and Capture 0 */ |
| 84 | #define REG_TC7_COUNT32_CC1 (*(RwReg *)0x43001820UL) /**< \brief (TC7) COUNT32 Compare and Capture 1 */ |
| 85 | #define REG_TC7_COUNT32_CCBUF0 (*(RwReg *)0x43001830UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */ |
| 86 | #define REG_TC7_COUNT32_CCBUF1 (*(RwReg *)0x43001834UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */ |
| 87 | #define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x43001814UL) /**< \brief (TC7) COUNT8 Count */ |
| 88 | #define REG_TC7_COUNT8_PER (*(RwReg8 *)0x4300181BUL) /**< \brief (TC7) COUNT8 Period */ |
| 89 | #define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x4300181CUL) /**< \brief (TC7) COUNT8 Compare and Capture 0 */ |
| 90 | #define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x4300181DUL) /**< \brief (TC7) COUNT8 Compare and Capture 1 */ |
| 91 | #define REG_TC7_COUNT8_PERBUF (*(RwReg8 *)0x4300182FUL) /**< \brief (TC7) COUNT8 Period Buffer */ |
| 92 | #define REG_TC7_COUNT8_CCBUF0 (*(RwReg8 *)0x43001830UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */ |
| 93 | #define REG_TC7_COUNT8_CCBUF1 (*(RwReg8 *)0x43001831UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */ |
| 94 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 95 | |
| 96 | /* ========== Instance parameters for TC7 peripheral ========== */ |
| 97 | #define TC7_CC_NUM 2 |
| 98 | #define TC7_DMAC_ID_MC_0 66 |
| 99 | #define TC7_DMAC_ID_MC_1 67 |
| 100 | #define TC7_DMAC_ID_MC_LSB 66 |
| 101 | #define TC7_DMAC_ID_MC_MSB 67 |
| 102 | #define TC7_DMAC_ID_MC_SIZE 2 |
| 103 | #define TC7_DMAC_ID_OVF 65 // Indexes of DMA Overflow trigger |
| 104 | #define TC7_EXT 0 // Coding of implemented extended features (keep 0 value) |
| 105 | #define TC7_GCLK_ID 39 // Index of Generic Clock |
| 106 | #define TC7_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave |
| 107 | #define TC7_OW_NUM 2 // Number of Output Waveforms |
| 108 | |
| 109 | #endif /* _SAME54_TC7_INSTANCE_ */ |