Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for PORT |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_PORT_INSTANCE_ |
| 31 | #define _SAME54_PORT_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for PORT peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_PORT_DIR0 (0x41008000) /**< \brief (PORT) Data Direction 0 */ |
| 36 | #define REG_PORT_DIRCLR0 (0x41008004) /**< \brief (PORT) Data Direction Clear 0 */ |
| 37 | #define REG_PORT_DIRSET0 (0x41008008) /**< \brief (PORT) Data Direction Set 0 */ |
| 38 | #define REG_PORT_DIRTGL0 (0x4100800C) /**< \brief (PORT) Data Direction Toggle 0 */ |
| 39 | #define REG_PORT_OUT0 (0x41008010) /**< \brief (PORT) Data Output Value 0 */ |
| 40 | #define REG_PORT_OUTCLR0 (0x41008014) /**< \brief (PORT) Data Output Value Clear 0 */ |
| 41 | #define REG_PORT_OUTSET0 (0x41008018) /**< \brief (PORT) Data Output Value Set 0 */ |
| 42 | #define REG_PORT_OUTTGL0 (0x4100801C) /**< \brief (PORT) Data Output Value Toggle 0 */ |
| 43 | #define REG_PORT_IN0 (0x41008020) /**< \brief (PORT) Data Input Value 0 */ |
| 44 | #define REG_PORT_CTRL0 (0x41008024) /**< \brief (PORT) Control 0 */ |
| 45 | #define REG_PORT_WRCONFIG0 (0x41008028) /**< \brief (PORT) Write Configuration 0 */ |
| 46 | #define REG_PORT_EVCTRL0 (0x4100802C) /**< \brief (PORT) Event Input Control 0 */ |
| 47 | #define REG_PORT_PMUX0 (0x41008030) /**< \brief (PORT) Peripheral Multiplexing 0 */ |
| 48 | #define REG_PORT_PINCFG0 (0x41008040) /**< \brief (PORT) Pin Configuration 0 */ |
| 49 | #define REG_PORT_DIR1 (0x41008080) /**< \brief (PORT) Data Direction 1 */ |
| 50 | #define REG_PORT_DIRCLR1 (0x41008084) /**< \brief (PORT) Data Direction Clear 1 */ |
| 51 | #define REG_PORT_DIRSET1 (0x41008088) /**< \brief (PORT) Data Direction Set 1 */ |
| 52 | #define REG_PORT_DIRTGL1 (0x4100808C) /**< \brief (PORT) Data Direction Toggle 1 */ |
| 53 | #define REG_PORT_OUT1 (0x41008090) /**< \brief (PORT) Data Output Value 1 */ |
| 54 | #define REG_PORT_OUTCLR1 (0x41008094) /**< \brief (PORT) Data Output Value Clear 1 */ |
| 55 | #define REG_PORT_OUTSET1 (0x41008098) /**< \brief (PORT) Data Output Value Set 1 */ |
| 56 | #define REG_PORT_OUTTGL1 (0x4100809C) /**< \brief (PORT) Data Output Value Toggle 1 */ |
| 57 | #define REG_PORT_IN1 (0x410080A0) /**< \brief (PORT) Data Input Value 1 */ |
| 58 | #define REG_PORT_CTRL1 (0x410080A4) /**< \brief (PORT) Control 1 */ |
| 59 | #define REG_PORT_WRCONFIG1 (0x410080A8) /**< \brief (PORT) Write Configuration 1 */ |
| 60 | #define REG_PORT_EVCTRL1 (0x410080AC) /**< \brief (PORT) Event Input Control 1 */ |
| 61 | #define REG_PORT_PMUX1 (0x410080B0) /**< \brief (PORT) Peripheral Multiplexing 1 */ |
| 62 | #define REG_PORT_PINCFG1 (0x410080C0) /**< \brief (PORT) Pin Configuration 1 */ |
| 63 | #define REG_PORT_DIR2 (0x41008100) /**< \brief (PORT) Data Direction 2 */ |
| 64 | #define REG_PORT_DIRCLR2 (0x41008104) /**< \brief (PORT) Data Direction Clear 2 */ |
| 65 | #define REG_PORT_DIRSET2 (0x41008108) /**< \brief (PORT) Data Direction Set 2 */ |
| 66 | #define REG_PORT_DIRTGL2 (0x4100810C) /**< \brief (PORT) Data Direction Toggle 2 */ |
| 67 | #define REG_PORT_OUT2 (0x41008110) /**< \brief (PORT) Data Output Value 2 */ |
| 68 | #define REG_PORT_OUTCLR2 (0x41008114) /**< \brief (PORT) Data Output Value Clear 2 */ |
| 69 | #define REG_PORT_OUTSET2 (0x41008118) /**< \brief (PORT) Data Output Value Set 2 */ |
| 70 | #define REG_PORT_OUTTGL2 (0x4100811C) /**< \brief (PORT) Data Output Value Toggle 2 */ |
| 71 | #define REG_PORT_IN2 (0x41008120) /**< \brief (PORT) Data Input Value 2 */ |
| 72 | #define REG_PORT_CTRL2 (0x41008124) /**< \brief (PORT) Control 2 */ |
| 73 | #define REG_PORT_WRCONFIG2 (0x41008128) /**< \brief (PORT) Write Configuration 2 */ |
| 74 | #define REG_PORT_EVCTRL2 (0x4100812C) /**< \brief (PORT) Event Input Control 2 */ |
| 75 | #define REG_PORT_PMUX2 (0x41008130) /**< \brief (PORT) Peripheral Multiplexing 2 */ |
| 76 | #define REG_PORT_PINCFG2 (0x41008140) /**< \brief (PORT) Pin Configuration 2 */ |
| 77 | #define REG_PORT_DIR3 (0x41008180) /**< \brief (PORT) Data Direction 3 */ |
| 78 | #define REG_PORT_DIRCLR3 (0x41008184) /**< \brief (PORT) Data Direction Clear 3 */ |
| 79 | #define REG_PORT_DIRSET3 (0x41008188) /**< \brief (PORT) Data Direction Set 3 */ |
| 80 | #define REG_PORT_DIRTGL3 (0x4100818C) /**< \brief (PORT) Data Direction Toggle 3 */ |
| 81 | #define REG_PORT_OUT3 (0x41008190) /**< \brief (PORT) Data Output Value 3 */ |
| 82 | #define REG_PORT_OUTCLR3 (0x41008194) /**< \brief (PORT) Data Output Value Clear 3 */ |
| 83 | #define REG_PORT_OUTSET3 (0x41008198) /**< \brief (PORT) Data Output Value Set 3 */ |
| 84 | #define REG_PORT_OUTTGL3 (0x4100819C) /**< \brief (PORT) Data Output Value Toggle 3 */ |
| 85 | #define REG_PORT_IN3 (0x410081A0) /**< \brief (PORT) Data Input Value 3 */ |
| 86 | #define REG_PORT_CTRL3 (0x410081A4) /**< \brief (PORT) Control 3 */ |
| 87 | #define REG_PORT_WRCONFIG3 (0x410081A8) /**< \brief (PORT) Write Configuration 3 */ |
| 88 | #define REG_PORT_EVCTRL3 (0x410081AC) /**< \brief (PORT) Event Input Control 3 */ |
| 89 | #define REG_PORT_PMUX3 (0x410081B0) /**< \brief (PORT) Peripheral Multiplexing 3 */ |
| 90 | #define REG_PORT_PINCFG3 (0x410081C0) /**< \brief (PORT) Pin Configuration 3 */ |
| 91 | #else |
| 92 | #define REG_PORT_DIR0 (*(RwReg *)0x41008000UL) /**< \brief (PORT) Data Direction 0 */ |
| 93 | #define REG_PORT_DIRCLR0 (*(RwReg *)0x41008004UL) /**< \brief (PORT) Data Direction Clear 0 */ |
| 94 | #define REG_PORT_DIRSET0 (*(RwReg *)0x41008008UL) /**< \brief (PORT) Data Direction Set 0 */ |
| 95 | #define REG_PORT_DIRTGL0 (*(RwReg *)0x4100800CUL) /**< \brief (PORT) Data Direction Toggle 0 */ |
| 96 | #define REG_PORT_OUT0 (*(RwReg *)0x41008010UL) /**< \brief (PORT) Data Output Value 0 */ |
| 97 | #define REG_PORT_OUTCLR0 (*(RwReg *)0x41008014UL) /**< \brief (PORT) Data Output Value Clear 0 */ |
| 98 | #define REG_PORT_OUTSET0 (*(RwReg *)0x41008018UL) /**< \brief (PORT) Data Output Value Set 0 */ |
| 99 | #define REG_PORT_OUTTGL0 (*(RwReg *)0x4100801CUL) /**< \brief (PORT) Data Output Value Toggle 0 */ |
| 100 | #define REG_PORT_IN0 (*(RoReg *)0x41008020UL) /**< \brief (PORT) Data Input Value 0 */ |
| 101 | #define REG_PORT_CTRL0 (*(RwReg *)0x41008024UL) /**< \brief (PORT) Control 0 */ |
| 102 | #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41008028UL) /**< \brief (PORT) Write Configuration 0 */ |
| 103 | #define REG_PORT_EVCTRL0 (*(RwReg *)0x4100802CUL) /**< \brief (PORT) Event Input Control 0 */ |
| 104 | #define REG_PORT_PMUX0 (*(RwReg8 *)0x41008030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */ |
| 105 | #define REG_PORT_PINCFG0 (*(RwReg8 *)0x41008040UL) /**< \brief (PORT) Pin Configuration 0 */ |
| 106 | #define REG_PORT_DIR1 (*(RwReg *)0x41008080UL) /**< \brief (PORT) Data Direction 1 */ |
| 107 | #define REG_PORT_DIRCLR1 (*(RwReg *)0x41008084UL) /**< \brief (PORT) Data Direction Clear 1 */ |
| 108 | #define REG_PORT_DIRSET1 (*(RwReg *)0x41008088UL) /**< \brief (PORT) Data Direction Set 1 */ |
| 109 | #define REG_PORT_DIRTGL1 (*(RwReg *)0x4100808CUL) /**< \brief (PORT) Data Direction Toggle 1 */ |
| 110 | #define REG_PORT_OUT1 (*(RwReg *)0x41008090UL) /**< \brief (PORT) Data Output Value 1 */ |
| 111 | #define REG_PORT_OUTCLR1 (*(RwReg *)0x41008094UL) /**< \brief (PORT) Data Output Value Clear 1 */ |
| 112 | #define REG_PORT_OUTSET1 (*(RwReg *)0x41008098UL) /**< \brief (PORT) Data Output Value Set 1 */ |
| 113 | #define REG_PORT_OUTTGL1 (*(RwReg *)0x4100809CUL) /**< \brief (PORT) Data Output Value Toggle 1 */ |
| 114 | #define REG_PORT_IN1 (*(RoReg *)0x410080A0UL) /**< \brief (PORT) Data Input Value 1 */ |
| 115 | #define REG_PORT_CTRL1 (*(RwReg *)0x410080A4UL) /**< \brief (PORT) Control 1 */ |
| 116 | #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410080A8UL) /**< \brief (PORT) Write Configuration 1 */ |
| 117 | #define REG_PORT_EVCTRL1 (*(RwReg *)0x410080ACUL) /**< \brief (PORT) Event Input Control 1 */ |
| 118 | #define REG_PORT_PMUX1 (*(RwReg8 *)0x410080B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */ |
| 119 | #define REG_PORT_PINCFG1 (*(RwReg8 *)0x410080C0UL) /**< \brief (PORT) Pin Configuration 1 */ |
| 120 | #define REG_PORT_DIR2 (*(RwReg *)0x41008100UL) /**< \brief (PORT) Data Direction 2 */ |
| 121 | #define REG_PORT_DIRCLR2 (*(RwReg *)0x41008104UL) /**< \brief (PORT) Data Direction Clear 2 */ |
| 122 | #define REG_PORT_DIRSET2 (*(RwReg *)0x41008108UL) /**< \brief (PORT) Data Direction Set 2 */ |
| 123 | #define REG_PORT_DIRTGL2 (*(RwReg *)0x4100810CUL) /**< \brief (PORT) Data Direction Toggle 2 */ |
| 124 | #define REG_PORT_OUT2 (*(RwReg *)0x41008110UL) /**< \brief (PORT) Data Output Value 2 */ |
| 125 | #define REG_PORT_OUTCLR2 (*(RwReg *)0x41008114UL) /**< \brief (PORT) Data Output Value Clear 2 */ |
| 126 | #define REG_PORT_OUTSET2 (*(RwReg *)0x41008118UL) /**< \brief (PORT) Data Output Value Set 2 */ |
| 127 | #define REG_PORT_OUTTGL2 (*(RwReg *)0x4100811CUL) /**< \brief (PORT) Data Output Value Toggle 2 */ |
| 128 | #define REG_PORT_IN2 (*(RoReg *)0x41008120UL) /**< \brief (PORT) Data Input Value 2 */ |
| 129 | #define REG_PORT_CTRL2 (*(RwReg *)0x41008124UL) /**< \brief (PORT) Control 2 */ |
| 130 | #define REG_PORT_WRCONFIG2 (*(WoReg *)0x41008128UL) /**< \brief (PORT) Write Configuration 2 */ |
| 131 | #define REG_PORT_EVCTRL2 (*(RwReg *)0x4100812CUL) /**< \brief (PORT) Event Input Control 2 */ |
| 132 | #define REG_PORT_PMUX2 (*(RwReg8 *)0x41008130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */ |
| 133 | #define REG_PORT_PINCFG2 (*(RwReg8 *)0x41008140UL) /**< \brief (PORT) Pin Configuration 2 */ |
| 134 | #define REG_PORT_DIR3 (*(RwReg *)0x41008180UL) /**< \brief (PORT) Data Direction 3 */ |
| 135 | #define REG_PORT_DIRCLR3 (*(RwReg *)0x41008184UL) /**< \brief (PORT) Data Direction Clear 3 */ |
| 136 | #define REG_PORT_DIRSET3 (*(RwReg *)0x41008188UL) /**< \brief (PORT) Data Direction Set 3 */ |
| 137 | #define REG_PORT_DIRTGL3 (*(RwReg *)0x4100818CUL) /**< \brief (PORT) Data Direction Toggle 3 */ |
| 138 | #define REG_PORT_OUT3 (*(RwReg *)0x41008190UL) /**< \brief (PORT) Data Output Value 3 */ |
| 139 | #define REG_PORT_OUTCLR3 (*(RwReg *)0x41008194UL) /**< \brief (PORT) Data Output Value Clear 3 */ |
| 140 | #define REG_PORT_OUTSET3 (*(RwReg *)0x41008198UL) /**< \brief (PORT) Data Output Value Set 3 */ |
| 141 | #define REG_PORT_OUTTGL3 (*(RwReg *)0x4100819CUL) /**< \brief (PORT) Data Output Value Toggle 3 */ |
| 142 | #define REG_PORT_IN3 (*(RoReg *)0x410081A0UL) /**< \brief (PORT) Data Input Value 3 */ |
| 143 | #define REG_PORT_CTRL3 (*(RwReg *)0x410081A4UL) /**< \brief (PORT) Control 3 */ |
| 144 | #define REG_PORT_WRCONFIG3 (*(WoReg *)0x410081A8UL) /**< \brief (PORT) Write Configuration 3 */ |
| 145 | #define REG_PORT_EVCTRL3 (*(RwReg *)0x410081ACUL) /**< \brief (PORT) Event Input Control 3 */ |
| 146 | #define REG_PORT_PMUX3 (*(RwReg8 *)0x410081B0UL) /**< \brief (PORT) Peripheral Multiplexing 3 */ |
| 147 | #define REG_PORT_PINCFG3 (*(RwReg8 *)0x410081C0UL) /**< \brief (PORT) Pin Configuration 3 */ |
| 148 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 149 | |
| 150 | /* ========== Instance parameters for PORT peripheral ========== */ |
| 151 | #define PORT_BITS 118 |
| 152 | #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 153 | #define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 154 | #define PORT_DRVSTR 1 // DRVSTR supported |
| 155 | #define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 156 | #define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 157 | #define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 158 | #define PORT_EV_NUM 4 |
| 159 | #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 160 | #define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 161 | #define PORT_ODRAIN 0 // ODRAIN supported |
| 162 | #define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 163 | #define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 164 | #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 165 | #define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 166 | #define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 167 | #define PORT_PMUXBIT0_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 } |
| 168 | #define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 } |
| 169 | #define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 } |
| 170 | #define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 } |
| 171 | #define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 } |
| 172 | #define PORT_PMUXBIT2_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 } |
| 173 | #define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 174 | #define PORT_PMUXBIT3_IMPLEMENTED { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 } |
| 175 | #define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 } |
| 176 | #define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 177 | #define PORT_PPP_IMPLEMENTED { 0x00000001 } // IOBUS2 implemented? |
| 178 | #define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 179 | #define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 } |
| 180 | #define PORT_SLEWLIM 0 // SLEWLIM supported |
| 181 | #define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 182 | #define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } |
| 183 | |
| 184 | #endif /* _SAME54_PORT_INSTANCE_ */ |