Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /**************************************************************************//** |
| 2 | * @file core_cm0.h |
| 3 | * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
| 4 | * @version V5.0.1 |
| 5 | * @date 25. November 2016 |
| 6 | ******************************************************************************/ |
| 7 | /* |
| 8 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. |
| 9 | * |
| 10 | * SPDX-License-Identifier: Apache-2.0 |
| 11 | * |
| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 13 | * not use this file except in compliance with the License. |
| 14 | * You may obtain a copy of the License at |
| 15 | * |
| 16 | * www.apache.org/licenses/LICENSE-2.0 |
| 17 | * |
| 18 | * Unless required by applicable law or agreed to in writing, software |
| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 21 | * See the License for the specific language governing permissions and |
| 22 | * limitations under the License. |
| 23 | */ |
| 24 | |
| 25 | #if defined ( __ICCARM__ ) |
| 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
| 27 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| 28 | #pragma clang system_header /* treat file as system include file */ |
| 29 | #endif |
| 30 | |
| 31 | #ifndef __CORE_CM0_H_GENERIC |
| 32 | #define __CORE_CM0_H_GENERIC |
| 33 | |
| 34 | #include <stdint.h> |
| 35 | |
| 36 | #ifdef __cplusplus |
| 37 | extern "C" { |
| 38 | #endif |
| 39 | |
| 40 | /** |
| 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| 42 | CMSIS violates the following MISRA-C:2004 rules: |
| 43 | |
| 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
| 45 | Function definitions in header files are used to allow 'inlining'. |
| 46 | |
| 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| 48 | Unions are used for effective representation of core registers. |
| 49 | |
| 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
| 51 | Function-like macros are used to allow more efficient code. |
| 52 | */ |
| 53 | |
| 54 | |
| 55 | /******************************************************************************* |
| 56 | * CMSIS definitions |
| 57 | ******************************************************************************/ |
| 58 | /** |
| 59 | \ingroup Cortex_M0 |
| 60 | @{ |
| 61 | */ |
| 62 | |
| 63 | /* CMSIS CM0 definitions */ |
| 64 | #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ |
| 65 | #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ |
| 66 | #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ |
| 67 | __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
| 68 | |
| 69 | #define __CORTEX_M (0U) /*!< Cortex-M Core */ |
| 70 | |
| 71 | /** __FPU_USED indicates whether an FPU is used or not. |
| 72 | This core does not support an FPU at all |
| 73 | */ |
| 74 | #define __FPU_USED 0U |
| 75 | |
| 76 | #if defined ( __CC_ARM ) |
| 77 | #if defined __TARGET_FPU_VFP |
| 78 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 79 | #endif |
| 80 | |
| 81 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| 82 | #if defined __ARM_PCS_VFP |
| 83 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 84 | #endif |
| 85 | |
| 86 | #elif defined ( __GNUC__ ) |
| 87 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| 88 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 89 | #endif |
| 90 | |
| 91 | #elif defined ( __ICCARM__ ) |
| 92 | #if defined __ARMVFP__ |
| 93 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 94 | #endif |
| 95 | |
| 96 | #elif defined ( __TI_ARM__ ) |
| 97 | #if defined __TI_VFP_SUPPORT__ |
| 98 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 99 | #endif |
| 100 | |
| 101 | #elif defined ( __TASKING__ ) |
| 102 | #if defined __FPU_VFP__ |
| 103 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 104 | #endif |
| 105 | |
| 106 | #elif defined ( __CSMC__ ) |
| 107 | #if ( __CSMC__ & 0x400U) |
| 108 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 109 | #endif |
| 110 | |
| 111 | #endif |
| 112 | |
| 113 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
| 114 | |
| 115 | |
| 116 | #ifdef __cplusplus |
| 117 | } |
| 118 | #endif |
| 119 | |
| 120 | #endif /* __CORE_CM0_H_GENERIC */ |
| 121 | |
| 122 | #ifndef __CMSIS_GENERIC |
| 123 | |
| 124 | #ifndef __CORE_CM0_H_DEPENDANT |
| 125 | #define __CORE_CM0_H_DEPENDANT |
| 126 | |
| 127 | #ifdef __cplusplus |
| 128 | extern "C" { |
| 129 | #endif |
| 130 | |
| 131 | /* check device defines and use defaults */ |
| 132 | #if defined __CHECK_DEVICE_DEFINES |
| 133 | #ifndef __CM0_REV |
| 134 | #define __CM0_REV 0x0000U |
| 135 | #warning "__CM0_REV not defined in device header file; using default!" |
| 136 | #endif |
| 137 | |
| 138 | #ifndef __NVIC_PRIO_BITS |
| 139 | #define __NVIC_PRIO_BITS 2U |
| 140 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| 141 | #endif |
| 142 | |
| 143 | #ifndef __Vendor_SysTickConfig |
| 144 | #define __Vendor_SysTickConfig 0U |
| 145 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| 146 | #endif |
| 147 | #endif |
| 148 | |
| 149 | /* IO definitions (access restrictions to peripheral registers) */ |
| 150 | /** |
| 151 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| 152 | |
| 153 | <strong>IO Type Qualifiers</strong> are used |
| 154 | \li to specify the access to peripheral variables. |
| 155 | \li for automatic generation of peripheral register debug information. |
| 156 | */ |
| 157 | #ifdef __cplusplus |
| 158 | #define __I volatile /*!< Defines 'read only' permissions */ |
| 159 | #else |
| 160 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| 161 | #endif |
| 162 | #define __O volatile /*!< Defines 'write only' permissions */ |
| 163 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| 164 | |
| 165 | /* following defines should be used for structure members */ |
| 166 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
| 167 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
| 168 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
| 169 | |
| 170 | /*@} end of group Cortex_M0 */ |
| 171 | |
| 172 | |
| 173 | |
| 174 | /******************************************************************************* |
| 175 | * Register Abstraction |
| 176 | Core Register contain: |
| 177 | - Core Register |
| 178 | - Core NVIC Register |
| 179 | - Core SCB Register |
| 180 | - Core SysTick Register |
| 181 | ******************************************************************************/ |
| 182 | /** |
| 183 | \defgroup CMSIS_core_register Defines and Type Definitions |
| 184 | \brief Type definitions and defines for Cortex-M processor based devices. |
| 185 | */ |
| 186 | |
| 187 | /** |
| 188 | \ingroup CMSIS_core_register |
| 189 | \defgroup CMSIS_CORE Status and Control Registers |
| 190 | \brief Core Register type definitions. |
| 191 | @{ |
| 192 | */ |
| 193 | |
| 194 | /** |
| 195 | \brief Union type to access the Application Program Status Register (APSR). |
| 196 | */ |
| 197 | typedef union |
| 198 | { |
| 199 | struct |
| 200 | { |
| 201 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
| 202 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| 203 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| 204 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| 205 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| 206 | } b; /*!< Structure used for bit access */ |
| 207 | uint32_t w; /*!< Type used for word access */ |
| 208 | } APSR_Type; |
| 209 | |
| 210 | /* APSR Register Definitions */ |
| 211 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
| 212 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
| 213 | |
| 214 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
| 215 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
| 216 | |
| 217 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
| 218 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
| 219 | |
| 220 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
| 221 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
| 222 | |
| 223 | |
| 224 | /** |
| 225 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
| 226 | */ |
| 227 | typedef union |
| 228 | { |
| 229 | struct |
| 230 | { |
| 231 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| 232 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| 233 | } b; /*!< Structure used for bit access */ |
| 234 | uint32_t w; /*!< Type used for word access */ |
| 235 | } IPSR_Type; |
| 236 | |
| 237 | /* IPSR Register Definitions */ |
| 238 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
| 239 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
| 240 | |
| 241 | |
| 242 | /** |
| 243 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| 244 | */ |
| 245 | typedef union |
| 246 | { |
| 247 | struct |
| 248 | { |
| 249 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| 250 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
| 251 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| 252 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
| 253 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| 254 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| 255 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| 256 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| 257 | } b; /*!< Structure used for bit access */ |
| 258 | uint32_t w; /*!< Type used for word access */ |
| 259 | } xPSR_Type; |
| 260 | |
| 261 | /* xPSR Register Definitions */ |
| 262 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
| 263 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
| 264 | |
| 265 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
| 266 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
| 267 | |
| 268 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
| 269 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
| 270 | |
| 271 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
| 272 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
| 273 | |
| 274 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
| 275 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
| 276 | |
| 277 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
| 278 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
| 279 | |
| 280 | |
| 281 | /** |
| 282 | \brief Union type to access the Control Registers (CONTROL). |
| 283 | */ |
| 284 | typedef union |
| 285 | { |
| 286 | struct |
| 287 | { |
| 288 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
| 289 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| 290 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
| 291 | } b; /*!< Structure used for bit access */ |
| 292 | uint32_t w; /*!< Type used for word access */ |
| 293 | } CONTROL_Type; |
| 294 | |
| 295 | /* CONTROL Register Definitions */ |
| 296 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
| 297 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
| 298 | |
| 299 | /*@} end of group CMSIS_CORE */ |
| 300 | |
| 301 | |
| 302 | /** |
| 303 | \ingroup CMSIS_core_register |
| 304 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| 305 | \brief Type definitions for the NVIC Registers |
| 306 | @{ |
| 307 | */ |
| 308 | |
| 309 | /** |
| 310 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| 311 | */ |
| 312 | typedef struct |
| 313 | { |
| 314 | __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| 315 | uint32_t RESERVED0[31U]; |
| 316 | __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| 317 | uint32_t RSERVED1[31U]; |
| 318 | __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| 319 | uint32_t RESERVED2[31U]; |
| 320 | __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| 321 | uint32_t RESERVED3[31U]; |
| 322 | uint32_t RESERVED4[64U]; |
| 323 | __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
| 324 | } NVIC_Type; |
| 325 | |
| 326 | /*@} end of group CMSIS_NVIC */ |
| 327 | |
| 328 | |
| 329 | /** |
| 330 | \ingroup CMSIS_core_register |
| 331 | \defgroup CMSIS_SCB System Control Block (SCB) |
| 332 | \brief Type definitions for the System Control Block Registers |
| 333 | @{ |
| 334 | */ |
| 335 | |
| 336 | /** |
| 337 | \brief Structure type to access the System Control Block (SCB). |
| 338 | */ |
| 339 | typedef struct |
| 340 | { |
| 341 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| 342 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| 343 | uint32_t RESERVED0; |
| 344 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| 345 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| 346 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| 347 | uint32_t RESERVED1; |
| 348 | __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
| 349 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| 350 | } SCB_Type; |
| 351 | |
| 352 | /* SCB CPUID Register Definitions */ |
| 353 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
| 354 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| 355 | |
| 356 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
| 357 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| 358 | |
| 359 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
| 360 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| 361 | |
| 362 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
| 363 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| 364 | |
| 365 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
| 366 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
| 367 | |
| 368 | /* SCB Interrupt Control State Register Definitions */ |
| 369 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
| 370 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| 371 | |
| 372 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
| 373 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| 374 | |
| 375 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
| 376 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| 377 | |
| 378 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
| 379 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| 380 | |
| 381 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
| 382 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| 383 | |
| 384 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
| 385 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| 386 | |
| 387 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
| 388 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| 389 | |
| 390 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
| 391 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| 392 | |
| 393 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
| 394 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
| 395 | |
| 396 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
| 397 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
| 398 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| 399 | |
| 400 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| 401 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| 402 | |
| 403 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
| 404 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| 405 | |
| 406 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
| 407 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| 408 | |
| 409 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| 410 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| 411 | |
| 412 | /* SCB System Control Register Definitions */ |
| 413 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
| 414 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| 415 | |
| 416 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
| 417 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| 418 | |
| 419 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
| 420 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| 421 | |
| 422 | /* SCB Configuration Control Register Definitions */ |
| 423 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
| 424 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| 425 | |
| 426 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
| 427 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| 428 | |
| 429 | /* SCB System Handler Control and State Register Definitions */ |
| 430 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
| 431 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| 432 | |
| 433 | /*@} end of group CMSIS_SCB */ |
| 434 | |
| 435 | |
| 436 | /** |
| 437 | \ingroup CMSIS_core_register |
| 438 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| 439 | \brief Type definitions for the System Timer Registers. |
| 440 | @{ |
| 441 | */ |
| 442 | |
| 443 | /** |
| 444 | \brief Structure type to access the System Timer (SysTick). |
| 445 | */ |
| 446 | typedef struct |
| 447 | { |
| 448 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| 449 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| 450 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| 451 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| 452 | } SysTick_Type; |
| 453 | |
| 454 | /* SysTick Control / Status Register Definitions */ |
| 455 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
| 456 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| 457 | |
| 458 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
| 459 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| 460 | |
| 461 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
| 462 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| 463 | |
| 464 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
| 465 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
| 466 | |
| 467 | /* SysTick Reload Register Definitions */ |
| 468 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
| 469 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
| 470 | |
| 471 | /* SysTick Current Register Definitions */ |
| 472 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
| 473 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
| 474 | |
| 475 | /* SysTick Calibration Register Definitions */ |
| 476 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
| 477 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| 478 | |
| 479 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
| 480 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| 481 | |
| 482 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
| 483 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
| 484 | |
| 485 | /*@} end of group CMSIS_SysTick */ |
| 486 | |
| 487 | |
| 488 | /** |
| 489 | \ingroup CMSIS_core_register |
| 490 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| 491 | \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
| 492 | Therefore they are not covered by the Cortex-M0 header file. |
| 493 | @{ |
| 494 | */ |
| 495 | /*@} end of group CMSIS_CoreDebug */ |
| 496 | |
| 497 | |
| 498 | /** |
| 499 | \ingroup CMSIS_core_register |
| 500 | \defgroup CMSIS_core_bitfield Core register bit field macros |
| 501 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
| 502 | @{ |
| 503 | */ |
| 504 | |
| 505 | /** |
| 506 | \brief Mask and shift a bit field value for use in a register bit range. |
| 507 | \param[in] field Name of the register bit field. |
| 508 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
| 509 | \return Masked and shifted value. |
| 510 | */ |
| 511 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
| 512 | |
| 513 | /** |
| 514 | \brief Mask and shift a register value to extract a bit filed value. |
| 515 | \param[in] field Name of the register bit field. |
| 516 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
| 517 | \return Masked and shifted bit field value. |
| 518 | */ |
| 519 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
| 520 | |
| 521 | /*@} end of group CMSIS_core_bitfield */ |
| 522 | |
| 523 | |
| 524 | /** |
| 525 | \ingroup CMSIS_core_register |
| 526 | \defgroup CMSIS_core_base Core Definitions |
| 527 | \brief Definitions for base addresses, unions, and structures. |
| 528 | @{ |
| 529 | */ |
| 530 | |
| 531 | /* Memory mapping of Core Hardware */ |
| 532 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| 533 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| 534 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| 535 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| 536 | |
| 537 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| 538 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| 539 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| 540 | |
| 541 | |
| 542 | /*@} */ |
| 543 | |
| 544 | |
| 545 | |
| 546 | /******************************************************************************* |
| 547 | * Hardware Abstraction Layer |
| 548 | Core Function Interface contains: |
| 549 | - Core NVIC Functions |
| 550 | - Core SysTick Functions |
| 551 | - Core Register Access Functions |
| 552 | ******************************************************************************/ |
| 553 | /** |
| 554 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| 555 | */ |
| 556 | |
| 557 | |
| 558 | |
| 559 | /* ########################## NVIC functions #################################### */ |
| 560 | /** |
| 561 | \ingroup CMSIS_Core_FunctionInterface |
| 562 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| 563 | \brief Functions that manage interrupts and exceptions via the NVIC. |
| 564 | @{ |
| 565 | */ |
| 566 | |
| 567 | #ifndef CMSIS_NVIC_VIRTUAL |
| 568 | /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ |
| 569 | /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ |
| 570 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
| 571 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
| 572 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
| 573 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
| 574 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
| 575 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
| 576 | /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ |
| 577 | #define NVIC_SetPriority __NVIC_SetPriority |
| 578 | #define NVIC_GetPriority __NVIC_GetPriority |
| 579 | #endif /* CMSIS_NVIC_VIRTUAL */ |
| 580 | |
| 581 | #ifndef CMSIS_VECTAB_VIRTUAL |
| 582 | #define NVIC_SetVector __NVIC_SetVector |
| 583 | #define NVIC_GetVector __NVIC_GetVector |
| 584 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
| 585 | |
| 586 | #define NVIC_USER_IRQ_OFFSET 16 |
| 587 | |
| 588 | |
| 589 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
| 590 | /* The following MACROS handle generation of the register offset and byte masks */ |
| 591 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
| 592 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
| 593 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
| 594 | |
| 595 | |
| 596 | /** |
| 597 | \brief Enable Interrupt |
| 598 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
| 599 | \param [in] IRQn Device specific interrupt number. |
| 600 | \note IRQn must not be negative. |
| 601 | */ |
| 602 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
| 603 | { |
| 604 | if ((int32_t)(IRQn) >= 0) |
| 605 | { |
| 606 | NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | |
| 611 | /** |
| 612 | \brief Get Interrupt Enable status |
| 613 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
| 614 | \param [in] IRQn Device specific interrupt number. |
| 615 | \return 0 Interrupt is not enabled. |
| 616 | \return 1 Interrupt is enabled. |
| 617 | \note IRQn must not be negative. |
| 618 | */ |
| 619 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
| 620 | { |
| 621 | if ((int32_t)(IRQn) >= 0) |
| 622 | { |
| 623 | return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| 624 | } |
| 625 | else |
| 626 | { |
| 627 | return(0U); |
| 628 | } |
| 629 | } |
| 630 | |
| 631 | |
| 632 | /** |
| 633 | \brief Disable Interrupt |
| 634 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
| 635 | \param [in] IRQn Device specific interrupt number. |
| 636 | \note IRQn must not be negative. |
| 637 | */ |
| 638 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
| 639 | { |
| 640 | if ((int32_t)(IRQn) >= 0) |
| 641 | { |
| 642 | NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 643 | __DSB(); |
| 644 | __ISB(); |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | |
| 649 | /** |
| 650 | \brief Get Pending Interrupt |
| 651 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
| 652 | \param [in] IRQn Device specific interrupt number. |
| 653 | \return 0 Interrupt status is not pending. |
| 654 | \return 1 Interrupt status is pending. |
| 655 | \note IRQn must not be negative. |
| 656 | */ |
| 657 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| 658 | { |
| 659 | if ((int32_t)(IRQn) >= 0) |
| 660 | { |
| 661 | return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| 662 | } |
| 663 | else |
| 664 | { |
| 665 | return(0U); |
| 666 | } |
| 667 | } |
| 668 | |
| 669 | |
| 670 | /** |
| 671 | \brief Set Pending Interrupt |
| 672 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
| 673 | \param [in] IRQn Device specific interrupt number. |
| 674 | \note IRQn must not be negative. |
| 675 | */ |
| 676 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| 677 | { |
| 678 | if ((int32_t)(IRQn) >= 0) |
| 679 | { |
| 680 | NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 681 | } |
| 682 | } |
| 683 | |
| 684 | |
| 685 | /** |
| 686 | \brief Clear Pending Interrupt |
| 687 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
| 688 | \param [in] IRQn Device specific interrupt number. |
| 689 | \note IRQn must not be negative. |
| 690 | */ |
| 691 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| 692 | { |
| 693 | if ((int32_t)(IRQn) >= 0) |
| 694 | { |
| 695 | NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 696 | } |
| 697 | } |
| 698 | |
| 699 | |
| 700 | /** |
| 701 | \brief Set Interrupt Priority |
| 702 | \details Sets the priority of a device specific interrupt or a processor exception. |
| 703 | The interrupt number can be positive to specify a device specific interrupt, |
| 704 | or negative to specify a processor exception. |
| 705 | \param [in] IRQn Interrupt number. |
| 706 | \param [in] priority Priority to set. |
| 707 | \note The priority cannot be set for every processor exception. |
| 708 | */ |
| 709 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| 710 | { |
| 711 | if ((int32_t)(IRQn) >= 0) |
| 712 | { |
| 713 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
| 714 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
| 715 | } |
| 716 | else |
| 717 | { |
| 718 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
| 719 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | |
| 724 | /** |
| 725 | \brief Get Interrupt Priority |
| 726 | \details Reads the priority of a device specific interrupt or a processor exception. |
| 727 | The interrupt number can be positive to specify a device specific interrupt, |
| 728 | or negative to specify a processor exception. |
| 729 | \param [in] IRQn Interrupt number. |
| 730 | \return Interrupt Priority. |
| 731 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
| 732 | */ |
| 733 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
| 734 | { |
| 735 | |
| 736 | if ((int32_t)(IRQn) >= 0) |
| 737 | { |
| 738 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
| 739 | } |
| 740 | else |
| 741 | { |
| 742 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | |
| 747 | /** |
| 748 | \brief Set Interrupt Vector |
| 749 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
| 750 | The interrupt number can be positive to specify a device specific interrupt, |
| 751 | or negative to specify a processor exception. |
| 752 | Address 0 must be mapped to SRAM. |
| 753 | \param [in] IRQn Interrupt number |
| 754 | \param [in] vector Address of interrupt handler function |
| 755 | */ |
| 756 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
| 757 | { |
| 758 | uint32_t *vectors = (uint32_t *)0x0U; |
| 759 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
| 760 | } |
| 761 | |
| 762 | |
| 763 | /** |
| 764 | \brief Get Interrupt Vector |
| 765 | \details Reads an interrupt vector from interrupt vector table. |
| 766 | The interrupt number can be positive to specify a device specific interrupt, |
| 767 | or negative to specify a processor exception. |
| 768 | \param [in] IRQn Interrupt number. |
| 769 | \return Address of interrupt handler function |
| 770 | */ |
| 771 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
| 772 | { |
| 773 | uint32_t *vectors = (uint32_t *)0x0U; |
| 774 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
| 775 | } |
| 776 | |
| 777 | |
| 778 | /** |
| 779 | \brief System Reset |
| 780 | \details Initiates a system reset request to reset the MCU. |
| 781 | */ |
| 782 | __STATIC_INLINE void NVIC_SystemReset(void) |
| 783 | { |
| 784 | __DSB(); /* Ensure all outstanding memory accesses included |
| 785 | buffered write are completed before reset */ |
| 786 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| 787 | SCB_AIRCR_SYSRESETREQ_Msk); |
| 788 | __DSB(); /* Ensure completion of memory access */ |
| 789 | |
| 790 | for(;;) /* wait until reset */ |
| 791 | { |
| 792 | __NOP(); |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | /*@} end of CMSIS_Core_NVICFunctions */ |
| 797 | |
| 798 | |
| 799 | /* ########################## FPU functions #################################### */ |
| 800 | /** |
| 801 | \ingroup CMSIS_Core_FunctionInterface |
| 802 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
| 803 | \brief Function that provides FPU type. |
| 804 | @{ |
| 805 | */ |
| 806 | |
| 807 | /** |
| 808 | \brief get FPU type |
| 809 | \details returns the FPU type |
| 810 | \returns |
| 811 | - \b 0: No FPU |
| 812 | - \b 1: Single precision FPU |
| 813 | - \b 2: Double + Single precision FPU |
| 814 | */ |
| 815 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
| 816 | { |
| 817 | return 0U; /* No FPU */ |
| 818 | } |
| 819 | |
| 820 | |
| 821 | /*@} end of CMSIS_Core_FpuFunctions */ |
| 822 | |
| 823 | |
| 824 | |
| 825 | /* ################################## SysTick function ############################################ */ |
| 826 | /** |
| 827 | \ingroup CMSIS_Core_FunctionInterface |
| 828 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| 829 | \brief Functions that configure the System. |
| 830 | @{ |
| 831 | */ |
| 832 | |
| 833 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
| 834 | |
| 835 | /** |
| 836 | \brief System Tick Configuration |
| 837 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| 838 | Counter is in free running mode to generate periodic interrupts. |
| 839 | \param [in] ticks Number of ticks between two interrupts. |
| 840 | \return 0 Function succeeded. |
| 841 | \return 1 Function failed. |
| 842 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| 843 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| 844 | must contain a vendor-specific implementation of this function. |
| 845 | */ |
| 846 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| 847 | { |
| 848 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
| 849 | { |
| 850 | return (1UL); /* Reload value impossible */ |
| 851 | } |
| 852 | |
| 853 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
| 854 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
| 855 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
| 856 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| 857 | SysTick_CTRL_TICKINT_Msk | |
| 858 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| 859 | return (0UL); /* Function successful */ |
| 860 | } |
| 861 | |
| 862 | #endif |
| 863 | |
| 864 | /*@} end of CMSIS_Core_SysTickFunctions */ |
| 865 | |
| 866 | |
| 867 | |
| 868 | |
| 869 | #ifdef __cplusplus |
| 870 | } |
| 871 | #endif |
| 872 | |
| 873 | #endif /* __CORE_CM0_H_DEPENDANT */ |
| 874 | |
| 875 | #endif /* __CMSIS_GENERIC */ |