Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /**************************************************************************//** |
| 2 | * @file cmsis_armclang.h |
| 3 | * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file |
| 4 | * @version V5.0.1 |
| 5 | * @date 02. February 2017 |
| 6 | ******************************************************************************/ |
| 7 | /* |
| 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
| 9 | * |
| 10 | * SPDX-License-Identifier: Apache-2.0 |
| 11 | * |
| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 13 | * not use this file except in compliance with the License. |
| 14 | * You may obtain a copy of the License at |
| 15 | * |
| 16 | * www.apache.org/licenses/LICENSE-2.0 |
| 17 | * |
| 18 | * Unless required by applicable law or agreed to in writing, software |
| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 21 | * See the License for the specific language governing permissions and |
| 22 | * limitations under the License. |
| 23 | */ |
| 24 | |
| 25 | #ifndef __CMSIS_ARMCLANG_H |
| 26 | #define __CMSIS_ARMCLANG_H |
| 27 | |
| 28 | #ifndef __ARM_COMPAT_H |
| 29 | #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */ |
| 30 | #endif |
| 31 | |
| 32 | /* CMSIS compiler specific defines */ |
| 33 | #ifndef __ASM |
| 34 | #define __ASM __asm |
| 35 | #endif |
| 36 | #ifndef __INLINE |
| 37 | #define __INLINE __inline |
| 38 | #endif |
| 39 | #ifndef __STATIC_INLINE |
| 40 | #define __STATIC_INLINE static __inline |
| 41 | #endif |
| 42 | #ifndef __NO_RETURN |
| 43 | #define __NO_RETURN __attribute__((noreturn)) |
| 44 | #endif |
| 45 | #ifndef __USED |
| 46 | #define __USED __attribute__((used)) |
| 47 | #endif |
| 48 | #ifndef __WEAK |
| 49 | #define __WEAK __attribute__((weak)) |
| 50 | #endif |
| 51 | #ifndef __UNALIGNED_UINT32 |
| 52 | #pragma clang diagnostic push |
| 53 | #pragma clang diagnostic ignored "-Wpacked" |
| 54 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; |
| 55 | #pragma clang diagnostic pop |
| 56 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
| 57 | #endif |
| 58 | #ifndef __ALIGNED |
| 59 | #define __ALIGNED(x) __attribute__((aligned(x))) |
| 60 | #endif |
| 61 | #ifndef __PACKED |
| 62 | #define __PACKED __attribute__((packed, aligned(1))) |
| 63 | #endif |
| 64 | #ifndef __PACKED_STRUCT |
| 65 | #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) |
| 66 | #endif |
| 67 | |
| 68 | |
| 69 | /* ########################### Core Function Access ########################### */ |
| 70 | /** \ingroup CMSIS_Core_FunctionInterface |
| 71 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
| 72 | @{ |
| 73 | */ |
| 74 | |
| 75 | /** |
| 76 | \brief Enable IRQ Interrupts |
| 77 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR. |
| 78 | Can only be executed in Privileged modes. |
| 79 | */ |
| 80 | /* intrinsic void __enable_irq(); see arm_compat.h */ |
| 81 | |
| 82 | |
| 83 | /** |
| 84 | \brief Disable IRQ Interrupts |
| 85 | \details Disables IRQ interrupts by setting the I-bit in the CPSR. |
| 86 | Can only be executed in Privileged modes. |
| 87 | */ |
| 88 | /* intrinsic void __disable_irq(); see arm_compat.h */ |
| 89 | |
| 90 | |
| 91 | /** |
| 92 | \brief Get Control Register |
| 93 | \details Returns the content of the Control Register. |
| 94 | \return Control Register value |
| 95 | */ |
| 96 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) |
| 97 | { |
| 98 | uint32_t result; |
| 99 | |
| 100 | __ASM volatile ("MRS %0, control" : "=r" (result) ); |
| 101 | return(result); |
| 102 | } |
| 103 | |
| 104 | |
| 105 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 106 | /** |
| 107 | \brief Get Control Register (non-secure) |
| 108 | \details Returns the content of the non-secure Control Register when in secure mode. |
| 109 | \return non-secure Control Register value |
| 110 | */ |
| 111 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) |
| 112 | { |
| 113 | uint32_t result; |
| 114 | |
| 115 | __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); |
| 116 | return(result); |
| 117 | } |
| 118 | #endif |
| 119 | |
| 120 | |
| 121 | /** |
| 122 | \brief Set Control Register |
| 123 | \details Writes the given value to the Control Register. |
| 124 | \param [in] control Control Register value to set |
| 125 | */ |
| 126 | __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) |
| 127 | { |
| 128 | __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); |
| 129 | } |
| 130 | |
| 131 | |
| 132 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 133 | /** |
| 134 | \brief Set Control Register (non-secure) |
| 135 | \details Writes the given value to the non-secure Control Register when in secure state. |
| 136 | \param [in] control Control Register value to set |
| 137 | */ |
| 138 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) |
| 139 | { |
| 140 | __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); |
| 141 | } |
| 142 | #endif |
| 143 | |
| 144 | |
| 145 | /** |
| 146 | \brief Get IPSR Register |
| 147 | \details Returns the content of the IPSR Register. |
| 148 | \return IPSR Register value |
| 149 | */ |
| 150 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) |
| 151 | { |
| 152 | uint32_t result; |
| 153 | |
| 154 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
| 155 | return(result); |
| 156 | } |
| 157 | |
| 158 | |
| 159 | /** |
| 160 | \brief Get APSR Register |
| 161 | \details Returns the content of the APSR Register. |
| 162 | \return APSR Register value |
| 163 | */ |
| 164 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) |
| 165 | { |
| 166 | uint32_t result; |
| 167 | |
| 168 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
| 169 | return(result); |
| 170 | } |
| 171 | |
| 172 | |
| 173 | /** |
| 174 | \brief Get xPSR Register |
| 175 | \details Returns the content of the xPSR Register. |
| 176 | \return xPSR Register value |
| 177 | */ |
| 178 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) |
| 179 | { |
| 180 | uint32_t result; |
| 181 | |
| 182 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
| 183 | return(result); |
| 184 | } |
| 185 | |
| 186 | |
| 187 | /** |
| 188 | \brief Get Process Stack Pointer |
| 189 | \details Returns the current value of the Process Stack Pointer (PSP). |
| 190 | \return PSP Register value |
| 191 | */ |
| 192 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) |
| 193 | { |
| 194 | register uint32_t result; |
| 195 | |
| 196 | __ASM volatile ("MRS %0, psp" : "=r" (result) ); |
| 197 | return(result); |
| 198 | } |
| 199 | |
| 200 | |
| 201 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 202 | /** |
| 203 | \brief Get Process Stack Pointer (non-secure) |
| 204 | \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. |
| 205 | \return PSP Register value |
| 206 | */ |
| 207 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) |
| 208 | { |
| 209 | register uint32_t result; |
| 210 | |
| 211 | __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); |
| 212 | return(result); |
| 213 | } |
| 214 | #endif |
| 215 | |
| 216 | |
| 217 | /** |
| 218 | \brief Set Process Stack Pointer |
| 219 | \details Assigns the given value to the Process Stack Pointer (PSP). |
| 220 | \param [in] topOfProcStack Process Stack Pointer value to set |
| 221 | */ |
| 222 | __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
| 223 | { |
| 224 | __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); |
| 225 | } |
| 226 | |
| 227 | |
| 228 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 229 | /** |
| 230 | \brief Set Process Stack Pointer (non-secure) |
| 231 | \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. |
| 232 | \param [in] topOfProcStack Process Stack Pointer value to set |
| 233 | */ |
| 234 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) |
| 235 | { |
| 236 | __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); |
| 237 | } |
| 238 | #endif |
| 239 | |
| 240 | |
| 241 | /** |
| 242 | \brief Get Main Stack Pointer |
| 243 | \details Returns the current value of the Main Stack Pointer (MSP). |
| 244 | \return MSP Register value |
| 245 | */ |
| 246 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) |
| 247 | { |
| 248 | register uint32_t result; |
| 249 | |
| 250 | __ASM volatile ("MRS %0, msp" : "=r" (result) ); |
| 251 | return(result); |
| 252 | } |
| 253 | |
| 254 | |
| 255 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 256 | /** |
| 257 | \brief Get Main Stack Pointer (non-secure) |
| 258 | \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. |
| 259 | \return MSP Register value |
| 260 | */ |
| 261 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) |
| 262 | { |
| 263 | register uint32_t result; |
| 264 | |
| 265 | __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); |
| 266 | return(result); |
| 267 | } |
| 268 | #endif |
| 269 | |
| 270 | |
| 271 | /** |
| 272 | \brief Set Main Stack Pointer |
| 273 | \details Assigns the given value to the Main Stack Pointer (MSP). |
| 274 | \param [in] topOfMainStack Main Stack Pointer value to set |
| 275 | */ |
| 276 | __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
| 277 | { |
| 278 | __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); |
| 279 | } |
| 280 | |
| 281 | |
| 282 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 283 | /** |
| 284 | \brief Set Main Stack Pointer (non-secure) |
| 285 | \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. |
| 286 | \param [in] topOfMainStack Main Stack Pointer value to set |
| 287 | */ |
| 288 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) |
| 289 | { |
| 290 | __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); |
| 291 | } |
| 292 | #endif |
| 293 | |
| 294 | |
| 295 | /** |
| 296 | \brief Get Priority Mask |
| 297 | \details Returns the current state of the priority mask bit from the Priority Mask Register. |
| 298 | \return Priority Mask value |
| 299 | */ |
| 300 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) |
| 301 | { |
| 302 | uint32_t result; |
| 303 | |
| 304 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); |
| 305 | return(result); |
| 306 | } |
| 307 | |
| 308 | |
| 309 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 310 | /** |
| 311 | \brief Get Priority Mask (non-secure) |
| 312 | \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. |
| 313 | \return Priority Mask value |
| 314 | */ |
| 315 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) |
| 316 | { |
| 317 | uint32_t result; |
| 318 | |
| 319 | __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); |
| 320 | return(result); |
| 321 | } |
| 322 | #endif |
| 323 | |
| 324 | |
| 325 | /** |
| 326 | \brief Set Priority Mask |
| 327 | \details Assigns the given value to the Priority Mask Register. |
| 328 | \param [in] priMask Priority Mask |
| 329 | */ |
| 330 | __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
| 331 | { |
| 332 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); |
| 333 | } |
| 334 | |
| 335 | |
| 336 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 337 | /** |
| 338 | \brief Set Priority Mask (non-secure) |
| 339 | \details Assigns the given value to the non-secure Priority Mask Register when in secure state. |
| 340 | \param [in] priMask Priority Mask |
| 341 | */ |
| 342 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) |
| 343 | { |
| 344 | __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); |
| 345 | } |
| 346 | #endif |
| 347 | |
| 348 | |
| 349 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 350 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 351 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 352 | /** |
| 353 | \brief Enable FIQ |
| 354 | \details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
| 355 | Can only be executed in Privileged modes. |
| 356 | */ |
| 357 | #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ |
| 358 | |
| 359 | |
| 360 | /** |
| 361 | \brief Disable FIQ |
| 362 | \details Disables FIQ interrupts by setting the F-bit in the CPSR. |
| 363 | Can only be executed in Privileged modes. |
| 364 | */ |
| 365 | #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ |
| 366 | |
| 367 | |
| 368 | /** |
| 369 | \brief Get Base Priority |
| 370 | \details Returns the current value of the Base Priority register. |
| 371 | \return Base Priority register value |
| 372 | */ |
| 373 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) |
| 374 | { |
| 375 | uint32_t result; |
| 376 | |
| 377 | __ASM volatile ("MRS %0, basepri" : "=r" (result) ); |
| 378 | return(result); |
| 379 | } |
| 380 | |
| 381 | |
| 382 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 383 | /** |
| 384 | \brief Get Base Priority (non-secure) |
| 385 | \details Returns the current value of the non-secure Base Priority register when in secure state. |
| 386 | \return Base Priority register value |
| 387 | */ |
| 388 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) |
| 389 | { |
| 390 | uint32_t result; |
| 391 | |
| 392 | __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); |
| 393 | return(result); |
| 394 | } |
| 395 | #endif |
| 396 | |
| 397 | |
| 398 | /** |
| 399 | \brief Set Base Priority |
| 400 | \details Assigns the given value to the Base Priority register. |
| 401 | \param [in] basePri Base Priority value to set |
| 402 | */ |
| 403 | __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
| 404 | { |
| 405 | __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); |
| 406 | } |
| 407 | |
| 408 | |
| 409 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 410 | /** |
| 411 | \brief Set Base Priority (non-secure) |
| 412 | \details Assigns the given value to the non-secure Base Priority register when in secure state. |
| 413 | \param [in] basePri Base Priority value to set |
| 414 | */ |
| 415 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) |
| 416 | { |
| 417 | __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); |
| 418 | } |
| 419 | #endif |
| 420 | |
| 421 | |
| 422 | /** |
| 423 | \brief Set Base Priority with condition |
| 424 | \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
| 425 | or the new value increases the BASEPRI priority level. |
| 426 | \param [in] basePri Base Priority value to set |
| 427 | */ |
| 428 | __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
| 429 | { |
| 430 | __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); |
| 431 | } |
| 432 | |
| 433 | |
| 434 | /** |
| 435 | \brief Get Fault Mask |
| 436 | \details Returns the current value of the Fault Mask register. |
| 437 | \return Fault Mask register value |
| 438 | */ |
| 439 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) |
| 440 | { |
| 441 | uint32_t result; |
| 442 | |
| 443 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
| 444 | return(result); |
| 445 | } |
| 446 | |
| 447 | |
| 448 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 449 | /** |
| 450 | \brief Get Fault Mask (non-secure) |
| 451 | \details Returns the current value of the non-secure Fault Mask register when in secure state. |
| 452 | \return Fault Mask register value |
| 453 | */ |
| 454 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) |
| 455 | { |
| 456 | uint32_t result; |
| 457 | |
| 458 | __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); |
| 459 | return(result); |
| 460 | } |
| 461 | #endif |
| 462 | |
| 463 | |
| 464 | /** |
| 465 | \brief Set Fault Mask |
| 466 | \details Assigns the given value to the Fault Mask register. |
| 467 | \param [in] faultMask Fault Mask value to set |
| 468 | */ |
| 469 | __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
| 470 | { |
| 471 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); |
| 472 | } |
| 473 | |
| 474 | |
| 475 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 476 | /** |
| 477 | \brief Set Fault Mask (non-secure) |
| 478 | \details Assigns the given value to the non-secure Fault Mask register when in secure state. |
| 479 | \param [in] faultMask Fault Mask value to set |
| 480 | */ |
| 481 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) |
| 482 | { |
| 483 | __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); |
| 484 | } |
| 485 | #endif |
| 486 | |
| 487 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 488 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 489 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
| 490 | |
| 491 | |
| 492 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 493 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
| 494 | |
| 495 | /** |
| 496 | \brief Get Process Stack Pointer Limit |
| 497 | \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). |
| 498 | \return PSPLIM Register value |
| 499 | */ |
| 500 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) |
| 501 | { |
| 502 | register uint32_t result; |
| 503 | |
| 504 | __ASM volatile ("MRS %0, psplim" : "=r" (result) ); |
| 505 | return(result); |
| 506 | } |
| 507 | |
| 508 | |
| 509 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 510 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 511 | /** |
| 512 | \brief Get Process Stack Pointer Limit (non-secure) |
| 513 | \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. |
| 514 | \return PSPLIM Register value |
| 515 | */ |
| 516 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) |
| 517 | { |
| 518 | register uint32_t result; |
| 519 | |
| 520 | __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); |
| 521 | return(result); |
| 522 | } |
| 523 | #endif |
| 524 | |
| 525 | |
| 526 | /** |
| 527 | \brief Set Process Stack Pointer Limit |
| 528 | \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). |
| 529 | \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
| 530 | */ |
| 531 | __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) |
| 532 | { |
| 533 | __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); |
| 534 | } |
| 535 | |
| 536 | |
| 537 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 538 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 539 | /** |
| 540 | \brief Set Process Stack Pointer (non-secure) |
| 541 | \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. |
| 542 | \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
| 543 | */ |
| 544 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) |
| 545 | { |
| 546 | __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); |
| 547 | } |
| 548 | #endif |
| 549 | |
| 550 | |
| 551 | /** |
| 552 | \brief Get Main Stack Pointer Limit |
| 553 | \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). |
| 554 | \return MSPLIM Register value |
| 555 | */ |
| 556 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) |
| 557 | { |
| 558 | register uint32_t result; |
| 559 | |
| 560 | __ASM volatile ("MRS %0, msplim" : "=r" (result) ); |
| 561 | |
| 562 | return(result); |
| 563 | } |
| 564 | |
| 565 | |
| 566 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 567 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 568 | /** |
| 569 | \brief Get Main Stack Pointer Limit (non-secure) |
| 570 | \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. |
| 571 | \return MSPLIM Register value |
| 572 | */ |
| 573 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) |
| 574 | { |
| 575 | register uint32_t result; |
| 576 | |
| 577 | __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); |
| 578 | return(result); |
| 579 | } |
| 580 | #endif |
| 581 | |
| 582 | |
| 583 | /** |
| 584 | \brief Set Main Stack Pointer Limit |
| 585 | \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). |
| 586 | \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set |
| 587 | */ |
| 588 | __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) |
| 589 | { |
| 590 | __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); |
| 591 | } |
| 592 | |
| 593 | |
| 594 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 595 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 596 | /** |
| 597 | \brief Set Main Stack Pointer Limit (non-secure) |
| 598 | \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. |
| 599 | \param [in] MainStackPtrLimit Main Stack Pointer value to set |
| 600 | */ |
| 601 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) |
| 602 | { |
| 603 | __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); |
| 604 | } |
| 605 | #endif |
| 606 | |
| 607 | #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 608 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
| 609 | |
| 610 | |
| 611 | #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 612 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 613 | |
| 614 | /** |
| 615 | \brief Get FPSCR |
| 616 | \details Returns the current value of the Floating Point Status/Control register. |
| 617 | \return Floating Point Status/Control register value |
| 618 | */ |
| 619 | /* #define __get_FPSCR __builtin_arm_get_fpscr */ |
| 620 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) |
| 621 | { |
| 622 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
| 623 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
| 624 | uint32_t result; |
| 625 | |
| 626 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
| 627 | return(result); |
| 628 | #else |
| 629 | return(0U); |
| 630 | #endif |
| 631 | } |
| 632 | |
| 633 | |
| 634 | /** |
| 635 | \brief Set FPSCR |
| 636 | \details Assigns the given value to the Floating Point Status/Control register. |
| 637 | \param [in] fpscr Floating Point Status/Control value to set |
| 638 | */ |
| 639 | /* #define __set_FPSCR __builtin_arm_set_fpscr */ |
| 640 | __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
| 641 | { |
| 642 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
| 643 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
| 644 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); |
| 645 | #else |
| 646 | (void)fpscr; |
| 647 | #endif |
| 648 | } |
| 649 | |
| 650 | #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 651 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
| 652 | |
| 653 | |
| 654 | |
| 655 | /*@} end of CMSIS_Core_RegAccFunctions */ |
| 656 | |
| 657 | |
| 658 | /* ########################## Core Instruction Access ######################### */ |
| 659 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
| 660 | Access to dedicated instructions |
| 661 | @{ |
| 662 | */ |
| 663 | |
| 664 | /* Define macros for porting to both thumb1 and thumb2. |
| 665 | * For thumb1, use low register (r0-r7), specified by constraint "l" |
| 666 | * Otherwise, use general registers, specified by constraint "r" */ |
| 667 | #if defined (__thumb__) && !defined (__thumb2__) |
| 668 | #define __CMSIS_GCC_OUT_REG(r) "=l" (r) |
| 669 | #define __CMSIS_GCC_USE_REG(r) "l" (r) |
| 670 | #else |
| 671 | #define __CMSIS_GCC_OUT_REG(r) "=r" (r) |
| 672 | #define __CMSIS_GCC_USE_REG(r) "r" (r) |
| 673 | #endif |
| 674 | |
| 675 | /** |
| 676 | \brief No Operation |
| 677 | \details No Operation does nothing. This instruction can be used for code alignment purposes. |
| 678 | */ |
| 679 | #define __NOP __builtin_arm_nop |
| 680 | |
| 681 | /** |
| 682 | \brief Wait For Interrupt |
| 683 | \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. |
| 684 | */ |
| 685 | #define __WFI __builtin_arm_wfi |
| 686 | |
| 687 | |
| 688 | /** |
| 689 | \brief Wait For Event |
| 690 | \details Wait For Event is a hint instruction that permits the processor to enter |
| 691 | a low-power state until one of a number of events occurs. |
| 692 | */ |
| 693 | #define __WFE __builtin_arm_wfe |
| 694 | |
| 695 | |
| 696 | /** |
| 697 | \brief Send Event |
| 698 | \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
| 699 | */ |
| 700 | #define __SEV __builtin_arm_sev |
| 701 | |
| 702 | |
| 703 | /** |
| 704 | \brief Instruction Synchronization Barrier |
| 705 | \details Instruction Synchronization Barrier flushes the pipeline in the processor, |
| 706 | so that all instructions following the ISB are fetched from cache or memory, |
| 707 | after the instruction has been completed. |
| 708 | */ |
| 709 | #define __ISB() __builtin_arm_isb(0xF); |
| 710 | |
| 711 | /** |
| 712 | \brief Data Synchronization Barrier |
| 713 | \details Acts as a special kind of Data Memory Barrier. |
| 714 | It completes when all explicit memory accesses before this instruction complete. |
| 715 | */ |
| 716 | #define __DSB() __builtin_arm_dsb(0xF); |
| 717 | |
| 718 | |
| 719 | /** |
| 720 | \brief Data Memory Barrier |
| 721 | \details Ensures the apparent order of the explicit memory operations before |
| 722 | and after the instruction, without ensuring their completion. |
| 723 | */ |
| 724 | #define __DMB() __builtin_arm_dmb(0xF); |
| 725 | |
| 726 | |
| 727 | /** |
| 728 | \brief Reverse byte order (32 bit) |
| 729 | \details Reverses the byte order in integer value. |
| 730 | \param [in] value Value to reverse |
| 731 | \return Reversed value |
| 732 | */ |
| 733 | #define __REV __builtin_bswap32 |
| 734 | |
| 735 | |
| 736 | /** |
| 737 | \brief Reverse byte order (16 bit) |
| 738 | \details Reverses the byte order in two unsigned short values. |
| 739 | \param [in] value Value to reverse |
| 740 | \return Reversed value |
| 741 | */ |
| 742 | #define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ |
| 743 | #if 0 |
| 744 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) |
| 745 | { |
| 746 | uint32_t result; |
| 747 | |
| 748 | __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
| 749 | return(result); |
| 750 | } |
| 751 | #endif |
| 752 | |
| 753 | |
| 754 | /** |
| 755 | \brief Reverse byte order in signed short value |
| 756 | \details Reverses the byte order in a signed short value with sign extension to integer. |
| 757 | \param [in] value Value to reverse |
| 758 | \return Reversed value |
| 759 | */ |
| 760 | /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ |
| 761 | __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) |
| 762 | { |
| 763 | int32_t result; |
| 764 | |
| 765 | __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
| 766 | return(result); |
| 767 | } |
| 768 | |
| 769 | |
| 770 | /** |
| 771 | \brief Rotate Right in unsigned value (32 bit) |
| 772 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
| 773 | \param [in] op1 Value to rotate |
| 774 | \param [in] op2 Number of Bits to rotate |
| 775 | \return Rotated value |
| 776 | */ |
| 777 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) |
| 778 | { |
| 779 | return (op1 >> op2) | (op1 << (32U - op2)); |
| 780 | } |
| 781 | |
| 782 | |
| 783 | /** |
| 784 | \brief Breakpoint |
| 785 | \details Causes the processor to enter Debug state. |
| 786 | Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
| 787 | \param [in] value is ignored by the processor. |
| 788 | If required, a debugger can use it to store additional information about the breakpoint. |
| 789 | */ |
| 790 | #define __BKPT(value) __ASM volatile ("bkpt "#value) |
| 791 | |
| 792 | |
| 793 | /** |
| 794 | \brief Reverse bit order of value |
| 795 | \details Reverses the bit order of the given value. |
| 796 | \param [in] value Value to reverse |
| 797 | \return Reversed value |
| 798 | */ |
| 799 | /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ |
| 800 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
| 801 | { |
| 802 | uint32_t result; |
| 803 | |
| 804 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 805 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 806 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 807 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
| 808 | #else |
| 809 | int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ |
| 810 | |
| 811 | result = value; /* r will be reversed bits of v; first get LSB of v */ |
| 812 | for (value >>= 1U; value; value >>= 1U) |
| 813 | { |
| 814 | result <<= 1U; |
| 815 | result |= value & 1U; |
| 816 | s--; |
| 817 | } |
| 818 | result <<= s; /* shift when v's highest bits are zero */ |
| 819 | #endif |
| 820 | return(result); |
| 821 | } |
| 822 | |
| 823 | |
| 824 | /** |
| 825 | \brief Count leading zeros |
| 826 | \details Counts the number of leading zeros of a data value. |
| 827 | \param [in] value Value to count the leading zeros |
| 828 | \return number of leading zeros in value |
| 829 | */ |
| 830 | #define __CLZ __builtin_clz |
| 831 | |
| 832 | |
| 833 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 834 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 835 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 836 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
| 837 | /** |
| 838 | \brief LDR Exclusive (8 bit) |
| 839 | \details Executes a exclusive LDR instruction for 8 bit value. |
| 840 | \param [in] ptr Pointer to data |
| 841 | \return value of type uint8_t at (*ptr) |
| 842 | */ |
| 843 | #define __LDREXB (uint8_t)__builtin_arm_ldrex |
| 844 | |
| 845 | |
| 846 | /** |
| 847 | \brief LDR Exclusive (16 bit) |
| 848 | \details Executes a exclusive LDR instruction for 16 bit values. |
| 849 | \param [in] ptr Pointer to data |
| 850 | \return value of type uint16_t at (*ptr) |
| 851 | */ |
| 852 | #define __LDREXH (uint16_t)__builtin_arm_ldrex |
| 853 | |
| 854 | |
| 855 | /** |
| 856 | \brief LDR Exclusive (32 bit) |
| 857 | \details Executes a exclusive LDR instruction for 32 bit values. |
| 858 | \param [in] ptr Pointer to data |
| 859 | \return value of type uint32_t at (*ptr) |
| 860 | */ |
| 861 | #define __LDREXW (uint32_t)__builtin_arm_ldrex |
| 862 | |
| 863 | |
| 864 | /** |
| 865 | \brief STR Exclusive (8 bit) |
| 866 | \details Executes a exclusive STR instruction for 8 bit values. |
| 867 | \param [in] value Value to store |
| 868 | \param [in] ptr Pointer to location |
| 869 | \return 0 Function succeeded |
| 870 | \return 1 Function failed |
| 871 | */ |
| 872 | #define __STREXB (uint32_t)__builtin_arm_strex |
| 873 | |
| 874 | |
| 875 | /** |
| 876 | \brief STR Exclusive (16 bit) |
| 877 | \details Executes a exclusive STR instruction for 16 bit values. |
| 878 | \param [in] value Value to store |
| 879 | \param [in] ptr Pointer to location |
| 880 | \return 0 Function succeeded |
| 881 | \return 1 Function failed |
| 882 | */ |
| 883 | #define __STREXH (uint32_t)__builtin_arm_strex |
| 884 | |
| 885 | |
| 886 | /** |
| 887 | \brief STR Exclusive (32 bit) |
| 888 | \details Executes a exclusive STR instruction for 32 bit values. |
| 889 | \param [in] value Value to store |
| 890 | \param [in] ptr Pointer to location |
| 891 | \return 0 Function succeeded |
| 892 | \return 1 Function failed |
| 893 | */ |
| 894 | #define __STREXW (uint32_t)__builtin_arm_strex |
| 895 | |
| 896 | |
| 897 | /** |
| 898 | \brief Remove the exclusive lock |
| 899 | \details Removes the exclusive lock which is created by LDREX. |
| 900 | */ |
| 901 | #define __CLREX __builtin_arm_clrex |
| 902 | |
| 903 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 904 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 905 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 906 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
| 907 | |
| 908 | |
| 909 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 910 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 911 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 912 | /** |
| 913 | \brief Signed Saturate |
| 914 | \details Saturates a signed value. |
| 915 | \param [in] value Value to be saturated |
| 916 | \param [in] sat Bit position to saturate to (1..32) |
| 917 | \return Saturated value |
| 918 | */ |
| 919 | #define __SSAT __builtin_arm_ssat |
| 920 | |
| 921 | |
| 922 | /** |
| 923 | \brief Unsigned Saturate |
| 924 | \details Saturates an unsigned value. |
| 925 | \param [in] value Value to be saturated |
| 926 | \param [in] sat Bit position to saturate to (0..31) |
| 927 | \return Saturated value |
| 928 | */ |
| 929 | #define __USAT __builtin_arm_usat |
| 930 | |
| 931 | |
| 932 | /** |
| 933 | \brief Rotate Right with Extend (32 bit) |
| 934 | \details Moves each bit of a bitstring right by one bit. |
| 935 | The carry input is shifted in at the left end of the bitstring. |
| 936 | \param [in] value Value to rotate |
| 937 | \return Rotated value |
| 938 | */ |
| 939 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) |
| 940 | { |
| 941 | uint32_t result; |
| 942 | |
| 943 | __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
| 944 | return(result); |
| 945 | } |
| 946 | |
| 947 | |
| 948 | /** |
| 949 | \brief LDRT Unprivileged (8 bit) |
| 950 | \details Executes a Unprivileged LDRT instruction for 8 bit value. |
| 951 | \param [in] ptr Pointer to data |
| 952 | \return value of type uint8_t at (*ptr) |
| 953 | */ |
| 954 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) |
| 955 | { |
| 956 | uint32_t result; |
| 957 | |
| 958 | __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 959 | return ((uint8_t) result); /* Add explicit type cast here */ |
| 960 | } |
| 961 | |
| 962 | |
| 963 | /** |
| 964 | \brief LDRT Unprivileged (16 bit) |
| 965 | \details Executes a Unprivileged LDRT instruction for 16 bit values. |
| 966 | \param [in] ptr Pointer to data |
| 967 | \return value of type uint16_t at (*ptr) |
| 968 | */ |
| 969 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) |
| 970 | { |
| 971 | uint32_t result; |
| 972 | |
| 973 | __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 974 | return ((uint16_t) result); /* Add explicit type cast here */ |
| 975 | } |
| 976 | |
| 977 | |
| 978 | /** |
| 979 | \brief LDRT Unprivileged (32 bit) |
| 980 | \details Executes a Unprivileged LDRT instruction for 32 bit values. |
| 981 | \param [in] ptr Pointer to data |
| 982 | \return value of type uint32_t at (*ptr) |
| 983 | */ |
| 984 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) |
| 985 | { |
| 986 | uint32_t result; |
| 987 | |
| 988 | __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 989 | return(result); |
| 990 | } |
| 991 | |
| 992 | |
| 993 | /** |
| 994 | \brief STRT Unprivileged (8 bit) |
| 995 | \details Executes a Unprivileged STRT instruction for 8 bit values. |
| 996 | \param [in] value Value to store |
| 997 | \param [in] ptr Pointer to location |
| 998 | */ |
| 999 | __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) |
| 1000 | { |
| 1001 | __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1002 | } |
| 1003 | |
| 1004 | |
| 1005 | /** |
| 1006 | \brief STRT Unprivileged (16 bit) |
| 1007 | \details Executes a Unprivileged STRT instruction for 16 bit values. |
| 1008 | \param [in] value Value to store |
| 1009 | \param [in] ptr Pointer to location |
| 1010 | */ |
| 1011 | __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) |
| 1012 | { |
| 1013 | __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1014 | } |
| 1015 | |
| 1016 | |
| 1017 | /** |
| 1018 | \brief STRT Unprivileged (32 bit) |
| 1019 | \details Executes a Unprivileged STRT instruction for 32 bit values. |
| 1020 | \param [in] value Value to store |
| 1021 | \param [in] ptr Pointer to location |
| 1022 | */ |
| 1023 | __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) |
| 1024 | { |
| 1025 | __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); |
| 1026 | } |
| 1027 | |
| 1028 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 1029 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 1030 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
| 1031 | |
| 1032 | |
| 1033 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 1034 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
| 1035 | /** |
| 1036 | \brief Load-Acquire (8 bit) |
| 1037 | \details Executes a LDAB instruction for 8 bit value. |
| 1038 | \param [in] ptr Pointer to data |
| 1039 | \return value of type uint8_t at (*ptr) |
| 1040 | */ |
| 1041 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) |
| 1042 | { |
| 1043 | uint32_t result; |
| 1044 | |
| 1045 | __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1046 | return ((uint8_t) result); |
| 1047 | } |
| 1048 | |
| 1049 | |
| 1050 | /** |
| 1051 | \brief Load-Acquire (16 bit) |
| 1052 | \details Executes a LDAH instruction for 16 bit values. |
| 1053 | \param [in] ptr Pointer to data |
| 1054 | \return value of type uint16_t at (*ptr) |
| 1055 | */ |
| 1056 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) |
| 1057 | { |
| 1058 | uint32_t result; |
| 1059 | |
| 1060 | __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1061 | return ((uint16_t) result); |
| 1062 | } |
| 1063 | |
| 1064 | |
| 1065 | /** |
| 1066 | \brief Load-Acquire (32 bit) |
| 1067 | \details Executes a LDA instruction for 32 bit values. |
| 1068 | \param [in] ptr Pointer to data |
| 1069 | \return value of type uint32_t at (*ptr) |
| 1070 | */ |
| 1071 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) |
| 1072 | { |
| 1073 | uint32_t result; |
| 1074 | |
| 1075 | __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1076 | return(result); |
| 1077 | } |
| 1078 | |
| 1079 | |
| 1080 | /** |
| 1081 | \brief Store-Release (8 bit) |
| 1082 | \details Executes a STLB instruction for 8 bit values. |
| 1083 | \param [in] value Value to store |
| 1084 | \param [in] ptr Pointer to location |
| 1085 | */ |
| 1086 | __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) |
| 1087 | { |
| 1088 | __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1089 | } |
| 1090 | |
| 1091 | |
| 1092 | /** |
| 1093 | \brief Store-Release (16 bit) |
| 1094 | \details Executes a STLH instruction for 16 bit values. |
| 1095 | \param [in] value Value to store |
| 1096 | \param [in] ptr Pointer to location |
| 1097 | */ |
| 1098 | __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) |
| 1099 | { |
| 1100 | __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1101 | } |
| 1102 | |
| 1103 | |
| 1104 | /** |
| 1105 | \brief Store-Release (32 bit) |
| 1106 | \details Executes a STL instruction for 32 bit values. |
| 1107 | \param [in] value Value to store |
| 1108 | \param [in] ptr Pointer to location |
| 1109 | */ |
| 1110 | __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) |
| 1111 | { |
| 1112 | __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1113 | } |
| 1114 | |
| 1115 | |
| 1116 | /** |
| 1117 | \brief Load-Acquire Exclusive (8 bit) |
| 1118 | \details Executes a LDAB exclusive instruction for 8 bit value. |
| 1119 | \param [in] ptr Pointer to data |
| 1120 | \return value of type uint8_t at (*ptr) |
| 1121 | */ |
| 1122 | #define __LDAEXB (uint8_t)__builtin_arm_ldaex |
| 1123 | |
| 1124 | |
| 1125 | /** |
| 1126 | \brief Load-Acquire Exclusive (16 bit) |
| 1127 | \details Executes a LDAH exclusive instruction for 16 bit values. |
| 1128 | \param [in] ptr Pointer to data |
| 1129 | \return value of type uint16_t at (*ptr) |
| 1130 | */ |
| 1131 | #define __LDAEXH (uint16_t)__builtin_arm_ldaex |
| 1132 | |
| 1133 | |
| 1134 | /** |
| 1135 | \brief Load-Acquire Exclusive (32 bit) |
| 1136 | \details Executes a LDA exclusive instruction for 32 bit values. |
| 1137 | \param [in] ptr Pointer to data |
| 1138 | \return value of type uint32_t at (*ptr) |
| 1139 | */ |
| 1140 | #define __LDAEX (uint32_t)__builtin_arm_ldaex |
| 1141 | |
| 1142 | |
| 1143 | /** |
| 1144 | \brief Store-Release Exclusive (8 bit) |
| 1145 | \details Executes a STLB exclusive instruction for 8 bit values. |
| 1146 | \param [in] value Value to store |
| 1147 | \param [in] ptr Pointer to location |
| 1148 | \return 0 Function succeeded |
| 1149 | \return 1 Function failed |
| 1150 | */ |
| 1151 | #define __STLEXB (uint32_t)__builtin_arm_stlex |
| 1152 | |
| 1153 | |
| 1154 | /** |
| 1155 | \brief Store-Release Exclusive (16 bit) |
| 1156 | \details Executes a STLH exclusive instruction for 16 bit values. |
| 1157 | \param [in] value Value to store |
| 1158 | \param [in] ptr Pointer to location |
| 1159 | \return 0 Function succeeded |
| 1160 | \return 1 Function failed |
| 1161 | */ |
| 1162 | #define __STLEXH (uint32_t)__builtin_arm_stlex |
| 1163 | |
| 1164 | |
| 1165 | /** |
| 1166 | \brief Store-Release Exclusive (32 bit) |
| 1167 | \details Executes a STL exclusive instruction for 32 bit values. |
| 1168 | \param [in] value Value to store |
| 1169 | \param [in] ptr Pointer to location |
| 1170 | \return 0 Function succeeded |
| 1171 | \return 1 Function failed |
| 1172 | */ |
| 1173 | #define __STLEX (uint32_t)__builtin_arm_stlex |
| 1174 | |
| 1175 | #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 1176 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
| 1177 | |
| 1178 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
| 1179 | |
| 1180 | |
| 1181 | /* ################### Compiler specific Intrinsics ########################### */ |
| 1182 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics |
| 1183 | Access to dedicated SIMD instructions |
| 1184 | @{ |
| 1185 | */ |
| 1186 | |
| 1187 | #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) |
| 1188 | |
| 1189 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) |
| 1190 | { |
| 1191 | uint32_t result; |
| 1192 | |
| 1193 | __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1194 | return(result); |
| 1195 | } |
| 1196 | |
| 1197 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) |
| 1198 | { |
| 1199 | uint32_t result; |
| 1200 | |
| 1201 | __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1202 | return(result); |
| 1203 | } |
| 1204 | |
| 1205 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) |
| 1206 | { |
| 1207 | uint32_t result; |
| 1208 | |
| 1209 | __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1210 | return(result); |
| 1211 | } |
| 1212 | |
| 1213 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) |
| 1214 | { |
| 1215 | uint32_t result; |
| 1216 | |
| 1217 | __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1218 | return(result); |
| 1219 | } |
| 1220 | |
| 1221 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) |
| 1222 | { |
| 1223 | uint32_t result; |
| 1224 | |
| 1225 | __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1226 | return(result); |
| 1227 | } |
| 1228 | |
| 1229 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) |
| 1230 | { |
| 1231 | uint32_t result; |
| 1232 | |
| 1233 | __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1234 | return(result); |
| 1235 | } |
| 1236 | |
| 1237 | |
| 1238 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) |
| 1239 | { |
| 1240 | uint32_t result; |
| 1241 | |
| 1242 | __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1243 | return(result); |
| 1244 | } |
| 1245 | |
| 1246 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) |
| 1247 | { |
| 1248 | uint32_t result; |
| 1249 | |
| 1250 | __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1251 | return(result); |
| 1252 | } |
| 1253 | |
| 1254 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) |
| 1255 | { |
| 1256 | uint32_t result; |
| 1257 | |
| 1258 | __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1259 | return(result); |
| 1260 | } |
| 1261 | |
| 1262 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) |
| 1263 | { |
| 1264 | uint32_t result; |
| 1265 | |
| 1266 | __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1267 | return(result); |
| 1268 | } |
| 1269 | |
| 1270 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) |
| 1271 | { |
| 1272 | uint32_t result; |
| 1273 | |
| 1274 | __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1275 | return(result); |
| 1276 | } |
| 1277 | |
| 1278 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) |
| 1279 | { |
| 1280 | uint32_t result; |
| 1281 | |
| 1282 | __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1283 | return(result); |
| 1284 | } |
| 1285 | |
| 1286 | |
| 1287 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) |
| 1288 | { |
| 1289 | uint32_t result; |
| 1290 | |
| 1291 | __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1292 | return(result); |
| 1293 | } |
| 1294 | |
| 1295 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) |
| 1296 | { |
| 1297 | uint32_t result; |
| 1298 | |
| 1299 | __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1300 | return(result); |
| 1301 | } |
| 1302 | |
| 1303 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) |
| 1304 | { |
| 1305 | uint32_t result; |
| 1306 | |
| 1307 | __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1308 | return(result); |
| 1309 | } |
| 1310 | |
| 1311 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) |
| 1312 | { |
| 1313 | uint32_t result; |
| 1314 | |
| 1315 | __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1316 | return(result); |
| 1317 | } |
| 1318 | |
| 1319 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) |
| 1320 | { |
| 1321 | uint32_t result; |
| 1322 | |
| 1323 | __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1324 | return(result); |
| 1325 | } |
| 1326 | |
| 1327 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) |
| 1328 | { |
| 1329 | uint32_t result; |
| 1330 | |
| 1331 | __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1332 | return(result); |
| 1333 | } |
| 1334 | |
| 1335 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) |
| 1336 | { |
| 1337 | uint32_t result; |
| 1338 | |
| 1339 | __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1340 | return(result); |
| 1341 | } |
| 1342 | |
| 1343 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) |
| 1344 | { |
| 1345 | uint32_t result; |
| 1346 | |
| 1347 | __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1348 | return(result); |
| 1349 | } |
| 1350 | |
| 1351 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) |
| 1352 | { |
| 1353 | uint32_t result; |
| 1354 | |
| 1355 | __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1356 | return(result); |
| 1357 | } |
| 1358 | |
| 1359 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) |
| 1360 | { |
| 1361 | uint32_t result; |
| 1362 | |
| 1363 | __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1364 | return(result); |
| 1365 | } |
| 1366 | |
| 1367 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) |
| 1368 | { |
| 1369 | uint32_t result; |
| 1370 | |
| 1371 | __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1372 | return(result); |
| 1373 | } |
| 1374 | |
| 1375 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) |
| 1376 | { |
| 1377 | uint32_t result; |
| 1378 | |
| 1379 | __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1380 | return(result); |
| 1381 | } |
| 1382 | |
| 1383 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) |
| 1384 | { |
| 1385 | uint32_t result; |
| 1386 | |
| 1387 | __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1388 | return(result); |
| 1389 | } |
| 1390 | |
| 1391 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) |
| 1392 | { |
| 1393 | uint32_t result; |
| 1394 | |
| 1395 | __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1396 | return(result); |
| 1397 | } |
| 1398 | |
| 1399 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) |
| 1400 | { |
| 1401 | uint32_t result; |
| 1402 | |
| 1403 | __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1404 | return(result); |
| 1405 | } |
| 1406 | |
| 1407 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) |
| 1408 | { |
| 1409 | uint32_t result; |
| 1410 | |
| 1411 | __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1412 | return(result); |
| 1413 | } |
| 1414 | |
| 1415 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) |
| 1416 | { |
| 1417 | uint32_t result; |
| 1418 | |
| 1419 | __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1420 | return(result); |
| 1421 | } |
| 1422 | |
| 1423 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) |
| 1424 | { |
| 1425 | uint32_t result; |
| 1426 | |
| 1427 | __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1428 | return(result); |
| 1429 | } |
| 1430 | |
| 1431 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) |
| 1432 | { |
| 1433 | uint32_t result; |
| 1434 | |
| 1435 | __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1436 | return(result); |
| 1437 | } |
| 1438 | |
| 1439 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) |
| 1440 | { |
| 1441 | uint32_t result; |
| 1442 | |
| 1443 | __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1444 | return(result); |
| 1445 | } |
| 1446 | |
| 1447 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) |
| 1448 | { |
| 1449 | uint32_t result; |
| 1450 | |
| 1451 | __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1452 | return(result); |
| 1453 | } |
| 1454 | |
| 1455 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) |
| 1456 | { |
| 1457 | uint32_t result; |
| 1458 | |
| 1459 | __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1460 | return(result); |
| 1461 | } |
| 1462 | |
| 1463 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) |
| 1464 | { |
| 1465 | uint32_t result; |
| 1466 | |
| 1467 | __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1468 | return(result); |
| 1469 | } |
| 1470 | |
| 1471 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) |
| 1472 | { |
| 1473 | uint32_t result; |
| 1474 | |
| 1475 | __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1476 | return(result); |
| 1477 | } |
| 1478 | |
| 1479 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) |
| 1480 | { |
| 1481 | uint32_t result; |
| 1482 | |
| 1483 | __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1484 | return(result); |
| 1485 | } |
| 1486 | |
| 1487 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) |
| 1488 | { |
| 1489 | uint32_t result; |
| 1490 | |
| 1491 | __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1492 | return(result); |
| 1493 | } |
| 1494 | |
| 1495 | #define __SSAT16(ARG1,ARG2) \ |
| 1496 | ({ \ |
| 1497 | int32_t __RES, __ARG1 = (ARG1); \ |
| 1498 | __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| 1499 | __RES; \ |
| 1500 | }) |
| 1501 | |
| 1502 | #define __USAT16(ARG1,ARG2) \ |
| 1503 | ({ \ |
| 1504 | uint32_t __RES, __ARG1 = (ARG1); \ |
| 1505 | __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| 1506 | __RES; \ |
| 1507 | }) |
| 1508 | |
| 1509 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) |
| 1510 | { |
| 1511 | uint32_t result; |
| 1512 | |
| 1513 | __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); |
| 1514 | return(result); |
| 1515 | } |
| 1516 | |
| 1517 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) |
| 1518 | { |
| 1519 | uint32_t result; |
| 1520 | |
| 1521 | __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1522 | return(result); |
| 1523 | } |
| 1524 | |
| 1525 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) |
| 1526 | { |
| 1527 | uint32_t result; |
| 1528 | |
| 1529 | __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); |
| 1530 | return(result); |
| 1531 | } |
| 1532 | |
| 1533 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) |
| 1534 | { |
| 1535 | uint32_t result; |
| 1536 | |
| 1537 | __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1538 | return(result); |
| 1539 | } |
| 1540 | |
| 1541 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) |
| 1542 | { |
| 1543 | uint32_t result; |
| 1544 | |
| 1545 | __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1546 | return(result); |
| 1547 | } |
| 1548 | |
| 1549 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) |
| 1550 | { |
| 1551 | uint32_t result; |
| 1552 | |
| 1553 | __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1554 | return(result); |
| 1555 | } |
| 1556 | |
| 1557 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1558 | { |
| 1559 | uint32_t result; |
| 1560 | |
| 1561 | __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1562 | return(result); |
| 1563 | } |
| 1564 | |
| 1565 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1566 | { |
| 1567 | uint32_t result; |
| 1568 | |
| 1569 | __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1570 | return(result); |
| 1571 | } |
| 1572 | |
| 1573 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1574 | { |
| 1575 | union llreg_u{ |
| 1576 | uint32_t w32[2]; |
| 1577 | uint64_t w64; |
| 1578 | } llr; |
| 1579 | llr.w64 = acc; |
| 1580 | |
| 1581 | #ifndef __ARMEB__ /* Little endian */ |
| 1582 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1583 | #else /* Big endian */ |
| 1584 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1585 | #endif |
| 1586 | |
| 1587 | return(llr.w64); |
| 1588 | } |
| 1589 | |
| 1590 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1591 | { |
| 1592 | union llreg_u{ |
| 1593 | uint32_t w32[2]; |
| 1594 | uint64_t w64; |
| 1595 | } llr; |
| 1596 | llr.w64 = acc; |
| 1597 | |
| 1598 | #ifndef __ARMEB__ /* Little endian */ |
| 1599 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1600 | #else /* Big endian */ |
| 1601 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1602 | #endif |
| 1603 | |
| 1604 | return(llr.w64); |
| 1605 | } |
| 1606 | |
| 1607 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) |
| 1608 | { |
| 1609 | uint32_t result; |
| 1610 | |
| 1611 | __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1612 | return(result); |
| 1613 | } |
| 1614 | |
| 1615 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) |
| 1616 | { |
| 1617 | uint32_t result; |
| 1618 | |
| 1619 | __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1620 | return(result); |
| 1621 | } |
| 1622 | |
| 1623 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1624 | { |
| 1625 | uint32_t result; |
| 1626 | |
| 1627 | __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1628 | return(result); |
| 1629 | } |
| 1630 | |
| 1631 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1632 | { |
| 1633 | uint32_t result; |
| 1634 | |
| 1635 | __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1636 | return(result); |
| 1637 | } |
| 1638 | |
| 1639 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1640 | { |
| 1641 | union llreg_u{ |
| 1642 | uint32_t w32[2]; |
| 1643 | uint64_t w64; |
| 1644 | } llr; |
| 1645 | llr.w64 = acc; |
| 1646 | |
| 1647 | #ifndef __ARMEB__ /* Little endian */ |
| 1648 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1649 | #else /* Big endian */ |
| 1650 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1651 | #endif |
| 1652 | |
| 1653 | return(llr.w64); |
| 1654 | } |
| 1655 | |
| 1656 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1657 | { |
| 1658 | union llreg_u{ |
| 1659 | uint32_t w32[2]; |
| 1660 | uint64_t w64; |
| 1661 | } llr; |
| 1662 | llr.w64 = acc; |
| 1663 | |
| 1664 | #ifndef __ARMEB__ /* Little endian */ |
| 1665 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1666 | #else /* Big endian */ |
| 1667 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1668 | #endif |
| 1669 | |
| 1670 | return(llr.w64); |
| 1671 | } |
| 1672 | |
| 1673 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) |
| 1674 | { |
| 1675 | uint32_t result; |
| 1676 | |
| 1677 | __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1678 | return(result); |
| 1679 | } |
| 1680 | |
| 1681 | __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) |
| 1682 | { |
| 1683 | int32_t result; |
| 1684 | |
| 1685 | __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1686 | return(result); |
| 1687 | } |
| 1688 | |
| 1689 | __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) |
| 1690 | { |
| 1691 | int32_t result; |
| 1692 | |
| 1693 | __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1694 | return(result); |
| 1695 | } |
| 1696 | |
| 1697 | #if 0 |
| 1698 | #define __PKHBT(ARG1,ARG2,ARG3) \ |
| 1699 | ({ \ |
| 1700 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ |
| 1701 | __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ |
| 1702 | __RES; \ |
| 1703 | }) |
| 1704 | |
| 1705 | #define __PKHTB(ARG1,ARG2,ARG3) \ |
| 1706 | ({ \ |
| 1707 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ |
| 1708 | if (ARG3 == 0) \ |
| 1709 | __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ |
| 1710 | else \ |
| 1711 | __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ |
| 1712 | __RES; \ |
| 1713 | }) |
| 1714 | #endif |
| 1715 | |
| 1716 | #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ |
| 1717 | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) |
| 1718 | |
| 1719 | #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ |
| 1720 | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) |
| 1721 | |
| 1722 | __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) |
| 1723 | { |
| 1724 | int32_t result; |
| 1725 | |
| 1726 | __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); |
| 1727 | return(result); |
| 1728 | } |
| 1729 | |
| 1730 | #endif /* (__ARM_FEATURE_DSP == 1) */ |
| 1731 | /*@} end of group CMSIS_SIMD_intrinsics */ |
| 1732 | |
| 1733 | |
| 1734 | #endif /* __CMSIS_ARMCLANG_H */ |