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gerrit.osmocom.org / osmo-ccid-firmware / 1b9a5b81253e0fc147b1b8942704fecfe1c860d6 / . / sysmoOCTSIM / CMSIS / Include / core_sc300.h
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Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**************************************************************************//**
2 * @file core_sc300.h
3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
4 * @version V5.0.1
5 * @date 25. November 2016
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_SC300_H_GENERIC
32#define __CORE_SC300_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup SC3000
60 @{
61 */
62
63/* CMSIS SC300 definitions */
64#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
67 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69#define __CORTEX_SC (300U) /*!< Cortex secure core */
70
71/** __FPU_USED indicates whether an FPU is used or not.
72 This core does not support an FPU at all
73*/
74#define __FPU_USED 0U
75
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #endif
80
81#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
82 #if defined __ARM_PCS_VFP
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #endif
85
86#elif defined ( __GNUC__ )
87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89 #endif
90
91#elif defined ( __ICCARM__ )
92 #if defined __ARMVFP__
93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #endif
95
96#elif defined ( __TI_ARM__ )
97 #if defined __TI_VFP_SUPPORT__
98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99 #endif
100
101#elif defined ( __TASKING__ )
102 #if defined __FPU_VFP__
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #endif
105
106#elif defined ( __CSMC__ )
107 #if ( __CSMC__ & 0x400U)
108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109 #endif
110
111#endif
112
113#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
114
115
116#ifdef __cplusplus
117}
118#endif
119
120#endif /* __CORE_SC300_H_GENERIC */
121
122#ifndef __CMSIS_GENERIC
123
124#ifndef __CORE_SC300_H_DEPENDANT
125#define __CORE_SC300_H_DEPENDANT
126
127#ifdef __cplusplus
128 extern "C" {
129#endif
130
131/* check device defines and use defaults */
132#if defined __CHECK_DEVICE_DEFINES
133 #ifndef __SC300_REV
134 #define __SC300_REV 0x0000U
135 #warning "__SC300_REV not defined in device header file; using default!"
136 #endif
137
138 #ifndef __MPU_PRESENT
139 #define __MPU_PRESENT 0U
140 #warning "__MPU_PRESENT not defined in device header file; using default!"
141 #endif
142
143 #ifndef __NVIC_PRIO_BITS
144 #define __NVIC_PRIO_BITS 3U
145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
146 #endif
147
148 #ifndef __Vendor_SysTickConfig
149 #define __Vendor_SysTickConfig 0U
150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
151 #endif
152#endif
153
154/* IO definitions (access restrictions to peripheral registers) */
155/**
156 \defgroup CMSIS_glob_defs CMSIS Global Defines
157
158 <strong>IO Type Qualifiers</strong> are used
159 \li to specify the access to peripheral variables.
160 \li for automatic generation of peripheral register debug information.
161*/
162#ifdef __cplusplus
163 #define __I volatile /*!< Defines 'read only' permissions */
164#else
165 #define __I volatile const /*!< Defines 'read only' permissions */
166#endif
167#define __O volatile /*!< Defines 'write only' permissions */
168#define __IO volatile /*!< Defines 'read / write' permissions */
169
170/* following defines should be used for structure members */
171#define __IM volatile const /*! Defines 'read only' structure member permissions */
172#define __OM volatile /*! Defines 'write only' structure member permissions */
173#define __IOM volatile /*! Defines 'read / write' structure member permissions */
174
175/*@} end of group SC300 */
176
177
178
179/*******************************************************************************
180 * Register Abstraction
181 Core Register contain:
182 - Core Register
183 - Core NVIC Register
184 - Core SCB Register
185 - Core SysTick Register
186 - Core Debug Register
187 - Core MPU Register
188 ******************************************************************************/
189/**
190 \defgroup CMSIS_core_register Defines and Type Definitions
191 \brief Type definitions and defines for Cortex-M processor based devices.
192*/
193
194/**
195 \ingroup CMSIS_core_register
196 \defgroup CMSIS_CORE Status and Control Registers
197 \brief Core Register type definitions.
198 @{
199 */
200
201/**
202 \brief Union type to access the Application Program Status Register (APSR).
203 */
204typedef union
205{
206 struct
207 {
208 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
209 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
214 } b; /*!< Structure used for bit access */
215 uint32_t w; /*!< Type used for word access */
216} APSR_Type;
217
218/* APSR Register Definitions */
219#define APSR_N_Pos 31U /*!< APSR: N Position */
220#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
221
222#define APSR_Z_Pos 30U /*!< APSR: Z Position */
223#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
224
225#define APSR_C_Pos 29U /*!< APSR: C Position */
226#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
227
228#define APSR_V_Pos 28U /*!< APSR: V Position */
229#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
230
231#define APSR_Q_Pos 27U /*!< APSR: Q Position */
232#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
233
234
235/**
236 \brief Union type to access the Interrupt Program Status Register (IPSR).
237 */
238typedef union
239{
240 struct
241 {
242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
244 } b; /*!< Structure used for bit access */
245 uint32_t w; /*!< Type used for word access */
246} IPSR_Type;
247
248/* IPSR Register Definitions */
249#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
250#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
251
252
253/**
254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
255 */
256typedef union
257{
258 struct
259 {
260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
261 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
262 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
263 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
264 uint32_t T:1; /*!< bit: 24 Thumb bit */
265 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
271 } b; /*!< Structure used for bit access */
272 uint32_t w; /*!< Type used for word access */
273} xPSR_Type;
274
275/* xPSR Register Definitions */
276#define xPSR_N_Pos 31U /*!< xPSR: N Position */
277#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
278
279#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
280#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
281
282#define xPSR_C_Pos 29U /*!< xPSR: C Position */
283#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
284
285#define xPSR_V_Pos 28U /*!< xPSR: V Position */
286#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
287
288#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
289#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
290
291#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
292#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
293
294#define xPSR_T_Pos 24U /*!< xPSR: T Position */
295#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
296
297#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
298#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
299
300#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
301#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
302
303
304/**
305 \brief Union type to access the Control Registers (CONTROL).
306 */
307typedef union
308{
309 struct
310 {
311 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
312 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
313 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
314 } b; /*!< Structure used for bit access */
315 uint32_t w; /*!< Type used for word access */
316} CONTROL_Type;
317
318/* CONTROL Register Definitions */
319#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
320#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
321
322#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
323#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
324
325/*@} end of group CMSIS_CORE */
326
327
328/**
329 \ingroup CMSIS_core_register
330 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
331 \brief Type definitions for the NVIC Registers
332 @{
333 */
334
335/**
336 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
337 */
338typedef struct
339{
340 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
341 uint32_t RESERVED0[24U];
342 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
343 uint32_t RSERVED1[24U];
344 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
345 uint32_t RESERVED2[24U];
346 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
347 uint32_t RESERVED3[24U];
348 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
349 uint32_t RESERVED4[56U];
350 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
351 uint32_t RESERVED5[644U];
352 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
353} NVIC_Type;
354
355/* Software Triggered Interrupt Register Definitions */
356#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
357#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
358
359/*@} end of group CMSIS_NVIC */
360
361
362/**
363 \ingroup CMSIS_core_register
364 \defgroup CMSIS_SCB System Control Block (SCB)
365 \brief Type definitions for the System Control Block Registers
366 @{
367 */
368
369/**
370 \brief Structure type to access the System Control Block (SCB).
371 */
372typedef struct
373{
374 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
375 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
376 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
377 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
378 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
379 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
380 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
381 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
382 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
383 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
384 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
385 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
386 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
387 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
388 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
389 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
390 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
391 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
392 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
393 uint32_t RESERVED0[5U];
394 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
395 uint32_t RESERVED1[129U];
396 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
397} SCB_Type;
398
399/* SCB CPUID Register Definitions */
400#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
401#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
402
403#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
404#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
405
406#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
407#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
408
409#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
410#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
411
412#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
413#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
414
415/* SCB Interrupt Control State Register Definitions */
416#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
417#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
418
419#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
420#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
421
422#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
423#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
424
425#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
426#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
427
428#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
429#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
430
431#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
432#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
433
434#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
435#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
436
437#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
438#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
439
440#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
441#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
442
443#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
444#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
445
446/* SCB Vector Table Offset Register Definitions */
447#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
448#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
449
450#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
451#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
452
453/* SCB Application Interrupt and Reset Control Register Definitions */
454#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
455#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
456
457#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
458#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
459
460#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
461#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
462
463#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
464#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
465
466#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
467#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
468
469#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
470#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
471
472#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
473#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
474
475/* SCB System Control Register Definitions */
476#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
477#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
478
479#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
480#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
481
482#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
483#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
484
485/* SCB Configuration Control Register Definitions */
486#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
487#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
488
489#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
490#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
491
492#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
493#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
494
495#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
496#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
497
498#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
499#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
500
501#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
502#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
503
504/* SCB System Handler Control and State Register Definitions */
505#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
506#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
507
508#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
509#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
510
511#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
512#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
513
514#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
515#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
516
517#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
518#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
519
520#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
521#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
522
523#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
524#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
525
526#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
527#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
528
529#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
530#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
531
532#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
533#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
534
535#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
536#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
537
538#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
539#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
540
541#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
542#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
543
544#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
545#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
546
547/* SCB Configurable Fault Status Register Definitions */
548#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
549#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
550
551#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
552#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
553
554#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
555#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
556
557/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
558#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
559#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
560
561#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
562#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
563
564#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
565#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
566
567#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
568#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
569
570#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
571#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
572
573/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
574#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
575#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
576
577#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
578#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
579
580#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
581#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
582
583#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
584#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
585
586#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
587#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
588
589#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
590#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
591
592/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
593#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
594#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
595
596#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
597#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
598
599#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
600#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
601
602#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
603#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
604
605#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
606#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
607
608#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
609#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
610
611/* SCB Hard Fault Status Register Definitions */
612#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
613#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
614
615#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
616#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
617
618#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
619#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
620
621/* SCB Debug Fault Status Register Definitions */
622#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
623#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
624
625#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
626#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
627
628#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
629#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
630
631#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
632#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
633
634#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
635#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
636
637/*@} end of group CMSIS_SCB */
638
639
640/**
641 \ingroup CMSIS_core_register
642 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
643 \brief Type definitions for the System Control and ID Register not in the SCB
644 @{
645 */
646
647/**
648 \brief Structure type to access the System Control and ID Register not in the SCB.
649 */
650typedef struct
651{
652 uint32_t RESERVED0[1U];
653 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
654 uint32_t RESERVED1[1U];
655} SCnSCB_Type;
656
657/* Interrupt Controller Type Register Definitions */
658#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
659#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
660
661/*@} end of group CMSIS_SCnotSCB */
662
663
664/**
665 \ingroup CMSIS_core_register
666 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
667 \brief Type definitions for the System Timer Registers.
668 @{
669 */
670
671/**
672 \brief Structure type to access the System Timer (SysTick).
673 */
674typedef struct
675{
676 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
677 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
678 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
679 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
680} SysTick_Type;
681
682/* SysTick Control / Status Register Definitions */
683#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
684#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
685
686#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
687#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
688
689#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
690#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
691
692#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
693#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
694
695/* SysTick Reload Register Definitions */
696#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
697#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
698
699/* SysTick Current Register Definitions */
700#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
701#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
702
703/* SysTick Calibration Register Definitions */
704#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
705#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
706
707#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
708#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
709
710#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
711#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
712
713/*@} end of group CMSIS_SysTick */
714
715
716/**
717 \ingroup CMSIS_core_register
718 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
719 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
720 @{
721 */
722
723/**
724 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
725 */
726typedef struct
727{
728 __OM union
729 {
730 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
731 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
732 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
733 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
734 uint32_t RESERVED0[864U];
735 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
736 uint32_t RESERVED1[15U];
737 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
738 uint32_t RESERVED2[15U];
739 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
740 uint32_t RESERVED3[29U];
741 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
742 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
743 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
744 uint32_t RESERVED4[43U];
745 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
746 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
747 uint32_t RESERVED5[6U];
748 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
749 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
750 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
751 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
752 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
753 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
754 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
755 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
756 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
757 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
758 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
759 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
760} ITM_Type;
761
762/* ITM Trace Privilege Register Definitions */
763#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
764#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
765
766/* ITM Trace Control Register Definitions */
767#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
768#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
769
770#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
771#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
772
773#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
774#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
775
776#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
777#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
778
779#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
780#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
781
782#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
783#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
784
785#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
786#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
787
788#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
789#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
790
791#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
792#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
793
794/* ITM Integration Write Register Definitions */
795#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
796#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
797
798/* ITM Integration Read Register Definitions */
799#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
800#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
801
802/* ITM Integration Mode Control Register Definitions */
803#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
804#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
805
806/* ITM Lock Status Register Definitions */
807#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
808#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
809
810#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
811#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
812
813#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
814#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
815
816/*@}*/ /* end of group CMSIS_ITM */
817
818
819/**
820 \ingroup CMSIS_core_register
821 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
822 \brief Type definitions for the Data Watchpoint and Trace (DWT)
823 @{
824 */
825
826/**
827 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
828 */
829typedef struct
830{
831 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
832 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
833 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
834 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
835 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
836 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
837 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
838 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
839 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
840 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
841 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
842 uint32_t RESERVED0[1U];
843 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
844 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
845 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
846 uint32_t RESERVED1[1U];
847 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
848 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
849 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
850 uint32_t RESERVED2[1U];
851 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
852 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
853 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
854} DWT_Type;
855
856/* DWT Control Register Definitions */
857#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
858#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
859
860#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
861#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
862
863#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
864#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
865
866#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
867#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
868
869#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
870#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
871
872#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
873#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
874
875#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
876#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
877
878#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
879#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
880
881#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
882#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
883
884#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
885#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
886
887#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
888#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
889
890#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
891#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
892
893#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
894#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
895
896#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
897#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
898
899#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
900#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
901
902#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
903#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
904
905#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
906#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
907
908#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
909#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
910
911/* DWT CPI Count Register Definitions */
912#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
913#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
914
915/* DWT Exception Overhead Count Register Definitions */
916#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
917#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
918
919/* DWT Sleep Count Register Definitions */
920#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
921#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
922
923/* DWT LSU Count Register Definitions */
924#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
925#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
926
927/* DWT Folded-instruction Count Register Definitions */
928#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
929#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
930
931/* DWT Comparator Mask Register Definitions */
932#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
933#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
934
935/* DWT Comparator Function Register Definitions */
936#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
937#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
938
939#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
940#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
941
942#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
943#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
944
945#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
946#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
947
948#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
949#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
950
951#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
952#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
953
954#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
955#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
956
957#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
958#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
959
960#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
961#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
962
963/*@}*/ /* end of group CMSIS_DWT */
964
965
966/**
967 \ingroup CMSIS_core_register
968 \defgroup CMSIS_TPI Trace Port Interface (TPI)
969 \brief Type definitions for the Trace Port Interface (TPI)
970 @{
971 */
972
973/**
974 \brief Structure type to access the Trace Port Interface Register (TPI).
975 */
976typedef struct
977{
978 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
979 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
980 uint32_t RESERVED0[2U];
981 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
982 uint32_t RESERVED1[55U];
983 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
984 uint32_t RESERVED2[131U];
985 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
986 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
987 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
988 uint32_t RESERVED3[759U];
989 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
990 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
991 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
992 uint32_t RESERVED4[1U];
993 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
994 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
995 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
996 uint32_t RESERVED5[39U];
997 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
998 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
999 uint32_t RESERVED7[8U];
1000 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1001 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1002} TPI_Type;
1003
1004/* TPI Asynchronous Clock Prescaler Register Definitions */
1005#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1006#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1007
1008/* TPI Selected Pin Protocol Register Definitions */
1009#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1010#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1011
1012/* TPI Formatter and Flush Status Register Definitions */
1013#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1014#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1015
1016#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1017#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1018
1019#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1020#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1021
1022#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1023#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1024
1025/* TPI Formatter and Flush Control Register Definitions */
1026#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1027#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1028
1029#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1030#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1031
1032/* TPI TRIGGER Register Definitions */
1033#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1034#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1035
1036/* TPI Integration ETM Data Register Definitions (FIFO0) */
1037#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1038#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1039
1040#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1041#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1042
1043#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1044#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1045
1046#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1047#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1048
1049#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1050#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1051
1052#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1053#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1054
1055#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1056#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1057
1058/* TPI ITATBCTR2 Register Definitions */
1059#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1060#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1061
1062/* TPI Integration ITM Data Register Definitions (FIFO1) */
1063#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1064#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1065
1066#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1067#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1068
1069#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1070#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1071
1072#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1073#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1074
1075#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1076#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1077
1078#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1079#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1080
1081#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1082#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1083
1084/* TPI ITATBCTR0 Register Definitions */
1085#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1086#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1087
1088/* TPI Integration Mode Control Register Definitions */
1089#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1090#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1091
1092/* TPI DEVID Register Definitions */
1093#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1094#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1095
1096#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1097#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1098
1099#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1100#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1101
1102#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1103#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1104
1105#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1106#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1107
1108#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1109#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1110
1111/* TPI DEVTYPE Register Definitions */
1112#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1113#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1114
1115#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1116#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1117
1118/*@}*/ /* end of group CMSIS_TPI */
1119
1120
1121#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1122/**
1123 \ingroup CMSIS_core_register
1124 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1125 \brief Type definitions for the Memory Protection Unit (MPU)
1126 @{
1127 */
1128
1129/**
1130 \brief Structure type to access the Memory Protection Unit (MPU).
1131 */
1132typedef struct
1133{
1134 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1135 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1136 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1137 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1138 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1139 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1140 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1141 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1142 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1143 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1144 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1145} MPU_Type;
1146
1147/* MPU Type Register Definitions */
1148#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1149#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1150
1151#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1152#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1153
1154#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1155#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1156
1157/* MPU Control Register Definitions */
1158#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1159#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1160
1161#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1162#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1163
1164#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1165#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1166
1167/* MPU Region Number Register Definitions */
1168#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1169#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1170
1171/* MPU Region Base Address Register Definitions */
1172#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1173#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1174
1175#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1176#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1177
1178#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1179#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1180
1181/* MPU Region Attribute and Size Register Definitions */
1182#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1183#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1184
1185#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1186#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1187
1188#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1189#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1190
1191#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1192#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1193
1194#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1195#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1196
1197#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1198#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1199
1200#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1201#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1202
1203#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1204#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1205
1206#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1207#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1208
1209#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1210#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1211
1212/*@} end of group CMSIS_MPU */
1213#endif
1214
1215
1216/**
1217 \ingroup CMSIS_core_register
1218 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1219 \brief Type definitions for the Core Debug Registers
1220 @{
1221 */
1222
1223/**
1224 \brief Structure type to access the Core Debug Register (CoreDebug).
1225 */
1226typedef struct
1227{
1228 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1229 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1230 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1231 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1232} CoreDebug_Type;
1233
1234/* Debug Halting Control and Status Register Definitions */
1235#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1236#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1237
1238#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1239#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1240
1241#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1242#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1243
1244#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1245#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1246
1247#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1248#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1249
1250#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1251#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1252
1253#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1254#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1255
1256#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1257#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1258
1259#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1260#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1261
1262#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1263#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1264
1265#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1266#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1267
1268#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1269#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1270
1271/* Debug Core Register Selector Register Definitions */
1272#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1273#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1274
1275#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1276#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1277
1278/* Debug Exception and Monitor Control Register Definitions */
1279#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1280#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1281
1282#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1283#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1284
1285#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1286#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1287
1288#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1289#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1290
1291#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1292#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1293
1294#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1295#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1296
1297#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1298#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1299
1300#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1301#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1302
1303#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1304#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1305
1306#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1307#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1308
1309#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1310#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1311
1312#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1313#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1314
1315#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1316#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1317
1318/*@} end of group CMSIS_CoreDebug */
1319
1320
1321/**
1322 \ingroup CMSIS_core_register
1323 \defgroup CMSIS_core_bitfield Core register bit field macros
1324 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1325 @{
1326 */
1327
1328/**
1329 \brief Mask and shift a bit field value for use in a register bit range.
1330 \param[in] field Name of the register bit field.
1331 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1332 \return Masked and shifted value.
1333*/
1334#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1335
1336/**
1337 \brief Mask and shift a register value to extract a bit filed value.
1338 \param[in] field Name of the register bit field.
1339 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1340 \return Masked and shifted bit field value.
1341*/
1342#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1343
1344/*@} end of group CMSIS_core_bitfield */
1345
1346
1347/**
1348 \ingroup CMSIS_core_register
1349 \defgroup CMSIS_core_base Core Definitions
1350 \brief Definitions for base addresses, unions, and structures.
1351 @{
1352 */
1353
1354/* Memory mapping of Core Hardware */
1355#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1356#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1357#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1358#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1359#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1360#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1361#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1362#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1363
1364#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1365#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1366#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1367#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1368#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1369#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1370#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1371#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1372
1373#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1374 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1375 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1376#endif
1377
1378/*@} */
1379
1380
1381
1382/*******************************************************************************
1383 * Hardware Abstraction Layer
1384 Core Function Interface contains:
1385 - Core NVIC Functions
1386 - Core SysTick Functions
1387 - Core Debug Functions
1388 - Core Register Access Functions
1389 ******************************************************************************/
1390/**
1391 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1392*/
1393
1394
1395
1396/* ########################## NVIC functions #################################### */
1397/**
1398 \ingroup CMSIS_Core_FunctionInterface
1399 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1400 \brief Functions that manage interrupts and exceptions via the NVIC.
1401 @{
1402 */
1403
1404#ifndef CMSIS_NVIC_VIRTUAL
1405 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1406 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1407 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1408 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1409 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1410 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1411 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1412 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1413 #define NVIC_GetActive __NVIC_GetActive
1414 #define NVIC_SetPriority __NVIC_SetPriority
1415 #define NVIC_GetPriority __NVIC_GetPriority
1416#endif /* CMSIS_NVIC_VIRTUAL */
1417
1418#ifndef CMSIS_VECTAB_VIRTUAL
1419 #define NVIC_SetVector __NVIC_SetVector
1420 #define NVIC_GetVector __NVIC_GetVector
1421#endif /* (CMSIS_VECTAB_VIRTUAL) */
1422
1423#define NVIC_USER_IRQ_OFFSET 16
1424
1425
1426
1427/**
1428 \brief Set Priority Grouping
1429 \details Sets the priority grouping field using the required unlock sequence.
1430 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1431 Only values from 0..7 are used.
1432 In case of a conflict between priority grouping and available
1433 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1434 \param [in] PriorityGroup Priority grouping field.
1435 */
1436__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1437{
1438 uint32_t reg_value;
1439 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1440
1441 reg_value = SCB->AIRCR; /* read old register configuration */
1442 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1443 reg_value = (reg_value |
1444 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1445 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1446 SCB->AIRCR = reg_value;
1447}
1448
1449
1450/**
1451 \brief Get Priority Grouping
1452 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1454 */
1455__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1456{
1457 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1458}
1459
1460
1461/**
1462 \brief Enable Interrupt
1463 \details Enables a device specific interrupt in the NVIC interrupt controller.
1464 \param [in] IRQn Device specific interrupt number.
1465 \note IRQn must not be negative.
1466 */
1467__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1468{
1469 if ((int32_t)(IRQn) >= 0)
1470 {
1471 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1472 }
1473}
1474
1475
1476/**
1477 \brief Get Interrupt Enable status
1478 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1479 \param [in] IRQn Device specific interrupt number.
1480 \return 0 Interrupt is not enabled.
1481 \return 1 Interrupt is enabled.
1482 \note IRQn must not be negative.
1483 */
1484__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1485{
1486 if ((int32_t)(IRQn) >= 0)
1487 {
1488 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1489 }
1490 else
1491 {
1492 return(0U);
1493 }
1494}
1495
1496
1497/**
1498 \brief Disable Interrupt
1499 \details Disables a device specific interrupt in the NVIC interrupt controller.
1500 \param [in] IRQn Device specific interrupt number.
1501 \note IRQn must not be negative.
1502 */
1503__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1504{
1505 if ((int32_t)(IRQn) >= 0)
1506 {
1507 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1508 __DSB();
1509 __ISB();
1510 }
1511}
1512
1513
1514/**
1515 \brief Get Pending Interrupt
1516 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1517 \param [in] IRQn Device specific interrupt number.
1518 \return 0 Interrupt status is not pending.
1519 \return 1 Interrupt status is pending.
1520 \note IRQn must not be negative.
1521 */
1522__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1523{
1524 if ((int32_t)(IRQn) >= 0)
1525 {
1526 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1527 }
1528 else
1529 {
1530 return(0U);
1531 }
1532}
1533
1534
1535/**
1536 \brief Set Pending Interrupt
1537 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1538 \param [in] IRQn Device specific interrupt number.
1539 \note IRQn must not be negative.
1540 */
1541__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1542{
1543 if ((int32_t)(IRQn) >= 0)
1544 {
1545 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1546 }
1547}
1548
1549
1550/**
1551 \brief Clear Pending Interrupt
1552 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1553 \param [in] IRQn Device specific interrupt number.
1554 \note IRQn must not be negative.
1555 */
1556__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1557{
1558 if ((int32_t)(IRQn) >= 0)
1559 {
1560 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1561 }
1562}
1563
1564
1565/**
1566 \brief Get Active Interrupt
1567 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1568 \param [in] IRQn Device specific interrupt number.
1569 \return 0 Interrupt status is not active.
1570 \return 1 Interrupt status is active.
1571 \note IRQn must not be negative.
1572 */
1573__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1574{
1575 if ((int32_t)(IRQn) >= 0)
1576 {
1577 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1578 }
1579 else
1580 {
1581 return(0U);
1582 }
1583}
1584
1585
1586/**
1587 \brief Set Interrupt Priority
1588 \details Sets the priority of a device specific interrupt or a processor exception.
1589 The interrupt number can be positive to specify a device specific interrupt,
1590 or negative to specify a processor exception.
1591 \param [in] IRQn Interrupt number.
1592 \param [in] priority Priority to set.
1593 \note The priority cannot be set for every processor exception.
1594 */
1595__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1596{
1597 if ((int32_t)(IRQn) >= 0)
1598 {
1599 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1600 }
1601 else
1602 {
1603 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1604 }
1605}
1606
1607
1608/**
1609 \brief Get Interrupt Priority
1610 \details Reads the priority of a device specific interrupt or a processor exception.
1611 The interrupt number can be positive to specify a device specific interrupt,
1612 or negative to specify a processor exception.
1613 \param [in] IRQn Interrupt number.
1614 \return Interrupt Priority.
1615 Value is aligned automatically to the implemented priority bits of the microcontroller.
1616 */
1617__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1618{
1619
1620 if ((int32_t)(IRQn) >= 0)
1621 {
1622 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1623 }
1624 else
1625 {
1626 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1627 }
1628}
1629
1630
1631/**
1632 \brief Encode Priority
1633 \details Encodes the priority for an interrupt with the given priority group,
1634 preemptive priority value, and subpriority value.
1635 In case of a conflict between priority grouping and available
1636 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1637 \param [in] PriorityGroup Used priority group.
1638 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1639 \param [in] SubPriority Subpriority value (starting from 0).
1640 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1641 */
1642__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1643{
1644 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1645 uint32_t PreemptPriorityBits;
1646 uint32_t SubPriorityBits;
1647
1648 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1649 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1650
1651 return (
1652 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1653 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1654 );
1655}
1656
1657
1658/**
1659 \brief Decode Priority
1660 \details Decodes an interrupt priority value with a given priority group to
1661 preemptive priority value and subpriority value.
1662 In case of a conflict between priority grouping and available
1663 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1664 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1665 \param [in] PriorityGroup Used priority group.
1666 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1667 \param [out] pSubPriority Subpriority value (starting from 0).
1668 */
1669__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1670{
1671 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1672 uint32_t PreemptPriorityBits;
1673 uint32_t SubPriorityBits;
1674
1675 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1676 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1677
1678 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1679 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1680}
1681
1682
1683/**
1684 \brief Set Interrupt Vector
1685 \details Sets an interrupt vector in SRAM based interrupt vector table.
1686 The interrupt number can be positive to specify a device specific interrupt,
1687 or negative to specify a processor exception.
1688 VTOR must been relocated to SRAM before.
1689 \param [in] IRQn Interrupt number
1690 \param [in] vector Address of interrupt handler function
1691 */
1692__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1693{
1694 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1695 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1696}
1697
1698
1699/**
1700 \brief Get Interrupt Vector
1701 \details Reads an interrupt vector from interrupt vector table.
1702 The interrupt number can be positive to specify a device specific interrupt,
1703 or negative to specify a processor exception.
1704 \param [in] IRQn Interrupt number.
1705 \return Address of interrupt handler function
1706 */
1707__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1708{
1709 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1710 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1711}
1712
1713
1714/**
1715 \brief System Reset
1716 \details Initiates a system reset request to reset the MCU.
1717 */
1718__STATIC_INLINE void NVIC_SystemReset(void)
1719{
1720 __DSB(); /* Ensure all outstanding memory accesses included
1721 buffered write are completed before reset */
1722 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1723 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1724 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1725 __DSB(); /* Ensure completion of memory access */
1726
1727 for(;;) /* wait until reset */
1728 {
1729 __NOP();
1730 }
1731}
1732
1733/*@} end of CMSIS_Core_NVICFunctions */
1734
1735
1736/* ########################## FPU functions #################################### */
1737/**
1738 \ingroup CMSIS_Core_FunctionInterface
1739 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1740 \brief Function that provides FPU type.
1741 @{
1742 */
1743
1744/**
1745 \brief get FPU type
1746 \details returns the FPU type
1747 \returns
1748 - \b 0: No FPU
1749 - \b 1: Single precision FPU
1750 - \b 2: Double + Single precision FPU
1751 */
1752__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1753{
1754 return 0U; /* No FPU */
1755}
1756
1757
1758/*@} end of CMSIS_Core_FpuFunctions */
1759
1760
1761
1762/* ################################## SysTick function ############################################ */
1763/**
1764 \ingroup CMSIS_Core_FunctionInterface
1765 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1766 \brief Functions that configure the System.
1767 @{
1768 */
1769
1770#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1771
1772/**
1773 \brief System Tick Configuration
1774 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1775 Counter is in free running mode to generate periodic interrupts.
1776 \param [in] ticks Number of ticks between two interrupts.
1777 \return 0 Function succeeded.
1778 \return 1 Function failed.
1779 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1780 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1781 must contain a vendor-specific implementation of this function.
1782 */
1783__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1784{
1785 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1786 {
1787 return (1UL); /* Reload value impossible */
1788 }
1789
1790 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1791 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1792 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1793 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1794 SysTick_CTRL_TICKINT_Msk |
1795 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1796 return (0UL); /* Function successful */
1797}
1798
1799#endif
1800
1801/*@} end of CMSIS_Core_SysTickFunctions */
1802
1803
1804
1805/* ##################################### Debug In/Output function ########################################### */
1806/**
1807 \ingroup CMSIS_Core_FunctionInterface
1808 \defgroup CMSIS_core_DebugFunctions ITM Functions
1809 \brief Functions that access the ITM debug interface.
1810 @{
1811 */
1812
1813extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1814#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1815
1816
1817/**
1818 \brief ITM Send Character
1819 \details Transmits a character via the ITM channel 0, and
1820 \li Just returns when no debugger is connected that has booked the output.
1821 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1822 \param [in] ch Character to transmit.
1823 \returns Character to transmit.
1824 */
1825__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1826{
1827 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1828 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1829 {
1830 while (ITM->PORT[0U].u32 == 0UL)
1831 {
1832 __NOP();
1833 }
1834 ITM->PORT[0U].u8 = (uint8_t)ch;
1835 }
1836 return (ch);
1837}
1838
1839
1840/**
1841 \brief ITM Receive Character
1842 \details Inputs a character via the external variable \ref ITM_RxBuffer.
1843 \return Received character.
1844 \return -1 No character pending.
1845 */
1846__STATIC_INLINE int32_t ITM_ReceiveChar (void)
1847{
1848 int32_t ch = -1; /* no character available */
1849
1850 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1851 {
1852 ch = ITM_RxBuffer;
1853 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1854 }
1855
1856 return (ch);
1857}
1858
1859
1860/**
1861 \brief ITM Check Character
1862 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1863 \return 0 No character available.
1864 \return 1 Character available.
1865 */
1866__STATIC_INLINE int32_t ITM_CheckChar (void)
1867{
1868
1869 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1870 {
1871 return (0); /* no character available */
1872 }
1873 else
1874 {
1875 return (1); /* character available */
1876 }
1877}
1878
1879/*@} end of CMSIS_core_DebugFunctions */
1880
1881
1882
1883
1884#ifdef __cplusplus
1885}
1886#endif
1887
1888#endif /* __CORE_SC300_H_DEPENDANT */
1889
1890#endif /* __CMSIS_GENERIC */