Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for QSPI
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_QSPI_INSTANCE_
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| 31 | #define _SAME54_QSPI_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for QSPI peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_QSPI_CTRLA (0x42003400) /**< \brief (QSPI) Control A */
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| 36 | #define REG_QSPI_CTRLB (0x42003404) /**< \brief (QSPI) Control B */
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| 37 | #define REG_QSPI_BAUD (0x42003408) /**< \brief (QSPI) Baud Rate */
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| 38 | #define REG_QSPI_RXDATA (0x4200340C) /**< \brief (QSPI) Receive Data */
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| 39 | #define REG_QSPI_TXDATA (0x42003410) /**< \brief (QSPI) Transmit Data */
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| 40 | #define REG_QSPI_INTENCLR (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */
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| 41 | #define REG_QSPI_INTENSET (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */
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| 42 | #define REG_QSPI_INTFLAG (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */
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| 43 | #define REG_QSPI_STATUS (0x42003420) /**< \brief (QSPI) Status Register */
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| 44 | #define REG_QSPI_INSTRADDR (0x42003430) /**< \brief (QSPI) Instruction Address */
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| 45 | #define REG_QSPI_INSTRCTRL (0x42003434) /**< \brief (QSPI) Instruction Code */
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| 46 | #define REG_QSPI_INSTRFRAME (0x42003438) /**< \brief (QSPI) Instruction Frame */
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| 47 | #define REG_QSPI_SCRAMBCTRL (0x42003440) /**< \brief (QSPI) Scrambling Mode */
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| 48 | #define REG_QSPI_SCRAMBKEY (0x42003444) /**< \brief (QSPI) Scrambling Key */
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| 49 | #else
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| 50 | #define REG_QSPI_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (QSPI) Control A */
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| 51 | #define REG_QSPI_CTRLB (*(RwReg *)0x42003404UL) /**< \brief (QSPI) Control B */
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| 52 | #define REG_QSPI_BAUD (*(RwReg *)0x42003408UL) /**< \brief (QSPI) Baud Rate */
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| 53 | #define REG_QSPI_RXDATA (*(RoReg *)0x4200340CUL) /**< \brief (QSPI) Receive Data */
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| 54 | #define REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) /**< \brief (QSPI) Transmit Data */
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| 55 | #define REG_QSPI_INTENCLR (*(RwReg *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */
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| 56 | #define REG_QSPI_INTENSET (*(RwReg *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */
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| 57 | #define REG_QSPI_INTFLAG (*(RwReg *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */
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| 58 | #define REG_QSPI_STATUS (*(RoReg *)0x42003420UL) /**< \brief (QSPI) Status Register */
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| 59 | #define REG_QSPI_INSTRADDR (*(RwReg *)0x42003430UL) /**< \brief (QSPI) Instruction Address */
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| 60 | #define REG_QSPI_INSTRCTRL (*(RwReg *)0x42003434UL) /**< \brief (QSPI) Instruction Code */
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| 61 | #define REG_QSPI_INSTRFRAME (*(RwReg *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */
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| 62 | #define REG_QSPI_SCRAMBCTRL (*(RwReg *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */
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| 63 | #define REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */
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| 64 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 65 |
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| 66 | /* ========== Instance parameters for QSPI peripheral ========== */
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| 67 | #define QSPI_DMAC_ID_RX 83
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| 68 | #define QSPI_DMAC_ID_TX 84
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| 69 | #define QSPI_HADDR_MSB 23
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| 70 | #define QSPI_OCMS 1
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| 71 |
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| 72 | #endif /* _SAME54_QSPI_INSTANCE_ */
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