Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for DAC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_DAC_INSTANCE_
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| 31 | #define _SAME54_DAC_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for DAC peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_DAC_CTRLA (0x43002400) /**< \brief (DAC) Control A */
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| 36 | #define REG_DAC_CTRLB (0x43002401) /**< \brief (DAC) Control B */
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| 37 | #define REG_DAC_EVCTRL (0x43002402) /**< \brief (DAC) Event Control */
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| 38 | #define REG_DAC_INTENCLR (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */
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| 39 | #define REG_DAC_INTENSET (0x43002405) /**< \brief (DAC) Interrupt Enable Set */
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| 40 | #define REG_DAC_INTFLAG (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */
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| 41 | #define REG_DAC_STATUS (0x43002407) /**< \brief (DAC) Status */
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| 42 | #define REG_DAC_SYNCBUSY (0x43002408) /**< \brief (DAC) Synchronization Busy */
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| 43 | #define REG_DAC_DACCTRL0 (0x4300240C) /**< \brief (DAC) DAC 0 Control */
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| 44 | #define REG_DAC_DACCTRL1 (0x4300240E) /**< \brief (DAC) DAC 1 Control */
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| 45 | #define REG_DAC_DATA0 (0x43002410) /**< \brief (DAC) DAC 0 Data */
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| 46 | #define REG_DAC_DATA1 (0x43002412) /**< \brief (DAC) DAC 1 Data */
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| 47 | #define REG_DAC_DATABUF0 (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */
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| 48 | #define REG_DAC_DATABUF1 (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */
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| 49 | #define REG_DAC_DBGCTRL (0x43002418) /**< \brief (DAC) Debug Control */
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| 50 | #define REG_DAC_RESULT0 (0x4300241C) /**< \brief (DAC) Filter Result 0 */
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| 51 | #define REG_DAC_RESULT1 (0x4300241E) /**< \brief (DAC) Filter Result 1 */
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| 52 | #else
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| 53 | #define REG_DAC_CTRLA (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */
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| 54 | #define REG_DAC_CTRLB (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */
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| 55 | #define REG_DAC_EVCTRL (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */
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| 56 | #define REG_DAC_INTENCLR (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */
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| 57 | #define REG_DAC_INTENSET (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */
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| 58 | #define REG_DAC_INTFLAG (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
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| 59 | #define REG_DAC_STATUS (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */
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| 60 | #define REG_DAC_SYNCBUSY (*(RoReg *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */
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| 61 | #define REG_DAC_DACCTRL0 (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */
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| 62 | #define REG_DAC_DACCTRL1 (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */
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| 63 | #define REG_DAC_DATA0 (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */
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| 64 | #define REG_DAC_DATA1 (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */
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| 65 | #define REG_DAC_DATABUF0 (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */
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| 66 | #define REG_DAC_DATABUF1 (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */
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| 67 | #define REG_DAC_DBGCTRL (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */
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| 68 | #define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
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| 69 | #define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
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| 70 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 71 |
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| 72 | /* ========== Instance parameters for DAC peripheral ========== */
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| 73 | #define DAC_CHANNEL_SIZE 2 // Number of DACs
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| 74 | #define DAC_DATA_SIZE 12 // Number of bits in data
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| 75 | #define DAC_DMAC_ID_EMPTY_0 72
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| 76 | #define DAC_DMAC_ID_EMPTY_1 73
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| 77 | #define DAC_DMAC_ID_EMPTY_LSB 72
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| 78 | #define DAC_DMAC_ID_EMPTY_MSB 73
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| 79 | #define DAC_DMAC_ID_EMPTY_SIZE 2
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| 80 | #define DAC_DMAC_ID_RESRDY_0 74
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| 81 | #define DAC_DMAC_ID_RESRDY_1 75
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| 82 | #define DAC_DMAC_ID_RESRDY_LSB 74
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| 83 | #define DAC_DMAC_ID_RESRDY_MSB 75
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| 84 | #define DAC_DMAC_ID_RESRDY_SIZE 2
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| 85 | #define DAC_GCLK_ID 42 // Index of Generic Clock
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| 86 | #define DAC_STEP 7 // Number of steps to reach full scale
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| 87 |
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| 88 | #endif /* _SAME54_DAC_INSTANCE_ */
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