Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for SUPC |
| 5 | * |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 6 | * Copyright (c) 2019 Microchip Technology Inc.
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_SUPC_COMPONENT_ |
| 31 | #define _SAME54_SUPC_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR SUPC */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_SUPC Supply Controller */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define SUPC_U2407 |
| 40 | #define REV_SUPC 0x110 |
| 41 | |
| 42 | /* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| 47 | uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| 48 | uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 49 | uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 50 | uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| 51 | uint32_t :1; /*!< bit: 9 Reserved */ |
| 52 | uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| 53 | uint32_t :21; /*!< bit: 11..31 Reserved */ |
| 54 | } bit; /*!< Structure used for bit access */ |
| 55 | uint32_t reg; /*!< Type used for register access */ |
| 56 | } SUPC_INTENCLR_Type; |
| 57 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 58 | |
| 59 | #define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */ |
| 60 | #define SUPC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */ |
| 61 | |
| 62 | #define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */ |
| 63 | #define SUPC_INTENCLR_BOD33RDY (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos) |
| 64 | #define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */ |
| 65 | #define SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos) |
| 66 | #define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */ |
| 67 | #define SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos) |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 68 | #define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */ |
| 69 | #define SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos) |
| 70 | #define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */ |
| 71 | #define SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos) |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 72 | #define SUPC_INTENCLR_MASK _U_(0x00000507) /**< \brief (SUPC_INTENCLR) MASK Register */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 73 | |
| 74 | /* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ |
| 75 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 76 | typedef union { |
| 77 | struct { |
| 78 | uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| 79 | uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| 80 | uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 81 | uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 82 | uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| 83 | uint32_t :1; /*!< bit: 9 Reserved */ |
| 84 | uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| 85 | uint32_t :21; /*!< bit: 11..31 Reserved */ |
| 86 | } bit; /*!< Structure used for bit access */ |
| 87 | uint32_t reg; /*!< Type used for register access */ |
| 88 | } SUPC_INTENSET_Type; |
| 89 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 90 | |
| 91 | #define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */ |
| 92 | #define SUPC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */ |
| 93 | |
| 94 | #define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */ |
| 95 | #define SUPC_INTENSET_BOD33RDY (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos) |
| 96 | #define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */ |
| 97 | #define SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos) |
| 98 | #define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */ |
| 99 | #define SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos) |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 100 | #define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */ |
| 101 | #define SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos) |
| 102 | #define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */ |
| 103 | #define SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos) |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 104 | #define SUPC_INTENSET_MASK _U_(0x00000507) /**< \brief (SUPC_INTENSET) MASK Register */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 105 | |
| 106 | /* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ |
| 107 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 108 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 109 | struct { |
| 110 | __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| 111 | __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| 112 | __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 113 | __I uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 114 | __I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| 115 | __I uint32_t :1; /*!< bit: 9 Reserved */ |
| 116 | __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| 117 | __I uint32_t :21; /*!< bit: 11..31 Reserved */ |
| 118 | } bit; /*!< Structure used for bit access */ |
| 119 | uint32_t reg; /*!< Type used for register access */ |
| 120 | } SUPC_INTFLAG_Type; |
| 121 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 122 | |
| 123 | #define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */ |
| 124 | #define SUPC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| 125 | |
| 126 | #define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */ |
| 127 | #define SUPC_INTFLAG_BOD33RDY (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos) |
| 128 | #define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */ |
| 129 | #define SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos) |
| 130 | #define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */ |
| 131 | #define SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos) |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 132 | #define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */ |
| 133 | #define SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos) |
| 134 | #define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */ |
| 135 | #define SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos) |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 136 | #define SUPC_INTFLAG_MASK _U_(0x00000507) /**< \brief (SUPC_INTFLAG) MASK Register */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 137 | |
| 138 | /* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ |
| 139 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 140 | typedef union { |
| 141 | struct { |
| 142 | uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| 143 | uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| 144 | uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 145 | uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 146 | uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| 147 | uint32_t :1; /*!< bit: 9 Reserved */ |
| 148 | uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| 149 | uint32_t :21; /*!< bit: 11..31 Reserved */ |
| 150 | } bit; /*!< Structure used for bit access */ |
| 151 | uint32_t reg; /*!< Type used for register access */ |
| 152 | } SUPC_STATUS_Type; |
| 153 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 154 | |
| 155 | #define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */ |
| 156 | #define SUPC_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */ |
| 157 | |
| 158 | #define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */ |
| 159 | #define SUPC_STATUS_BOD33RDY (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos) |
| 160 | #define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */ |
| 161 | #define SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos) |
| 162 | #define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */ |
| 163 | #define SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos) |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 164 | #define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */ |
| 165 | #define SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos) |
| 166 | #define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */ |
| 167 | #define SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos) |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 168 | #define SUPC_STATUS_MASK _U_(0x00000507) /**< \brief (SUPC_STATUS) MASK Register */
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 169 | |
| 170 | /* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ |
| 171 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 172 | typedef union { |
| 173 | struct { |
| 174 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 175 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
| 176 | uint32_t ACTION:2; /*!< bit: 2.. 3 Action when Threshold Crossed */ |
| 177 | uint32_t STDBYCFG:1; /*!< bit: 4 Configuration in Standby mode */ |
| 178 | uint32_t RUNSTDBY:1; /*!< bit: 5 Run in Standby mode */ |
| 179 | uint32_t RUNHIB:1; /*!< bit: 6 Run in Hibernate mode */ |
| 180 | uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */ |
| 181 | uint32_t HYST:4; /*!< bit: 8..11 Hysteresis value */ |
| 182 | uint32_t PSEL:3; /*!< bit: 12..14 Prescaler Select */ |
| 183 | uint32_t :1; /*!< bit: 15 Reserved */ |
| 184 | uint32_t LEVEL:8; /*!< bit: 16..23 Threshold Level for VDD */ |
| 185 | uint32_t VBATLEVEL:8; /*!< bit: 24..31 Threshold Level in battery backup sleep mode for VBAT */ |
| 186 | } bit; /*!< Structure used for bit access */ |
| 187 | uint32_t reg; /*!< Type used for register access */ |
| 188 | } SUPC_BOD33_Type; |
| 189 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 190 | |
| 191 | #define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */ |
| 192 | #define SUPC_BOD33_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */ |
| 193 | |
| 194 | #define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */ |
| 195 | #define SUPC_BOD33_ENABLE (_U_(0x1) << SUPC_BOD33_ENABLE_Pos) |
| 196 | #define SUPC_BOD33_ACTION_Pos 2 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */ |
| 197 | #define SUPC_BOD33_ACTION_Msk (_U_(0x3) << SUPC_BOD33_ACTION_Pos) |
| 198 | #define SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos)) |
| 199 | #define SUPC_BOD33_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD33) No action */ |
| 200 | #define SUPC_BOD33_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD33) The BOD33 generates a reset */ |
| 201 | #define SUPC_BOD33_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */ |
| 202 | #define SUPC_BOD33_ACTION_BKUP_Val _U_(0x3) /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */ |
| 203 | #define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos) |
| 204 | #define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos) |
| 205 | #define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos) |
| 206 | #define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos) |
| 207 | #define SUPC_BOD33_STDBYCFG_Pos 4 /**< \brief (SUPC_BOD33) Configuration in Standby mode */ |
| 208 | #define SUPC_BOD33_STDBYCFG (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos) |
| 209 | #define SUPC_BOD33_RUNSTDBY_Pos 5 /**< \brief (SUPC_BOD33) Run in Standby mode */ |
| 210 | #define SUPC_BOD33_RUNSTDBY (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos) |
| 211 | #define SUPC_BOD33_RUNHIB_Pos 6 /**< \brief (SUPC_BOD33) Run in Hibernate mode */ |
| 212 | #define SUPC_BOD33_RUNHIB (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos) |
| 213 | #define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Run in Backup mode */ |
| 214 | #define SUPC_BOD33_RUNBKUP (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos) |
| 215 | #define SUPC_BOD33_HYST_Pos 8 /**< \brief (SUPC_BOD33) Hysteresis value */ |
| 216 | #define SUPC_BOD33_HYST_Msk (_U_(0xF) << SUPC_BOD33_HYST_Pos) |
| 217 | #define SUPC_BOD33_HYST(value) (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos)) |
| 218 | #define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */ |
| 219 | #define SUPC_BOD33_PSEL_Msk (_U_(0x7) << SUPC_BOD33_PSEL_Pos) |
| 220 | #define SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos)) |
| 221 | #define SUPC_BOD33_PSEL_NODIV_Val _U_(0x0) /**< \brief (SUPC_BOD33) Not divided */ |
| 222 | #define SUPC_BOD33_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD33) Divide clock by 4 */ |
| 223 | #define SUPC_BOD33_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD33) Divide clock by 8 */ |
| 224 | #define SUPC_BOD33_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD33) Divide clock by 16 */ |
| 225 | #define SUPC_BOD33_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD33) Divide clock by 32 */ |
| 226 | #define SUPC_BOD33_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD33) Divide clock by 64 */ |
| 227 | #define SUPC_BOD33_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD33) Divide clock by 128 */ |
| 228 | #define SUPC_BOD33_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD33) Divide clock by 256 */ |
| 229 | #define SUPC_BOD33_PSEL_NODIV (SUPC_BOD33_PSEL_NODIV_Val << SUPC_BOD33_PSEL_Pos) |
| 230 | #define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos) |
| 231 | #define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos) |
| 232 | #define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos) |
| 233 | #define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos) |
| 234 | #define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos) |
| 235 | #define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos) |
| 236 | #define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos) |
| 237 | #define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */ |
| 238 | #define SUPC_BOD33_LEVEL_Msk (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos) |
| 239 | #define SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos)) |
| 240 | #define SUPC_BOD33_VBATLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT */ |
| 241 | #define SUPC_BOD33_VBATLEVEL_Msk (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos) |
| 242 | #define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos)) |
| 243 | #define SUPC_BOD33_MASK _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */ |
| 244 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 245 | /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ |
| 246 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 247 | typedef union { |
| 248 | struct { |
| 249 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 250 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
| 251 | uint32_t SEL:1; /*!< bit: 2 Voltage Regulator Selection */ |
| 252 | uint32_t :4; /*!< bit: 3.. 6 Reserved */ |
| 253 | uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */ |
| 254 | uint32_t :8; /*!< bit: 8..15 Reserved */ |
| 255 | uint32_t VSEN:1; /*!< bit: 16 Voltage Scaling Enable */ |
| 256 | uint32_t :7; /*!< bit: 17..23 Reserved */ |
| 257 | uint32_t VSPER:3; /*!< bit: 24..26 Voltage Scaling Period */ |
| 258 | uint32_t :5; /*!< bit: 27..31 Reserved */ |
| 259 | } bit; /*!< Structure used for bit access */ |
| 260 | uint32_t reg; /*!< Type used for register access */ |
| 261 | } SUPC_VREG_Type; |
| 262 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 263 | |
| 264 | #define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */ |
| 265 | #define SUPC_VREG_RESETVALUE _U_(0x00000002) /**< \brief (SUPC_VREG reset_value) VREG Control */ |
| 266 | |
| 267 | #define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */ |
| 268 | #define SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos) |
| 269 | #define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection */ |
| 270 | #define SUPC_VREG_SEL (_U_(0x1) << SUPC_VREG_SEL_Pos) |
| 271 | #define SUPC_VREG_SEL_LDO_Val _U_(0x0) /**< \brief (SUPC_VREG) LDO selection */ |
| 272 | #define SUPC_VREG_SEL_BUCK_Val _U_(0x1) /**< \brief (SUPC_VREG) Buck selection */ |
| 273 | #define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos) |
| 274 | #define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos) |
| 275 | #define SUPC_VREG_RUNBKUP_Pos 7 /**< \brief (SUPC_VREG) Run in Backup mode */ |
| 276 | #define SUPC_VREG_RUNBKUP (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos) |
| 277 | #define SUPC_VREG_VSEN_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Enable */ |
| 278 | #define SUPC_VREG_VSEN (_U_(0x1) << SUPC_VREG_VSEN_Pos) |
| 279 | #define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */ |
| 280 | #define SUPC_VREG_VSPER_Msk (_U_(0x7) << SUPC_VREG_VSPER_Pos) |
| 281 | #define SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos)) |
| 282 | #define SUPC_VREG_MASK _U_(0x07010086) /**< \brief (SUPC_VREG) MASK Register */ |
| 283 | |
| 284 | /* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ |
| 285 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 286 | typedef union { |
| 287 | struct { |
| 288 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 289 | uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */ |
| 290 | uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ |
| 291 | uint32_t TSSEL:1; /*!< bit: 3 Temperature Sensor Selection */ |
| 292 | uint32_t :2; /*!< bit: 4.. 5 Reserved */ |
| 293 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ |
| 294 | uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ |
| 295 | uint32_t :8; /*!< bit: 8..15 Reserved */ |
| 296 | uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ |
| 297 | uint32_t :12; /*!< bit: 20..31 Reserved */ |
| 298 | } bit; /*!< Structure used for bit access */ |
| 299 | uint32_t reg; /*!< Type used for register access */ |
| 300 | } SUPC_VREF_Type; |
| 301 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 302 | |
| 303 | #define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */ |
| 304 | #define SUPC_VREF_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */ |
| 305 | |
| 306 | #define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */ |
| 307 | #define SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos) |
| 308 | #define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */ |
| 309 | #define SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos) |
| 310 | #define SUPC_VREF_TSSEL_Pos 3 /**< \brief (SUPC_VREF) Temperature Sensor Selection */ |
| 311 | #define SUPC_VREF_TSSEL (_U_(0x1) << SUPC_VREF_TSSEL_Pos) |
| 312 | #define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */ |
| 313 | #define SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos) |
| 314 | #define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */ |
| 315 | #define SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos) |
| 316 | #define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */ |
| 317 | #define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos) |
| 318 | #define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos)) |
| 319 | #define SUPC_VREF_SEL_1V0_Val _U_(0x0) /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */ |
| 320 | #define SUPC_VREF_SEL_1V1_Val _U_(0x1) /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */ |
| 321 | #define SUPC_VREF_SEL_1V2_Val _U_(0x2) /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */ |
| 322 | #define SUPC_VREF_SEL_1V25_Val _U_(0x3) /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */ |
| 323 | #define SUPC_VREF_SEL_2V0_Val _U_(0x4) /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */ |
| 324 | #define SUPC_VREF_SEL_2V2_Val _U_(0x5) /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */ |
| 325 | #define SUPC_VREF_SEL_2V4_Val _U_(0x6) /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */ |
| 326 | #define SUPC_VREF_SEL_2V5_Val _U_(0x7) /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */ |
| 327 | #define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos) |
| 328 | #define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos) |
| 329 | #define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos) |
| 330 | #define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos) |
| 331 | #define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos) |
| 332 | #define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos) |
| 333 | #define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos) |
| 334 | #define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos) |
| 335 | #define SUPC_VREF_MASK _U_(0x000F00CE) /**< \brief (SUPC_VREF) MASK Register */ |
| 336 | |
| 337 | /* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */ |
| 338 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 339 | typedef union { |
| 340 | struct { |
| 341 | uint32_t CONF:1; /*!< bit: 0 Battery Backup Configuration */ |
| 342 | uint32_t :1; /*!< bit: 1 Reserved */ |
| 343 | uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */ |
| 344 | uint32_t :29; /*!< bit: 3..31 Reserved */ |
| 345 | } bit; /*!< Structure used for bit access */ |
| 346 | uint32_t reg; /*!< Type used for register access */ |
| 347 | } SUPC_BBPS_Type; |
| 348 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 349 | |
| 350 | #define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */ |
| 351 | #define SUPC_BBPS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */ |
| 352 | |
| 353 | #define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */ |
| 354 | #define SUPC_BBPS_CONF (_U_(0x1) << SUPC_BBPS_CONF_Pos) |
| 355 | #define SUPC_BBPS_CONF_BOD33_Val _U_(0x0) /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */ |
| 356 | #define SUPC_BBPS_CONF_FORCED_Val _U_(0x1) /**< \brief (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */ |
| 357 | #define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos) |
| 358 | #define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos) |
| 359 | #define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */ |
| 360 | #define SUPC_BBPS_WAKEEN (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos) |
| 361 | #define SUPC_BBPS_MASK _U_(0x00000005) /**< \brief (SUPC_BBPS) MASK Register */ |
| 362 | |
| 363 | /* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */ |
| 364 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 365 | typedef union { |
| 366 | struct { |
| 367 | uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */ |
| 368 | uint32_t :6; /*!< bit: 2.. 7 Reserved */ |
| 369 | uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */ |
| 370 | uint32_t :6; /*!< bit: 10..15 Reserved */ |
| 371 | uint32_t SET:2; /*!< bit: 16..17 Set Output */ |
| 372 | uint32_t :6; /*!< bit: 18..23 Reserved */ |
| 373 | uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */ |
| 374 | uint32_t :6; /*!< bit: 26..31 Reserved */ |
| 375 | } bit; /*!< Structure used for bit access */ |
| 376 | uint32_t reg; /*!< Type used for register access */ |
| 377 | } SUPC_BKOUT_Type; |
| 378 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 379 | |
| 380 | #define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */ |
| 381 | #define SUPC_BKOUT_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */ |
| 382 | |
| 383 | #define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */ |
| 384 | #define SUPC_BKOUT_EN_Msk (_U_(0x3) << SUPC_BKOUT_EN_Pos) |
| 385 | #define SUPC_BKOUT_EN(value) (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos)) |
| 386 | #define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */ |
| 387 | #define SUPC_BKOUT_CLR_Msk (_U_(0x3) << SUPC_BKOUT_CLR_Pos) |
| 388 | #define SUPC_BKOUT_CLR(value) (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos)) |
| 389 | #define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */ |
| 390 | #define SUPC_BKOUT_SET_Msk (_U_(0x3) << SUPC_BKOUT_SET_Pos) |
| 391 | #define SUPC_BKOUT_SET(value) (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos)) |
| 392 | #define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */ |
| 393 | #define SUPC_BKOUT_RTCTGL_Msk (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos) |
| 394 | #define SUPC_BKOUT_RTCTGL(value) (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos)) |
| 395 | #define SUPC_BKOUT_MASK _U_(0x03030303) /**< \brief (SUPC_BKOUT) MASK Register */ |
| 396 | |
| 397 | /* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */ |
| 398 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 399 | typedef union { |
| 400 | struct { |
| 401 | uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */ |
| 402 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 403 | } bit; /*!< Structure used for bit access */ |
| 404 | uint32_t reg; /*!< Type used for register access */ |
| 405 | } SUPC_BKIN_Type; |
| 406 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 407 | |
| 408 | #define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */ |
| 409 | #define SUPC_BKIN_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKIN reset_value) Backup Input Control */ |
| 410 | |
| 411 | #define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */ |
| 412 | #define SUPC_BKIN_BKIN_Msk (_U_(0xFF) << SUPC_BKIN_BKIN_Pos) |
| 413 | #define SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos)) |
| 414 | #define SUPC_BKIN_MASK _U_(0x000000FF) /**< \brief (SUPC_BKIN) MASK Register */ |
| 415 | |
| 416 | /** \brief SUPC hardware registers */ |
| 417 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 418 | typedef struct { |
| 419 | __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ |
| 420 | __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ |
| 421 | __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ |
| 422 | __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ |
| 423 | __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */ |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 424 | RoReg8 Reserved1[0x4];
|
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 425 | __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ |
| 426 | __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ |
| 427 | __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */ |
| 428 | __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */ |
| 429 | __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */ |
| 430 | } Supc; |
| 431 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 432 | |
| 433 | /*@}*/ |
| 434 | |
| 435 | #endif /* _SAME54_SUPC_COMPONENT_ */ |