Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for GMAC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_GMAC_COMPONENT_
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| 31 | #define _SAME54_GMAC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR GMAC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_GMAC Ethernet MAC */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define GMAC_U2005
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| 40 | #define REV_GMAC 0x100
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| 41 |
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| 42 | /* -------- GMAC_NCR : (GMAC Offset: 0x000) (R/W 32) Network Control Register -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint32_t :1; /*!< bit: 0 Reserved */
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| 47 | uint32_t LBL:1; /*!< bit: 1 Loop Back Local */
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| 48 | uint32_t RXEN:1; /*!< bit: 2 Receive Enable */
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| 49 | uint32_t TXEN:1; /*!< bit: 3 Transmit Enable */
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| 50 | uint32_t MPE:1; /*!< bit: 4 Management Port Enable */
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| 51 | uint32_t CLRSTAT:1; /*!< bit: 5 Clear Statistics Registers */
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| 52 | uint32_t INCSTAT:1; /*!< bit: 6 Increment Statistics Registers */
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| 53 | uint32_t WESTAT:1; /*!< bit: 7 Write Enable for Statistics Registers */
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| 54 | uint32_t BP:1; /*!< bit: 8 Back pressure */
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| 55 | uint32_t TSTART:1; /*!< bit: 9 Start Transmission */
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| 56 | uint32_t THALT:1; /*!< bit: 10 Transmit Halt */
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| 57 | uint32_t TXPF:1; /*!< bit: 11 Transmit Pause Frame */
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| 58 | uint32_t TXZQPF:1; /*!< bit: 12 Transmit Zero Quantum Pause Frame */
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| 59 | uint32_t :2; /*!< bit: 13..14 Reserved */
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| 60 | uint32_t SRTSM:1; /*!< bit: 15 Store Receive Time Stamp to Memory */
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| 61 | uint32_t ENPBPR:1; /*!< bit: 16 Enable PFC Priority-based Pause Reception */
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| 62 | uint32_t TXPBPF:1; /*!< bit: 17 Transmit PFC Priority-based Pause Frame */
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| 63 | uint32_t FNP:1; /*!< bit: 18 Flush Next Packet */
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| 64 | uint32_t LPI:1; /*!< bit: 19 Low Power Idle Enable */
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| 65 | uint32_t :12; /*!< bit: 20..31 Reserved */
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| 66 | } bit; /*!< Structure used for bit access */
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| 67 | uint32_t reg; /*!< Type used for register access */
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| 68 | } GMAC_NCR_Type;
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| 69 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 70 |
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| 71 | #define GMAC_NCR_OFFSET 0x000 /**< \brief (GMAC_NCR offset) Network Control Register */
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| 72 | #define GMAC_NCR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NCR reset_value) Network Control Register */
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| 73 |
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| 74 | #define GMAC_NCR_LBL_Pos 1 /**< \brief (GMAC_NCR) Loop Back Local */
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| 75 | #define GMAC_NCR_LBL (_U_(0x1) << GMAC_NCR_LBL_Pos)
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| 76 | #define GMAC_NCR_RXEN_Pos 2 /**< \brief (GMAC_NCR) Receive Enable */
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| 77 | #define GMAC_NCR_RXEN (_U_(0x1) << GMAC_NCR_RXEN_Pos)
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| 78 | #define GMAC_NCR_TXEN_Pos 3 /**< \brief (GMAC_NCR) Transmit Enable */
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| 79 | #define GMAC_NCR_TXEN (_U_(0x1) << GMAC_NCR_TXEN_Pos)
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| 80 | #define GMAC_NCR_MPE_Pos 4 /**< \brief (GMAC_NCR) Management Port Enable */
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| 81 | #define GMAC_NCR_MPE (_U_(0x1) << GMAC_NCR_MPE_Pos)
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| 82 | #define GMAC_NCR_CLRSTAT_Pos 5 /**< \brief (GMAC_NCR) Clear Statistics Registers */
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| 83 | #define GMAC_NCR_CLRSTAT (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos)
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| 84 | #define GMAC_NCR_INCSTAT_Pos 6 /**< \brief (GMAC_NCR) Increment Statistics Registers */
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| 85 | #define GMAC_NCR_INCSTAT (_U_(0x1) << GMAC_NCR_INCSTAT_Pos)
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| 86 | #define GMAC_NCR_WESTAT_Pos 7 /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */
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| 87 | #define GMAC_NCR_WESTAT (_U_(0x1) << GMAC_NCR_WESTAT_Pos)
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| 88 | #define GMAC_NCR_BP_Pos 8 /**< \brief (GMAC_NCR) Back pressure */
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| 89 | #define GMAC_NCR_BP (_U_(0x1) << GMAC_NCR_BP_Pos)
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| 90 | #define GMAC_NCR_TSTART_Pos 9 /**< \brief (GMAC_NCR) Start Transmission */
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| 91 | #define GMAC_NCR_TSTART (_U_(0x1) << GMAC_NCR_TSTART_Pos)
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| 92 | #define GMAC_NCR_THALT_Pos 10 /**< \brief (GMAC_NCR) Transmit Halt */
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| 93 | #define GMAC_NCR_THALT (_U_(0x1) << GMAC_NCR_THALT_Pos)
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| 94 | #define GMAC_NCR_TXPF_Pos 11 /**< \brief (GMAC_NCR) Transmit Pause Frame */
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| 95 | #define GMAC_NCR_TXPF (_U_(0x1) << GMAC_NCR_TXPF_Pos)
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| 96 | #define GMAC_NCR_TXZQPF_Pos 12 /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */
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| 97 | #define GMAC_NCR_TXZQPF (_U_(0x1) << GMAC_NCR_TXZQPF_Pos)
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| 98 | #define GMAC_NCR_SRTSM_Pos 15 /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */
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| 99 | #define GMAC_NCR_SRTSM (_U_(0x1) << GMAC_NCR_SRTSM_Pos)
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| 100 | #define GMAC_NCR_ENPBPR_Pos 16 /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */
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| 101 | #define GMAC_NCR_ENPBPR (_U_(0x1) << GMAC_NCR_ENPBPR_Pos)
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| 102 | #define GMAC_NCR_TXPBPF_Pos 17 /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */
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| 103 | #define GMAC_NCR_TXPBPF (_U_(0x1) << GMAC_NCR_TXPBPF_Pos)
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| 104 | #define GMAC_NCR_FNP_Pos 18 /**< \brief (GMAC_NCR) Flush Next Packet */
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| 105 | #define GMAC_NCR_FNP (_U_(0x1) << GMAC_NCR_FNP_Pos)
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| 106 | #define GMAC_NCR_LPI_Pos 19 /**< \brief (GMAC_NCR) Low Power Idle Enable */
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| 107 | #define GMAC_NCR_LPI (_U_(0x1) << GMAC_NCR_LPI_Pos)
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| 108 | #define GMAC_NCR_MASK _U_(0x000F9FFE) /**< \brief (GMAC_NCR) MASK Register */
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| 109 |
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| 110 | /* -------- GMAC_NCFGR : (GMAC Offset: 0x004) (R/W 32) Network Configuration Register -------- */
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| 111 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 112 | typedef union {
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| 113 | struct {
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| 114 | uint32_t SPD:1; /*!< bit: 0 Speed */
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| 115 | uint32_t FD:1; /*!< bit: 1 Full Duplex */
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| 116 | uint32_t DNVLAN:1; /*!< bit: 2 Discard Non-VLAN FRAMES */
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| 117 | uint32_t JFRAME:1; /*!< bit: 3 Jumbo Frame Size */
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| 118 | uint32_t CAF:1; /*!< bit: 4 Copy All Frames */
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| 119 | uint32_t NBC:1; /*!< bit: 5 No Broadcast */
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| 120 | uint32_t MTIHEN:1; /*!< bit: 6 Multicast Hash Enable */
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| 121 | uint32_t UNIHEN:1; /*!< bit: 7 Unicast Hash Enable */
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| 122 | uint32_t MAXFS:1; /*!< bit: 8 1536 Maximum Frame Size */
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| 123 | uint32_t :3; /*!< bit: 9..11 Reserved */
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| 124 | uint32_t RTY:1; /*!< bit: 12 Retry Test */
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| 125 | uint32_t PEN:1; /*!< bit: 13 Pause Enable */
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| 126 | uint32_t RXBUFO:2; /*!< bit: 14..15 Receive Buffer Offset */
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| 127 | uint32_t LFERD:1; /*!< bit: 16 Length Field Error Frame Discard */
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| 128 | uint32_t RFCS:1; /*!< bit: 17 Remove FCS */
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| 129 | uint32_t CLK:3; /*!< bit: 18..20 MDC CLock Division */
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| 130 | uint32_t DBW:2; /*!< bit: 21..22 Data Bus Width */
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| 131 | uint32_t DCPF:1; /*!< bit: 23 Disable Copy of Pause Frames */
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| 132 | uint32_t RXCOEN:1; /*!< bit: 24 Receive Checksum Offload Enable */
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| 133 | uint32_t EFRHD:1; /*!< bit: 25 Enable Frames Received in Half Duplex */
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| 134 | uint32_t IRXFCS:1; /*!< bit: 26 Ignore RX FCS */
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| 135 | uint32_t :1; /*!< bit: 27 Reserved */
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| 136 | uint32_t IPGSEN:1; /*!< bit: 28 IP Stretch Enable */
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| 137 | uint32_t RXBP:1; /*!< bit: 29 Receive Bad Preamble */
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| 138 | uint32_t IRXER:1; /*!< bit: 30 Ignore IPG GRXER */
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| 139 | uint32_t :1; /*!< bit: 31 Reserved */
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| 140 | } bit; /*!< Structure used for bit access */
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| 141 | uint32_t reg; /*!< Type used for register access */
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| 142 | } GMAC_NCFGR_Type;
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| 143 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 144 |
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| 145 | #define GMAC_NCFGR_OFFSET 0x004 /**< \brief (GMAC_NCFGR offset) Network Configuration Register */
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| 146 | #define GMAC_NCFGR_RESETVALUE _U_(0x00080000) /**< \brief (GMAC_NCFGR reset_value) Network Configuration Register */
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| 147 |
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| 148 | #define GMAC_NCFGR_SPD_Pos 0 /**< \brief (GMAC_NCFGR) Speed */
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| 149 | #define GMAC_NCFGR_SPD (_U_(0x1) << GMAC_NCFGR_SPD_Pos)
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| 150 | #define GMAC_NCFGR_FD_Pos 1 /**< \brief (GMAC_NCFGR) Full Duplex */
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| 151 | #define GMAC_NCFGR_FD (_U_(0x1) << GMAC_NCFGR_FD_Pos)
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| 152 | #define GMAC_NCFGR_DNVLAN_Pos 2 /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */
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| 153 | #define GMAC_NCFGR_DNVLAN (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos)
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| 154 | #define GMAC_NCFGR_JFRAME_Pos 3 /**< \brief (GMAC_NCFGR) Jumbo Frame Size */
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| 155 | #define GMAC_NCFGR_JFRAME (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos)
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| 156 | #define GMAC_NCFGR_CAF_Pos 4 /**< \brief (GMAC_NCFGR) Copy All Frames */
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| 157 | #define GMAC_NCFGR_CAF (_U_(0x1) << GMAC_NCFGR_CAF_Pos)
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| 158 | #define GMAC_NCFGR_NBC_Pos 5 /**< \brief (GMAC_NCFGR) No Broadcast */
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| 159 | #define GMAC_NCFGR_NBC (_U_(0x1) << GMAC_NCFGR_NBC_Pos)
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| 160 | #define GMAC_NCFGR_MTIHEN_Pos 6 /**< \brief (GMAC_NCFGR) Multicast Hash Enable */
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| 161 | #define GMAC_NCFGR_MTIHEN (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos)
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| 162 | #define GMAC_NCFGR_UNIHEN_Pos 7 /**< \brief (GMAC_NCFGR) Unicast Hash Enable */
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| 163 | #define GMAC_NCFGR_UNIHEN (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos)
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| 164 | #define GMAC_NCFGR_MAXFS_Pos 8 /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */
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| 165 | #define GMAC_NCFGR_MAXFS (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos)
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| 166 | #define GMAC_NCFGR_RTY_Pos 12 /**< \brief (GMAC_NCFGR) Retry Test */
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| 167 | #define GMAC_NCFGR_RTY (_U_(0x1) << GMAC_NCFGR_RTY_Pos)
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| 168 | #define GMAC_NCFGR_PEN_Pos 13 /**< \brief (GMAC_NCFGR) Pause Enable */
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| 169 | #define GMAC_NCFGR_PEN (_U_(0x1) << GMAC_NCFGR_PEN_Pos)
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| 170 | #define GMAC_NCFGR_RXBUFO_Pos 14 /**< \brief (GMAC_NCFGR) Receive Buffer Offset */
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| 171 | #define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos)
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| 172 | #define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))
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| 173 | #define GMAC_NCFGR_LFERD_Pos 16 /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */
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| 174 | #define GMAC_NCFGR_LFERD (_U_(0x1) << GMAC_NCFGR_LFERD_Pos)
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| 175 | #define GMAC_NCFGR_RFCS_Pos 17 /**< \brief (GMAC_NCFGR) Remove FCS */
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| 176 | #define GMAC_NCFGR_RFCS (_U_(0x1) << GMAC_NCFGR_RFCS_Pos)
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| 177 | #define GMAC_NCFGR_CLK_Pos 18 /**< \brief (GMAC_NCFGR) MDC CLock Division */
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| 178 | #define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos)
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| 179 | #define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))
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| 180 | #define GMAC_NCFGR_DBW_Pos 21 /**< \brief (GMAC_NCFGR) Data Bus Width */
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| 181 | #define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos)
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| 182 | #define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))
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| 183 | #define GMAC_NCFGR_DCPF_Pos 23 /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */
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| 184 | #define GMAC_NCFGR_DCPF (_U_(0x1) << GMAC_NCFGR_DCPF_Pos)
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| 185 | #define GMAC_NCFGR_RXCOEN_Pos 24 /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */
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| 186 | #define GMAC_NCFGR_RXCOEN (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos)
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| 187 | #define GMAC_NCFGR_EFRHD_Pos 25 /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */
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| 188 | #define GMAC_NCFGR_EFRHD (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos)
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| 189 | #define GMAC_NCFGR_IRXFCS_Pos 26 /**< \brief (GMAC_NCFGR) Ignore RX FCS */
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| 190 | #define GMAC_NCFGR_IRXFCS (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos)
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| 191 | #define GMAC_NCFGR_IPGSEN_Pos 28 /**< \brief (GMAC_NCFGR) IP Stretch Enable */
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| 192 | #define GMAC_NCFGR_IPGSEN (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos)
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| 193 | #define GMAC_NCFGR_RXBP_Pos 29 /**< \brief (GMAC_NCFGR) Receive Bad Preamble */
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| 194 | #define GMAC_NCFGR_RXBP (_U_(0x1) << GMAC_NCFGR_RXBP_Pos)
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| 195 | #define GMAC_NCFGR_IRXER_Pos 30 /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */
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| 196 | #define GMAC_NCFGR_IRXER (_U_(0x1) << GMAC_NCFGR_IRXER_Pos)
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| 197 | #define GMAC_NCFGR_MASK _U_(0x77FFF1FF) /**< \brief (GMAC_NCFGR) MASK Register */
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| 198 |
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| 199 | /* -------- GMAC_NSR : (GMAC Offset: 0x008) (R/ 32) Network Status Register -------- */
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| 200 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 201 | typedef union {
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| 202 | struct {
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| 203 | uint32_t :1; /*!< bit: 0 Reserved */
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| 204 | uint32_t MDIO:1; /*!< bit: 1 MDIO Input Status */
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| 205 | uint32_t IDLE:1; /*!< bit: 2 PHY Management Logic Idle */
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| 206 | uint32_t :29; /*!< bit: 3..31 Reserved */
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| 207 | } bit; /*!< Structure used for bit access */
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| 208 | uint32_t reg; /*!< Type used for register access */
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| 209 | } GMAC_NSR_Type;
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| 210 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 211 |
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| 212 | #define GMAC_NSR_OFFSET 0x008 /**< \brief (GMAC_NSR offset) Network Status Register */
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| 213 | #define GMAC_NSR_RESETVALUE _U_(0x00000004) /**< \brief (GMAC_NSR reset_value) Network Status Register */
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| 214 |
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| 215 | #define GMAC_NSR_MDIO_Pos 1 /**< \brief (GMAC_NSR) MDIO Input Status */
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| 216 | #define GMAC_NSR_MDIO (_U_(0x1) << GMAC_NSR_MDIO_Pos)
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| 217 | #define GMAC_NSR_IDLE_Pos 2 /**< \brief (GMAC_NSR) PHY Management Logic Idle */
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| 218 | #define GMAC_NSR_IDLE (_U_(0x1) << GMAC_NSR_IDLE_Pos)
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| 219 | #define GMAC_NSR_MASK _U_(0x00000006) /**< \brief (GMAC_NSR) MASK Register */
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| 220 |
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| 221 | /* -------- GMAC_UR : (GMAC Offset: 0x00C) (R/W 32) User Register -------- */
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| 222 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 223 | typedef union {
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| 224 | struct {
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| 225 | uint32_t MII:1; /*!< bit: 0 MII Mode */
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| 226 | uint32_t :31; /*!< bit: 1..31 Reserved */
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| 227 | } bit; /*!< Structure used for bit access */
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| 228 | uint32_t reg; /*!< Type used for register access */
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| 229 | } GMAC_UR_Type;
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| 230 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 231 |
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| 232 | #define GMAC_UR_OFFSET 0x00C /**< \brief (GMAC_UR offset) User Register */
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| 233 | #define GMAC_UR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UR reset_value) User Register */
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| 234 |
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| 235 | #define GMAC_UR_MII_Pos 0 /**< \brief (GMAC_UR) MII Mode */
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| 236 | #define GMAC_UR_MII (_U_(0x1) << GMAC_UR_MII_Pos)
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| 237 | #define GMAC_UR_MASK _U_(0x00000001) /**< \brief (GMAC_UR) MASK Register */
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| 238 |
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| 239 | /* -------- GMAC_DCFGR : (GMAC Offset: 0x010) (R/W 32) DMA Configuration Register -------- */
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| 240 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 241 | typedef union {
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| 242 | struct {
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| 243 | uint32_t FBLDO:5; /*!< bit: 0.. 4 Fixed Burst Length for DMA Data Operations: */
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| 244 | uint32_t :1; /*!< bit: 5 Reserved */
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| 245 | uint32_t ESMA:1; /*!< bit: 6 Endian Swap Mode Enable for Management Descriptor Accesses */
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| 246 | uint32_t ESPA:1; /*!< bit: 7 Endian Swap Mode Enable for Packet Data Accesses */
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| 247 | uint32_t RXBMS:2; /*!< bit: 8.. 9 Receiver Packet Buffer Memory Size Select */
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| 248 | uint32_t TXPBMS:1; /*!< bit: 10 Transmitter Packet Buffer Memory Size Select */
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| 249 | uint32_t TXCOEN:1; /*!< bit: 11 Transmitter Checksum Generation Offload Enable */
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| 250 | uint32_t :4; /*!< bit: 12..15 Reserved */
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| 251 | uint32_t DRBS:8; /*!< bit: 16..23 DMA Receive Buffer Size */
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| 252 | uint32_t DDRP:1; /*!< bit: 24 DMA Discard Receive Packets */
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| 253 | uint32_t :7; /*!< bit: 25..31 Reserved */
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| 254 | } bit; /*!< Structure used for bit access */
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| 255 | uint32_t reg; /*!< Type used for register access */
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| 256 | } GMAC_DCFGR_Type;
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| 257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 258 |
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| 259 | #define GMAC_DCFGR_OFFSET 0x010 /**< \brief (GMAC_DCFGR offset) DMA Configuration Register */
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| 260 | #define GMAC_DCFGR_RESETVALUE _U_(0x00020704) /**< \brief (GMAC_DCFGR reset_value) DMA Configuration Register */
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| 261 |
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| 262 | #define GMAC_DCFGR_FBLDO_Pos 0 /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */
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| 263 | #define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos)
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| 264 | #define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))
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| 265 | #define GMAC_DCFGR_ESMA_Pos 6 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */
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| 266 | #define GMAC_DCFGR_ESMA (_U_(0x1) << GMAC_DCFGR_ESMA_Pos)
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| 267 | #define GMAC_DCFGR_ESPA_Pos 7 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */
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| 268 | #define GMAC_DCFGR_ESPA (_U_(0x1) << GMAC_DCFGR_ESPA_Pos)
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| 269 | #define GMAC_DCFGR_RXBMS_Pos 8 /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */
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| 270 | #define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos)
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| 271 | #define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))
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| 272 | #define GMAC_DCFGR_TXPBMS_Pos 10 /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */
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| 273 | #define GMAC_DCFGR_TXPBMS (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos)
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| 274 | #define GMAC_DCFGR_TXCOEN_Pos 11 /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */
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| 275 | #define GMAC_DCFGR_TXCOEN (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos)
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| 276 | #define GMAC_DCFGR_DRBS_Pos 16 /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */
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| 277 | #define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos)
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| 278 | #define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))
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| 279 | #define GMAC_DCFGR_DDRP_Pos 24 /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */
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| 280 | #define GMAC_DCFGR_DDRP (_U_(0x1) << GMAC_DCFGR_DDRP_Pos)
|
| 281 | #define GMAC_DCFGR_MASK _U_(0x01FF0FDF) /**< \brief (GMAC_DCFGR) MASK Register */
|
| 282 |
|
| 283 | /* -------- GMAC_TSR : (GMAC Offset: 0x014) (R/W 32) Transmit Status Register -------- */
|
| 284 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 285 | typedef union {
|
| 286 | struct {
|
| 287 | uint32_t UBR:1; /*!< bit: 0 Used Bit Read */
|
| 288 | uint32_t COL:1; /*!< bit: 1 Collision Occurred */
|
| 289 | uint32_t RLE:1; /*!< bit: 2 Retry Limit Exceeded */
|
| 290 | uint32_t TXGO:1; /*!< bit: 3 Transmit Go */
|
| 291 | uint32_t TFC:1; /*!< bit: 4 Transmit Frame Corruption Due to AHB Error */
|
| 292 | uint32_t TXCOMP:1; /*!< bit: 5 Transmit Complete */
|
| 293 | uint32_t UND:1; /*!< bit: 6 Transmit Underrun */
|
| 294 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 295 | uint32_t HRESP:1; /*!< bit: 8 HRESP Not OK */
|
| 296 | uint32_t :23; /*!< bit: 9..31 Reserved */
|
| 297 | } bit; /*!< Structure used for bit access */
|
| 298 | uint32_t reg; /*!< Type used for register access */
|
| 299 | } GMAC_TSR_Type;
|
| 300 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 301 |
|
| 302 | #define GMAC_TSR_OFFSET 0x014 /**< \brief (GMAC_TSR offset) Transmit Status Register */
|
| 303 | #define GMAC_TSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSR reset_value) Transmit Status Register */
|
| 304 |
|
| 305 | #define GMAC_TSR_UBR_Pos 0 /**< \brief (GMAC_TSR) Used Bit Read */
|
| 306 | #define GMAC_TSR_UBR (_U_(0x1) << GMAC_TSR_UBR_Pos)
|
| 307 | #define GMAC_TSR_COL_Pos 1 /**< \brief (GMAC_TSR) Collision Occurred */
|
| 308 | #define GMAC_TSR_COL (_U_(0x1) << GMAC_TSR_COL_Pos)
|
| 309 | #define GMAC_TSR_RLE_Pos 2 /**< \brief (GMAC_TSR) Retry Limit Exceeded */
|
| 310 | #define GMAC_TSR_RLE (_U_(0x1) << GMAC_TSR_RLE_Pos)
|
| 311 | #define GMAC_TSR_TXGO_Pos 3 /**< \brief (GMAC_TSR) Transmit Go */
|
| 312 | #define GMAC_TSR_TXGO (_U_(0x1) << GMAC_TSR_TXGO_Pos)
|
| 313 | #define GMAC_TSR_TFC_Pos 4 /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */
|
| 314 | #define GMAC_TSR_TFC (_U_(0x1) << GMAC_TSR_TFC_Pos)
|
| 315 | #define GMAC_TSR_TXCOMP_Pos 5 /**< \brief (GMAC_TSR) Transmit Complete */
|
| 316 | #define GMAC_TSR_TXCOMP (_U_(0x1) << GMAC_TSR_TXCOMP_Pos)
|
| 317 | #define GMAC_TSR_UND_Pos 6 /**< \brief (GMAC_TSR) Transmit Underrun */
|
| 318 | #define GMAC_TSR_UND (_U_(0x1) << GMAC_TSR_UND_Pos)
|
| 319 | #define GMAC_TSR_HRESP_Pos 8 /**< \brief (GMAC_TSR) HRESP Not OK */
|
| 320 | #define GMAC_TSR_HRESP (_U_(0x1) << GMAC_TSR_HRESP_Pos)
|
| 321 | #define GMAC_TSR_MASK _U_(0x0000017F) /**< \brief (GMAC_TSR) MASK Register */
|
| 322 |
|
| 323 | /* -------- GMAC_RBQB : (GMAC Offset: 0x018) (R/W 32) Receive Buffer Queue Base Address -------- */
|
| 324 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 325 | typedef union {
|
| 326 | struct {
|
| 327 | uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
| 328 | uint32_t ADDR:30; /*!< bit: 2..31 Receive Buffer Queue Base Address */
|
| 329 | } bit; /*!< Structure used for bit access */
|
| 330 | uint32_t reg; /*!< Type used for register access */
|
| 331 | } GMAC_RBQB_Type;
|
| 332 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 333 |
|
| 334 | #define GMAC_RBQB_OFFSET 0x018 /**< \brief (GMAC_RBQB offset) Receive Buffer Queue Base Address */
|
| 335 | #define GMAC_RBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RBQB reset_value) Receive Buffer Queue Base Address */
|
| 336 |
|
| 337 | #define GMAC_RBQB_ADDR_Pos 2 /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */
|
| 338 | #define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos)
|
| 339 | #define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))
|
| 340 | #define GMAC_RBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_RBQB) MASK Register */
|
| 341 |
|
| 342 | /* -------- GMAC_TBQB : (GMAC Offset: 0x01C) (R/W 32) Transmit Buffer Queue Base Address -------- */
|
| 343 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 344 | typedef union {
|
| 345 | struct {
|
| 346 | uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
| 347 | uint32_t ADDR:30; /*!< bit: 2..31 Transmit Buffer Queue Base Address */
|
| 348 | } bit; /*!< Structure used for bit access */
|
| 349 | uint32_t reg; /*!< Type used for register access */
|
| 350 | } GMAC_TBQB_Type;
|
| 351 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 352 |
|
| 353 | #define GMAC_TBQB_OFFSET 0x01C /**< \brief (GMAC_TBQB offset) Transmit Buffer Queue Base Address */
|
| 354 | #define GMAC_TBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBQB reset_value) Transmit Buffer Queue Base Address */
|
| 355 |
|
| 356 | #define GMAC_TBQB_ADDR_Pos 2 /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */
|
| 357 | #define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos)
|
| 358 | #define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))
|
| 359 | #define GMAC_TBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_TBQB) MASK Register */
|
| 360 |
|
| 361 | /* -------- GMAC_RSR : (GMAC Offset: 0x020) (R/W 32) Receive Status Register -------- */
|
| 362 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 363 | typedef union {
|
| 364 | struct {
|
| 365 | uint32_t BNA:1; /*!< bit: 0 Buffer Not Available */
|
| 366 | uint32_t REC:1; /*!< bit: 1 Frame Received */
|
| 367 | uint32_t RXOVR:1; /*!< bit: 2 Receive Overrun */
|
| 368 | uint32_t HNO:1; /*!< bit: 3 HRESP Not OK */
|
| 369 | uint32_t :28; /*!< bit: 4..31 Reserved */
|
| 370 | } bit; /*!< Structure used for bit access */
|
| 371 | uint32_t reg; /*!< Type used for register access */
|
| 372 | } GMAC_RSR_Type;
|
| 373 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 374 |
|
| 375 | #define GMAC_RSR_OFFSET 0x020 /**< \brief (GMAC_RSR offset) Receive Status Register */
|
| 376 | #define GMAC_RSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSR reset_value) Receive Status Register */
|
| 377 |
|
| 378 | #define GMAC_RSR_BNA_Pos 0 /**< \brief (GMAC_RSR) Buffer Not Available */
|
| 379 | #define GMAC_RSR_BNA (_U_(0x1) << GMAC_RSR_BNA_Pos)
|
| 380 | #define GMAC_RSR_REC_Pos 1 /**< \brief (GMAC_RSR) Frame Received */
|
| 381 | #define GMAC_RSR_REC (_U_(0x1) << GMAC_RSR_REC_Pos)
|
| 382 | #define GMAC_RSR_RXOVR_Pos 2 /**< \brief (GMAC_RSR) Receive Overrun */
|
| 383 | #define GMAC_RSR_RXOVR (_U_(0x1) << GMAC_RSR_RXOVR_Pos)
|
| 384 | #define GMAC_RSR_HNO_Pos 3 /**< \brief (GMAC_RSR) HRESP Not OK */
|
| 385 | #define GMAC_RSR_HNO (_U_(0x1) << GMAC_RSR_HNO_Pos)
|
| 386 | #define GMAC_RSR_MASK _U_(0x0000000F) /**< \brief (GMAC_RSR) MASK Register */
|
| 387 |
|
| 388 | /* -------- GMAC_ISR : (GMAC Offset: 0x024) (R/W 32) Interrupt Status Register -------- */
|
| 389 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 390 | typedef union {
|
| 391 | struct {
|
| 392 | uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
|
| 393 | uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
|
| 394 | uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
|
| 395 | uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
|
| 396 | uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
|
| 397 | uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
|
| 398 | uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
|
| 399 | uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
|
| 400 | uint32_t :2; /*!< bit: 8.. 9 Reserved */
|
| 401 | uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
|
| 402 | uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
|
| 403 | uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
|
| 404 | uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
|
| 405 | uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
|
| 406 | uint32_t :3; /*!< bit: 15..17 Reserved */
|
| 407 | uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
|
| 408 | uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
|
| 409 | uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
|
| 410 | uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
|
| 411 | uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
|
| 412 | uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
|
| 413 | uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
|
| 414 | uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
|
| 415 | uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
|
| 416 | uint32_t :1; /*!< bit: 27 Reserved */
|
| 417 | uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
|
| 418 | uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
|
| 419 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 420 | } bit; /*!< Structure used for bit access */
|
| 421 | uint32_t reg; /*!< Type used for register access */
|
| 422 | } GMAC_ISR_Type;
|
| 423 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 424 |
|
| 425 | #define GMAC_ISR_OFFSET 0x024 /**< \brief (GMAC_ISR offset) Interrupt Status Register */
|
| 426 | #define GMAC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ISR reset_value) Interrupt Status Register */
|
| 427 |
|
| 428 | #define GMAC_ISR_MFS_Pos 0 /**< \brief (GMAC_ISR) Management Frame Sent */
|
| 429 | #define GMAC_ISR_MFS (_U_(0x1) << GMAC_ISR_MFS_Pos)
|
| 430 | #define GMAC_ISR_RCOMP_Pos 1 /**< \brief (GMAC_ISR) Receive Complete */
|
| 431 | #define GMAC_ISR_RCOMP (_U_(0x1) << GMAC_ISR_RCOMP_Pos)
|
| 432 | #define GMAC_ISR_RXUBR_Pos 2 /**< \brief (GMAC_ISR) RX Used Bit Read */
|
| 433 | #define GMAC_ISR_RXUBR (_U_(0x1) << GMAC_ISR_RXUBR_Pos)
|
| 434 | #define GMAC_ISR_TXUBR_Pos 3 /**< \brief (GMAC_ISR) TX Used Bit Read */
|
| 435 | #define GMAC_ISR_TXUBR (_U_(0x1) << GMAC_ISR_TXUBR_Pos)
|
| 436 | #define GMAC_ISR_TUR_Pos 4 /**< \brief (GMAC_ISR) Transmit Underrun */
|
| 437 | #define GMAC_ISR_TUR (_U_(0x1) << GMAC_ISR_TUR_Pos)
|
| 438 | #define GMAC_ISR_RLEX_Pos 5 /**< \brief (GMAC_ISR) Retry Limit Exceeded */
|
| 439 | #define GMAC_ISR_RLEX (_U_(0x1) << GMAC_ISR_RLEX_Pos)
|
| 440 | #define GMAC_ISR_TFC_Pos 6 /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */
|
| 441 | #define GMAC_ISR_TFC (_U_(0x1) << GMAC_ISR_TFC_Pos)
|
| 442 | #define GMAC_ISR_TCOMP_Pos 7 /**< \brief (GMAC_ISR) Transmit Complete */
|
| 443 | #define GMAC_ISR_TCOMP (_U_(0x1) << GMAC_ISR_TCOMP_Pos)
|
| 444 | #define GMAC_ISR_ROVR_Pos 10 /**< \brief (GMAC_ISR) Receive Overrun */
|
| 445 | #define GMAC_ISR_ROVR (_U_(0x1) << GMAC_ISR_ROVR_Pos)
|
| 446 | #define GMAC_ISR_HRESP_Pos 11 /**< \brief (GMAC_ISR) HRESP Not OK */
|
| 447 | #define GMAC_ISR_HRESP (_U_(0x1) << GMAC_ISR_HRESP_Pos)
|
| 448 | #define GMAC_ISR_PFNZ_Pos 12 /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */
|
| 449 | #define GMAC_ISR_PFNZ (_U_(0x1) << GMAC_ISR_PFNZ_Pos)
|
| 450 | #define GMAC_ISR_PTZ_Pos 13 /**< \brief (GMAC_ISR) Pause Time Zero */
|
| 451 | #define GMAC_ISR_PTZ (_U_(0x1) << GMAC_ISR_PTZ_Pos)
|
| 452 | #define GMAC_ISR_PFTR_Pos 14 /**< \brief (GMAC_ISR) Pause Frame Transmitted */
|
| 453 | #define GMAC_ISR_PFTR (_U_(0x1) << GMAC_ISR_PFTR_Pos)
|
| 454 | #define GMAC_ISR_DRQFR_Pos 18 /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */
|
| 455 | #define GMAC_ISR_DRQFR (_U_(0x1) << GMAC_ISR_DRQFR_Pos)
|
| 456 | #define GMAC_ISR_SFR_Pos 19 /**< \brief (GMAC_ISR) PTP Sync Frame Received */
|
| 457 | #define GMAC_ISR_SFR (_U_(0x1) << GMAC_ISR_SFR_Pos)
|
| 458 | #define GMAC_ISR_DRQFT_Pos 20 /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */
|
| 459 | #define GMAC_ISR_DRQFT (_U_(0x1) << GMAC_ISR_DRQFT_Pos)
|
| 460 | #define GMAC_ISR_SFT_Pos 21 /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */
|
| 461 | #define GMAC_ISR_SFT (_U_(0x1) << GMAC_ISR_SFT_Pos)
|
| 462 | #define GMAC_ISR_PDRQFR_Pos 22 /**< \brief (GMAC_ISR) PDelay Request Frame Received */
|
| 463 | #define GMAC_ISR_PDRQFR (_U_(0x1) << GMAC_ISR_PDRQFR_Pos)
|
| 464 | #define GMAC_ISR_PDRSFR_Pos 23 /**< \brief (GMAC_ISR) PDelay Response Frame Received */
|
| 465 | #define GMAC_ISR_PDRSFR (_U_(0x1) << GMAC_ISR_PDRSFR_Pos)
|
| 466 | #define GMAC_ISR_PDRQFT_Pos 24 /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */
|
| 467 | #define GMAC_ISR_PDRQFT (_U_(0x1) << GMAC_ISR_PDRQFT_Pos)
|
| 468 | #define GMAC_ISR_PDRSFT_Pos 25 /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */
|
| 469 | #define GMAC_ISR_PDRSFT (_U_(0x1) << GMAC_ISR_PDRSFT_Pos)
|
| 470 | #define GMAC_ISR_SRI_Pos 26 /**< \brief (GMAC_ISR) TSU Seconds Register Increment */
|
| 471 | #define GMAC_ISR_SRI (_U_(0x1) << GMAC_ISR_SRI_Pos)
|
| 472 | #define GMAC_ISR_WOL_Pos 28 /**< \brief (GMAC_ISR) Wake On LAN */
|
| 473 | #define GMAC_ISR_WOL (_U_(0x1) << GMAC_ISR_WOL_Pos)
|
| 474 | #define GMAC_ISR_TSUCMP_Pos 29 /**< \brief (GMAC_ISR) Tsu timer comparison */
|
| 475 | #define GMAC_ISR_TSUCMP (_U_(0x1) << GMAC_ISR_TSUCMP_Pos)
|
| 476 | #define GMAC_ISR_MASK _U_(0x37FC7CFF) /**< \brief (GMAC_ISR) MASK Register */
|
| 477 |
|
| 478 | /* -------- GMAC_IER : (GMAC Offset: 0x028) ( /W 32) Interrupt Enable Register -------- */
|
| 479 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 480 | typedef union {
|
| 481 | struct {
|
| 482 | uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
|
| 483 | uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
|
| 484 | uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
|
| 485 | uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
|
| 486 | uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
|
| 487 | uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
|
| 488 | uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
|
| 489 | uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
|
| 490 | uint32_t :2; /*!< bit: 8.. 9 Reserved */
|
| 491 | uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
|
| 492 | uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
|
| 493 | uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
|
| 494 | uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
|
| 495 | uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
|
| 496 | uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
|
| 497 | uint32_t :2; /*!< bit: 16..17 Reserved */
|
| 498 | uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
|
| 499 | uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
|
| 500 | uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
|
| 501 | uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
|
| 502 | uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
|
| 503 | uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
|
| 504 | uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
|
| 505 | uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
|
| 506 | uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
|
| 507 | uint32_t :1; /*!< bit: 27 Reserved */
|
| 508 | uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
|
| 509 | uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
|
| 510 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 511 | } bit; /*!< Structure used for bit access */
|
| 512 | uint32_t reg; /*!< Type used for register access */
|
| 513 | } GMAC_IER_Type;
|
| 514 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 515 |
|
| 516 | #define GMAC_IER_OFFSET 0x028 /**< \brief (GMAC_IER offset) Interrupt Enable Register */
|
| 517 |
|
| 518 | #define GMAC_IER_MFS_Pos 0 /**< \brief (GMAC_IER) Management Frame Sent */
|
| 519 | #define GMAC_IER_MFS (_U_(0x1) << GMAC_IER_MFS_Pos)
|
| 520 | #define GMAC_IER_RCOMP_Pos 1 /**< \brief (GMAC_IER) Receive Complete */
|
| 521 | #define GMAC_IER_RCOMP (_U_(0x1) << GMAC_IER_RCOMP_Pos)
|
| 522 | #define GMAC_IER_RXUBR_Pos 2 /**< \brief (GMAC_IER) RX Used Bit Read */
|
| 523 | #define GMAC_IER_RXUBR (_U_(0x1) << GMAC_IER_RXUBR_Pos)
|
| 524 | #define GMAC_IER_TXUBR_Pos 3 /**< \brief (GMAC_IER) TX Used Bit Read */
|
| 525 | #define GMAC_IER_TXUBR (_U_(0x1) << GMAC_IER_TXUBR_Pos)
|
| 526 | #define GMAC_IER_TUR_Pos 4 /**< \brief (GMAC_IER) Transmit Underrun */
|
| 527 | #define GMAC_IER_TUR (_U_(0x1) << GMAC_IER_TUR_Pos)
|
| 528 | #define GMAC_IER_RLEX_Pos 5 /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */
|
| 529 | #define GMAC_IER_RLEX (_U_(0x1) << GMAC_IER_RLEX_Pos)
|
| 530 | #define GMAC_IER_TFC_Pos 6 /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */
|
| 531 | #define GMAC_IER_TFC (_U_(0x1) << GMAC_IER_TFC_Pos)
|
| 532 | #define GMAC_IER_TCOMP_Pos 7 /**< \brief (GMAC_IER) Transmit Complete */
|
| 533 | #define GMAC_IER_TCOMP (_U_(0x1) << GMAC_IER_TCOMP_Pos)
|
| 534 | #define GMAC_IER_ROVR_Pos 10 /**< \brief (GMAC_IER) Receive Overrun */
|
| 535 | #define GMAC_IER_ROVR (_U_(0x1) << GMAC_IER_ROVR_Pos)
|
| 536 | #define GMAC_IER_HRESP_Pos 11 /**< \brief (GMAC_IER) HRESP Not OK */
|
| 537 | #define GMAC_IER_HRESP (_U_(0x1) << GMAC_IER_HRESP_Pos)
|
| 538 | #define GMAC_IER_PFNZ_Pos 12 /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */
|
| 539 | #define GMAC_IER_PFNZ (_U_(0x1) << GMAC_IER_PFNZ_Pos)
|
| 540 | #define GMAC_IER_PTZ_Pos 13 /**< \brief (GMAC_IER) Pause Time Zero */
|
| 541 | #define GMAC_IER_PTZ (_U_(0x1) << GMAC_IER_PTZ_Pos)
|
| 542 | #define GMAC_IER_PFTR_Pos 14 /**< \brief (GMAC_IER) Pause Frame Transmitted */
|
| 543 | #define GMAC_IER_PFTR (_U_(0x1) << GMAC_IER_PFTR_Pos)
|
| 544 | #define GMAC_IER_EXINT_Pos 15 /**< \brief (GMAC_IER) External Interrupt */
|
| 545 | #define GMAC_IER_EXINT (_U_(0x1) << GMAC_IER_EXINT_Pos)
|
| 546 | #define GMAC_IER_DRQFR_Pos 18 /**< \brief (GMAC_IER) PTP Delay Request Frame Received */
|
| 547 | #define GMAC_IER_DRQFR (_U_(0x1) << GMAC_IER_DRQFR_Pos)
|
| 548 | #define GMAC_IER_SFR_Pos 19 /**< \brief (GMAC_IER) PTP Sync Frame Received */
|
| 549 | #define GMAC_IER_SFR (_U_(0x1) << GMAC_IER_SFR_Pos)
|
| 550 | #define GMAC_IER_DRQFT_Pos 20 /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */
|
| 551 | #define GMAC_IER_DRQFT (_U_(0x1) << GMAC_IER_DRQFT_Pos)
|
| 552 | #define GMAC_IER_SFT_Pos 21 /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */
|
| 553 | #define GMAC_IER_SFT (_U_(0x1) << GMAC_IER_SFT_Pos)
|
| 554 | #define GMAC_IER_PDRQFR_Pos 22 /**< \brief (GMAC_IER) PDelay Request Frame Received */
|
| 555 | #define GMAC_IER_PDRQFR (_U_(0x1) << GMAC_IER_PDRQFR_Pos)
|
| 556 | #define GMAC_IER_PDRSFR_Pos 23 /**< \brief (GMAC_IER) PDelay Response Frame Received */
|
| 557 | #define GMAC_IER_PDRSFR (_U_(0x1) << GMAC_IER_PDRSFR_Pos)
|
| 558 | #define GMAC_IER_PDRQFT_Pos 24 /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */
|
| 559 | #define GMAC_IER_PDRQFT (_U_(0x1) << GMAC_IER_PDRQFT_Pos)
|
| 560 | #define GMAC_IER_PDRSFT_Pos 25 /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */
|
| 561 | #define GMAC_IER_PDRSFT (_U_(0x1) << GMAC_IER_PDRSFT_Pos)
|
| 562 | #define GMAC_IER_SRI_Pos 26 /**< \brief (GMAC_IER) TSU Seconds Register Increment */
|
| 563 | #define GMAC_IER_SRI (_U_(0x1) << GMAC_IER_SRI_Pos)
|
| 564 | #define GMAC_IER_WOL_Pos 28 /**< \brief (GMAC_IER) Wake On LAN */
|
| 565 | #define GMAC_IER_WOL (_U_(0x1) << GMAC_IER_WOL_Pos)
|
| 566 | #define GMAC_IER_TSUCMP_Pos 29 /**< \brief (GMAC_IER) Tsu timer comparison */
|
| 567 | #define GMAC_IER_TSUCMP (_U_(0x1) << GMAC_IER_TSUCMP_Pos)
|
| 568 | #define GMAC_IER_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IER) MASK Register */
|
| 569 |
|
| 570 | /* -------- GMAC_IDR : (GMAC Offset: 0x02C) ( /W 32) Interrupt Disable Register -------- */
|
| 571 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 572 | typedef union {
|
| 573 | struct {
|
| 574 | uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
|
| 575 | uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
|
| 576 | uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
|
| 577 | uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
|
| 578 | uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
|
| 579 | uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
|
| 580 | uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
|
| 581 | uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
|
| 582 | uint32_t :2; /*!< bit: 8.. 9 Reserved */
|
| 583 | uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
|
| 584 | uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
|
| 585 | uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
|
| 586 | uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
|
| 587 | uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
|
| 588 | uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
|
| 589 | uint32_t :2; /*!< bit: 16..17 Reserved */
|
| 590 | uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
|
| 591 | uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
|
| 592 | uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
|
| 593 | uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
|
| 594 | uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
|
| 595 | uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
|
| 596 | uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
|
| 597 | uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
|
| 598 | uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
|
| 599 | uint32_t :1; /*!< bit: 27 Reserved */
|
| 600 | uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
|
| 601 | uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
|
| 602 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 603 | } bit; /*!< Structure used for bit access */
|
| 604 | uint32_t reg; /*!< Type used for register access */
|
| 605 | } GMAC_IDR_Type;
|
| 606 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 607 |
|
| 608 | #define GMAC_IDR_OFFSET 0x02C /**< \brief (GMAC_IDR offset) Interrupt Disable Register */
|
| 609 |
|
| 610 | #define GMAC_IDR_MFS_Pos 0 /**< \brief (GMAC_IDR) Management Frame Sent */
|
| 611 | #define GMAC_IDR_MFS (_U_(0x1) << GMAC_IDR_MFS_Pos)
|
| 612 | #define GMAC_IDR_RCOMP_Pos 1 /**< \brief (GMAC_IDR) Receive Complete */
|
| 613 | #define GMAC_IDR_RCOMP (_U_(0x1) << GMAC_IDR_RCOMP_Pos)
|
| 614 | #define GMAC_IDR_RXUBR_Pos 2 /**< \brief (GMAC_IDR) RX Used Bit Read */
|
| 615 | #define GMAC_IDR_RXUBR (_U_(0x1) << GMAC_IDR_RXUBR_Pos)
|
| 616 | #define GMAC_IDR_TXUBR_Pos 3 /**< \brief (GMAC_IDR) TX Used Bit Read */
|
| 617 | #define GMAC_IDR_TXUBR (_U_(0x1) << GMAC_IDR_TXUBR_Pos)
|
| 618 | #define GMAC_IDR_TUR_Pos 4 /**< \brief (GMAC_IDR) Transmit Underrun */
|
| 619 | #define GMAC_IDR_TUR (_U_(0x1) << GMAC_IDR_TUR_Pos)
|
| 620 | #define GMAC_IDR_RLEX_Pos 5 /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */
|
| 621 | #define GMAC_IDR_RLEX (_U_(0x1) << GMAC_IDR_RLEX_Pos)
|
| 622 | #define GMAC_IDR_TFC_Pos 6 /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */
|
| 623 | #define GMAC_IDR_TFC (_U_(0x1) << GMAC_IDR_TFC_Pos)
|
| 624 | #define GMAC_IDR_TCOMP_Pos 7 /**< \brief (GMAC_IDR) Transmit Complete */
|
| 625 | #define GMAC_IDR_TCOMP (_U_(0x1) << GMAC_IDR_TCOMP_Pos)
|
| 626 | #define GMAC_IDR_ROVR_Pos 10 /**< \brief (GMAC_IDR) Receive Overrun */
|
| 627 | #define GMAC_IDR_ROVR (_U_(0x1) << GMAC_IDR_ROVR_Pos)
|
| 628 | #define GMAC_IDR_HRESP_Pos 11 /**< \brief (GMAC_IDR) HRESP Not OK */
|
| 629 | #define GMAC_IDR_HRESP (_U_(0x1) << GMAC_IDR_HRESP_Pos)
|
| 630 | #define GMAC_IDR_PFNZ_Pos 12 /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */
|
| 631 | #define GMAC_IDR_PFNZ (_U_(0x1) << GMAC_IDR_PFNZ_Pos)
|
| 632 | #define GMAC_IDR_PTZ_Pos 13 /**< \brief (GMAC_IDR) Pause Time Zero */
|
| 633 | #define GMAC_IDR_PTZ (_U_(0x1) << GMAC_IDR_PTZ_Pos)
|
| 634 | #define GMAC_IDR_PFTR_Pos 14 /**< \brief (GMAC_IDR) Pause Frame Transmitted */
|
| 635 | #define GMAC_IDR_PFTR (_U_(0x1) << GMAC_IDR_PFTR_Pos)
|
| 636 | #define GMAC_IDR_EXINT_Pos 15 /**< \brief (GMAC_IDR) External Interrupt */
|
| 637 | #define GMAC_IDR_EXINT (_U_(0x1) << GMAC_IDR_EXINT_Pos)
|
| 638 | #define GMAC_IDR_DRQFR_Pos 18 /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */
|
| 639 | #define GMAC_IDR_DRQFR (_U_(0x1) << GMAC_IDR_DRQFR_Pos)
|
| 640 | #define GMAC_IDR_SFR_Pos 19 /**< \brief (GMAC_IDR) PTP Sync Frame Received */
|
| 641 | #define GMAC_IDR_SFR (_U_(0x1) << GMAC_IDR_SFR_Pos)
|
| 642 | #define GMAC_IDR_DRQFT_Pos 20 /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */
|
| 643 | #define GMAC_IDR_DRQFT (_U_(0x1) << GMAC_IDR_DRQFT_Pos)
|
| 644 | #define GMAC_IDR_SFT_Pos 21 /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */
|
| 645 | #define GMAC_IDR_SFT (_U_(0x1) << GMAC_IDR_SFT_Pos)
|
| 646 | #define GMAC_IDR_PDRQFR_Pos 22 /**< \brief (GMAC_IDR) PDelay Request Frame Received */
|
| 647 | #define GMAC_IDR_PDRQFR (_U_(0x1) << GMAC_IDR_PDRQFR_Pos)
|
| 648 | #define GMAC_IDR_PDRSFR_Pos 23 /**< \brief (GMAC_IDR) PDelay Response Frame Received */
|
| 649 | #define GMAC_IDR_PDRSFR (_U_(0x1) << GMAC_IDR_PDRSFR_Pos)
|
| 650 | #define GMAC_IDR_PDRQFT_Pos 24 /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */
|
| 651 | #define GMAC_IDR_PDRQFT (_U_(0x1) << GMAC_IDR_PDRQFT_Pos)
|
| 652 | #define GMAC_IDR_PDRSFT_Pos 25 /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */
|
| 653 | #define GMAC_IDR_PDRSFT (_U_(0x1) << GMAC_IDR_PDRSFT_Pos)
|
| 654 | #define GMAC_IDR_SRI_Pos 26 /**< \brief (GMAC_IDR) TSU Seconds Register Increment */
|
| 655 | #define GMAC_IDR_SRI (_U_(0x1) << GMAC_IDR_SRI_Pos)
|
| 656 | #define GMAC_IDR_WOL_Pos 28 /**< \brief (GMAC_IDR) Wake On LAN */
|
| 657 | #define GMAC_IDR_WOL (_U_(0x1) << GMAC_IDR_WOL_Pos)
|
| 658 | #define GMAC_IDR_TSUCMP_Pos 29 /**< \brief (GMAC_IDR) Tsu timer comparison */
|
| 659 | #define GMAC_IDR_TSUCMP (_U_(0x1) << GMAC_IDR_TSUCMP_Pos)
|
| 660 | #define GMAC_IDR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IDR) MASK Register */
|
| 661 |
|
| 662 | /* -------- GMAC_IMR : (GMAC Offset: 0x030) (R/ 32) Interrupt Mask Register -------- */
|
| 663 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 664 | typedef union {
|
| 665 | struct {
|
| 666 | uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
|
| 667 | uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
|
| 668 | uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
|
| 669 | uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
|
| 670 | uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
|
| 671 | uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
|
| 672 | uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
|
| 673 | uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
|
| 674 | uint32_t :2; /*!< bit: 8.. 9 Reserved */
|
| 675 | uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
|
| 676 | uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
|
| 677 | uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
|
| 678 | uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
|
| 679 | uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
|
| 680 | uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
|
| 681 | uint32_t :2; /*!< bit: 16..17 Reserved */
|
| 682 | uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
|
| 683 | uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
|
| 684 | uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
|
| 685 | uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
|
| 686 | uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
|
| 687 | uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
|
| 688 | uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
|
| 689 | uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
|
| 690 | uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
|
| 691 | uint32_t :1; /*!< bit: 27 Reserved */
|
| 692 | uint32_t WOL:1; /*!< bit: 28 Wake On Lan */
|
| 693 | uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
|
| 694 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 695 | } bit; /*!< Structure used for bit access */
|
| 696 | uint32_t reg; /*!< Type used for register access */
|
| 697 | } GMAC_IMR_Type;
|
| 698 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 699 |
|
| 700 | #define GMAC_IMR_OFFSET 0x030 /**< \brief (GMAC_IMR offset) Interrupt Mask Register */
|
| 701 | #define GMAC_IMR_RESETVALUE _U_(0x3FFFFFFF) /**< \brief (GMAC_IMR reset_value) Interrupt Mask Register */
|
| 702 |
|
| 703 | #define GMAC_IMR_MFS_Pos 0 /**< \brief (GMAC_IMR) Management Frame Sent */
|
| 704 | #define GMAC_IMR_MFS (_U_(0x1) << GMAC_IMR_MFS_Pos)
|
| 705 | #define GMAC_IMR_RCOMP_Pos 1 /**< \brief (GMAC_IMR) Receive Complete */
|
| 706 | #define GMAC_IMR_RCOMP (_U_(0x1) << GMAC_IMR_RCOMP_Pos)
|
| 707 | #define GMAC_IMR_RXUBR_Pos 2 /**< \brief (GMAC_IMR) RX Used Bit Read */
|
| 708 | #define GMAC_IMR_RXUBR (_U_(0x1) << GMAC_IMR_RXUBR_Pos)
|
| 709 | #define GMAC_IMR_TXUBR_Pos 3 /**< \brief (GMAC_IMR) TX Used Bit Read */
|
| 710 | #define GMAC_IMR_TXUBR (_U_(0x1) << GMAC_IMR_TXUBR_Pos)
|
| 711 | #define GMAC_IMR_TUR_Pos 4 /**< \brief (GMAC_IMR) Transmit Underrun */
|
| 712 | #define GMAC_IMR_TUR (_U_(0x1) << GMAC_IMR_TUR_Pos)
|
| 713 | #define GMAC_IMR_RLEX_Pos 5 /**< \brief (GMAC_IMR) Retry Limit Exceeded */
|
| 714 | #define GMAC_IMR_RLEX (_U_(0x1) << GMAC_IMR_RLEX_Pos)
|
| 715 | #define GMAC_IMR_TFC_Pos 6 /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */
|
| 716 | #define GMAC_IMR_TFC (_U_(0x1) << GMAC_IMR_TFC_Pos)
|
| 717 | #define GMAC_IMR_TCOMP_Pos 7 /**< \brief (GMAC_IMR) Transmit Complete */
|
| 718 | #define GMAC_IMR_TCOMP (_U_(0x1) << GMAC_IMR_TCOMP_Pos)
|
| 719 | #define GMAC_IMR_ROVR_Pos 10 /**< \brief (GMAC_IMR) Receive Overrun */
|
| 720 | #define GMAC_IMR_ROVR (_U_(0x1) << GMAC_IMR_ROVR_Pos)
|
| 721 | #define GMAC_IMR_HRESP_Pos 11 /**< \brief (GMAC_IMR) HRESP Not OK */
|
| 722 | #define GMAC_IMR_HRESP (_U_(0x1) << GMAC_IMR_HRESP_Pos)
|
| 723 | #define GMAC_IMR_PFNZ_Pos 12 /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */
|
| 724 | #define GMAC_IMR_PFNZ (_U_(0x1) << GMAC_IMR_PFNZ_Pos)
|
| 725 | #define GMAC_IMR_PTZ_Pos 13 /**< \brief (GMAC_IMR) Pause Time Zero */
|
| 726 | #define GMAC_IMR_PTZ (_U_(0x1) << GMAC_IMR_PTZ_Pos)
|
| 727 | #define GMAC_IMR_PFTR_Pos 14 /**< \brief (GMAC_IMR) Pause Frame Transmitted */
|
| 728 | #define GMAC_IMR_PFTR (_U_(0x1) << GMAC_IMR_PFTR_Pos)
|
| 729 | #define GMAC_IMR_EXINT_Pos 15 /**< \brief (GMAC_IMR) External Interrupt */
|
| 730 | #define GMAC_IMR_EXINT (_U_(0x1) << GMAC_IMR_EXINT_Pos)
|
| 731 | #define GMAC_IMR_DRQFR_Pos 18 /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */
|
| 732 | #define GMAC_IMR_DRQFR (_U_(0x1) << GMAC_IMR_DRQFR_Pos)
|
| 733 | #define GMAC_IMR_SFR_Pos 19 /**< \brief (GMAC_IMR) PTP Sync Frame Received */
|
| 734 | #define GMAC_IMR_SFR (_U_(0x1) << GMAC_IMR_SFR_Pos)
|
| 735 | #define GMAC_IMR_DRQFT_Pos 20 /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */
|
| 736 | #define GMAC_IMR_DRQFT (_U_(0x1) << GMAC_IMR_DRQFT_Pos)
|
| 737 | #define GMAC_IMR_SFT_Pos 21 /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */
|
| 738 | #define GMAC_IMR_SFT (_U_(0x1) << GMAC_IMR_SFT_Pos)
|
| 739 | #define GMAC_IMR_PDRQFR_Pos 22 /**< \brief (GMAC_IMR) PDelay Request Frame Received */
|
| 740 | #define GMAC_IMR_PDRQFR (_U_(0x1) << GMAC_IMR_PDRQFR_Pos)
|
| 741 | #define GMAC_IMR_PDRSFR_Pos 23 /**< \brief (GMAC_IMR) PDelay Response Frame Received */
|
| 742 | #define GMAC_IMR_PDRSFR (_U_(0x1) << GMAC_IMR_PDRSFR_Pos)
|
| 743 | #define GMAC_IMR_PDRQFT_Pos 24 /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */
|
| 744 | #define GMAC_IMR_PDRQFT (_U_(0x1) << GMAC_IMR_PDRQFT_Pos)
|
| 745 | #define GMAC_IMR_PDRSFT_Pos 25 /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */
|
| 746 | #define GMAC_IMR_PDRSFT (_U_(0x1) << GMAC_IMR_PDRSFT_Pos)
|
| 747 | #define GMAC_IMR_SRI_Pos 26 /**< \brief (GMAC_IMR) TSU Seconds Register Increment */
|
| 748 | #define GMAC_IMR_SRI (_U_(0x1) << GMAC_IMR_SRI_Pos)
|
| 749 | #define GMAC_IMR_WOL_Pos 28 /**< \brief (GMAC_IMR) Wake On Lan */
|
| 750 | #define GMAC_IMR_WOL (_U_(0x1) << GMAC_IMR_WOL_Pos)
|
| 751 | #define GMAC_IMR_TSUCMP_Pos 29 /**< \brief (GMAC_IMR) Tsu timer comparison */
|
| 752 | #define GMAC_IMR_TSUCMP (_U_(0x1) << GMAC_IMR_TSUCMP_Pos)
|
| 753 | #define GMAC_IMR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IMR) MASK Register */
|
| 754 |
|
| 755 | /* -------- GMAC_MAN : (GMAC Offset: 0x034) (R/W 32) PHY Maintenance Register -------- */
|
| 756 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 757 | typedef union {
|
| 758 | struct {
|
| 759 | uint32_t DATA:16; /*!< bit: 0..15 PHY Data */
|
| 760 | uint32_t WTN:2; /*!< bit: 16..17 Write Ten */
|
| 761 | uint32_t REGA:5; /*!< bit: 18..22 Register Address */
|
| 762 | uint32_t PHYA:5; /*!< bit: 23..27 PHY Address */
|
| 763 | uint32_t OP:2; /*!< bit: 28..29 Operation */
|
| 764 | uint32_t CLTTO:1; /*!< bit: 30 Clause 22 Operation */
|
| 765 | uint32_t WZO:1; /*!< bit: 31 Write ZERO */
|
| 766 | } bit; /*!< Structure used for bit access */
|
| 767 | uint32_t reg; /*!< Type used for register access */
|
| 768 | } GMAC_MAN_Type;
|
| 769 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 770 |
|
| 771 | #define GMAC_MAN_OFFSET 0x034 /**< \brief (GMAC_MAN offset) PHY Maintenance Register */
|
| 772 | #define GMAC_MAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MAN reset_value) PHY Maintenance Register */
|
| 773 |
|
| 774 | #define GMAC_MAN_DATA_Pos 0 /**< \brief (GMAC_MAN) PHY Data */
|
| 775 | #define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos)
|
| 776 | #define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))
|
| 777 | #define GMAC_MAN_WTN_Pos 16 /**< \brief (GMAC_MAN) Write Ten */
|
| 778 | #define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos)
|
| 779 | #define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))
|
| 780 | #define GMAC_MAN_REGA_Pos 18 /**< \brief (GMAC_MAN) Register Address */
|
| 781 | #define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos)
|
| 782 | #define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))
|
| 783 | #define GMAC_MAN_PHYA_Pos 23 /**< \brief (GMAC_MAN) PHY Address */
|
| 784 | #define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos)
|
| 785 | #define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))
|
| 786 | #define GMAC_MAN_OP_Pos 28 /**< \brief (GMAC_MAN) Operation */
|
| 787 | #define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos)
|
| 788 | #define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))
|
| 789 | #define GMAC_MAN_CLTTO_Pos 30 /**< \brief (GMAC_MAN) Clause 22 Operation */
|
| 790 | #define GMAC_MAN_CLTTO (_U_(0x1) << GMAC_MAN_CLTTO_Pos)
|
| 791 | #define GMAC_MAN_WZO_Pos 31 /**< \brief (GMAC_MAN) Write ZERO */
|
| 792 | #define GMAC_MAN_WZO (_U_(0x1) << GMAC_MAN_WZO_Pos)
|
| 793 | #define GMAC_MAN_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MAN) MASK Register */
|
| 794 |
|
| 795 | /* -------- GMAC_RPQ : (GMAC Offset: 0x038) (R/ 32) Received Pause Quantum Register -------- */
|
| 796 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 797 | typedef union {
|
| 798 | struct {
|
| 799 | uint32_t RPQ:16; /*!< bit: 0..15 Received Pause Quantum */
|
| 800 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 801 | } bit; /*!< Structure used for bit access */
|
| 802 | uint32_t reg; /*!< Type used for register access */
|
| 803 | } GMAC_RPQ_Type;
|
| 804 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 805 |
|
| 806 | #define GMAC_RPQ_OFFSET 0x038 /**< \brief (GMAC_RPQ offset) Received Pause Quantum Register */
|
| 807 | #define GMAC_RPQ_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RPQ reset_value) Received Pause Quantum Register */
|
| 808 |
|
| 809 | #define GMAC_RPQ_RPQ_Pos 0 /**< \brief (GMAC_RPQ) Received Pause Quantum */
|
| 810 | #define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos)
|
| 811 | #define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos))
|
| 812 | #define GMAC_RPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RPQ) MASK Register */
|
| 813 |
|
| 814 | /* -------- GMAC_TPQ : (GMAC Offset: 0x03C) (R/W 32) Transmit Pause Quantum Register -------- */
|
| 815 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 816 | typedef union {
|
| 817 | struct {
|
| 818 | uint32_t TPQ:16; /*!< bit: 0..15 Transmit Pause Quantum */
|
| 819 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 820 | } bit; /*!< Structure used for bit access */
|
| 821 | uint32_t reg; /*!< Type used for register access */
|
| 822 | } GMAC_TPQ_Type;
|
| 823 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 824 |
|
| 825 | #define GMAC_TPQ_OFFSET 0x03C /**< \brief (GMAC_TPQ offset) Transmit Pause Quantum Register */
|
| 826 | #define GMAC_TPQ_RESETVALUE _U_(0x0000FFFF) /**< \brief (GMAC_TPQ reset_value) Transmit Pause Quantum Register */
|
| 827 |
|
| 828 | #define GMAC_TPQ_TPQ_Pos 0 /**< \brief (GMAC_TPQ) Transmit Pause Quantum */
|
| 829 | #define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos)
|
| 830 | #define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))
|
| 831 | #define GMAC_TPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPQ) MASK Register */
|
| 832 |
|
| 833 | /* -------- GMAC_TPSF : (GMAC Offset: 0x040) (R/W 32) TX partial store and forward Register -------- */
|
| 834 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 835 | typedef union {
|
| 836 | struct {
|
| 837 | uint32_t TPB1ADR:10; /*!< bit: 0.. 9 TX packet buffer address */
|
| 838 | uint32_t :21; /*!< bit: 10..30 Reserved */
|
| 839 | uint32_t ENTXP:1; /*!< bit: 31 Enable TX partial store and forward operation */
|
| 840 | } bit; /*!< Structure used for bit access */
|
| 841 | uint32_t reg; /*!< Type used for register access */
|
| 842 | } GMAC_TPSF_Type;
|
| 843 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 844 |
|
| 845 | #define GMAC_TPSF_OFFSET 0x040 /**< \brief (GMAC_TPSF offset) TX partial store and forward Register */
|
| 846 | #define GMAC_TPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_TPSF reset_value) TX partial store and forward Register */
|
| 847 |
|
| 848 | #define GMAC_TPSF_TPB1ADR_Pos 0 /**< \brief (GMAC_TPSF) TX packet buffer address */
|
| 849 | #define GMAC_TPSF_TPB1ADR_Msk (_U_(0x3FF) << GMAC_TPSF_TPB1ADR_Pos)
|
| 850 | #define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))
|
| 851 | #define GMAC_TPSF_ENTXP_Pos 31 /**< \brief (GMAC_TPSF) Enable TX partial store and forward operation */
|
| 852 | #define GMAC_TPSF_ENTXP (_U_(0x1) << GMAC_TPSF_ENTXP_Pos)
|
| 853 | #define GMAC_TPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_TPSF) MASK Register */
|
| 854 |
|
| 855 | /* -------- GMAC_RPSF : (GMAC Offset: 0x044) (R/W 32) RX partial store and forward Register -------- */
|
| 856 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 857 | typedef union {
|
| 858 | struct {
|
| 859 | uint32_t RPB1ADR:10; /*!< bit: 0.. 9 RX packet buffer address */
|
| 860 | uint32_t :21; /*!< bit: 10..30 Reserved */
|
| 861 | uint32_t ENRXP:1; /*!< bit: 31 Enable RX partial store and forward operation */
|
| 862 | } bit; /*!< Structure used for bit access */
|
| 863 | uint32_t reg; /*!< Type used for register access */
|
| 864 | } GMAC_RPSF_Type;
|
| 865 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 866 |
|
| 867 | #define GMAC_RPSF_OFFSET 0x044 /**< \brief (GMAC_RPSF offset) RX partial store and forward Register */
|
| 868 | #define GMAC_RPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_RPSF reset_value) RX partial store and forward Register */
|
| 869 |
|
| 870 | #define GMAC_RPSF_RPB1ADR_Pos 0 /**< \brief (GMAC_RPSF) RX packet buffer address */
|
| 871 | #define GMAC_RPSF_RPB1ADR_Msk (_U_(0x3FF) << GMAC_RPSF_RPB1ADR_Pos)
|
| 872 | #define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))
|
| 873 | #define GMAC_RPSF_ENRXP_Pos 31 /**< \brief (GMAC_RPSF) Enable RX partial store and forward operation */
|
| 874 | #define GMAC_RPSF_ENRXP (_U_(0x1) << GMAC_RPSF_ENRXP_Pos)
|
| 875 | #define GMAC_RPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_RPSF) MASK Register */
|
| 876 |
|
| 877 | /* -------- GMAC_RJFML : (GMAC Offset: 0x048) (R/W 32) RX Jumbo Frame Max Length Register -------- */
|
| 878 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 879 | typedef union {
|
| 880 | struct {
|
| 881 | uint32_t FML:14; /*!< bit: 0..13 Frame Max Length */
|
| 882 | uint32_t :18; /*!< bit: 14..31 Reserved */
|
| 883 | } bit; /*!< Structure used for bit access */
|
| 884 | uint32_t reg; /*!< Type used for register access */
|
| 885 | } GMAC_RJFML_Type;
|
| 886 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 887 |
|
| 888 | #define GMAC_RJFML_OFFSET 0x048 /**< \brief (GMAC_RJFML offset) RX Jumbo Frame Max Length Register */
|
| 889 | #define GMAC_RJFML_RESETVALUE _U_(0x00003FFF) /**< \brief (GMAC_RJFML reset_value) RX Jumbo Frame Max Length Register */
|
| 890 |
|
| 891 | #define GMAC_RJFML_FML_Pos 0 /**< \brief (GMAC_RJFML) Frame Max Length */
|
| 892 | #define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos)
|
| 893 | #define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))
|
| 894 | #define GMAC_RJFML_MASK _U_(0x00003FFF) /**< \brief (GMAC_RJFML) MASK Register */
|
| 895 |
|
| 896 | /* -------- GMAC_HRB : (GMAC Offset: 0x080) (R/W 32) Hash Register Bottom [31:0] -------- */
|
| 897 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 898 | typedef union {
|
| 899 | struct {
|
| 900 | uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
|
| 901 | } bit; /*!< Structure used for bit access */
|
| 902 | uint32_t reg; /*!< Type used for register access */
|
| 903 | } GMAC_HRB_Type;
|
| 904 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 905 |
|
| 906 | #define GMAC_HRB_OFFSET 0x080 /**< \brief (GMAC_HRB offset) Hash Register Bottom [31:0] */
|
| 907 | #define GMAC_HRB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRB reset_value) Hash Register Bottom [31:0] */
|
| 908 |
|
| 909 | #define GMAC_HRB_ADDR_Pos 0 /**< \brief (GMAC_HRB) Hash Address */
|
| 910 | #define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos)
|
| 911 | #define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))
|
| 912 | #define GMAC_HRB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRB) MASK Register */
|
| 913 |
|
| 914 | /* -------- GMAC_HRT : (GMAC Offset: 0x084) (R/W 32) Hash Register Top [63:32] -------- */
|
| 915 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 916 | typedef union {
|
| 917 | struct {
|
| 918 | uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
|
| 919 | } bit; /*!< Structure used for bit access */
|
| 920 | uint32_t reg; /*!< Type used for register access */
|
| 921 | } GMAC_HRT_Type;
|
| 922 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 923 |
|
| 924 | #define GMAC_HRT_OFFSET 0x084 /**< \brief (GMAC_HRT offset) Hash Register Top [63:32] */
|
| 925 | #define GMAC_HRT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRT reset_value) Hash Register Top [63:32] */
|
| 926 |
|
| 927 | #define GMAC_HRT_ADDR_Pos 0 /**< \brief (GMAC_HRT) Hash Address */
|
| 928 | #define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos)
|
| 929 | #define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))
|
| 930 | #define GMAC_HRT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRT) MASK Register */
|
| 931 |
|
| 932 | /* -------- GMAC_SAB : (GMAC Offset: 0x088) (R/W 32) SA Specific Address Bottom [31:0] Register -------- */
|
| 933 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 934 | typedef union {
|
| 935 | struct {
|
| 936 | uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 */
|
| 937 | } bit; /*!< Structure used for bit access */
|
| 938 | uint32_t reg; /*!< Type used for register access */
|
| 939 | } GMAC_SAB_Type;
|
| 940 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 941 |
|
| 942 | #define GMAC_SAB_OFFSET 0x088 /**< \brief (GMAC_SAB offset) Specific Address Bottom [31:0] Register */
|
| 943 | #define GMAC_SAB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAB reset_value) Specific Address Bottom [31:0] Register */
|
| 944 |
|
| 945 | #define GMAC_SAB_ADDR_Pos 0 /**< \brief (GMAC_SAB) Specific Address 1 */
|
| 946 | #define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos)
|
| 947 | #define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))
|
| 948 | #define GMAC_SAB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAB) MASK Register */
|
| 949 |
|
| 950 | /* -------- GMAC_SAT : (GMAC Offset: 0x08C) (R/W 32) SA Specific Address Top [47:32] Register -------- */
|
| 951 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 952 | typedef union {
|
| 953 | struct {
|
| 954 | uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 */
|
| 955 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 956 | } bit; /*!< Structure used for bit access */
|
| 957 | uint32_t reg; /*!< Type used for register access */
|
| 958 | } GMAC_SAT_Type;
|
| 959 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 960 |
|
| 961 | #define GMAC_SAT_OFFSET 0x08C /**< \brief (GMAC_SAT offset) Specific Address Top [47:32] Register */
|
| 962 | #define GMAC_SAT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAT reset_value) Specific Address Top [47:32] Register */
|
| 963 |
|
| 964 | #define GMAC_SAT_ADDR_Pos 0 /**< \brief (GMAC_SAT) Specific Address 1 */
|
| 965 | #define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos)
|
| 966 | #define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))
|
| 967 | #define GMAC_SAT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAT) MASK Register */
|
| 968 |
|
| 969 | /* -------- GMAC_TIDM : (GMAC Offset: 0x0A8) (R/W 32) Type ID Match Register -------- */
|
| 970 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 971 | typedef union {
|
| 972 | struct {
|
| 973 | uint32_t TID:16; /*!< bit: 0..15 Type ID Match 1 */
|
| 974 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 975 | } bit; /*!< Structure used for bit access */
|
| 976 | uint32_t reg; /*!< Type used for register access */
|
| 977 | } GMAC_TIDM_Type;
|
| 978 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 979 |
|
| 980 | #define GMAC_TIDM_OFFSET 0x0A8 /**< \brief (GMAC_TIDM offset) Type ID Match Register */
|
| 981 | #define GMAC_TIDM_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TIDM reset_value) Type ID Match Register */
|
| 982 |
|
| 983 | #define GMAC_TIDM_TID_Pos 0 /**< \brief (GMAC_TIDM) Type ID Match 1 */
|
| 984 | #define GMAC_TIDM_TID_Msk (_U_(0xFFFF) << GMAC_TIDM_TID_Pos)
|
| 985 | #define GMAC_TIDM_TID(value) (GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))
|
| 986 | #define GMAC_TIDM_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TIDM) MASK Register */
|
| 987 |
|
| 988 | /* -------- GMAC_WOL : (GMAC Offset: 0x0B8) (R/W 32) Wake on LAN -------- */
|
| 989 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 990 | typedef union {
|
| 991 | struct {
|
| 992 | uint32_t IP:16; /*!< bit: 0..15 IP address */
|
| 993 | uint32_t MAG:1; /*!< bit: 16 Event enable */
|
| 994 | uint32_t ARP:1; /*!< bit: 17 LAN ARP req */
|
| 995 | uint32_t SA1:1; /*!< bit: 18 WOL specific address reg 1 */
|
| 996 | uint32_t MTI:1; /*!< bit: 19 WOL LAN multicast */
|
| 997 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 998 | } bit; /*!< Structure used for bit access */
|
| 999 | uint32_t reg; /*!< Type used for register access */
|
| 1000 | } GMAC_WOL_Type;
|
| 1001 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1002 |
|
| 1003 | #define GMAC_WOL_OFFSET 0x0B8 /**< \brief (GMAC_WOL offset) Wake on LAN */
|
| 1004 | #define GMAC_WOL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_WOL reset_value) Wake on LAN */
|
| 1005 |
|
| 1006 | #define GMAC_WOL_IP_Pos 0 /**< \brief (GMAC_WOL) IP address */
|
| 1007 | #define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos)
|
| 1008 | #define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))
|
| 1009 | #define GMAC_WOL_MAG_Pos 16 /**< \brief (GMAC_WOL) Event enable */
|
| 1010 | #define GMAC_WOL_MAG (_U_(0x1) << GMAC_WOL_MAG_Pos)
|
| 1011 | #define GMAC_WOL_ARP_Pos 17 /**< \brief (GMAC_WOL) LAN ARP req */
|
| 1012 | #define GMAC_WOL_ARP (_U_(0x1) << GMAC_WOL_ARP_Pos)
|
| 1013 | #define GMAC_WOL_SA1_Pos 18 /**< \brief (GMAC_WOL) WOL specific address reg 1 */
|
| 1014 | #define GMAC_WOL_SA1 (_U_(0x1) << GMAC_WOL_SA1_Pos)
|
| 1015 | #define GMAC_WOL_MTI_Pos 19 /**< \brief (GMAC_WOL) WOL LAN multicast */
|
| 1016 | #define GMAC_WOL_MTI (_U_(0x1) << GMAC_WOL_MTI_Pos)
|
| 1017 | #define GMAC_WOL_MASK _U_(0x000FFFFF) /**< \brief (GMAC_WOL) MASK Register */
|
| 1018 |
|
| 1019 | /* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) (R/W 32) IPG Stretch Register -------- */
|
| 1020 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1021 | typedef union {
|
| 1022 | struct {
|
| 1023 | uint32_t FL:16; /*!< bit: 0..15 Frame Length */
|
| 1024 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1025 | } bit; /*!< Structure used for bit access */
|
| 1026 | uint32_t reg; /*!< Type used for register access */
|
| 1027 | } GMAC_IPGS_Type;
|
| 1028 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1029 |
|
| 1030 | #define GMAC_IPGS_OFFSET 0x0BC /**< \brief (GMAC_IPGS offset) IPG Stretch Register */
|
| 1031 | #define GMAC_IPGS_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IPGS reset_value) IPG Stretch Register */
|
| 1032 |
|
| 1033 | #define GMAC_IPGS_FL_Pos 0 /**< \brief (GMAC_IPGS) Frame Length */
|
| 1034 | #define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos)
|
| 1035 | #define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))
|
| 1036 | #define GMAC_IPGS_MASK _U_(0x0000FFFF) /**< \brief (GMAC_IPGS) MASK Register */
|
| 1037 |
|
| 1038 | /* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) (R/W 32) Stacked VLAN Register -------- */
|
| 1039 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1040 | typedef union {
|
| 1041 | struct {
|
| 1042 | uint32_t VLAN_TYPE:16; /*!< bit: 0..15 User Defined VLAN_TYPE Field */
|
| 1043 | uint32_t :15; /*!< bit: 16..30 Reserved */
|
| 1044 | uint32_t ESVLAN:1; /*!< bit: 31 Enable Stacked VLAN Processing Mode */
|
| 1045 | } bit; /*!< Structure used for bit access */
|
| 1046 | uint32_t reg; /*!< Type used for register access */
|
| 1047 | } GMAC_SVLAN_Type;
|
| 1048 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1049 |
|
| 1050 | #define GMAC_SVLAN_OFFSET 0x0C0 /**< \brief (GMAC_SVLAN offset) Stacked VLAN Register */
|
| 1051 | #define GMAC_SVLAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SVLAN reset_value) Stacked VLAN Register */
|
| 1052 |
|
| 1053 | #define GMAC_SVLAN_VLAN_TYPE_Pos 0 /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */
|
| 1054 | #define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos)
|
| 1055 | #define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))
|
| 1056 | #define GMAC_SVLAN_ESVLAN_Pos 31 /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */
|
| 1057 | #define GMAC_SVLAN_ESVLAN (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos)
|
| 1058 | #define GMAC_SVLAN_MASK _U_(0x8000FFFF) /**< \brief (GMAC_SVLAN) MASK Register */
|
| 1059 |
|
| 1060 | /* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) (R/W 32) Transmit PFC Pause Register -------- */
|
| 1061 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1062 | typedef union {
|
| 1063 | struct {
|
| 1064 | uint32_t PEV:8; /*!< bit: 0.. 7 Priority Enable Vector */
|
| 1065 | uint32_t PQ:8; /*!< bit: 8..15 Pause Quantum */
|
| 1066 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1067 | } bit; /*!< Structure used for bit access */
|
| 1068 | uint32_t reg; /*!< Type used for register access */
|
| 1069 | } GMAC_TPFCP_Type;
|
| 1070 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1071 |
|
| 1072 | #define GMAC_TPFCP_OFFSET 0x0C4 /**< \brief (GMAC_TPFCP offset) Transmit PFC Pause Register */
|
| 1073 | #define GMAC_TPFCP_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TPFCP reset_value) Transmit PFC Pause Register */
|
| 1074 |
|
| 1075 | #define GMAC_TPFCP_PEV_Pos 0 /**< \brief (GMAC_TPFCP) Priority Enable Vector */
|
| 1076 | #define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos)
|
| 1077 | #define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))
|
| 1078 | #define GMAC_TPFCP_PQ_Pos 8 /**< \brief (GMAC_TPFCP) Pause Quantum */
|
| 1079 | #define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos)
|
| 1080 | #define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))
|
| 1081 | #define GMAC_TPFCP_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPFCP) MASK Register */
|
| 1082 |
|
| 1083 | /* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */
|
| 1084 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1085 | typedef union {
|
| 1086 | struct {
|
| 1087 | uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 Mask */
|
| 1088 | } bit; /*!< Structure used for bit access */
|
| 1089 | uint32_t reg; /*!< Type used for register access */
|
| 1090 | } GMAC_SAMB1_Type;
|
| 1091 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1092 |
|
| 1093 | #define GMAC_SAMB1_OFFSET 0x0C8 /**< \brief (GMAC_SAMB1 offset) Specific Address 1 Mask Bottom [31:0] Register */
|
| 1094 | #define GMAC_SAMB1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMB1 reset_value) Specific Address 1 Mask Bottom [31:0] Register */
|
| 1095 |
|
| 1096 | #define GMAC_SAMB1_ADDR_Pos 0 /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */
|
| 1097 | #define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos)
|
| 1098 | #define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))
|
| 1099 | #define GMAC_SAMB1_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAMB1) MASK Register */
|
| 1100 |
|
| 1101 | /* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */
|
| 1102 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1103 | typedef union {
|
| 1104 | struct {
|
| 1105 | uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 Mask */
|
| 1106 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1107 | } bit; /*!< Structure used for bit access */
|
| 1108 | uint32_t reg; /*!< Type used for register access */
|
| 1109 | } GMAC_SAMT1_Type;
|
| 1110 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1111 |
|
| 1112 | #define GMAC_SAMT1_OFFSET 0x0CC /**< \brief (GMAC_SAMT1 offset) Specific Address 1 Mask Top [47:32] Register */
|
| 1113 | #define GMAC_SAMT1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMT1 reset_value) Specific Address 1 Mask Top [47:32] Register */
|
| 1114 |
|
| 1115 | #define GMAC_SAMT1_ADDR_Pos 0 /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */
|
| 1116 | #define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos)
|
| 1117 | #define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))
|
| 1118 | #define GMAC_SAMT1_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAMT1) MASK Register */
|
| 1119 |
|
| 1120 | /* -------- GMAC_NSC : (GMAC Offset: 0x0DC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */
|
| 1121 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1122 | typedef union {
|
| 1123 | struct {
|
| 1124 | uint32_t NANOSEC:21; /*!< bit: 0..20 1588 Timer Nanosecond comparison value */
|
| 1125 | uint32_t :11; /*!< bit: 21..31 Reserved */
|
| 1126 | } bit; /*!< Structure used for bit access */
|
| 1127 | uint32_t reg; /*!< Type used for register access */
|
| 1128 | } GMAC_NSC_Type;
|
| 1129 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1130 |
|
| 1131 | #define GMAC_NSC_OFFSET 0x0DC /**< \brief (GMAC_NSC offset) Tsu timer comparison nanoseconds Register */
|
| 1132 | #define GMAC_NSC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NSC reset_value) Tsu timer comparison nanoseconds Register */
|
| 1133 |
|
| 1134 | #define GMAC_NSC_NANOSEC_Pos 0 /**< \brief (GMAC_NSC) 1588 Timer Nanosecond comparison value */
|
| 1135 | #define GMAC_NSC_NANOSEC_Msk (_U_(0x1FFFFF) << GMAC_NSC_NANOSEC_Pos)
|
| 1136 | #define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))
|
| 1137 | #define GMAC_NSC_MASK _U_(0x001FFFFF) /**< \brief (GMAC_NSC) MASK Register */
|
| 1138 |
|
| 1139 | /* -------- GMAC_SCL : (GMAC Offset: 0x0E0) (R/W 32) Tsu timer second comparison Register -------- */
|
| 1140 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1141 | typedef union {
|
| 1142 | struct {
|
| 1143 | uint32_t SEC:32; /*!< bit: 0..31 1588 Timer Second comparison value */
|
| 1144 | } bit; /*!< Structure used for bit access */
|
| 1145 | uint32_t reg; /*!< Type used for register access */
|
| 1146 | } GMAC_SCL_Type;
|
| 1147 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1148 |
|
| 1149 | #define GMAC_SCL_OFFSET 0x0E0 /**< \brief (GMAC_SCL offset) Tsu timer second comparison Register */
|
| 1150 | #define GMAC_SCL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCL reset_value) Tsu timer second comparison Register */
|
| 1151 |
|
| 1152 | #define GMAC_SCL_SEC_Pos 0 /**< \brief (GMAC_SCL) 1588 Timer Second comparison value */
|
| 1153 | #define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos)
|
| 1154 | #define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))
|
| 1155 | #define GMAC_SCL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SCL) MASK Register */
|
| 1156 |
|
| 1157 | /* -------- GMAC_SCH : (GMAC Offset: 0x0E4) (R/W 32) Tsu timer second comparison Register -------- */
|
| 1158 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1159 | typedef union {
|
| 1160 | struct {
|
| 1161 | uint32_t SEC:16; /*!< bit: 0..15 1588 Timer Second comparison value */
|
| 1162 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1163 | } bit; /*!< Structure used for bit access */
|
| 1164 | uint32_t reg; /*!< Type used for register access */
|
| 1165 | } GMAC_SCH_Type;
|
| 1166 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1167 |
|
| 1168 | #define GMAC_SCH_OFFSET 0x0E4 /**< \brief (GMAC_SCH offset) Tsu timer second comparison Register */
|
| 1169 | #define GMAC_SCH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCH reset_value) Tsu timer second comparison Register */
|
| 1170 |
|
| 1171 | #define GMAC_SCH_SEC_Pos 0 /**< \brief (GMAC_SCH) 1588 Timer Second comparison value */
|
| 1172 | #define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos)
|
| 1173 | #define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))
|
| 1174 | #define GMAC_SCH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SCH) MASK Register */
|
| 1175 |
|
| 1176 | /* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) (R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */
|
| 1177 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1178 | typedef union {
|
| 1179 | struct {
|
| 1180 | uint32_t RUD:16; /*!< bit: 0..15 Register Update */
|
| 1181 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1182 | } bit; /*!< Structure used for bit access */
|
| 1183 | uint32_t reg; /*!< Type used for register access */
|
| 1184 | } GMAC_EFTSH_Type;
|
| 1185 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1186 |
|
| 1187 | #define GMAC_EFTSH_OFFSET 0x0E8 /**< \brief (GMAC_EFTSH offset) PTP Event Frame Transmitted Seconds High Register */
|
| 1188 | #define GMAC_EFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSH reset_value) PTP Event Frame Transmitted Seconds High Register */
|
| 1189 |
|
| 1190 | #define GMAC_EFTSH_RUD_Pos 0 /**< \brief (GMAC_EFTSH) Register Update */
|
| 1191 | #define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos)
|
| 1192 | #define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos))
|
| 1193 | #define GMAC_EFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFTSH) MASK Register */
|
| 1194 |
|
| 1195 | /* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) (R/ 32) PTP Event Frame Received Seconds High Register -------- */
|
| 1196 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1197 | typedef union {
|
| 1198 | struct {
|
| 1199 | uint32_t RUD:16; /*!< bit: 0..15 Register Update */
|
| 1200 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1201 | } bit; /*!< Structure used for bit access */
|
| 1202 | uint32_t reg; /*!< Type used for register access */
|
| 1203 | } GMAC_EFRSH_Type;
|
| 1204 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1205 |
|
| 1206 | #define GMAC_EFRSH_OFFSET 0x0EC /**< \brief (GMAC_EFRSH offset) PTP Event Frame Received Seconds High Register */
|
| 1207 | #define GMAC_EFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSH reset_value) PTP Event Frame Received Seconds High Register */
|
| 1208 |
|
| 1209 | #define GMAC_EFRSH_RUD_Pos 0 /**< \brief (GMAC_EFRSH) Register Update */
|
| 1210 | #define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos)
|
| 1211 | #define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos))
|
| 1212 | #define GMAC_EFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFRSH) MASK Register */
|
| 1213 |
|
| 1214 | /* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */
|
| 1215 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1216 | typedef union {
|
| 1217 | struct {
|
| 1218 | uint32_t RUD:16; /*!< bit: 0..15 Register Update */
|
| 1219 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1220 | } bit; /*!< Structure used for bit access */
|
| 1221 | uint32_t reg; /*!< Type used for register access */
|
| 1222 | } GMAC_PEFTSH_Type;
|
| 1223 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1224 |
|
| 1225 | #define GMAC_PEFTSH_OFFSET 0x0F0 /**< \brief (GMAC_PEFTSH offset) PTP Peer Event Frame Transmitted Seconds High Register */
|
| 1226 | #define GMAC_PEFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSH reset_value) PTP Peer Event Frame Transmitted Seconds High Register */
|
| 1227 |
|
| 1228 | #define GMAC_PEFTSH_RUD_Pos 0 /**< \brief (GMAC_PEFTSH) Register Update */
|
| 1229 | #define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos)
|
| 1230 | #define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos))
|
| 1231 | #define GMAC_PEFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFTSH) MASK Register */
|
| 1232 |
|
| 1233 | /* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) (R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */
|
| 1234 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1235 | typedef union {
|
| 1236 | struct {
|
| 1237 | uint32_t RUD:16; /*!< bit: 0..15 Register Update */
|
| 1238 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1239 | } bit; /*!< Structure used for bit access */
|
| 1240 | uint32_t reg; /*!< Type used for register access */
|
| 1241 | } GMAC_PEFRSH_Type;
|
| 1242 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1243 |
|
| 1244 | #define GMAC_PEFRSH_OFFSET 0x0F4 /**< \brief (GMAC_PEFRSH offset) PTP Peer Event Frame Received Seconds High Register */
|
| 1245 | #define GMAC_PEFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSH reset_value) PTP Peer Event Frame Received Seconds High Register */
|
| 1246 |
|
| 1247 | #define GMAC_PEFRSH_RUD_Pos 0 /**< \brief (GMAC_PEFRSH) Register Update */
|
| 1248 | #define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos)
|
| 1249 | #define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos))
|
| 1250 | #define GMAC_PEFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFRSH) MASK Register */
|
| 1251 |
|
| 1252 | /* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/ 32) Octets Transmitted [31:0] Register -------- */
|
| 1253 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1254 | typedef union {
|
| 1255 | struct {
|
| 1256 | uint32_t TXO:32; /*!< bit: 0..31 Transmitted Octets */
|
| 1257 | } bit; /*!< Structure used for bit access */
|
| 1258 | uint32_t reg; /*!< Type used for register access */
|
| 1259 | } GMAC_OTLO_Type;
|
| 1260 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1261 |
|
| 1262 | #define GMAC_OTLO_OFFSET 0x100 /**< \brief (GMAC_OTLO offset) Octets Transmitted [31:0] Register */
|
| 1263 | #define GMAC_OTLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTLO reset_value) Octets Transmitted [31:0] Register */
|
| 1264 |
|
| 1265 | #define GMAC_OTLO_TXO_Pos 0 /**< \brief (GMAC_OTLO) Transmitted Octets */
|
| 1266 | #define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos)
|
| 1267 | #define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos))
|
| 1268 | #define GMAC_OTLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_OTLO) MASK Register */
|
| 1269 |
|
| 1270 | /* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/ 32) Octets Transmitted [47:32] Register -------- */
|
| 1271 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1272 | typedef union {
|
| 1273 | struct {
|
| 1274 | uint32_t TXO:16; /*!< bit: 0..15 Transmitted Octets */
|
| 1275 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1276 | } bit; /*!< Structure used for bit access */
|
| 1277 | uint32_t reg; /*!< Type used for register access */
|
| 1278 | } GMAC_OTHI_Type;
|
| 1279 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1280 |
|
| 1281 | #define GMAC_OTHI_OFFSET 0x104 /**< \brief (GMAC_OTHI offset) Octets Transmitted [47:32] Register */
|
| 1282 | #define GMAC_OTHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTHI reset_value) Octets Transmitted [47:32] Register */
|
| 1283 |
|
| 1284 | #define GMAC_OTHI_TXO_Pos 0 /**< \brief (GMAC_OTHI) Transmitted Octets */
|
| 1285 | #define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos)
|
| 1286 | #define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos))
|
| 1287 | #define GMAC_OTHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_OTHI) MASK Register */
|
| 1288 |
|
| 1289 | /* -------- GMAC_FT : (GMAC Offset: 0x108) (R/ 32) Frames Transmitted Register -------- */
|
| 1290 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1291 | typedef union {
|
| 1292 | struct {
|
| 1293 | uint32_t FTX:32; /*!< bit: 0..31 Frames Transmitted without Error */
|
| 1294 | } bit; /*!< Structure used for bit access */
|
| 1295 | uint32_t reg; /*!< Type used for register access */
|
| 1296 | } GMAC_FT_Type;
|
| 1297 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1298 |
|
| 1299 | #define GMAC_FT_OFFSET 0x108 /**< \brief (GMAC_FT offset) Frames Transmitted Register */
|
| 1300 | #define GMAC_FT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FT reset_value) Frames Transmitted Register */
|
| 1301 |
|
| 1302 | #define GMAC_FT_FTX_Pos 0 /**< \brief (GMAC_FT) Frames Transmitted without Error */
|
| 1303 | #define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos)
|
| 1304 | #define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos))
|
| 1305 | #define GMAC_FT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FT) MASK Register */
|
| 1306 |
|
| 1307 | /* -------- GMAC_BCFT : (GMAC Offset: 0x10C) (R/ 32) Broadcast Frames Transmitted Register -------- */
|
| 1308 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1309 | typedef union {
|
| 1310 | struct {
|
| 1311 | uint32_t BFTX:32; /*!< bit: 0..31 Broadcast Frames Transmitted without Error */
|
| 1312 | } bit; /*!< Structure used for bit access */
|
| 1313 | uint32_t reg; /*!< Type used for register access */
|
| 1314 | } GMAC_BCFT_Type;
|
| 1315 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1316 |
|
| 1317 | #define GMAC_BCFT_OFFSET 0x10C /**< \brief (GMAC_BCFT offset) Broadcast Frames Transmitted Register */
|
| 1318 | #define GMAC_BCFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFT reset_value) Broadcast Frames Transmitted Register */
|
| 1319 |
|
| 1320 | #define GMAC_BCFT_BFTX_Pos 0 /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */
|
| 1321 | #define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos)
|
| 1322 | #define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos))
|
| 1323 | #define GMAC_BCFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFT) MASK Register */
|
| 1324 |
|
| 1325 | /* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/ 32) Multicast Frames Transmitted Register -------- */
|
| 1326 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1327 | typedef union {
|
| 1328 | struct {
|
| 1329 | uint32_t MFTX:32; /*!< bit: 0..31 Multicast Frames Transmitted without Error */
|
| 1330 | } bit; /*!< Structure used for bit access */
|
| 1331 | uint32_t reg; /*!< Type used for register access */
|
| 1332 | } GMAC_MFT_Type;
|
| 1333 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1334 |
|
| 1335 | #define GMAC_MFT_OFFSET 0x110 /**< \brief (GMAC_MFT offset) Multicast Frames Transmitted Register */
|
| 1336 | #define GMAC_MFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFT reset_value) Multicast Frames Transmitted Register */
|
| 1337 |
|
| 1338 | #define GMAC_MFT_MFTX_Pos 0 /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */
|
| 1339 | #define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos)
|
| 1340 | #define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos))
|
| 1341 | #define GMAC_MFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFT) MASK Register */
|
| 1342 |
|
| 1343 | /* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/ 32) Pause Frames Transmitted Register -------- */
|
| 1344 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1345 | typedef union {
|
| 1346 | struct {
|
| 1347 | uint32_t PFTX:16; /*!< bit: 0..15 Pause Frames Transmitted Register */
|
| 1348 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1349 | } bit; /*!< Structure used for bit access */
|
| 1350 | uint32_t reg; /*!< Type used for register access */
|
| 1351 | } GMAC_PFT_Type;
|
| 1352 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1353 |
|
| 1354 | #define GMAC_PFT_OFFSET 0x114 /**< \brief (GMAC_PFT offset) Pause Frames Transmitted Register */
|
| 1355 | #define GMAC_PFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFT reset_value) Pause Frames Transmitted Register */
|
| 1356 |
|
| 1357 | #define GMAC_PFT_PFTX_Pos 0 /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */
|
| 1358 | #define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos)
|
| 1359 | #define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos))
|
| 1360 | #define GMAC_PFT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFT) MASK Register */
|
| 1361 |
|
| 1362 | /* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/ 32) 64 Byte Frames Transmitted Register -------- */
|
| 1363 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1364 | typedef union {
|
| 1365 | struct {
|
| 1366 | uint32_t NFTX:32; /*!< bit: 0..31 64 Byte Frames Transmitted without Error */
|
| 1367 | } bit; /*!< Structure used for bit access */
|
| 1368 | uint32_t reg; /*!< Type used for register access */
|
| 1369 | } GMAC_BFT64_Type;
|
| 1370 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1371 |
|
| 1372 | #define GMAC_BFT64_OFFSET 0x118 /**< \brief (GMAC_BFT64 offset) 64 Byte Frames Transmitted Register */
|
| 1373 | #define GMAC_BFT64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFT64 reset_value) 64 Byte Frames Transmitted Register */
|
| 1374 |
|
| 1375 | #define GMAC_BFT64_NFTX_Pos 0 /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */
|
| 1376 | #define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos)
|
| 1377 | #define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos))
|
| 1378 | #define GMAC_BFT64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFT64) MASK Register */
|
| 1379 |
|
| 1380 | /* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) (R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */
|
| 1381 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1382 | typedef union {
|
| 1383 | struct {
|
| 1384 | uint32_t NFTX:32; /*!< bit: 0..31 65 to 127 Byte Frames Transmitted without Error */
|
| 1385 | } bit; /*!< Structure used for bit access */
|
| 1386 | uint32_t reg; /*!< Type used for register access */
|
| 1387 | } GMAC_TBFT127_Type;
|
| 1388 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1389 |
|
| 1390 | #define GMAC_TBFT127_OFFSET 0x11C /**< \brief (GMAC_TBFT127 offset) 65 to 127 Byte Frames Transmitted Register */
|
| 1391 | #define GMAC_TBFT127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT127 reset_value) 65 to 127 Byte Frames Transmitted Register */
|
| 1392 |
|
| 1393 | #define GMAC_TBFT127_NFTX_Pos 0 /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */
|
| 1394 | #define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos)
|
| 1395 | #define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos))
|
| 1396 | #define GMAC_TBFT127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT127) MASK Register */
|
| 1397 |
|
| 1398 | /* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */
|
| 1399 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1400 | typedef union {
|
| 1401 | struct {
|
| 1402 | uint32_t NFTX:32; /*!< bit: 0..31 128 to 255 Byte Frames Transmitted without Error */
|
| 1403 | } bit; /*!< Structure used for bit access */
|
| 1404 | uint32_t reg; /*!< Type used for register access */
|
| 1405 | } GMAC_TBFT255_Type;
|
| 1406 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1407 |
|
| 1408 | #define GMAC_TBFT255_OFFSET 0x120 /**< \brief (GMAC_TBFT255 offset) 128 to 255 Byte Frames Transmitted Register */
|
| 1409 | #define GMAC_TBFT255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT255 reset_value) 128 to 255 Byte Frames Transmitted Register */
|
| 1410 |
|
| 1411 | #define GMAC_TBFT255_NFTX_Pos 0 /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */
|
| 1412 | #define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos)
|
| 1413 | #define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos))
|
| 1414 | #define GMAC_TBFT255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT255) MASK Register */
|
| 1415 |
|
| 1416 | /* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */
|
| 1417 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1418 | typedef union {
|
| 1419 | struct {
|
| 1420 | uint32_t NFTX:32; /*!< bit: 0..31 256 to 511 Byte Frames Transmitted without Error */
|
| 1421 | } bit; /*!< Structure used for bit access */
|
| 1422 | uint32_t reg; /*!< Type used for register access */
|
| 1423 | } GMAC_TBFT511_Type;
|
| 1424 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1425 |
|
| 1426 | #define GMAC_TBFT511_OFFSET 0x124 /**< \brief (GMAC_TBFT511 offset) 256 to 511 Byte Frames Transmitted Register */
|
| 1427 | #define GMAC_TBFT511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT511 reset_value) 256 to 511 Byte Frames Transmitted Register */
|
| 1428 |
|
| 1429 | #define GMAC_TBFT511_NFTX_Pos 0 /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */
|
| 1430 | #define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos)
|
| 1431 | #define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos))
|
| 1432 | #define GMAC_TBFT511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT511) MASK Register */
|
| 1433 |
|
| 1434 | /* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */
|
| 1435 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1436 | typedef union {
|
| 1437 | struct {
|
| 1438 | uint32_t NFTX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Transmitted without Error */
|
| 1439 | } bit; /*!< Structure used for bit access */
|
| 1440 | uint32_t reg; /*!< Type used for register access */
|
| 1441 | } GMAC_TBFT1023_Type;
|
| 1442 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1443 |
|
| 1444 | #define GMAC_TBFT1023_OFFSET 0x128 /**< \brief (GMAC_TBFT1023 offset) 512 to 1023 Byte Frames Transmitted Register */
|
| 1445 | #define GMAC_TBFT1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1023 reset_value) 512 to 1023 Byte Frames Transmitted Register */
|
| 1446 |
|
| 1447 | #define GMAC_TBFT1023_NFTX_Pos 0 /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */
|
| 1448 | #define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos)
|
| 1449 | #define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos))
|
| 1450 | #define GMAC_TBFT1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1023) MASK Register */
|
| 1451 |
|
| 1452 | /* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) (R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */
|
| 1453 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1454 | typedef union {
|
| 1455 | struct {
|
| 1456 | uint32_t NFTX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Transmitted without Error */
|
| 1457 | } bit; /*!< Structure used for bit access */
|
| 1458 | uint32_t reg; /*!< Type used for register access */
|
| 1459 | } GMAC_TBFT1518_Type;
|
| 1460 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1461 |
|
| 1462 | #define GMAC_TBFT1518_OFFSET 0x12C /**< \brief (GMAC_TBFT1518 offset) 1024 to 1518 Byte Frames Transmitted Register */
|
| 1463 | #define GMAC_TBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1518 reset_value) 1024 to 1518 Byte Frames Transmitted Register */
|
| 1464 |
|
| 1465 | #define GMAC_TBFT1518_NFTX_Pos 0 /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */
|
| 1466 | #define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos)
|
| 1467 | #define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos))
|
| 1468 | #define GMAC_TBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1518) MASK Register */
|
| 1469 |
|
| 1470 | /* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */
|
| 1471 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1472 | typedef union {
|
| 1473 | struct {
|
| 1474 | uint32_t NFTX:32; /*!< bit: 0..31 Greater than 1518 Byte Frames Transmitted without Error */
|
| 1475 | } bit; /*!< Structure used for bit access */
|
| 1476 | uint32_t reg; /*!< Type used for register access */
|
| 1477 | } GMAC_GTBFT1518_Type;
|
| 1478 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1479 |
|
| 1480 | #define GMAC_GTBFT1518_OFFSET 0x130 /**< \brief (GMAC_GTBFT1518 offset) Greater Than 1518 Byte Frames Transmitted Register */
|
| 1481 | #define GMAC_GTBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_GTBFT1518 reset_value) Greater Than 1518 Byte Frames Transmitted Register */
|
| 1482 |
|
| 1483 | #define GMAC_GTBFT1518_NFTX_Pos 0 /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */
|
| 1484 | #define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos)
|
| 1485 | #define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos))
|
| 1486 | #define GMAC_GTBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_GTBFT1518) MASK Register */
|
| 1487 |
|
| 1488 | /* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/ 32) Transmit Underruns Register -------- */
|
| 1489 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1490 | typedef union {
|
| 1491 | struct {
|
| 1492 | uint32_t TXUNR:10; /*!< bit: 0.. 9 Transmit Underruns */
|
| 1493 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1494 | } bit; /*!< Structure used for bit access */
|
| 1495 | uint32_t reg; /*!< Type used for register access */
|
| 1496 | } GMAC_TUR_Type;
|
| 1497 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1498 |
|
| 1499 | #define GMAC_TUR_OFFSET 0x134 /**< \brief (GMAC_TUR offset) Transmit Underruns Register */
|
| 1500 | #define GMAC_TUR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TUR reset_value) Transmit Underruns Register */
|
| 1501 |
|
| 1502 | #define GMAC_TUR_TXUNR_Pos 0 /**< \brief (GMAC_TUR) Transmit Underruns */
|
| 1503 | #define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos)
|
| 1504 | #define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos))
|
| 1505 | #define GMAC_TUR_MASK _U_(0x000003FF) /**< \brief (GMAC_TUR) MASK Register */
|
| 1506 |
|
| 1507 | /* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/ 32) Single Collision Frames Register -------- */
|
| 1508 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1509 | typedef union {
|
| 1510 | struct {
|
| 1511 | uint32_t SCOL:18; /*!< bit: 0..17 Single Collision */
|
| 1512 | uint32_t :14; /*!< bit: 18..31 Reserved */
|
| 1513 | } bit; /*!< Structure used for bit access */
|
| 1514 | uint32_t reg; /*!< Type used for register access */
|
| 1515 | } GMAC_SCF_Type;
|
| 1516 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1517 |
|
| 1518 | #define GMAC_SCF_OFFSET 0x138 /**< \brief (GMAC_SCF offset) Single Collision Frames Register */
|
| 1519 | #define GMAC_SCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCF reset_value) Single Collision Frames Register */
|
| 1520 |
|
| 1521 | #define GMAC_SCF_SCOL_Pos 0 /**< \brief (GMAC_SCF) Single Collision */
|
| 1522 | #define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos)
|
| 1523 | #define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos))
|
| 1524 | #define GMAC_SCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_SCF) MASK Register */
|
| 1525 |
|
| 1526 | /* -------- GMAC_MCF : (GMAC Offset: 0x13C) (R/ 32) Multiple Collision Frames Register -------- */
|
| 1527 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1528 | typedef union {
|
| 1529 | struct {
|
| 1530 | uint32_t MCOL:18; /*!< bit: 0..17 Multiple Collision */
|
| 1531 | uint32_t :14; /*!< bit: 18..31 Reserved */
|
| 1532 | } bit; /*!< Structure used for bit access */
|
| 1533 | uint32_t reg; /*!< Type used for register access */
|
| 1534 | } GMAC_MCF_Type;
|
| 1535 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1536 |
|
| 1537 | #define GMAC_MCF_OFFSET 0x13C /**< \brief (GMAC_MCF offset) Multiple Collision Frames Register */
|
| 1538 | #define GMAC_MCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MCF reset_value) Multiple Collision Frames Register */
|
| 1539 |
|
| 1540 | #define GMAC_MCF_MCOL_Pos 0 /**< \brief (GMAC_MCF) Multiple Collision */
|
| 1541 | #define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos)
|
| 1542 | #define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos))
|
| 1543 | #define GMAC_MCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_MCF) MASK Register */
|
| 1544 |
|
| 1545 | /* -------- GMAC_EC : (GMAC Offset: 0x140) (R/ 32) Excessive Collisions Register -------- */
|
| 1546 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1547 | typedef union {
|
| 1548 | struct {
|
| 1549 | uint32_t XCOL:10; /*!< bit: 0.. 9 Excessive Collisions */
|
| 1550 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1551 | } bit; /*!< Structure used for bit access */
|
| 1552 | uint32_t reg; /*!< Type used for register access */
|
| 1553 | } GMAC_EC_Type;
|
| 1554 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1555 |
|
| 1556 | #define GMAC_EC_OFFSET 0x140 /**< \brief (GMAC_EC offset) Excessive Collisions Register */
|
| 1557 | #define GMAC_EC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EC reset_value) Excessive Collisions Register */
|
| 1558 |
|
| 1559 | #define GMAC_EC_XCOL_Pos 0 /**< \brief (GMAC_EC) Excessive Collisions */
|
| 1560 | #define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos)
|
| 1561 | #define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos))
|
| 1562 | #define GMAC_EC_MASK _U_(0x000003FF) /**< \brief (GMAC_EC) MASK Register */
|
| 1563 |
|
| 1564 | /* -------- GMAC_LC : (GMAC Offset: 0x144) (R/ 32) Late Collisions Register -------- */
|
| 1565 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1566 | typedef union {
|
| 1567 | struct {
|
| 1568 | uint32_t LCOL:10; /*!< bit: 0.. 9 Late Collisions */
|
| 1569 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1570 | } bit; /*!< Structure used for bit access */
|
| 1571 | uint32_t reg; /*!< Type used for register access */
|
| 1572 | } GMAC_LC_Type;
|
| 1573 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1574 |
|
| 1575 | #define GMAC_LC_OFFSET 0x144 /**< \brief (GMAC_LC offset) Late Collisions Register */
|
| 1576 | #define GMAC_LC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LC reset_value) Late Collisions Register */
|
| 1577 |
|
| 1578 | #define GMAC_LC_LCOL_Pos 0 /**< \brief (GMAC_LC) Late Collisions */
|
| 1579 | #define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos)
|
| 1580 | #define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos))
|
| 1581 | #define GMAC_LC_MASK _U_(0x000003FF) /**< \brief (GMAC_LC) MASK Register */
|
| 1582 |
|
| 1583 | /* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/ 32) Deferred Transmission Frames Register -------- */
|
| 1584 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1585 | typedef union {
|
| 1586 | struct {
|
| 1587 | uint32_t DEFT:18; /*!< bit: 0..17 Deferred Transmission */
|
| 1588 | uint32_t :14; /*!< bit: 18..31 Reserved */
|
| 1589 | } bit; /*!< Structure used for bit access */
|
| 1590 | uint32_t reg; /*!< Type used for register access */
|
| 1591 | } GMAC_DTF_Type;
|
| 1592 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1593 |
|
| 1594 | #define GMAC_DTF_OFFSET 0x148 /**< \brief (GMAC_DTF offset) Deferred Transmission Frames Register */
|
| 1595 | #define GMAC_DTF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_DTF reset_value) Deferred Transmission Frames Register */
|
| 1596 |
|
| 1597 | #define GMAC_DTF_DEFT_Pos 0 /**< \brief (GMAC_DTF) Deferred Transmission */
|
| 1598 | #define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos)
|
| 1599 | #define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos))
|
| 1600 | #define GMAC_DTF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_DTF) MASK Register */
|
| 1601 |
|
| 1602 | /* -------- GMAC_CSE : (GMAC Offset: 0x14C) (R/ 32) Carrier Sense Errors Register -------- */
|
| 1603 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1604 | typedef union {
|
| 1605 | struct {
|
| 1606 | uint32_t CSR:10; /*!< bit: 0.. 9 Carrier Sense Error */
|
| 1607 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1608 | } bit; /*!< Structure used for bit access */
|
| 1609 | uint32_t reg; /*!< Type used for register access */
|
| 1610 | } GMAC_CSE_Type;
|
| 1611 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1612 |
|
| 1613 | #define GMAC_CSE_OFFSET 0x14C /**< \brief (GMAC_CSE offset) Carrier Sense Errors Register */
|
| 1614 | #define GMAC_CSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_CSE reset_value) Carrier Sense Errors Register */
|
| 1615 |
|
| 1616 | #define GMAC_CSE_CSR_Pos 0 /**< \brief (GMAC_CSE) Carrier Sense Error */
|
| 1617 | #define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos)
|
| 1618 | #define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos))
|
| 1619 | #define GMAC_CSE_MASK _U_(0x000003FF) /**< \brief (GMAC_CSE) MASK Register */
|
| 1620 |
|
| 1621 | /* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/ 32) Octets Received [31:0] Received -------- */
|
| 1622 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1623 | typedef union {
|
| 1624 | struct {
|
| 1625 | uint32_t RXO:32; /*!< bit: 0..31 Received Octets */
|
| 1626 | } bit; /*!< Structure used for bit access */
|
| 1627 | uint32_t reg; /*!< Type used for register access */
|
| 1628 | } GMAC_ORLO_Type;
|
| 1629 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1630 |
|
| 1631 | #define GMAC_ORLO_OFFSET 0x150 /**< \brief (GMAC_ORLO offset) Octets Received [31:0] Received */
|
| 1632 | #define GMAC_ORLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORLO reset_value) Octets Received [31:0] Received */
|
| 1633 |
|
| 1634 | #define GMAC_ORLO_RXO_Pos 0 /**< \brief (GMAC_ORLO) Received Octets */
|
| 1635 | #define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos)
|
| 1636 | #define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos))
|
| 1637 | #define GMAC_ORLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_ORLO) MASK Register */
|
| 1638 |
|
| 1639 | /* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/ 32) Octets Received [47:32] Received -------- */
|
| 1640 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1641 | typedef union {
|
| 1642 | struct {
|
| 1643 | uint32_t RXO:16; /*!< bit: 0..15 Received Octets */
|
| 1644 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1645 | } bit; /*!< Structure used for bit access */
|
| 1646 | uint32_t reg; /*!< Type used for register access */
|
| 1647 | } GMAC_ORHI_Type;
|
| 1648 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1649 |
|
| 1650 | #define GMAC_ORHI_OFFSET 0x154 /**< \brief (GMAC_ORHI offset) Octets Received [47:32] Received */
|
| 1651 | #define GMAC_ORHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORHI reset_value) Octets Received [47:32] Received */
|
| 1652 |
|
| 1653 | #define GMAC_ORHI_RXO_Pos 0 /**< \brief (GMAC_ORHI) Received Octets */
|
| 1654 | #define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos)
|
| 1655 | #define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos))
|
| 1656 | #define GMAC_ORHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_ORHI) MASK Register */
|
| 1657 |
|
| 1658 | /* -------- GMAC_FR : (GMAC Offset: 0x158) (R/ 32) Frames Received Register -------- */
|
| 1659 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1660 | typedef union {
|
| 1661 | struct {
|
| 1662 | uint32_t FRX:32; /*!< bit: 0..31 Frames Received without Error */
|
| 1663 | } bit; /*!< Structure used for bit access */
|
| 1664 | uint32_t reg; /*!< Type used for register access */
|
| 1665 | } GMAC_FR_Type;
|
| 1666 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1667 |
|
| 1668 | #define GMAC_FR_OFFSET 0x158 /**< \brief (GMAC_FR offset) Frames Received Register */
|
| 1669 | #define GMAC_FR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FR reset_value) Frames Received Register */
|
| 1670 |
|
| 1671 | #define GMAC_FR_FRX_Pos 0 /**< \brief (GMAC_FR) Frames Received without Error */
|
| 1672 | #define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos)
|
| 1673 | #define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos))
|
| 1674 | #define GMAC_FR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FR) MASK Register */
|
| 1675 |
|
| 1676 | /* -------- GMAC_BCFR : (GMAC Offset: 0x15C) (R/ 32) Broadcast Frames Received Register -------- */
|
| 1677 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1678 | typedef union {
|
| 1679 | struct {
|
| 1680 | uint32_t BFRX:32; /*!< bit: 0..31 Broadcast Frames Received without Error */
|
| 1681 | } bit; /*!< Structure used for bit access */
|
| 1682 | uint32_t reg; /*!< Type used for register access */
|
| 1683 | } GMAC_BCFR_Type;
|
| 1684 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1685 |
|
| 1686 | #define GMAC_BCFR_OFFSET 0x15C /**< \brief (GMAC_BCFR offset) Broadcast Frames Received Register */
|
| 1687 | #define GMAC_BCFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFR reset_value) Broadcast Frames Received Register */
|
| 1688 |
|
| 1689 | #define GMAC_BCFR_BFRX_Pos 0 /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */
|
| 1690 | #define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos)
|
| 1691 | #define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos))
|
| 1692 | #define GMAC_BCFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFR) MASK Register */
|
| 1693 |
|
| 1694 | /* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/ 32) Multicast Frames Received Register -------- */
|
| 1695 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1696 | typedef union {
|
| 1697 | struct {
|
| 1698 | uint32_t MFRX:32; /*!< bit: 0..31 Multicast Frames Received without Error */
|
| 1699 | } bit; /*!< Structure used for bit access */
|
| 1700 | uint32_t reg; /*!< Type used for register access */
|
| 1701 | } GMAC_MFR_Type;
|
| 1702 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1703 |
|
| 1704 | #define GMAC_MFR_OFFSET 0x160 /**< \brief (GMAC_MFR offset) Multicast Frames Received Register */
|
| 1705 | #define GMAC_MFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFR reset_value) Multicast Frames Received Register */
|
| 1706 |
|
| 1707 | #define GMAC_MFR_MFRX_Pos 0 /**< \brief (GMAC_MFR) Multicast Frames Received without Error */
|
| 1708 | #define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos)
|
| 1709 | #define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos))
|
| 1710 | #define GMAC_MFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFR) MASK Register */
|
| 1711 |
|
| 1712 | /* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/ 32) Pause Frames Received Register -------- */
|
| 1713 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1714 | typedef union {
|
| 1715 | struct {
|
| 1716 | uint32_t PFRX:16; /*!< bit: 0..15 Pause Frames Received Register */
|
| 1717 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1718 | } bit; /*!< Structure used for bit access */
|
| 1719 | uint32_t reg; /*!< Type used for register access */
|
| 1720 | } GMAC_PFR_Type;
|
| 1721 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1722 |
|
| 1723 | #define GMAC_PFR_OFFSET 0x164 /**< \brief (GMAC_PFR offset) Pause Frames Received Register */
|
| 1724 | #define GMAC_PFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFR reset_value) Pause Frames Received Register */
|
| 1725 |
|
| 1726 | #define GMAC_PFR_PFRX_Pos 0 /**< \brief (GMAC_PFR) Pause Frames Received Register */
|
| 1727 | #define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos)
|
| 1728 | #define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos))
|
| 1729 | #define GMAC_PFR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFR) MASK Register */
|
| 1730 |
|
| 1731 | /* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/ 32) 64 Byte Frames Received Register -------- */
|
| 1732 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1733 | typedef union {
|
| 1734 | struct {
|
| 1735 | uint32_t NFRX:32; /*!< bit: 0..31 64 Byte Frames Received without Error */
|
| 1736 | } bit; /*!< Structure used for bit access */
|
| 1737 | uint32_t reg; /*!< Type used for register access */
|
| 1738 | } GMAC_BFR64_Type;
|
| 1739 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1740 |
|
| 1741 | #define GMAC_BFR64_OFFSET 0x168 /**< \brief (GMAC_BFR64 offset) 64 Byte Frames Received Register */
|
| 1742 | #define GMAC_BFR64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFR64 reset_value) 64 Byte Frames Received Register */
|
| 1743 |
|
| 1744 | #define GMAC_BFR64_NFRX_Pos 0 /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */
|
| 1745 | #define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos)
|
| 1746 | #define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos))
|
| 1747 | #define GMAC_BFR64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFR64) MASK Register */
|
| 1748 |
|
| 1749 | /* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) (R/ 32) 65 to 127 Byte Frames Received Register -------- */
|
| 1750 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1751 | typedef union {
|
| 1752 | struct {
|
| 1753 | uint32_t NFRX:32; /*!< bit: 0..31 65 to 127 Byte Frames Received without Error */
|
| 1754 | } bit; /*!< Structure used for bit access */
|
| 1755 | uint32_t reg; /*!< Type used for register access */
|
| 1756 | } GMAC_TBFR127_Type;
|
| 1757 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1758 |
|
| 1759 | #define GMAC_TBFR127_OFFSET 0x16C /**< \brief (GMAC_TBFR127 offset) 65 to 127 Byte Frames Received Register */
|
| 1760 | #define GMAC_TBFR127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR127 reset_value) 65 to 127 Byte Frames Received Register */
|
| 1761 |
|
| 1762 | #define GMAC_TBFR127_NFRX_Pos 0 /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */
|
| 1763 | #define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos)
|
| 1764 | #define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos))
|
| 1765 | #define GMAC_TBFR127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR127) MASK Register */
|
| 1766 |
|
| 1767 | /* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/ 32) 128 to 255 Byte Frames Received Register -------- */
|
| 1768 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1769 | typedef union {
|
| 1770 | struct {
|
| 1771 | uint32_t NFRX:32; /*!< bit: 0..31 128 to 255 Byte Frames Received without Error */
|
| 1772 | } bit; /*!< Structure used for bit access */
|
| 1773 | uint32_t reg; /*!< Type used for register access */
|
| 1774 | } GMAC_TBFR255_Type;
|
| 1775 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1776 |
|
| 1777 | #define GMAC_TBFR255_OFFSET 0x170 /**< \brief (GMAC_TBFR255 offset) 128 to 255 Byte Frames Received Register */
|
| 1778 | #define GMAC_TBFR255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR255 reset_value) 128 to 255 Byte Frames Received Register */
|
| 1779 |
|
| 1780 | #define GMAC_TBFR255_NFRX_Pos 0 /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */
|
| 1781 | #define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos)
|
| 1782 | #define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos))
|
| 1783 | #define GMAC_TBFR255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR255) MASK Register */
|
| 1784 |
|
| 1785 | /* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/ 32) 256 to 511Byte Frames Received Register -------- */
|
| 1786 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1787 | typedef union {
|
| 1788 | struct {
|
| 1789 | uint32_t NFRX:32; /*!< bit: 0..31 256 to 511 Byte Frames Received without Error */
|
| 1790 | } bit; /*!< Structure used for bit access */
|
| 1791 | uint32_t reg; /*!< Type used for register access */
|
| 1792 | } GMAC_TBFR511_Type;
|
| 1793 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1794 |
|
| 1795 | #define GMAC_TBFR511_OFFSET 0x174 /**< \brief (GMAC_TBFR511 offset) 256 to 511Byte Frames Received Register */
|
| 1796 | #define GMAC_TBFR511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR511 reset_value) 256 to 511Byte Frames Received Register */
|
| 1797 |
|
| 1798 | #define GMAC_TBFR511_NFRX_Pos 0 /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */
|
| 1799 | #define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos)
|
| 1800 | #define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos))
|
| 1801 | #define GMAC_TBFR511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR511) MASK Register */
|
| 1802 |
|
| 1803 | /* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/ 32) 512 to 1023 Byte Frames Received Register -------- */
|
| 1804 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1805 | typedef union {
|
| 1806 | struct {
|
| 1807 | uint32_t NFRX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Received without Error */
|
| 1808 | } bit; /*!< Structure used for bit access */
|
| 1809 | uint32_t reg; /*!< Type used for register access */
|
| 1810 | } GMAC_TBFR1023_Type;
|
| 1811 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1812 |
|
| 1813 | #define GMAC_TBFR1023_OFFSET 0x178 /**< \brief (GMAC_TBFR1023 offset) 512 to 1023 Byte Frames Received Register */
|
| 1814 | #define GMAC_TBFR1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1023 reset_value) 512 to 1023 Byte Frames Received Register */
|
| 1815 |
|
| 1816 | #define GMAC_TBFR1023_NFRX_Pos 0 /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */
|
| 1817 | #define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos)
|
| 1818 | #define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos))
|
| 1819 | #define GMAC_TBFR1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1023) MASK Register */
|
| 1820 |
|
| 1821 | /* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) (R/ 32) 1024 to 1518 Byte Frames Received Register -------- */
|
| 1822 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1823 | typedef union {
|
| 1824 | struct {
|
| 1825 | uint32_t NFRX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Received without Error */
|
| 1826 | } bit; /*!< Structure used for bit access */
|
| 1827 | uint32_t reg; /*!< Type used for register access */
|
| 1828 | } GMAC_TBFR1518_Type;
|
| 1829 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1830 |
|
| 1831 | #define GMAC_TBFR1518_OFFSET 0x17C /**< \brief (GMAC_TBFR1518 offset) 1024 to 1518 Byte Frames Received Register */
|
| 1832 | #define GMAC_TBFR1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1518 reset_value) 1024 to 1518 Byte Frames Received Register */
|
| 1833 |
|
| 1834 | #define GMAC_TBFR1518_NFRX_Pos 0 /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */
|
| 1835 | #define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos)
|
| 1836 | #define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos))
|
| 1837 | #define GMAC_TBFR1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1518) MASK Register */
|
| 1838 |
|
| 1839 | /* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/ 32) 1519 to Maximum Byte Frames Received Register -------- */
|
| 1840 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1841 | typedef union {
|
| 1842 | struct {
|
| 1843 | uint32_t NFRX:32; /*!< bit: 0..31 1519 to Maximum Byte Frames Received without Error */
|
| 1844 | } bit; /*!< Structure used for bit access */
|
| 1845 | uint32_t reg; /*!< Type used for register access */
|
| 1846 | } GMAC_TMXBFR_Type;
|
| 1847 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1848 |
|
| 1849 | #define GMAC_TMXBFR_OFFSET 0x180 /**< \brief (GMAC_TMXBFR offset) 1519 to Maximum Byte Frames Received Register */
|
| 1850 | #define GMAC_TMXBFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TMXBFR reset_value) 1519 to Maximum Byte Frames Received Register */
|
| 1851 |
|
| 1852 | #define GMAC_TMXBFR_NFRX_Pos 0 /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */
|
| 1853 | #define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos)
|
| 1854 | #define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos))
|
| 1855 | #define GMAC_TMXBFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TMXBFR) MASK Register */
|
| 1856 |
|
| 1857 | /* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/ 32) Undersize Frames Received Register -------- */
|
| 1858 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1859 | typedef union {
|
| 1860 | struct {
|
| 1861 | uint32_t UFRX:10; /*!< bit: 0.. 9 Undersize Frames Received */
|
| 1862 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1863 | } bit; /*!< Structure used for bit access */
|
| 1864 | uint32_t reg; /*!< Type used for register access */
|
| 1865 | } GMAC_UFR_Type;
|
| 1866 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1867 |
|
| 1868 | #define GMAC_UFR_OFFSET 0x184 /**< \brief (GMAC_UFR offset) Undersize Frames Received Register */
|
| 1869 | #define GMAC_UFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UFR reset_value) Undersize Frames Received Register */
|
| 1870 |
|
| 1871 | #define GMAC_UFR_UFRX_Pos 0 /**< \brief (GMAC_UFR) Undersize Frames Received */
|
| 1872 | #define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos)
|
| 1873 | #define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos))
|
| 1874 | #define GMAC_UFR_MASK _U_(0x000003FF) /**< \brief (GMAC_UFR) MASK Register */
|
| 1875 |
|
| 1876 | /* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/ 32) Oversize Frames Received Register -------- */
|
| 1877 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1878 | typedef union {
|
| 1879 | struct {
|
| 1880 | uint32_t OFRX:10; /*!< bit: 0.. 9 Oversized Frames Received */
|
| 1881 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1882 | } bit; /*!< Structure used for bit access */
|
| 1883 | uint32_t reg; /*!< Type used for register access */
|
| 1884 | } GMAC_OFR_Type;
|
| 1885 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1886 |
|
| 1887 | #define GMAC_OFR_OFFSET 0x188 /**< \brief (GMAC_OFR offset) Oversize Frames Received Register */
|
| 1888 | #define GMAC_OFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OFR reset_value) Oversize Frames Received Register */
|
| 1889 |
|
| 1890 | #define GMAC_OFR_OFRX_Pos 0 /**< \brief (GMAC_OFR) Oversized Frames Received */
|
| 1891 | #define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos)
|
| 1892 | #define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos))
|
| 1893 | #define GMAC_OFR_MASK _U_(0x000003FF) /**< \brief (GMAC_OFR) MASK Register */
|
| 1894 |
|
| 1895 | /* -------- GMAC_JR : (GMAC Offset: 0x18C) (R/ 32) Jabbers Received Register -------- */
|
| 1896 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1897 | typedef union {
|
| 1898 | struct {
|
| 1899 | uint32_t JRX:10; /*!< bit: 0.. 9 Jabbers Received */
|
| 1900 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1901 | } bit; /*!< Structure used for bit access */
|
| 1902 | uint32_t reg; /*!< Type used for register access */
|
| 1903 | } GMAC_JR_Type;
|
| 1904 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1905 |
|
| 1906 | #define GMAC_JR_OFFSET 0x18C /**< \brief (GMAC_JR offset) Jabbers Received Register */
|
| 1907 | #define GMAC_JR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_JR reset_value) Jabbers Received Register */
|
| 1908 |
|
| 1909 | #define GMAC_JR_JRX_Pos 0 /**< \brief (GMAC_JR) Jabbers Received */
|
| 1910 | #define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos)
|
| 1911 | #define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos))
|
| 1912 | #define GMAC_JR_MASK _U_(0x000003FF) /**< \brief (GMAC_JR) MASK Register */
|
| 1913 |
|
| 1914 | /* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/ 32) Frame Check Sequence Errors Register -------- */
|
| 1915 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1916 | typedef union {
|
| 1917 | struct {
|
| 1918 | uint32_t FCKR:10; /*!< bit: 0.. 9 Frame Check Sequence Errors */
|
| 1919 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1920 | } bit; /*!< Structure used for bit access */
|
| 1921 | uint32_t reg; /*!< Type used for register access */
|
| 1922 | } GMAC_FCSE_Type;
|
| 1923 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1924 |
|
| 1925 | #define GMAC_FCSE_OFFSET 0x190 /**< \brief (GMAC_FCSE offset) Frame Check Sequence Errors Register */
|
| 1926 | #define GMAC_FCSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FCSE reset_value) Frame Check Sequence Errors Register */
|
| 1927 |
|
| 1928 | #define GMAC_FCSE_FCKR_Pos 0 /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */
|
| 1929 | #define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos)
|
| 1930 | #define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos))
|
| 1931 | #define GMAC_FCSE_MASK _U_(0x000003FF) /**< \brief (GMAC_FCSE) MASK Register */
|
| 1932 |
|
| 1933 | /* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/ 32) Length Field Frame Errors Register -------- */
|
| 1934 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1935 | typedef union {
|
| 1936 | struct {
|
| 1937 | uint32_t LFER:10; /*!< bit: 0.. 9 Length Field Frame Errors */
|
| 1938 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1939 | } bit; /*!< Structure used for bit access */
|
| 1940 | uint32_t reg; /*!< Type used for register access */
|
| 1941 | } GMAC_LFFE_Type;
|
| 1942 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1943 |
|
| 1944 | #define GMAC_LFFE_OFFSET 0x194 /**< \brief (GMAC_LFFE offset) Length Field Frame Errors Register */
|
| 1945 | #define GMAC_LFFE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LFFE reset_value) Length Field Frame Errors Register */
|
| 1946 |
|
| 1947 | #define GMAC_LFFE_LFER_Pos 0 /**< \brief (GMAC_LFFE) Length Field Frame Errors */
|
| 1948 | #define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos)
|
| 1949 | #define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos))
|
| 1950 | #define GMAC_LFFE_MASK _U_(0x000003FF) /**< \brief (GMAC_LFFE) MASK Register */
|
| 1951 |
|
| 1952 | /* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/ 32) Receive Symbol Errors Register -------- */
|
| 1953 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1954 | typedef union {
|
| 1955 | struct {
|
| 1956 | uint32_t RXSE:10; /*!< bit: 0.. 9 Receive Symbol Errors */
|
| 1957 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1958 | } bit; /*!< Structure used for bit access */
|
| 1959 | uint32_t reg; /*!< Type used for register access */
|
| 1960 | } GMAC_RSE_Type;
|
| 1961 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1962 |
|
| 1963 | #define GMAC_RSE_OFFSET 0x198 /**< \brief (GMAC_RSE offset) Receive Symbol Errors Register */
|
| 1964 | #define GMAC_RSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSE reset_value) Receive Symbol Errors Register */
|
| 1965 |
|
| 1966 | #define GMAC_RSE_RXSE_Pos 0 /**< \brief (GMAC_RSE) Receive Symbol Errors */
|
| 1967 | #define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos)
|
| 1968 | #define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos))
|
| 1969 | #define GMAC_RSE_MASK _U_(0x000003FF) /**< \brief (GMAC_RSE) MASK Register */
|
| 1970 |
|
| 1971 | /* -------- GMAC_AE : (GMAC Offset: 0x19C) (R/ 32) Alignment Errors Register -------- */
|
| 1972 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1973 | typedef union {
|
| 1974 | struct {
|
| 1975 | uint32_t AER:10; /*!< bit: 0.. 9 Alignment Errors */
|
| 1976 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 1977 | } bit; /*!< Structure used for bit access */
|
| 1978 | uint32_t reg; /*!< Type used for register access */
|
| 1979 | } GMAC_AE_Type;
|
| 1980 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1981 |
|
| 1982 | #define GMAC_AE_OFFSET 0x19C /**< \brief (GMAC_AE offset) Alignment Errors Register */
|
| 1983 | #define GMAC_AE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_AE reset_value) Alignment Errors Register */
|
| 1984 |
|
| 1985 | #define GMAC_AE_AER_Pos 0 /**< \brief (GMAC_AE) Alignment Errors */
|
| 1986 | #define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos)
|
| 1987 | #define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos))
|
| 1988 | #define GMAC_AE_MASK _U_(0x000003FF) /**< \brief (GMAC_AE) MASK Register */
|
| 1989 |
|
| 1990 | /* -------- GMAC_RRE : (GMAC Offset: 0x1A0) (R/ 32) Receive Resource Errors Register -------- */
|
| 1991 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1992 | typedef union {
|
| 1993 | struct {
|
| 1994 | uint32_t RXRER:18; /*!< bit: 0..17 Receive Resource Errors */
|
| 1995 | uint32_t :14; /*!< bit: 18..31 Reserved */
|
| 1996 | } bit; /*!< Structure used for bit access */
|
| 1997 | uint32_t reg; /*!< Type used for register access */
|
| 1998 | } GMAC_RRE_Type;
|
| 1999 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2000 |
|
| 2001 | #define GMAC_RRE_OFFSET 0x1A0 /**< \brief (GMAC_RRE offset) Receive Resource Errors Register */
|
| 2002 | #define GMAC_RRE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RRE reset_value) Receive Resource Errors Register */
|
| 2003 |
|
| 2004 | #define GMAC_RRE_RXRER_Pos 0 /**< \brief (GMAC_RRE) Receive Resource Errors */
|
| 2005 | #define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos)
|
| 2006 | #define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos))
|
| 2007 | #define GMAC_RRE_MASK _U_(0x0003FFFF) /**< \brief (GMAC_RRE) MASK Register */
|
| 2008 |
|
| 2009 | /* -------- GMAC_ROE : (GMAC Offset: 0x1A4) (R/ 32) Receive Overrun Register -------- */
|
| 2010 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2011 | typedef union {
|
| 2012 | struct {
|
| 2013 | uint32_t RXOVR:10; /*!< bit: 0.. 9 Receive Overruns */
|
| 2014 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 2015 | } bit; /*!< Structure used for bit access */
|
| 2016 | uint32_t reg; /*!< Type used for register access */
|
| 2017 | } GMAC_ROE_Type;
|
| 2018 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2019 |
|
| 2020 | #define GMAC_ROE_OFFSET 0x1A4 /**< \brief (GMAC_ROE offset) Receive Overrun Register */
|
| 2021 | #define GMAC_ROE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ROE reset_value) Receive Overrun Register */
|
| 2022 |
|
| 2023 | #define GMAC_ROE_RXOVR_Pos 0 /**< \brief (GMAC_ROE) Receive Overruns */
|
| 2024 | #define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos)
|
| 2025 | #define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos))
|
| 2026 | #define GMAC_ROE_MASK _U_(0x000003FF) /**< \brief (GMAC_ROE) MASK Register */
|
| 2027 |
|
| 2028 | /* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) (R/ 32) IP Header Checksum Errors Register -------- */
|
| 2029 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2030 | typedef union {
|
| 2031 | struct {
|
| 2032 | uint32_t HCKER:8; /*!< bit: 0.. 7 IP Header Checksum Errors */
|
| 2033 | uint32_t :24; /*!< bit: 8..31 Reserved */
|
| 2034 | } bit; /*!< Structure used for bit access */
|
| 2035 | uint32_t reg; /*!< Type used for register access */
|
| 2036 | } GMAC_IHCE_Type;
|
| 2037 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2038 |
|
| 2039 | #define GMAC_IHCE_OFFSET 0x1A8 /**< \brief (GMAC_IHCE offset) IP Header Checksum Errors Register */
|
| 2040 | #define GMAC_IHCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IHCE reset_value) IP Header Checksum Errors Register */
|
| 2041 |
|
| 2042 | #define GMAC_IHCE_HCKER_Pos 0 /**< \brief (GMAC_IHCE) IP Header Checksum Errors */
|
| 2043 | #define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos)
|
| 2044 | #define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos))
|
| 2045 | #define GMAC_IHCE_MASK _U_(0x000000FF) /**< \brief (GMAC_IHCE) MASK Register */
|
| 2046 |
|
| 2047 | /* -------- GMAC_TCE : (GMAC Offset: 0x1AC) (R/ 32) TCP Checksum Errors Register -------- */
|
| 2048 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2049 | typedef union {
|
| 2050 | struct {
|
| 2051 | uint32_t TCKER:8; /*!< bit: 0.. 7 TCP Checksum Errors */
|
| 2052 | uint32_t :24; /*!< bit: 8..31 Reserved */
|
| 2053 | } bit; /*!< Structure used for bit access */
|
| 2054 | uint32_t reg; /*!< Type used for register access */
|
| 2055 | } GMAC_TCE_Type;
|
| 2056 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2057 |
|
| 2058 | #define GMAC_TCE_OFFSET 0x1AC /**< \brief (GMAC_TCE offset) TCP Checksum Errors Register */
|
| 2059 | #define GMAC_TCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TCE reset_value) TCP Checksum Errors Register */
|
| 2060 |
|
| 2061 | #define GMAC_TCE_TCKER_Pos 0 /**< \brief (GMAC_TCE) TCP Checksum Errors */
|
| 2062 | #define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos)
|
| 2063 | #define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos))
|
| 2064 | #define GMAC_TCE_MASK _U_(0x000000FF) /**< \brief (GMAC_TCE) MASK Register */
|
| 2065 |
|
| 2066 | /* -------- GMAC_UCE : (GMAC Offset: 0x1B0) (R/ 32) UDP Checksum Errors Register -------- */
|
| 2067 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2068 | typedef union {
|
| 2069 | struct {
|
| 2070 | uint32_t UCKER:8; /*!< bit: 0.. 7 UDP Checksum Errors */
|
| 2071 | uint32_t :24; /*!< bit: 8..31 Reserved */
|
| 2072 | } bit; /*!< Structure used for bit access */
|
| 2073 | uint32_t reg; /*!< Type used for register access */
|
| 2074 | } GMAC_UCE_Type;
|
| 2075 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2076 |
|
| 2077 | #define GMAC_UCE_OFFSET 0x1B0 /**< \brief (GMAC_UCE offset) UDP Checksum Errors Register */
|
| 2078 | #define GMAC_UCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UCE reset_value) UDP Checksum Errors Register */
|
| 2079 |
|
| 2080 | #define GMAC_UCE_UCKER_Pos 0 /**< \brief (GMAC_UCE) UDP Checksum Errors */
|
| 2081 | #define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos)
|
| 2082 | #define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos))
|
| 2083 | #define GMAC_UCE_MASK _U_(0x000000FF) /**< \brief (GMAC_UCE) MASK Register */
|
| 2084 |
|
| 2085 | /* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */
|
| 2086 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2087 | typedef union {
|
| 2088 | struct {
|
| 2089 | uint32_t LSBTIR:16; /*!< bit: 0..15 Lower Significant Bits of Timer Increment */
|
| 2090 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 2091 | } bit; /*!< Structure used for bit access */
|
| 2092 | uint32_t reg; /*!< Type used for register access */
|
| 2093 | } GMAC_TISUBN_Type;
|
| 2094 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2095 |
|
| 2096 | #define GMAC_TISUBN_OFFSET 0x1BC /**< \brief (GMAC_TISUBN offset) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
|
| 2097 | #define GMAC_TISUBN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TISUBN reset_value) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
|
| 2098 |
|
| 2099 | #define GMAC_TISUBN_LSBTIR_Pos 0 /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment */
|
| 2100 | #define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos)
|
| 2101 | #define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))
|
| 2102 | #define GMAC_TISUBN_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TISUBN) MASK Register */
|
| 2103 |
|
| 2104 | /* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */
|
| 2105 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2106 | typedef union {
|
| 2107 | struct {
|
| 2108 | uint32_t TCS:16; /*!< bit: 0..15 Timer Count in Seconds */
|
| 2109 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 2110 | } bit; /*!< Structure used for bit access */
|
| 2111 | uint32_t reg; /*!< Type used for register access */
|
| 2112 | } GMAC_TSH_Type;
|
| 2113 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2114 |
|
| 2115 | #define GMAC_TSH_OFFSET 0x1C0 /**< \brief (GMAC_TSH offset) 1588 Timer Seconds High [15:0] Register */
|
| 2116 | #define GMAC_TSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSH reset_value) 1588 Timer Seconds High [15:0] Register */
|
| 2117 |
|
| 2118 | #define GMAC_TSH_TCS_Pos 0 /**< \brief (GMAC_TSH) Timer Count in Seconds */
|
| 2119 | #define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos)
|
| 2120 | #define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))
|
| 2121 | #define GMAC_TSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TSH) MASK Register */
|
| 2122 |
|
| 2123 | /* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */
|
| 2124 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2125 | typedef union {
|
| 2126 | struct {
|
| 2127 | uint32_t VTS:32; /*!< bit: 0..31 Value of Timer Seconds Register Capture */
|
| 2128 | } bit; /*!< Structure used for bit access */
|
| 2129 | uint32_t reg; /*!< Type used for register access */
|
| 2130 | } GMAC_TSSSL_Type;
|
| 2131 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2132 |
|
| 2133 | #define GMAC_TSSSL_OFFSET 0x1C8 /**< \brief (GMAC_TSSSL offset) 1588 Timer Sync Strobe Seconds [31:0] Register */
|
| 2134 | #define GMAC_TSSSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSSL reset_value) 1588 Timer Sync Strobe Seconds [31:0] Register */
|
| 2135 |
|
| 2136 | #define GMAC_TSSSL_VTS_Pos 0 /**< \brief (GMAC_TSSSL) Value of Timer Seconds Register Capture */
|
| 2137 | #define GMAC_TSSSL_VTS_Msk (_U_(0xFFFFFFFF) << GMAC_TSSSL_VTS_Pos)
|
| 2138 | #define GMAC_TSSSL_VTS(value) (GMAC_TSSSL_VTS_Msk & ((value) << GMAC_TSSSL_VTS_Pos))
|
| 2139 | #define GMAC_TSSSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSSSL) MASK Register */
|
| 2140 |
|
| 2141 | /* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */
|
| 2142 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2143 | typedef union {
|
| 2144 | struct {
|
| 2145 | uint32_t VTN:30; /*!< bit: 0..29 Value Timer Nanoseconds Register Capture */
|
| 2146 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 2147 | } bit; /*!< Structure used for bit access */
|
| 2148 | uint32_t reg; /*!< Type used for register access */
|
| 2149 | } GMAC_TSSN_Type;
|
| 2150 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2151 |
|
| 2152 | #define GMAC_TSSN_OFFSET 0x1CC /**< \brief (GMAC_TSSN offset) 1588 Timer Sync Strobe Nanoseconds Register */
|
| 2153 | #define GMAC_TSSN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSN reset_value) 1588 Timer Sync Strobe Nanoseconds Register */
|
| 2154 |
|
| 2155 | #define GMAC_TSSN_VTN_Pos 0 /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */
|
| 2156 | #define GMAC_TSSN_VTN_Msk (_U_(0x3FFFFFFF) << GMAC_TSSN_VTN_Pos)
|
| 2157 | #define GMAC_TSSN_VTN(value) (GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))
|
| 2158 | #define GMAC_TSSN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TSSN) MASK Register */
|
| 2159 |
|
| 2160 | /* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */
|
| 2161 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2162 | typedef union {
|
| 2163 | struct {
|
| 2164 | uint32_t TCS:32; /*!< bit: 0..31 Timer Count in Seconds */
|
| 2165 | } bit; /*!< Structure used for bit access */
|
| 2166 | uint32_t reg; /*!< Type used for register access */
|
| 2167 | } GMAC_TSL_Type;
|
| 2168 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2169 |
|
| 2170 | #define GMAC_TSL_OFFSET 0x1D0 /**< \brief (GMAC_TSL offset) 1588 Timer Seconds [31:0] Register */
|
| 2171 | #define GMAC_TSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSL reset_value) 1588 Timer Seconds [31:0] Register */
|
| 2172 |
|
| 2173 | #define GMAC_TSL_TCS_Pos 0 /**< \brief (GMAC_TSL) Timer Count in Seconds */
|
| 2174 | #define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos)
|
| 2175 | #define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))
|
| 2176 | #define GMAC_TSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSL) MASK Register */
|
| 2177 |
|
| 2178 | /* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */
|
| 2179 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2180 | typedef union {
|
| 2181 | struct {
|
| 2182 | uint32_t TNS:30; /*!< bit: 0..29 Timer Count in Nanoseconds */
|
| 2183 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 2184 | } bit; /*!< Structure used for bit access */
|
| 2185 | uint32_t reg; /*!< Type used for register access */
|
| 2186 | } GMAC_TN_Type;
|
| 2187 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2188 |
|
| 2189 | #define GMAC_TN_OFFSET 0x1D4 /**< \brief (GMAC_TN offset) 1588 Timer Nanoseconds Register */
|
| 2190 | #define GMAC_TN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TN reset_value) 1588 Timer Nanoseconds Register */
|
| 2191 |
|
| 2192 | #define GMAC_TN_TNS_Pos 0 /**< \brief (GMAC_TN) Timer Count in Nanoseconds */
|
| 2193 | #define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos)
|
| 2194 | #define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))
|
| 2195 | #define GMAC_TN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TN) MASK Register */
|
| 2196 |
|
| 2197 | /* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */
|
| 2198 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2199 | typedef union {
|
| 2200 | struct {
|
| 2201 | uint32_t ITDT:30; /*!< bit: 0..29 Increment/Decrement */
|
| 2202 | uint32_t :1; /*!< bit: 30 Reserved */
|
| 2203 | uint32_t ADJ:1; /*!< bit: 31 Adjust 1588 Timer */
|
| 2204 | } bit; /*!< Structure used for bit access */
|
| 2205 | uint32_t reg; /*!< Type used for register access */
|
| 2206 | } GMAC_TA_Type;
|
| 2207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2208 |
|
| 2209 | #define GMAC_TA_OFFSET 0x1D8 /**< \brief (GMAC_TA offset) 1588 Timer Adjust Register */
|
| 2210 | #define GMAC_TA_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TA reset_value) 1588 Timer Adjust Register */
|
| 2211 |
|
| 2212 | #define GMAC_TA_ITDT_Pos 0 /**< \brief (GMAC_TA) Increment/Decrement */
|
| 2213 | #define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos)
|
| 2214 | #define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))
|
| 2215 | #define GMAC_TA_ADJ_Pos 31 /**< \brief (GMAC_TA) Adjust 1588 Timer */
|
| 2216 | #define GMAC_TA_ADJ (_U_(0x1) << GMAC_TA_ADJ_Pos)
|
| 2217 | #define GMAC_TA_MASK _U_(0xBFFFFFFF) /**< \brief (GMAC_TA) MASK Register */
|
| 2218 |
|
| 2219 | /* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */
|
| 2220 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2221 | typedef union {
|
| 2222 | struct {
|
| 2223 | uint32_t CNS:8; /*!< bit: 0.. 7 Count Nanoseconds */
|
| 2224 | uint32_t ACNS:8; /*!< bit: 8..15 Alternative Count Nanoseconds */
|
| 2225 | uint32_t NIT:8; /*!< bit: 16..23 Number of Increments */
|
| 2226 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 2227 | } bit; /*!< Structure used for bit access */
|
| 2228 | uint32_t reg; /*!< Type used for register access */
|
| 2229 | } GMAC_TI_Type;
|
| 2230 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2231 |
|
| 2232 | #define GMAC_TI_OFFSET 0x1DC /**< \brief (GMAC_TI offset) 1588 Timer Increment Register */
|
| 2233 | #define GMAC_TI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TI reset_value) 1588 Timer Increment Register */
|
| 2234 |
|
| 2235 | #define GMAC_TI_CNS_Pos 0 /**< \brief (GMAC_TI) Count Nanoseconds */
|
| 2236 | #define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos)
|
| 2237 | #define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))
|
| 2238 | #define GMAC_TI_ACNS_Pos 8 /**< \brief (GMAC_TI) Alternative Count Nanoseconds */
|
| 2239 | #define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos)
|
| 2240 | #define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))
|
| 2241 | #define GMAC_TI_NIT_Pos 16 /**< \brief (GMAC_TI) Number of Increments */
|
| 2242 | #define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos)
|
| 2243 | #define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))
|
| 2244 | #define GMAC_TI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TI) MASK Register */
|
| 2245 |
|
| 2246 | /* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) (R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */
|
| 2247 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2248 | typedef union {
|
| 2249 | struct {
|
| 2250 | uint32_t RUD:32; /*!< bit: 0..31 Register Update */
|
| 2251 | } bit; /*!< Structure used for bit access */
|
| 2252 | uint32_t reg; /*!< Type used for register access */
|
| 2253 | } GMAC_EFTSL_Type;
|
| 2254 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2255 |
|
| 2256 | #define GMAC_EFTSL_OFFSET 0x1E0 /**< \brief (GMAC_EFTSL offset) PTP Event Frame Transmitted Seconds Low Register */
|
| 2257 | #define GMAC_EFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSL reset_value) PTP Event Frame Transmitted Seconds Low Register */
|
| 2258 |
|
| 2259 | #define GMAC_EFTSL_RUD_Pos 0 /**< \brief (GMAC_EFTSL) Register Update */
|
| 2260 | #define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos)
|
| 2261 | #define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos))
|
| 2262 | #define GMAC_EFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFTSL) MASK Register */
|
| 2263 |
|
| 2264 | /* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) (R/ 32) PTP Event Frame Transmitted Nanoseconds -------- */
|
| 2265 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2266 | typedef union {
|
| 2267 | struct {
|
| 2268 | uint32_t RUD:30; /*!< bit: 0..29 Register Update */
|
| 2269 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 2270 | } bit; /*!< Structure used for bit access */
|
| 2271 | uint32_t reg; /*!< Type used for register access */
|
| 2272 | } GMAC_EFTN_Type;
|
| 2273 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2274 |
|
| 2275 | #define GMAC_EFTN_OFFSET 0x1E4 /**< \brief (GMAC_EFTN offset) PTP Event Frame Transmitted Nanoseconds */
|
| 2276 | #define GMAC_EFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTN reset_value) PTP Event Frame Transmitted Nanoseconds */
|
| 2277 |
|
| 2278 | #define GMAC_EFTN_RUD_Pos 0 /**< \brief (GMAC_EFTN) Register Update */
|
| 2279 | #define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos)
|
| 2280 | #define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos))
|
| 2281 | #define GMAC_EFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFTN) MASK Register */
|
| 2282 |
|
| 2283 | /* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) (R/ 32) PTP Event Frame Received Seconds Low Register -------- */
|
| 2284 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2285 | typedef union {
|
| 2286 | struct {
|
| 2287 | uint32_t RUD:32; /*!< bit: 0..31 Register Update */
|
| 2288 | } bit; /*!< Structure used for bit access */
|
| 2289 | uint32_t reg; /*!< Type used for register access */
|
| 2290 | } GMAC_EFRSL_Type;
|
| 2291 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2292 |
|
| 2293 | #define GMAC_EFRSL_OFFSET 0x1E8 /**< \brief (GMAC_EFRSL offset) PTP Event Frame Received Seconds Low Register */
|
| 2294 | #define GMAC_EFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSL reset_value) PTP Event Frame Received Seconds Low Register */
|
| 2295 |
|
| 2296 | #define GMAC_EFRSL_RUD_Pos 0 /**< \brief (GMAC_EFRSL) Register Update */
|
| 2297 | #define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos)
|
| 2298 | #define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos))
|
| 2299 | #define GMAC_EFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFRSL) MASK Register */
|
| 2300 |
|
| 2301 | /* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) (R/ 32) PTP Event Frame Received Nanoseconds -------- */
|
| 2302 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2303 | typedef union {
|
| 2304 | struct {
|
| 2305 | uint32_t RUD:30; /*!< bit: 0..29 Register Update */
|
| 2306 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 2307 | } bit; /*!< Structure used for bit access */
|
| 2308 | uint32_t reg; /*!< Type used for register access */
|
| 2309 | } GMAC_EFRN_Type;
|
| 2310 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2311 |
|
| 2312 | #define GMAC_EFRN_OFFSET 0x1EC /**< \brief (GMAC_EFRN offset) PTP Event Frame Received Nanoseconds */
|
| 2313 | #define GMAC_EFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRN reset_value) PTP Event Frame Received Nanoseconds */
|
| 2314 |
|
| 2315 | #define GMAC_EFRN_RUD_Pos 0 /**< \brief (GMAC_EFRN) Register Update */
|
| 2316 | #define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos)
|
| 2317 | #define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos))
|
| 2318 | #define GMAC_EFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFRN) MASK Register */
|
| 2319 |
|
| 2320 | /* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
|
| 2321 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2322 | typedef union {
|
| 2323 | struct {
|
| 2324 | uint32_t RUD:32; /*!< bit: 0..31 Register Update */
|
| 2325 | } bit; /*!< Structure used for bit access */
|
| 2326 | uint32_t reg; /*!< Type used for register access */
|
| 2327 | } GMAC_PEFTSL_Type;
|
| 2328 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2329 |
|
| 2330 | #define GMAC_PEFTSL_OFFSET 0x1F0 /**< \brief (GMAC_PEFTSL offset) PTP Peer Event Frame Transmitted Seconds Low Register */
|
| 2331 | #define GMAC_PEFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSL reset_value) PTP Peer Event Frame Transmitted Seconds Low Register */
|
| 2332 |
|
| 2333 | #define GMAC_PEFTSL_RUD_Pos 0 /**< \brief (GMAC_PEFTSL) Register Update */
|
| 2334 | #define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos)
|
| 2335 | #define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos))
|
| 2336 | #define GMAC_PEFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFTSL) MASK Register */
|
| 2337 |
|
| 2338 | /* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds -------- */
|
| 2339 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2340 | typedef union {
|
| 2341 | struct {
|
| 2342 | uint32_t RUD:30; /*!< bit: 0..29 Register Update */
|
| 2343 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 2344 | } bit; /*!< Structure used for bit access */
|
| 2345 | uint32_t reg; /*!< Type used for register access */
|
| 2346 | } GMAC_PEFTN_Type;
|
| 2347 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2348 |
|
| 2349 | #define GMAC_PEFTN_OFFSET 0x1F4 /**< \brief (GMAC_PEFTN offset) PTP Peer Event Frame Transmitted Nanoseconds */
|
| 2350 | #define GMAC_PEFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTN reset_value) PTP Peer Event Frame Transmitted Nanoseconds */
|
| 2351 |
|
| 2352 | #define GMAC_PEFTN_RUD_Pos 0 /**< \brief (GMAC_PEFTN) Register Update */
|
| 2353 | #define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos)
|
| 2354 | #define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos))
|
| 2355 | #define GMAC_PEFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFTN) MASK Register */
|
| 2356 |
|
| 2357 | /* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) (R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */
|
| 2358 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2359 | typedef union {
|
| 2360 | struct {
|
| 2361 | uint32_t RUD:32; /*!< bit: 0..31 Register Update */
|
| 2362 | } bit; /*!< Structure used for bit access */
|
| 2363 | uint32_t reg; /*!< Type used for register access */
|
| 2364 | } GMAC_PEFRSL_Type;
|
| 2365 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2366 |
|
| 2367 | #define GMAC_PEFRSL_OFFSET 0x1F8 /**< \brief (GMAC_PEFRSL offset) PTP Peer Event Frame Received Seconds Low Register */
|
| 2368 | #define GMAC_PEFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSL reset_value) PTP Peer Event Frame Received Seconds Low Register */
|
| 2369 |
|
| 2370 | #define GMAC_PEFRSL_RUD_Pos 0 /**< \brief (GMAC_PEFRSL) Register Update */
|
| 2371 | #define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos)
|
| 2372 | #define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos))
|
| 2373 | #define GMAC_PEFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFRSL) MASK Register */
|
| 2374 |
|
| 2375 | /* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) (R/ 32) PTP Peer Event Frame Received Nanoseconds -------- */
|
| 2376 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2377 | typedef union {
|
| 2378 | struct {
|
| 2379 | uint32_t RUD:30; /*!< bit: 0..29 Register Update */
|
| 2380 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 2381 | } bit; /*!< Structure used for bit access */
|
| 2382 | uint32_t reg; /*!< Type used for register access */
|
| 2383 | } GMAC_PEFRN_Type;
|
| 2384 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2385 |
|
| 2386 | #define GMAC_PEFRN_OFFSET 0x1FC /**< \brief (GMAC_PEFRN offset) PTP Peer Event Frame Received Nanoseconds */
|
| 2387 | #define GMAC_PEFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRN reset_value) PTP Peer Event Frame Received Nanoseconds */
|
| 2388 |
|
| 2389 | #define GMAC_PEFRN_RUD_Pos 0 /**< \brief (GMAC_PEFRN) Register Update */
|
| 2390 | #define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos)
|
| 2391 | #define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos))
|
| 2392 | #define GMAC_PEFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFRN) MASK Register */
|
| 2393 |
|
| 2394 | /* -------- GMAC_RLPITR : (GMAC Offset: 0x270) (R/ 32) Receive LPI transition Register -------- */
|
| 2395 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2396 | typedef union {
|
| 2397 | struct {
|
| 2398 | uint32_t RLPITR:16; /*!< bit: 0..15 Count number of times transition from rx normal idle to low power idle */
|
| 2399 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 2400 | } bit; /*!< Structure used for bit access */
|
| 2401 | uint32_t reg; /*!< Type used for register access */
|
| 2402 | } GMAC_RLPITR_Type;
|
| 2403 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2404 |
|
| 2405 | #define GMAC_RLPITR_OFFSET 0x270 /**< \brief (GMAC_RLPITR offset) Receive LPI transition Register */
|
| 2406 | #define GMAC_RLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITR reset_value) Receive LPI transition Register */
|
| 2407 |
|
| 2408 | #define GMAC_RLPITR_RLPITR_Pos 0 /**< \brief (GMAC_RLPITR) Count number of times transition from rx normal idle to low power idle */
|
| 2409 | #define GMAC_RLPITR_RLPITR_Msk (_U_(0xFFFF) << GMAC_RLPITR_RLPITR_Pos)
|
| 2410 | #define GMAC_RLPITR_RLPITR(value) (GMAC_RLPITR_RLPITR_Msk & ((value) << GMAC_RLPITR_RLPITR_Pos))
|
| 2411 | #define GMAC_RLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RLPITR) MASK Register */
|
| 2412 |
|
| 2413 | /* -------- GMAC_RLPITI : (GMAC Offset: 0x274) (R/ 32) Receive LPI Time Register -------- */
|
| 2414 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2415 | typedef union {
|
| 2416 | struct {
|
| 2417 | uint32_t RLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
|
| 2418 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 2419 | } bit; /*!< Structure used for bit access */
|
| 2420 | uint32_t reg; /*!< Type used for register access */
|
| 2421 | } GMAC_RLPITI_Type;
|
| 2422 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2423 |
|
| 2424 | #define GMAC_RLPITI_OFFSET 0x274 /**< \brief (GMAC_RLPITI offset) Receive LPI Time Register */
|
| 2425 | #define GMAC_RLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITI reset_value) Receive LPI Time Register */
|
| 2426 |
|
| 2427 | #define GMAC_RLPITI_RLPITI_Pos 0 /**< \brief (GMAC_RLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
|
| 2428 | #define GMAC_RLPITI_RLPITI_Msk (_U_(0xFFFFFF) << GMAC_RLPITI_RLPITI_Pos)
|
| 2429 | #define GMAC_RLPITI_RLPITI(value) (GMAC_RLPITI_RLPITI_Msk & ((value) << GMAC_RLPITI_RLPITI_Pos))
|
| 2430 | #define GMAC_RLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_RLPITI) MASK Register */
|
| 2431 |
|
| 2432 | /* -------- GMAC_TLPITR : (GMAC Offset: 0x278) (R/ 32) Receive LPI transition Register -------- */
|
| 2433 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2434 | typedef union {
|
| 2435 | struct {
|
| 2436 | uint32_t TLPITR:16; /*!< bit: 0..15 Count number of times enable LPI tx bit 20 goes from low to high */
|
| 2437 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 2438 | } bit; /*!< Structure used for bit access */
|
| 2439 | uint32_t reg; /*!< Type used for register access */
|
| 2440 | } GMAC_TLPITR_Type;
|
| 2441 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2442 |
|
| 2443 | #define GMAC_TLPITR_OFFSET 0x278 /**< \brief (GMAC_TLPITR offset) Receive LPI transition Register */
|
| 2444 | #define GMAC_TLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITR reset_value) Receive LPI transition Register */
|
| 2445 |
|
| 2446 | #define GMAC_TLPITR_TLPITR_Pos 0 /**< \brief (GMAC_TLPITR) Count number of times enable LPI tx bit 20 goes from low to high */
|
| 2447 | #define GMAC_TLPITR_TLPITR_Msk (_U_(0xFFFF) << GMAC_TLPITR_TLPITR_Pos)
|
| 2448 | #define GMAC_TLPITR_TLPITR(value) (GMAC_TLPITR_TLPITR_Msk & ((value) << GMAC_TLPITR_TLPITR_Pos))
|
| 2449 | #define GMAC_TLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TLPITR) MASK Register */
|
| 2450 |
|
| 2451 | /* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) (R/ 32) Receive LPI Time Register -------- */
|
| 2452 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2453 | typedef union {
|
| 2454 | struct {
|
| 2455 | uint32_t TLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
|
| 2456 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 2457 | } bit; /*!< Structure used for bit access */
|
| 2458 | uint32_t reg; /*!< Type used for register access */
|
| 2459 | } GMAC_TLPITI_Type;
|
| 2460 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2461 |
|
| 2462 | #define GMAC_TLPITI_OFFSET 0x27C /**< \brief (GMAC_TLPITI offset) Receive LPI Time Register */
|
| 2463 | #define GMAC_TLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITI reset_value) Receive LPI Time Register */
|
| 2464 |
|
| 2465 | #define GMAC_TLPITI_TLPITI_Pos 0 /**< \brief (GMAC_TLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
|
| 2466 | #define GMAC_TLPITI_TLPITI_Msk (_U_(0xFFFFFF) << GMAC_TLPITI_TLPITI_Pos)
|
| 2467 | #define GMAC_TLPITI_TLPITI(value) (GMAC_TLPITI_TLPITI_Msk & ((value) << GMAC_TLPITI_TLPITI_Pos))
|
| 2468 | #define GMAC_TLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TLPITI) MASK Register */
|
| 2469 |
|
| 2470 | /** \brief GmacSa hardware registers */
|
| 2471 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2472 | typedef struct {
|
| 2473 | __IO GMAC_SAB_Type SAB; /**< \brief Offset: 0x000 (R/W 32) Specific Address Bottom [31:0] Register */
|
| 2474 | __IO GMAC_SAT_Type SAT; /**< \brief Offset: 0x004 (R/W 32) Specific Address Top [47:32] Register */
|
| 2475 | } GmacSa;
|
| 2476 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2477 |
|
| 2478 | /** \brief GMAC hardware registers */
|
| 2479 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2480 | typedef struct {
|
| 2481 | __IO GMAC_NCR_Type NCR; /**< \brief Offset: 0x000 (R/W 32) Network Control Register */
|
| 2482 | __IO GMAC_NCFGR_Type NCFGR; /**< \brief Offset: 0x004 (R/W 32) Network Configuration Register */
|
| 2483 | __I GMAC_NSR_Type NSR; /**< \brief Offset: 0x008 (R/ 32) Network Status Register */
|
| 2484 | __IO GMAC_UR_Type UR; /**< \brief Offset: 0x00C (R/W 32) User Register */
|
| 2485 | __IO GMAC_DCFGR_Type DCFGR; /**< \brief Offset: 0x010 (R/W 32) DMA Configuration Register */
|
| 2486 | __IO GMAC_TSR_Type TSR; /**< \brief Offset: 0x014 (R/W 32) Transmit Status Register */
|
| 2487 | __IO GMAC_RBQB_Type RBQB; /**< \brief Offset: 0x018 (R/W 32) Receive Buffer Queue Base Address */
|
| 2488 | __IO GMAC_TBQB_Type TBQB; /**< \brief Offset: 0x01C (R/W 32) Transmit Buffer Queue Base Address */
|
| 2489 | __IO GMAC_RSR_Type RSR; /**< \brief Offset: 0x020 (R/W 32) Receive Status Register */
|
| 2490 | __IO GMAC_ISR_Type ISR; /**< \brief Offset: 0x024 (R/W 32) Interrupt Status Register */
|
| 2491 | __O GMAC_IER_Type IER; /**< \brief Offset: 0x028 ( /W 32) Interrupt Enable Register */
|
| 2492 | __O GMAC_IDR_Type IDR; /**< \brief Offset: 0x02C ( /W 32) Interrupt Disable Register */
|
| 2493 | __I GMAC_IMR_Type IMR; /**< \brief Offset: 0x030 (R/ 32) Interrupt Mask Register */
|
| 2494 | __IO GMAC_MAN_Type MAN; /**< \brief Offset: 0x034 (R/W 32) PHY Maintenance Register */
|
| 2495 | __I GMAC_RPQ_Type RPQ; /**< \brief Offset: 0x038 (R/ 32) Received Pause Quantum Register */
|
| 2496 | __IO GMAC_TPQ_Type TPQ; /**< \brief Offset: 0x03C (R/W 32) Transmit Pause Quantum Register */
|
| 2497 | __IO GMAC_TPSF_Type TPSF; /**< \brief Offset: 0x040 (R/W 32) TX partial store and forward Register */
|
| 2498 | __IO GMAC_RPSF_Type RPSF; /**< \brief Offset: 0x044 (R/W 32) RX partial store and forward Register */
|
| 2499 | __IO GMAC_RJFML_Type RJFML; /**< \brief Offset: 0x048 (R/W 32) RX Jumbo Frame Max Length Register */
|
| 2500 | RoReg8 Reserved1[0x34];
|
| 2501 | __IO GMAC_HRB_Type HRB; /**< \brief Offset: 0x080 (R/W 32) Hash Register Bottom [31:0] */
|
| 2502 | __IO GMAC_HRT_Type HRT; /**< \brief Offset: 0x084 (R/W 32) Hash Register Top [63:32] */
|
| 2503 | GmacSa Sa[4]; /**< \brief Offset: 0x088 GmacSa groups */
|
| 2504 | __IO GMAC_TIDM_Type TIDM[4]; /**< \brief Offset: 0x0A8 (R/W 32) Type ID Match Register */
|
| 2505 | __IO GMAC_WOL_Type WOL; /**< \brief Offset: 0x0B8 (R/W 32) Wake on LAN */
|
| 2506 | __IO GMAC_IPGS_Type IPGS; /**< \brief Offset: 0x0BC (R/W 32) IPG Stretch Register */
|
| 2507 | __IO GMAC_SVLAN_Type SVLAN; /**< \brief Offset: 0x0C0 (R/W 32) Stacked VLAN Register */
|
| 2508 | __IO GMAC_TPFCP_Type TPFCP; /**< \brief Offset: 0x0C4 (R/W 32) Transmit PFC Pause Register */
|
| 2509 | __IO GMAC_SAMB1_Type SAMB1; /**< \brief Offset: 0x0C8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register */
|
| 2510 | __IO GMAC_SAMT1_Type SAMT1; /**< \brief Offset: 0x0CC (R/W 32) Specific Address 1 Mask Top [47:32] Register */
|
| 2511 | RoReg8 Reserved2[0xC];
|
| 2512 | __IO GMAC_NSC_Type NSC; /**< \brief Offset: 0x0DC (R/W 32) Tsu timer comparison nanoseconds Register */
|
| 2513 | __IO GMAC_SCL_Type SCL; /**< \brief Offset: 0x0E0 (R/W 32) Tsu timer second comparison Register */
|
| 2514 | __IO GMAC_SCH_Type SCH; /**< \brief Offset: 0x0E4 (R/W 32) Tsu timer second comparison Register */
|
| 2515 | __I GMAC_EFTSH_Type EFTSH; /**< \brief Offset: 0x0E8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */
|
| 2516 | __I GMAC_EFRSH_Type EFRSH; /**< \brief Offset: 0x0EC (R/ 32) PTP Event Frame Received Seconds High Register */
|
| 2517 | __I GMAC_PEFTSH_Type PEFTSH; /**< \brief Offset: 0x0F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */
|
| 2518 | __I GMAC_PEFRSH_Type PEFRSH; /**< \brief Offset: 0x0F4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */
|
| 2519 | RoReg8 Reserved3[0x8];
|
| 2520 | __I GMAC_OTLO_Type OTLO; /**< \brief Offset: 0x100 (R/ 32) Octets Transmitted [31:0] Register */
|
| 2521 | __I GMAC_OTHI_Type OTHI; /**< \brief Offset: 0x104 (R/ 32) Octets Transmitted [47:32] Register */
|
| 2522 | __I GMAC_FT_Type FT; /**< \brief Offset: 0x108 (R/ 32) Frames Transmitted Register */
|
| 2523 | __I GMAC_BCFT_Type BCFT; /**< \brief Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */
|
| 2524 | __I GMAC_MFT_Type MFT; /**< \brief Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */
|
| 2525 | __I GMAC_PFT_Type PFT; /**< \brief Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */
|
| 2526 | __I GMAC_BFT64_Type BFT64; /**< \brief Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */
|
| 2527 | __I GMAC_TBFT127_Type TBFT127; /**< \brief Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */
|
| 2528 | __I GMAC_TBFT255_Type TBFT255; /**< \brief Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */
|
| 2529 | __I GMAC_TBFT511_Type TBFT511; /**< \brief Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */
|
| 2530 | __I GMAC_TBFT1023_Type TBFT1023; /**< \brief Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */
|
| 2531 | __I GMAC_TBFT1518_Type TBFT1518; /**< \brief Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */
|
| 2532 | __I GMAC_GTBFT1518_Type GTBFT1518; /**< \brief Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */
|
| 2533 | __I GMAC_TUR_Type TUR; /**< \brief Offset: 0x134 (R/ 32) Transmit Underruns Register */
|
| 2534 | __I GMAC_SCF_Type SCF; /**< \brief Offset: 0x138 (R/ 32) Single Collision Frames Register */
|
| 2535 | __I GMAC_MCF_Type MCF; /**< \brief Offset: 0x13C (R/ 32) Multiple Collision Frames Register */
|
| 2536 | __I GMAC_EC_Type EC; /**< \brief Offset: 0x140 (R/ 32) Excessive Collisions Register */
|
| 2537 | __I GMAC_LC_Type LC; /**< \brief Offset: 0x144 (R/ 32) Late Collisions Register */
|
| 2538 | __I GMAC_DTF_Type DTF; /**< \brief Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */
|
| 2539 | __I GMAC_CSE_Type CSE; /**< \brief Offset: 0x14C (R/ 32) Carrier Sense Errors Register */
|
| 2540 | __I GMAC_ORLO_Type ORLO; /**< \brief Offset: 0x150 (R/ 32) Octets Received [31:0] Received */
|
| 2541 | __I GMAC_ORHI_Type ORHI; /**< \brief Offset: 0x154 (R/ 32) Octets Received [47:32] Received */
|
| 2542 | __I GMAC_FR_Type FR; /**< \brief Offset: 0x158 (R/ 32) Frames Received Register */
|
| 2543 | __I GMAC_BCFR_Type BCFR; /**< \brief Offset: 0x15C (R/ 32) Broadcast Frames Received Register */
|
| 2544 | __I GMAC_MFR_Type MFR; /**< \brief Offset: 0x160 (R/ 32) Multicast Frames Received Register */
|
| 2545 | __I GMAC_PFR_Type PFR; /**< \brief Offset: 0x164 (R/ 32) Pause Frames Received Register */
|
| 2546 | __I GMAC_BFR64_Type BFR64; /**< \brief Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */
|
| 2547 | __I GMAC_TBFR127_Type TBFR127; /**< \brief Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */
|
| 2548 | __I GMAC_TBFR255_Type TBFR255; /**< \brief Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */
|
| 2549 | __I GMAC_TBFR511_Type TBFR511; /**< \brief Offset: 0x174 (R/ 32) 256 to 511Byte Frames Received Register */
|
| 2550 | __I GMAC_TBFR1023_Type TBFR1023; /**< \brief Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */
|
| 2551 | __I GMAC_TBFR1518_Type TBFR1518; /**< \brief Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */
|
| 2552 | __I GMAC_TMXBFR_Type TMXBFR; /**< \brief Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */
|
| 2553 | __I GMAC_UFR_Type UFR; /**< \brief Offset: 0x184 (R/ 32) Undersize Frames Received Register */
|
| 2554 | __I GMAC_OFR_Type OFR; /**< \brief Offset: 0x188 (R/ 32) Oversize Frames Received Register */
|
| 2555 | __I GMAC_JR_Type JR; /**< \brief Offset: 0x18C (R/ 32) Jabbers Received Register */
|
| 2556 | __I GMAC_FCSE_Type FCSE; /**< \brief Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */
|
| 2557 | __I GMAC_LFFE_Type LFFE; /**< \brief Offset: 0x194 (R/ 32) Length Field Frame Errors Register */
|
| 2558 | __I GMAC_RSE_Type RSE; /**< \brief Offset: 0x198 (R/ 32) Receive Symbol Errors Register */
|
| 2559 | __I GMAC_AE_Type AE; /**< \brief Offset: 0x19C (R/ 32) Alignment Errors Register */
|
| 2560 | __I GMAC_RRE_Type RRE; /**< \brief Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */
|
| 2561 | __I GMAC_ROE_Type ROE; /**< \brief Offset: 0x1A4 (R/ 32) Receive Overrun Register */
|
| 2562 | __I GMAC_IHCE_Type IHCE; /**< \brief Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */
|
| 2563 | __I GMAC_TCE_Type TCE; /**< \brief Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */
|
| 2564 | __I GMAC_UCE_Type UCE; /**< \brief Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */
|
| 2565 | RoReg8 Reserved4[0x8];
|
| 2566 | __IO GMAC_TISUBN_Type TISUBN; /**< \brief Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
|
| 2567 | __IO GMAC_TSH_Type TSH; /**< \brief Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register */
|
| 2568 | RoReg8 Reserved5[0x4];
|
| 2569 | __IO GMAC_TSSSL_Type TSSSL; /**< \brief Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register */
|
| 2570 | __IO GMAC_TSSN_Type TSSN; /**< \brief Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register */
|
| 2571 | __IO GMAC_TSL_Type TSL; /**< \brief Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register */
|
| 2572 | __IO GMAC_TN_Type TN; /**< \brief Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */
|
| 2573 | __O GMAC_TA_Type TA; /**< \brief Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */
|
| 2574 | __IO GMAC_TI_Type TI; /**< \brief Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */
|
| 2575 | __I GMAC_EFTSL_Type EFTSL; /**< \brief Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */
|
| 2576 | __I GMAC_EFTN_Type EFTN; /**< \brief Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds */
|
| 2577 | __I GMAC_EFRSL_Type EFRSL; /**< \brief Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */
|
| 2578 | __I GMAC_EFRN_Type EFRN; /**< \brief Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds */
|
| 2579 | __I GMAC_PEFTSL_Type PEFTSL; /**< \brief Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */
|
| 2580 | __I GMAC_PEFTN_Type PEFTN; /**< \brief Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds */
|
| 2581 | __I GMAC_PEFRSL_Type PEFRSL; /**< \brief Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */
|
| 2582 | __I GMAC_PEFRN_Type PEFRN; /**< \brief Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds */
|
| 2583 | RoReg8 Reserved6[0x70];
|
| 2584 | __I GMAC_RLPITR_Type RLPITR; /**< \brief Offset: 0x270 (R/ 32) Receive LPI transition Register */
|
| 2585 | __I GMAC_RLPITI_Type RLPITI; /**< \brief Offset: 0x274 (R/ 32) Receive LPI Time Register */
|
| 2586 | __I GMAC_TLPITR_Type TLPITR; /**< \brief Offset: 0x278 (R/ 32) Receive LPI transition Register */
|
| 2587 | __I GMAC_TLPITI_Type TLPITI; /**< \brief Offset: 0x27C (R/ 32) Receive LPI Time Register */
|
| 2588 | } Gmac;
|
| 2589 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2590 |
|
| 2591 | /*@}*/
|
| 2592 |
|
| 2593 | #endif /* _SAME54_GMAC_COMPONENT_ */
|