Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for CAN
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_CAN_COMPONENT_
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| 31 | #define _SAME54_CAN_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR CAN */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_CAN Control Area Network */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define CAN_U2003
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| 40 | #define REV_CAN 0x321
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| 41 |
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| 42 | /* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint32_t :20; /*!< bit: 0..19 Reserved */
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| 47 | uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */
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| 48 | uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */
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| 49 | uint32_t REL:4; /*!< bit: 28..31 Core Release */
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| 50 | } bit; /*!< Structure used for bit access */
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| 51 | uint32_t reg; /*!< Type used for register access */
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| 52 | } CAN_CREL_Type;
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| 53 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 54 |
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| 55 | #define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */
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| 56 | #define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */
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| 57 |
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| 58 | #define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */
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| 59 | #define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos)
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| 60 | #define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos))
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| 61 | #define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */
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| 62 | #define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos)
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| 63 | #define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos))
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| 64 | #define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */
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| 65 | #define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos)
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| 66 | #define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos))
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| 67 | #define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */
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| 68 |
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| 69 | /* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */
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| 70 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 71 | typedef union {
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| 72 | struct {
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| 73 | uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */
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| 74 | } bit; /*!< Structure used for bit access */
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| 75 | uint32_t reg; /*!< Type used for register access */
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| 76 | } CAN_ENDN_Type;
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| 77 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 78 |
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| 79 | #define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */
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| 80 | #define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */
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| 81 |
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| 82 | #define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */
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| 83 | #define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos)
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| 84 | #define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos))
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| 85 | #define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */
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| 86 |
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| 87 | /* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */
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| 88 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 89 | typedef union {
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| 90 | struct {
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| 91 | uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */
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| 92 | uint32_t :30; /*!< bit: 2..31 Reserved */
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| 93 | } bit; /*!< Structure used for bit access */
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| 94 | uint32_t reg; /*!< Type used for register access */
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| 95 | } CAN_MRCFG_Type;
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| 96 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 97 |
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| 98 | #define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */
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| 99 | #define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */
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| 100 |
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| 101 | #define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */
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| 102 | #define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos)
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| 103 | #define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos))
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| 104 | #define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */
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| 105 | #define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */
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| 106 | #define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */
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| 107 | #define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */
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| 108 | #define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos)
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| 109 | #define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos)
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| 110 | #define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos)
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| 111 | #define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos)
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| 112 | #define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */
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| 113 |
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| 114 | /* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */
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| 115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 116 | typedef union {
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| 117 | struct {
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| 118 | uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */
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| 119 | uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */
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| 120 | uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */
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| 121 | uint32_t :3; /*!< bit: 13..15 Reserved */
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| 122 | uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */
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| 123 | uint32_t :2; /*!< bit: 21..22 Reserved */
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| 124 | uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */
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| 125 | uint32_t :8; /*!< bit: 24..31 Reserved */
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| 126 | } bit; /*!< Structure used for bit access */
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| 127 | uint32_t reg; /*!< Type used for register access */
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| 128 | } CAN_DBTP_Type;
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| 129 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 130 |
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| 131 | #define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */
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| 132 | #define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */
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| 133 |
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| 134 | #define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */
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| 135 | #define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos)
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| 136 | #define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos))
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| 137 | #define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */
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| 138 | #define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos)
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| 139 | #define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos))
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| 140 | #define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */
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| 141 | #define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos)
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| 142 | #define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos))
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| 143 | #define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */
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| 144 | #define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos)
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| 145 | #define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos))
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| 146 | #define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */
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| 147 | #define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos)
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| 148 | #define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */
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| 149 |
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| 150 | /* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */
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| 151 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 152 | typedef union {
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| 153 | struct {
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| 154 | uint32_t :4; /*!< bit: 0.. 3 Reserved */
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| 155 | uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */
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| 156 | uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */
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| 157 | uint32_t RX:1; /*!< bit: 7 Receive Pin */
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| 158 | uint32_t :24; /*!< bit: 8..31 Reserved */
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| 159 | } bit; /*!< Structure used for bit access */
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| 160 | uint32_t reg; /*!< Type used for register access */
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| 161 | } CAN_TEST_Type;
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| 162 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 163 |
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| 164 | #define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */
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| 165 | #define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */
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| 166 |
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| 167 | #define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */
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| 168 | #define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos)
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| 169 | #define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */
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| 170 | #define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos)
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| 171 | #define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos))
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| 172 | #define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */
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| 173 | #define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */
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| 174 | #define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */
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| 175 | #define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */
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| 176 | #define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos)
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| 177 | #define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos)
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| 178 | #define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos)
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| 179 | #define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos)
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| 180 | #define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */
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| 181 | #define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos)
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| 182 | #define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */
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| 183 |
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| 184 | /* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */
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| 185 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 186 | typedef union {
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| 187 | struct {
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| 188 | uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */
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| 189 | uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */
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| 190 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 191 | } bit; /*!< Structure used for bit access */
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| 192 | uint32_t reg; /*!< Type used for register access */
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| 193 | } CAN_RWD_Type;
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| 194 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 195 |
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| 196 | #define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */
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| 197 | #define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */
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| 198 |
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| 199 | #define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */
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| 200 | #define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos)
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| 201 | #define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos))
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| 202 | #define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */
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| 203 | #define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos)
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| 204 | #define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos))
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| 205 | #define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */
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| 206 |
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| 207 | /* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */
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| 208 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 209 | typedef union {
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| 210 | struct {
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| 211 | uint32_t INIT:1; /*!< bit: 0 Initialization */
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| 212 | uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */
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| 213 | uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */
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| 214 | uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */
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| 215 | uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */
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| 216 | uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */
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| 217 | uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */
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| 218 | uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */
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| 219 | uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */
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| 220 | uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */
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| 221 | uint32_t :2; /*!< bit: 10..11 Reserved */
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| 222 | uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */
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| 223 | uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */
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| 224 | uint32_t TXP:1; /*!< bit: 14 Transmit Pause */
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| 225 | uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */
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| 226 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 227 | } bit; /*!< Structure used for bit access */
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| 228 | uint32_t reg; /*!< Type used for register access */
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| 229 | } CAN_CCCR_Type;
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| 230 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 231 |
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| 232 | #define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */
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| 233 | #define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */
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| 234 |
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| 235 | #define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */
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| 236 | #define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos)
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| 237 | #define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */
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| 238 | #define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos)
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| 239 | #define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */
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| 240 | #define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos)
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| 241 | #define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */
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| 242 | #define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos)
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| 243 | #define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */
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| 244 | #define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos)
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| 245 | #define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */
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| 246 | #define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos)
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| 247 | #define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */
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| 248 | #define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos)
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| 249 | #define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */
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| 250 | #define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos)
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| 251 | #define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */
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| 252 | #define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos)
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| 253 | #define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */
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| 254 | #define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos)
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| 255 | #define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */
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| 256 | #define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos)
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| 257 | #define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */
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| 258 | #define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos)
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| 259 | #define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */
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| 260 | #define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos)
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| 261 | #define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */
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| 262 | #define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos)
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| 263 | #define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */
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| 264 |
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| 265 | /* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
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| 266 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 267 | typedef union {
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| 268 | struct {
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| 269 | uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */
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| 270 | uint32_t :1; /*!< bit: 7 Reserved */
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| 271 | uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */
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| 272 | uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */
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| 273 | uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */
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| 274 | } bit; /*!< Structure used for bit access */
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| 275 | uint32_t reg; /*!< Type used for register access */
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| 276 | } CAN_NBTP_Type;
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| 277 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 278 |
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| 279 | #define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */
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| 280 | #define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */
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| 281 |
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| 282 | #define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */
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| 283 | #define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos)
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| 284 | #define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos))
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| 285 | #define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */
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| 286 | #define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos)
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| 287 | #define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos))
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| 288 | #define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */
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| 289 | #define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos)
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| 290 | #define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos))
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| 291 | #define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */
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| 292 | #define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos)
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| 293 | #define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos))
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| 294 | #define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */
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| 295 |
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| 296 | /* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */
|
| 297 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 298 | typedef union {
|
| 299 | struct {
|
| 300 | uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */
|
| 301 | uint32_t :14; /*!< bit: 2..15 Reserved */
|
| 302 | uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */
|
| 303 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 304 | } bit; /*!< Structure used for bit access */
|
| 305 | uint32_t reg; /*!< Type used for register access */
|
| 306 | } CAN_TSCC_Type;
|
| 307 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 308 |
|
| 309 | #define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */
|
| 310 | #define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */
|
| 311 |
|
| 312 | #define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */
|
| 313 | #define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos)
|
| 314 | #define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos))
|
| 315 | #define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */
|
| 316 | #define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */
|
| 317 | #define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */
|
| 318 | #define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos)
|
| 319 | #define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos)
|
| 320 | #define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos)
|
| 321 | #define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */
|
| 322 | #define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos)
|
| 323 | #define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos))
|
| 324 | #define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */
|
| 325 |
|
| 326 | /* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */
|
| 327 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 328 | typedef union {
|
| 329 | struct {
|
| 330 | uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */
|
| 331 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 332 | } bit; /*!< Structure used for bit access */
|
| 333 | uint32_t reg; /*!< Type used for register access */
|
| 334 | } CAN_TSCV_Type;
|
| 335 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 336 |
|
| 337 | #define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */
|
| 338 | #define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */
|
| 339 |
|
| 340 | #define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */
|
| 341 | #define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos)
|
| 342 | #define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos))
|
| 343 | #define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */
|
| 344 |
|
| 345 | /* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */
|
| 346 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 347 | typedef union {
|
| 348 | struct {
|
| 349 | uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */
|
| 350 | uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */
|
| 351 | uint32_t :13; /*!< bit: 3..15 Reserved */
|
| 352 | uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */
|
| 353 | } bit; /*!< Structure used for bit access */
|
| 354 | uint32_t reg; /*!< Type used for register access */
|
| 355 | } CAN_TOCC_Type;
|
| 356 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 357 |
|
| 358 | #define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */
|
| 359 | #define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */
|
| 360 |
|
| 361 | #define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */
|
| 362 | #define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos)
|
| 363 | #define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */
|
| 364 | #define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos)
|
| 365 | #define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos))
|
| 366 | #define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */
|
| 367 | #define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */
|
| 368 | #define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */
|
| 369 | #define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */
|
| 370 | #define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos)
|
| 371 | #define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos)
|
| 372 | #define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos)
|
| 373 | #define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos)
|
| 374 | #define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */
|
| 375 | #define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos)
|
| 376 | #define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos))
|
| 377 | #define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */
|
| 378 |
|
| 379 | /* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */
|
| 380 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 381 | typedef union {
|
| 382 | struct {
|
| 383 | uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */
|
| 384 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 385 | } bit; /*!< Structure used for bit access */
|
| 386 | uint32_t reg; /*!< Type used for register access */
|
| 387 | } CAN_TOCV_Type;
|
| 388 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 389 |
|
| 390 | #define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */
|
| 391 | #define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */
|
| 392 |
|
| 393 | #define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */
|
| 394 | #define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos)
|
| 395 | #define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos))
|
| 396 | #define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */
|
| 397 |
|
| 398 | /* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */
|
| 399 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 400 | typedef union {
|
| 401 | struct {
|
| 402 | uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */
|
| 403 | uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */
|
| 404 | uint32_t RP:1; /*!< bit: 15 Receive Error Passive */
|
| 405 | uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */
|
| 406 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 407 | } bit; /*!< Structure used for bit access */
|
| 408 | uint32_t reg; /*!< Type used for register access */
|
| 409 | } CAN_ECR_Type;
|
| 410 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 411 |
|
| 412 | #define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */
|
| 413 | #define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */
|
| 414 |
|
| 415 | #define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */
|
| 416 | #define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos)
|
| 417 | #define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos))
|
| 418 | #define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */
|
| 419 | #define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos)
|
| 420 | #define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos))
|
| 421 | #define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */
|
| 422 | #define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos)
|
| 423 | #define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */
|
| 424 | #define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos)
|
| 425 | #define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos))
|
| 426 | #define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */
|
| 427 |
|
| 428 | /* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */
|
| 429 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 430 | typedef union {
|
| 431 | struct {
|
| 432 | uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */
|
| 433 | uint32_t ACT:2; /*!< bit: 3.. 4 Activity */
|
| 434 | uint32_t EP:1; /*!< bit: 5 Error Passive */
|
| 435 | uint32_t EW:1; /*!< bit: 6 Warning Status */
|
| 436 | uint32_t BO:1; /*!< bit: 7 Bus_Off Status */
|
| 437 | uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */
|
| 438 | uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */
|
| 439 | uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */
|
| 440 | uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */
|
| 441 | uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */
|
| 442 | uint32_t :1; /*!< bit: 15 Reserved */
|
| 443 | uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */
|
| 444 | uint32_t :9; /*!< bit: 23..31 Reserved */
|
| 445 | } bit; /*!< Structure used for bit access */
|
| 446 | uint32_t reg; /*!< Type used for register access */
|
| 447 | } CAN_PSR_Type;
|
| 448 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 449 |
|
| 450 | #define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */
|
| 451 | #define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */
|
| 452 |
|
| 453 | #define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */
|
| 454 | #define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos)
|
| 455 | #define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos))
|
| 456 | #define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
|
| 457 | #define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
|
| 458 | #define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
|
| 459 | #define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
|
| 460 | #define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
|
| 461 | #define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
|
| 462 | #define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
|
| 463 | #define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
|
| 464 | #define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos)
|
| 465 | #define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos)
|
| 466 | #define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos)
|
| 467 | #define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos)
|
| 468 | #define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos)
|
| 469 | #define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos)
|
| 470 | #define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos)
|
| 471 | #define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos)
|
| 472 | #define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */
|
| 473 | #define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos)
|
| 474 | #define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos))
|
| 475 | #define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */
|
| 476 | #define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */
|
| 477 | #define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */
|
| 478 | #define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */
|
| 479 | #define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos)
|
| 480 | #define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos)
|
| 481 | #define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos)
|
| 482 | #define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos)
|
| 483 | #define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */
|
| 484 | #define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos)
|
| 485 | #define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */
|
| 486 | #define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos)
|
| 487 | #define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */
|
| 488 | #define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos)
|
| 489 | #define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */
|
| 490 | #define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos)
|
| 491 | #define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos))
|
| 492 | #define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
|
| 493 | #define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
|
| 494 | #define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
|
| 495 | #define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
|
| 496 | #define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
|
| 497 | #define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
|
| 498 | #define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
|
| 499 | #define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
|
| 500 | #define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos)
|
| 501 | #define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos)
|
| 502 | #define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos)
|
| 503 | #define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos)
|
| 504 | #define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos)
|
| 505 | #define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos)
|
| 506 | #define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos)
|
| 507 | #define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos)
|
| 508 | #define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */
|
| 509 | #define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos)
|
| 510 | #define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */
|
| 511 | #define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos)
|
| 512 | #define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */
|
| 513 | #define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos)
|
| 514 | #define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */
|
| 515 | #define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos)
|
| 516 | #define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */
|
| 517 | #define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos)
|
| 518 | #define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos))
|
| 519 | #define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */
|
| 520 |
|
| 521 | /* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */
|
| 522 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 523 | typedef union {
|
| 524 | struct {
|
| 525 | uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */
|
| 526 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 527 | uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */
|
| 528 | uint32_t :17; /*!< bit: 15..31 Reserved */
|
| 529 | } bit; /*!< Structure used for bit access */
|
| 530 | uint32_t reg; /*!< Type used for register access */
|
| 531 | } CAN_TDCR_Type;
|
| 532 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 533 |
|
| 534 | #define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */
|
| 535 | #define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */
|
| 536 |
|
| 537 | #define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */
|
| 538 | #define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos)
|
| 539 | #define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos))
|
| 540 | #define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */
|
| 541 | #define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos)
|
| 542 | #define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos))
|
| 543 | #define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */
|
| 544 |
|
| 545 | /* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */
|
| 546 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 547 | typedef union {
|
| 548 | struct {
|
| 549 | uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */
|
| 550 | uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */
|
| 551 | uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */
|
| 552 | uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */
|
| 553 | uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */
|
| 554 | uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */
|
| 555 | uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */
|
| 556 | uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */
|
| 557 | uint32_t HPM:1; /*!< bit: 8 High Priority Message */
|
| 558 | uint32_t TC:1; /*!< bit: 9 Timestamp Completed */
|
| 559 | uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */
|
| 560 | uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */
|
| 561 | uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */
|
| 562 | uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */
|
| 563 | uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */
|
| 564 | uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */
|
| 565 | uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */
|
| 566 | uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */
|
| 567 | uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */
|
| 568 | uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */
|
| 569 | uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */
|
| 570 | uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */
|
| 571 | uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */
|
| 572 | uint32_t EP:1; /*!< bit: 23 Error Passive */
|
| 573 | uint32_t EW:1; /*!< bit: 24 Warning Status */
|
| 574 | uint32_t BO:1; /*!< bit: 25 Bus_Off Status */
|
| 575 | uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */
|
| 576 | uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */
|
| 577 | uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */
|
| 578 | uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */
|
| 579 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 580 | } bit; /*!< Structure used for bit access */
|
| 581 | uint32_t reg; /*!< Type used for register access */
|
| 582 | } CAN_IR_Type;
|
| 583 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 584 |
|
| 585 | #define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */
|
| 586 | #define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */
|
| 587 |
|
| 588 | #define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */
|
| 589 | #define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos)
|
| 590 | #define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */
|
| 591 | #define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos)
|
| 592 | #define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */
|
| 593 | #define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos)
|
| 594 | #define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */
|
| 595 | #define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos)
|
| 596 | #define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */
|
| 597 | #define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos)
|
| 598 | #define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */
|
| 599 | #define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos)
|
| 600 | #define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */
|
| 601 | #define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos)
|
| 602 | #define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */
|
| 603 | #define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos)
|
| 604 | #define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */
|
| 605 | #define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos)
|
| 606 | #define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */
|
| 607 | #define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos)
|
| 608 | #define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */
|
| 609 | #define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos)
|
| 610 | #define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */
|
| 611 | #define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos)
|
| 612 | #define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */
|
| 613 | #define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos)
|
| 614 | #define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */
|
| 615 | #define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos)
|
| 616 | #define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */
|
| 617 | #define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos)
|
| 618 | #define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */
|
| 619 | #define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos)
|
| 620 | #define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */
|
| 621 | #define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos)
|
| 622 | #define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */
|
| 623 | #define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos)
|
| 624 | #define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */
|
| 625 | #define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos)
|
| 626 | #define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */
|
| 627 | #define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos)
|
| 628 | #define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */
|
| 629 | #define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos)
|
| 630 | #define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */
|
| 631 | #define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos)
|
| 632 | #define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */
|
| 633 | #define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos)
|
| 634 | #define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */
|
| 635 | #define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos)
|
| 636 | #define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */
|
| 637 | #define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos)
|
| 638 | #define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */
|
| 639 | #define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos)
|
| 640 | #define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */
|
| 641 | #define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos)
|
| 642 | #define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */
|
| 643 | #define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos)
|
| 644 | #define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */
|
| 645 | #define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos)
|
| 646 | #define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */
|
| 647 | #define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos)
|
| 648 | #define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */
|
| 649 |
|
| 650 | /* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */
|
| 651 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 652 | typedef union {
|
| 653 | struct {
|
| 654 | uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */
|
| 655 | uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */
|
| 656 | uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */
|
| 657 | uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */
|
| 658 | uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */
|
| 659 | uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */
|
| 660 | uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */
|
| 661 | uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */
|
| 662 | uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */
|
| 663 | uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */
|
| 664 | uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */
|
| 665 | uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */
|
| 666 | uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */
|
| 667 | uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */
|
| 668 | uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */
|
| 669 | uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */
|
| 670 | uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */
|
| 671 | uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */
|
| 672 | uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */
|
| 673 | uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */
|
| 674 | uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */
|
| 675 | uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */
|
| 676 | uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */
|
| 677 | uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */
|
| 678 | uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */
|
| 679 | uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */
|
| 680 | uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */
|
| 681 | uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */
|
| 682 | uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */
|
| 683 | uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */
|
| 684 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 685 | } bit; /*!< Structure used for bit access */
|
| 686 | uint32_t reg; /*!< Type used for register access */
|
| 687 | } CAN_IE_Type;
|
| 688 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 689 |
|
| 690 | #define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */
|
| 691 | #define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */
|
| 692 |
|
| 693 | #define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */
|
| 694 | #define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos)
|
| 695 | #define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */
|
| 696 | #define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos)
|
| 697 | #define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */
|
| 698 | #define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos)
|
| 699 | #define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */
|
| 700 | #define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos)
|
| 701 | #define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */
|
| 702 | #define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos)
|
| 703 | #define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */
|
| 704 | #define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos)
|
| 705 | #define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */
|
| 706 | #define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos)
|
| 707 | #define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */
|
| 708 | #define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos)
|
| 709 | #define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */
|
| 710 | #define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos)
|
| 711 | #define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */
|
| 712 | #define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos)
|
| 713 | #define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */
|
| 714 | #define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos)
|
| 715 | #define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */
|
| 716 | #define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos)
|
| 717 | #define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */
|
| 718 | #define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos)
|
| 719 | #define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
|
| 720 | #define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos)
|
| 721 | #define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */
|
| 722 | #define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos)
|
| 723 | #define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */
|
| 724 | #define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos)
|
| 725 | #define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */
|
| 726 | #define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos)
|
| 727 | #define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */
|
| 728 | #define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos)
|
| 729 | #define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */
|
| 730 | #define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos)
|
| 731 | #define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */
|
| 732 | #define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos)
|
| 733 | #define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */
|
| 734 | #define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos)
|
| 735 | #define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */
|
| 736 | #define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos)
|
| 737 | #define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */
|
| 738 | #define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos)
|
| 739 | #define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */
|
| 740 | #define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos)
|
| 741 | #define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */
|
| 742 | #define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos)
|
| 743 | #define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */
|
| 744 | #define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos)
|
| 745 | #define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */
|
| 746 | #define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos)
|
| 747 | #define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */
|
| 748 | #define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos)
|
| 749 | #define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */
|
| 750 | #define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos)
|
| 751 | #define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */
|
| 752 | #define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos)
|
| 753 | #define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */
|
| 754 |
|
| 755 | /* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */
|
| 756 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 757 | typedef union {
|
| 758 | struct {
|
| 759 | uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */
|
| 760 | uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */
|
| 761 | uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */
|
| 762 | uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */
|
| 763 | uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */
|
| 764 | uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */
|
| 765 | uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */
|
| 766 | uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */
|
| 767 | uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */
|
| 768 | uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */
|
| 769 | uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */
|
| 770 | uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */
|
| 771 | uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */
|
| 772 | uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */
|
| 773 | uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */
|
| 774 | uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */
|
| 775 | uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */
|
| 776 | uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */
|
| 777 | uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */
|
| 778 | uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */
|
| 779 | uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */
|
| 780 | uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */
|
| 781 | uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */
|
| 782 | uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */
|
| 783 | uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */
|
| 784 | uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */
|
| 785 | uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */
|
| 786 | uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */
|
| 787 | uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */
|
| 788 | uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */
|
| 789 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 790 | } bit; /*!< Structure used for bit access */
|
| 791 | uint32_t reg; /*!< Type used for register access */
|
| 792 | } CAN_ILS_Type;
|
| 793 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 794 |
|
| 795 | #define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */
|
| 796 | #define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */
|
| 797 |
|
| 798 | #define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */
|
| 799 | #define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos)
|
| 800 | #define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */
|
| 801 | #define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos)
|
| 802 | #define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */
|
| 803 | #define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos)
|
| 804 | #define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */
|
| 805 | #define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos)
|
| 806 | #define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */
|
| 807 | #define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos)
|
| 808 | #define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */
|
| 809 | #define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos)
|
| 810 | #define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */
|
| 811 | #define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos)
|
| 812 | #define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */
|
| 813 | #define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos)
|
| 814 | #define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */
|
| 815 | #define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos)
|
| 816 | #define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */
|
| 817 | #define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos)
|
| 818 | #define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */
|
| 819 | #define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos)
|
| 820 | #define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */
|
| 821 | #define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos)
|
| 822 | #define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */
|
| 823 | #define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos)
|
| 824 | #define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
|
| 825 | #define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos)
|
| 826 | #define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */
|
| 827 | #define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos)
|
| 828 | #define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */
|
| 829 | #define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos)
|
| 830 | #define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */
|
| 831 | #define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos)
|
| 832 | #define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */
|
| 833 | #define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos)
|
| 834 | #define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */
|
| 835 | #define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos)
|
| 836 | #define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */
|
| 837 | #define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos)
|
| 838 | #define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */
|
| 839 | #define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos)
|
| 840 | #define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */
|
| 841 | #define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos)
|
| 842 | #define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */
|
| 843 | #define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos)
|
| 844 | #define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */
|
| 845 | #define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos)
|
| 846 | #define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */
|
| 847 | #define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos)
|
| 848 | #define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */
|
| 849 | #define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos)
|
| 850 | #define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */
|
| 851 | #define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos)
|
| 852 | #define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */
|
| 853 | #define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos)
|
| 854 | #define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */
|
| 855 | #define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos)
|
| 856 | #define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */
|
| 857 | #define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos)
|
| 858 | #define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */
|
| 859 |
|
| 860 | /* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */
|
| 861 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 862 | typedef union {
|
| 863 | struct {
|
| 864 | uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */
|
| 865 | uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */
|
| 866 | uint32_t :30; /*!< bit: 2..31 Reserved */
|
| 867 | } bit; /*!< Structure used for bit access */
|
| 868 | uint32_t reg; /*!< Type used for register access */
|
| 869 | } CAN_ILE_Type;
|
| 870 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 871 |
|
| 872 | #define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */
|
| 873 | #define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */
|
| 874 |
|
| 875 | #define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */
|
| 876 | #define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos)
|
| 877 | #define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */
|
| 878 | #define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos)
|
| 879 | #define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */
|
| 880 |
|
| 881 | /* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */
|
| 882 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 883 | typedef union {
|
| 884 | struct {
|
| 885 | uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */
|
| 886 | uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */
|
| 887 | uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */
|
| 888 | uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */
|
| 889 | uint32_t :26; /*!< bit: 6..31 Reserved */
|
| 890 | } bit; /*!< Structure used for bit access */
|
| 891 | uint32_t reg; /*!< Type used for register access */
|
| 892 | } CAN_GFC_Type;
|
| 893 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 894 |
|
| 895 | #define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */
|
| 896 | #define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */
|
| 897 |
|
| 898 | #define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */
|
| 899 | #define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos)
|
| 900 | #define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */
|
| 901 | #define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos)
|
| 902 | #define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */
|
| 903 | #define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos)
|
| 904 | #define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos))
|
| 905 | #define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
|
| 906 | #define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
|
| 907 | #define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
|
| 908 | #define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos)
|
| 909 | #define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos)
|
| 910 | #define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos)
|
| 911 | #define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */
|
| 912 | #define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos)
|
| 913 | #define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos))
|
| 914 | #define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
|
| 915 | #define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
|
| 916 | #define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
|
| 917 | #define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos)
|
| 918 | #define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos)
|
| 919 | #define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos)
|
| 920 | #define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */
|
| 921 |
|
| 922 | /* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */
|
| 923 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 924 | typedef union {
|
| 925 | struct {
|
| 926 | uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */
|
| 927 | uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */
|
| 928 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 929 | } bit; /*!< Structure used for bit access */
|
| 930 | uint32_t reg; /*!< Type used for register access */
|
| 931 | } CAN_SIDFC_Type;
|
| 932 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 933 |
|
| 934 | #define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */
|
| 935 | #define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */
|
| 936 |
|
| 937 | #define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */
|
| 938 | #define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos)
|
| 939 | #define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos))
|
| 940 | #define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */
|
| 941 | #define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos)
|
| 942 | #define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos))
|
| 943 | #define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */
|
| 944 |
|
| 945 | /* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */
|
| 946 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 947 | typedef union {
|
| 948 | struct {
|
| 949 | uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */
|
| 950 | uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */
|
| 951 | uint32_t :9; /*!< bit: 23..31 Reserved */
|
| 952 | } bit; /*!< Structure used for bit access */
|
| 953 | uint32_t reg; /*!< Type used for register access */
|
| 954 | } CAN_XIDFC_Type;
|
| 955 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 956 |
|
| 957 | #define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */
|
| 958 | #define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */
|
| 959 |
|
| 960 | #define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */
|
| 961 | #define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos)
|
| 962 | #define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos))
|
| 963 | #define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */
|
| 964 | #define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos)
|
| 965 | #define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos))
|
| 966 | #define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */
|
| 967 |
|
| 968 | /* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */
|
| 969 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 970 | typedef union {
|
| 971 | struct {
|
| 972 | uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */
|
| 973 | uint32_t :3; /*!< bit: 29..31 Reserved */
|
| 974 | } bit; /*!< Structure used for bit access */
|
| 975 | uint32_t reg; /*!< Type used for register access */
|
| 976 | } CAN_XIDAM_Type;
|
| 977 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 978 |
|
| 979 | #define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */
|
| 980 | #define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */
|
| 981 |
|
| 982 | #define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */
|
| 983 | #define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos)
|
| 984 | #define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos))
|
| 985 | #define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */
|
| 986 |
|
| 987 | /* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */
|
| 988 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 989 | typedef union {
|
| 990 | struct {
|
| 991 | uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */
|
| 992 | uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */
|
| 993 | uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */
|
| 994 | uint32_t FLST:1; /*!< bit: 15 Filter List */
|
| 995 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 996 | } bit; /*!< Structure used for bit access */
|
| 997 | uint32_t reg; /*!< Type used for register access */
|
| 998 | } CAN_HPMS_Type;
|
| 999 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1000 |
|
| 1001 | #define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */
|
| 1002 | #define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */
|
| 1003 |
|
| 1004 | #define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */
|
| 1005 | #define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos)
|
| 1006 | #define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos))
|
| 1007 | #define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */
|
| 1008 | #define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos)
|
| 1009 | #define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos))
|
| 1010 | #define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */
|
| 1011 | #define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */
|
| 1012 | #define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */
|
| 1013 | #define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */
|
| 1014 | #define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos)
|
| 1015 | #define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos)
|
| 1016 | #define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos)
|
| 1017 | #define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos)
|
| 1018 | #define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */
|
| 1019 | #define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos)
|
| 1020 | #define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos))
|
| 1021 | #define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */
|
| 1022 | #define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos)
|
| 1023 | #define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */
|
| 1024 |
|
| 1025 | /* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */
|
| 1026 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1027 | typedef union {
|
| 1028 | struct {
|
| 1029 | uint32_t ND0:1; /*!< bit: 0 New Data 0 */
|
| 1030 | uint32_t ND1:1; /*!< bit: 1 New Data 1 */
|
| 1031 | uint32_t ND2:1; /*!< bit: 2 New Data 2 */
|
| 1032 | uint32_t ND3:1; /*!< bit: 3 New Data 3 */
|
| 1033 | uint32_t ND4:1; /*!< bit: 4 New Data 4 */
|
| 1034 | uint32_t ND5:1; /*!< bit: 5 New Data 5 */
|
| 1035 | uint32_t ND6:1; /*!< bit: 6 New Data 6 */
|
| 1036 | uint32_t ND7:1; /*!< bit: 7 New Data 7 */
|
| 1037 | uint32_t ND8:1; /*!< bit: 8 New Data 8 */
|
| 1038 | uint32_t ND9:1; /*!< bit: 9 New Data 9 */
|
| 1039 | uint32_t ND10:1; /*!< bit: 10 New Data 10 */
|
| 1040 | uint32_t ND11:1; /*!< bit: 11 New Data 11 */
|
| 1041 | uint32_t ND12:1; /*!< bit: 12 New Data 12 */
|
| 1042 | uint32_t ND13:1; /*!< bit: 13 New Data 13 */
|
| 1043 | uint32_t ND14:1; /*!< bit: 14 New Data 14 */
|
| 1044 | uint32_t ND15:1; /*!< bit: 15 New Data 15 */
|
| 1045 | uint32_t ND16:1; /*!< bit: 16 New Data 16 */
|
| 1046 | uint32_t ND17:1; /*!< bit: 17 New Data 17 */
|
| 1047 | uint32_t ND18:1; /*!< bit: 18 New Data 18 */
|
| 1048 | uint32_t ND19:1; /*!< bit: 19 New Data 19 */
|
| 1049 | uint32_t ND20:1; /*!< bit: 20 New Data 20 */
|
| 1050 | uint32_t ND21:1; /*!< bit: 21 New Data 21 */
|
| 1051 | uint32_t ND22:1; /*!< bit: 22 New Data 22 */
|
| 1052 | uint32_t ND23:1; /*!< bit: 23 New Data 23 */
|
| 1053 | uint32_t ND24:1; /*!< bit: 24 New Data 24 */
|
| 1054 | uint32_t ND25:1; /*!< bit: 25 New Data 25 */
|
| 1055 | uint32_t ND26:1; /*!< bit: 26 New Data 26 */
|
| 1056 | uint32_t ND27:1; /*!< bit: 27 New Data 27 */
|
| 1057 | uint32_t ND28:1; /*!< bit: 28 New Data 28 */
|
| 1058 | uint32_t ND29:1; /*!< bit: 29 New Data 29 */
|
| 1059 | uint32_t ND30:1; /*!< bit: 30 New Data 30 */
|
| 1060 | uint32_t ND31:1; /*!< bit: 31 New Data 31 */
|
| 1061 | } bit; /*!< Structure used for bit access */
|
| 1062 | uint32_t reg; /*!< Type used for register access */
|
| 1063 | } CAN_NDAT1_Type;
|
| 1064 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1065 |
|
| 1066 | #define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */
|
| 1067 | #define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */
|
| 1068 |
|
| 1069 | #define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */
|
| 1070 | #define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos)
|
| 1071 | #define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */
|
| 1072 | #define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos)
|
| 1073 | #define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */
|
| 1074 | #define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos)
|
| 1075 | #define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */
|
| 1076 | #define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos)
|
| 1077 | #define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */
|
| 1078 | #define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos)
|
| 1079 | #define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */
|
| 1080 | #define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos)
|
| 1081 | #define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */
|
| 1082 | #define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos)
|
| 1083 | #define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */
|
| 1084 | #define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos)
|
| 1085 | #define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */
|
| 1086 | #define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos)
|
| 1087 | #define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */
|
| 1088 | #define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos)
|
| 1089 | #define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */
|
| 1090 | #define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos)
|
| 1091 | #define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */
|
| 1092 | #define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos)
|
| 1093 | #define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */
|
| 1094 | #define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos)
|
| 1095 | #define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */
|
| 1096 | #define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos)
|
| 1097 | #define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */
|
| 1098 | #define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos)
|
| 1099 | #define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */
|
| 1100 | #define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos)
|
| 1101 | #define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */
|
| 1102 | #define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos)
|
| 1103 | #define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */
|
| 1104 | #define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos)
|
| 1105 | #define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */
|
| 1106 | #define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos)
|
| 1107 | #define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */
|
| 1108 | #define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos)
|
| 1109 | #define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */
|
| 1110 | #define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos)
|
| 1111 | #define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */
|
| 1112 | #define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos)
|
| 1113 | #define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */
|
| 1114 | #define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos)
|
| 1115 | #define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */
|
| 1116 | #define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos)
|
| 1117 | #define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */
|
| 1118 | #define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos)
|
| 1119 | #define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */
|
| 1120 | #define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos)
|
| 1121 | #define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */
|
| 1122 | #define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos)
|
| 1123 | #define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */
|
| 1124 | #define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos)
|
| 1125 | #define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */
|
| 1126 | #define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos)
|
| 1127 | #define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */
|
| 1128 | #define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos)
|
| 1129 | #define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */
|
| 1130 | #define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos)
|
| 1131 | #define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */
|
| 1132 | #define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos)
|
| 1133 | #define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */
|
| 1134 |
|
| 1135 | /* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */
|
| 1136 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1137 | typedef union {
|
| 1138 | struct {
|
| 1139 | uint32_t ND32:1; /*!< bit: 0 New Data 32 */
|
| 1140 | uint32_t ND33:1; /*!< bit: 1 New Data 33 */
|
| 1141 | uint32_t ND34:1; /*!< bit: 2 New Data 34 */
|
| 1142 | uint32_t ND35:1; /*!< bit: 3 New Data 35 */
|
| 1143 | uint32_t ND36:1; /*!< bit: 4 New Data 36 */
|
| 1144 | uint32_t ND37:1; /*!< bit: 5 New Data 37 */
|
| 1145 | uint32_t ND38:1; /*!< bit: 6 New Data 38 */
|
| 1146 | uint32_t ND39:1; /*!< bit: 7 New Data 39 */
|
| 1147 | uint32_t ND40:1; /*!< bit: 8 New Data 40 */
|
| 1148 | uint32_t ND41:1; /*!< bit: 9 New Data 41 */
|
| 1149 | uint32_t ND42:1; /*!< bit: 10 New Data 42 */
|
| 1150 | uint32_t ND43:1; /*!< bit: 11 New Data 43 */
|
| 1151 | uint32_t ND44:1; /*!< bit: 12 New Data 44 */
|
| 1152 | uint32_t ND45:1; /*!< bit: 13 New Data 45 */
|
| 1153 | uint32_t ND46:1; /*!< bit: 14 New Data 46 */
|
| 1154 | uint32_t ND47:1; /*!< bit: 15 New Data 47 */
|
| 1155 | uint32_t ND48:1; /*!< bit: 16 New Data 48 */
|
| 1156 | uint32_t ND49:1; /*!< bit: 17 New Data 49 */
|
| 1157 | uint32_t ND50:1; /*!< bit: 18 New Data 50 */
|
| 1158 | uint32_t ND51:1; /*!< bit: 19 New Data 51 */
|
| 1159 | uint32_t ND52:1; /*!< bit: 20 New Data 52 */
|
| 1160 | uint32_t ND53:1; /*!< bit: 21 New Data 53 */
|
| 1161 | uint32_t ND54:1; /*!< bit: 22 New Data 54 */
|
| 1162 | uint32_t ND55:1; /*!< bit: 23 New Data 55 */
|
| 1163 | uint32_t ND56:1; /*!< bit: 24 New Data 56 */
|
| 1164 | uint32_t ND57:1; /*!< bit: 25 New Data 57 */
|
| 1165 | uint32_t ND58:1; /*!< bit: 26 New Data 58 */
|
| 1166 | uint32_t ND59:1; /*!< bit: 27 New Data 59 */
|
| 1167 | uint32_t ND60:1; /*!< bit: 28 New Data 60 */
|
| 1168 | uint32_t ND61:1; /*!< bit: 29 New Data 61 */
|
| 1169 | uint32_t ND62:1; /*!< bit: 30 New Data 62 */
|
| 1170 | uint32_t ND63:1; /*!< bit: 31 New Data 63 */
|
| 1171 | } bit; /*!< Structure used for bit access */
|
| 1172 | uint32_t reg; /*!< Type used for register access */
|
| 1173 | } CAN_NDAT2_Type;
|
| 1174 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1175 |
|
| 1176 | #define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */
|
| 1177 | #define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */
|
| 1178 |
|
| 1179 | #define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */
|
| 1180 | #define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos)
|
| 1181 | #define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */
|
| 1182 | #define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos)
|
| 1183 | #define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */
|
| 1184 | #define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos)
|
| 1185 | #define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */
|
| 1186 | #define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos)
|
| 1187 | #define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */
|
| 1188 | #define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos)
|
| 1189 | #define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */
|
| 1190 | #define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos)
|
| 1191 | #define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */
|
| 1192 | #define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos)
|
| 1193 | #define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */
|
| 1194 | #define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos)
|
| 1195 | #define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */
|
| 1196 | #define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos)
|
| 1197 | #define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */
|
| 1198 | #define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos)
|
| 1199 | #define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */
|
| 1200 | #define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos)
|
| 1201 | #define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */
|
| 1202 | #define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos)
|
| 1203 | #define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */
|
| 1204 | #define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos)
|
| 1205 | #define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */
|
| 1206 | #define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos)
|
| 1207 | #define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */
|
| 1208 | #define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos)
|
| 1209 | #define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */
|
| 1210 | #define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos)
|
| 1211 | #define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */
|
| 1212 | #define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos)
|
| 1213 | #define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */
|
| 1214 | #define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos)
|
| 1215 | #define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */
|
| 1216 | #define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos)
|
| 1217 | #define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */
|
| 1218 | #define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos)
|
| 1219 | #define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */
|
| 1220 | #define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos)
|
| 1221 | #define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */
|
| 1222 | #define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos)
|
| 1223 | #define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */
|
| 1224 | #define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos)
|
| 1225 | #define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */
|
| 1226 | #define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos)
|
| 1227 | #define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */
|
| 1228 | #define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos)
|
| 1229 | #define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */
|
| 1230 | #define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos)
|
| 1231 | #define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */
|
| 1232 | #define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos)
|
| 1233 | #define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */
|
| 1234 | #define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos)
|
| 1235 | #define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */
|
| 1236 | #define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos)
|
| 1237 | #define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */
|
| 1238 | #define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos)
|
| 1239 | #define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */
|
| 1240 | #define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos)
|
| 1241 | #define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */
|
| 1242 | #define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos)
|
| 1243 | #define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */
|
| 1244 |
|
| 1245 | /* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */
|
| 1246 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1247 | typedef union {
|
| 1248 | struct {
|
| 1249 | uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */
|
| 1250 | uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */
|
| 1251 | uint32_t :1; /*!< bit: 23 Reserved */
|
| 1252 | uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */
|
| 1253 | uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */
|
| 1254 | } bit; /*!< Structure used for bit access */
|
| 1255 | uint32_t reg; /*!< Type used for register access */
|
| 1256 | } CAN_RXF0C_Type;
|
| 1257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1258 |
|
| 1259 | #define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */
|
| 1260 | #define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */
|
| 1261 |
|
| 1262 | #define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */
|
| 1263 | #define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos)
|
| 1264 | #define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos))
|
| 1265 | #define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */
|
| 1266 | #define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos)
|
| 1267 | #define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos))
|
| 1268 | #define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */
|
| 1269 | #define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos)
|
| 1270 | #define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos))
|
| 1271 | #define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */
|
| 1272 | #define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos)
|
| 1273 | #define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */
|
| 1274 |
|
| 1275 | /* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */
|
| 1276 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1277 | typedef union {
|
| 1278 | struct {
|
| 1279 | uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */
|
| 1280 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 1281 | uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */
|
| 1282 | uint32_t :2; /*!< bit: 14..15 Reserved */
|
| 1283 | uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */
|
| 1284 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 1285 | uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */
|
| 1286 | uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */
|
| 1287 | uint32_t :6; /*!< bit: 26..31 Reserved */
|
| 1288 | } bit; /*!< Structure used for bit access */
|
| 1289 | uint32_t reg; /*!< Type used for register access */
|
| 1290 | } CAN_RXF0S_Type;
|
| 1291 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1292 |
|
| 1293 | #define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */
|
| 1294 | #define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */
|
| 1295 |
|
| 1296 | #define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */
|
| 1297 | #define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos)
|
| 1298 | #define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos))
|
| 1299 | #define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */
|
| 1300 | #define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos)
|
| 1301 | #define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos))
|
| 1302 | #define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */
|
| 1303 | #define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos)
|
| 1304 | #define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos))
|
| 1305 | #define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */
|
| 1306 | #define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos)
|
| 1307 | #define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */
|
| 1308 | #define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos)
|
| 1309 | #define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */
|
| 1310 |
|
| 1311 | /* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */
|
| 1312 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1313 | typedef union {
|
| 1314 | struct {
|
| 1315 | uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */
|
| 1316 | uint32_t :26; /*!< bit: 6..31 Reserved */
|
| 1317 | } bit; /*!< Structure used for bit access */
|
| 1318 | uint32_t reg; /*!< Type used for register access */
|
| 1319 | } CAN_RXF0A_Type;
|
| 1320 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1321 |
|
| 1322 | #define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */
|
| 1323 | #define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */
|
| 1324 |
|
| 1325 | #define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */
|
| 1326 | #define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos)
|
| 1327 | #define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos))
|
| 1328 | #define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */
|
| 1329 |
|
| 1330 | /* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */
|
| 1331 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1332 | typedef union {
|
| 1333 | struct {
|
| 1334 | uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */
|
| 1335 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1336 | } bit; /*!< Structure used for bit access */
|
| 1337 | uint32_t reg; /*!< Type used for register access */
|
| 1338 | } CAN_RXBC_Type;
|
| 1339 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1340 |
|
| 1341 | #define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */
|
| 1342 | #define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */
|
| 1343 |
|
| 1344 | #define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */
|
| 1345 | #define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos)
|
| 1346 | #define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos))
|
| 1347 | #define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */
|
| 1348 |
|
| 1349 | /* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */
|
| 1350 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1351 | typedef union {
|
| 1352 | struct {
|
| 1353 | uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */
|
| 1354 | uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */
|
| 1355 | uint32_t :1; /*!< bit: 23 Reserved */
|
| 1356 | uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */
|
| 1357 | uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */
|
| 1358 | } bit; /*!< Structure used for bit access */
|
| 1359 | uint32_t reg; /*!< Type used for register access */
|
| 1360 | } CAN_RXF1C_Type;
|
| 1361 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1362 |
|
| 1363 | #define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */
|
| 1364 | #define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */
|
| 1365 |
|
| 1366 | #define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */
|
| 1367 | #define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos)
|
| 1368 | #define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos))
|
| 1369 | #define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */
|
| 1370 | #define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos)
|
| 1371 | #define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos))
|
| 1372 | #define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */
|
| 1373 | #define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos)
|
| 1374 | #define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos))
|
| 1375 | #define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */
|
| 1376 | #define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos)
|
| 1377 | #define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */
|
| 1378 |
|
| 1379 | /* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */
|
| 1380 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1381 | typedef union {
|
| 1382 | struct {
|
| 1383 | uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */
|
| 1384 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 1385 | uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */
|
| 1386 | uint32_t :2; /*!< bit: 14..15 Reserved */
|
| 1387 | uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */
|
| 1388 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 1389 | uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */
|
| 1390 | uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */
|
| 1391 | uint32_t :4; /*!< bit: 26..29 Reserved */
|
| 1392 | uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */
|
| 1393 | } bit; /*!< Structure used for bit access */
|
| 1394 | uint32_t reg; /*!< Type used for register access */
|
| 1395 | } CAN_RXF1S_Type;
|
| 1396 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1397 |
|
| 1398 | #define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */
|
| 1399 | #define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */
|
| 1400 |
|
| 1401 | #define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */
|
| 1402 | #define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos)
|
| 1403 | #define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos))
|
| 1404 | #define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */
|
| 1405 | #define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos)
|
| 1406 | #define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos))
|
| 1407 | #define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */
|
| 1408 | #define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos)
|
| 1409 | #define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos))
|
| 1410 | #define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */
|
| 1411 | #define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos)
|
| 1412 | #define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */
|
| 1413 | #define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos)
|
| 1414 | #define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */
|
| 1415 | #define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos)
|
| 1416 | #define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos))
|
| 1417 | #define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */
|
| 1418 | #define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */
|
| 1419 | #define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */
|
| 1420 | #define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */
|
| 1421 | #define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos)
|
| 1422 | #define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos)
|
| 1423 | #define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos)
|
| 1424 | #define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos)
|
| 1425 | #define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */
|
| 1426 |
|
| 1427 | /* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */
|
| 1428 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1429 | typedef union {
|
| 1430 | struct {
|
| 1431 | uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */
|
| 1432 | uint32_t :26; /*!< bit: 6..31 Reserved */
|
| 1433 | } bit; /*!< Structure used for bit access */
|
| 1434 | uint32_t reg; /*!< Type used for register access */
|
| 1435 | } CAN_RXF1A_Type;
|
| 1436 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1437 |
|
| 1438 | #define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */
|
| 1439 | #define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */
|
| 1440 |
|
| 1441 | #define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */
|
| 1442 | #define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos)
|
| 1443 | #define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos))
|
| 1444 | #define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */
|
| 1445 |
|
| 1446 | /* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */
|
| 1447 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1448 | typedef union {
|
| 1449 | struct {
|
| 1450 | uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */
|
| 1451 | uint32_t :1; /*!< bit: 3 Reserved */
|
| 1452 | uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */
|
| 1453 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 1454 | uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */
|
| 1455 | uint32_t :21; /*!< bit: 11..31 Reserved */
|
| 1456 | } bit; /*!< Structure used for bit access */
|
| 1457 | uint32_t reg; /*!< Type used for register access */
|
| 1458 | } CAN_RXESC_Type;
|
| 1459 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1460 |
|
| 1461 | #define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */
|
| 1462 | #define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */
|
| 1463 |
|
| 1464 | #define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */
|
| 1465 | #define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos)
|
| 1466 | #define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos))
|
| 1467 | #define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
|
| 1468 | #define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
|
| 1469 | #define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
|
| 1470 | #define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
|
| 1471 | #define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
|
| 1472 | #define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
|
| 1473 | #define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
|
| 1474 | #define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
|
| 1475 | #define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos)
|
| 1476 | #define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos)
|
| 1477 | #define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos)
|
| 1478 | #define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos)
|
| 1479 | #define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos)
|
| 1480 | #define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos)
|
| 1481 | #define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos)
|
| 1482 | #define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos)
|
| 1483 | #define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */
|
| 1484 | #define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos)
|
| 1485 | #define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos))
|
| 1486 | #define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
|
| 1487 | #define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
|
| 1488 | #define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
|
| 1489 | #define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
|
| 1490 | #define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
|
| 1491 | #define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
|
| 1492 | #define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
|
| 1493 | #define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
|
| 1494 | #define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos)
|
| 1495 | #define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos)
|
| 1496 | #define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos)
|
| 1497 | #define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos)
|
| 1498 | #define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos)
|
| 1499 | #define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos)
|
| 1500 | #define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos)
|
| 1501 | #define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos)
|
| 1502 | #define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */
|
| 1503 | #define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos)
|
| 1504 | #define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos))
|
| 1505 | #define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
|
| 1506 | #define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
|
| 1507 | #define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
|
| 1508 | #define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
|
| 1509 | #define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
|
| 1510 | #define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
|
| 1511 | #define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
|
| 1512 | #define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
|
| 1513 | #define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos)
|
| 1514 | #define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos)
|
| 1515 | #define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos)
|
| 1516 | #define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos)
|
| 1517 | #define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos)
|
| 1518 | #define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos)
|
| 1519 | #define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos)
|
| 1520 | #define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos)
|
| 1521 | #define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */
|
| 1522 |
|
| 1523 | /* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */
|
| 1524 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1525 | typedef union {
|
| 1526 | struct {
|
| 1527 | uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */
|
| 1528 | uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */
|
| 1529 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 1530 | uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */
|
| 1531 | uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */
|
| 1532 | uint32_t :1; /*!< bit: 31 Reserved */
|
| 1533 | } bit; /*!< Structure used for bit access */
|
| 1534 | uint32_t reg; /*!< Type used for register access */
|
| 1535 | } CAN_TXBC_Type;
|
| 1536 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1537 |
|
| 1538 | #define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */
|
| 1539 | #define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */
|
| 1540 |
|
| 1541 | #define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */
|
| 1542 | #define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos)
|
| 1543 | #define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos))
|
| 1544 | #define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */
|
| 1545 | #define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos)
|
| 1546 | #define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos))
|
| 1547 | #define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */
|
| 1548 | #define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos)
|
| 1549 | #define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos))
|
| 1550 | #define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */
|
| 1551 | #define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos)
|
| 1552 | #define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */
|
| 1553 |
|
| 1554 | /* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */
|
| 1555 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1556 | typedef union {
|
| 1557 | struct {
|
| 1558 | uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */
|
| 1559 | uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
| 1560 | uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */
|
| 1561 | uint32_t :3; /*!< bit: 13..15 Reserved */
|
| 1562 | uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */
|
| 1563 | uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */
|
| 1564 | uint32_t :10; /*!< bit: 22..31 Reserved */
|
| 1565 | } bit; /*!< Structure used for bit access */
|
| 1566 | uint32_t reg; /*!< Type used for register access */
|
| 1567 | } CAN_TXFQS_Type;
|
| 1568 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1569 |
|
| 1570 | #define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */
|
| 1571 | #define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */
|
| 1572 |
|
| 1573 | #define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */
|
| 1574 | #define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos)
|
| 1575 | #define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos))
|
| 1576 | #define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */
|
| 1577 | #define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos)
|
| 1578 | #define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos))
|
| 1579 | #define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */
|
| 1580 | #define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos)
|
| 1581 | #define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos))
|
| 1582 | #define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */
|
| 1583 | #define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos)
|
| 1584 | #define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */
|
| 1585 |
|
| 1586 | /* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */
|
| 1587 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1588 | typedef union {
|
| 1589 | struct {
|
| 1590 | uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */
|
| 1591 | uint32_t :29; /*!< bit: 3..31 Reserved */
|
| 1592 | } bit; /*!< Structure used for bit access */
|
| 1593 | uint32_t reg; /*!< Type used for register access */
|
| 1594 | } CAN_TXESC_Type;
|
| 1595 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1596 |
|
| 1597 | #define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */
|
| 1598 | #define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */
|
| 1599 |
|
| 1600 | #define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */
|
| 1601 | #define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos)
|
| 1602 | #define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos))
|
| 1603 | #define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */
|
| 1604 | #define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */
|
| 1605 | #define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */
|
| 1606 | #define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */
|
| 1607 | #define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */
|
| 1608 | #define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */
|
| 1609 | #define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */
|
| 1610 | #define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */
|
| 1611 | #define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos)
|
| 1612 | #define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos)
|
| 1613 | #define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos)
|
| 1614 | #define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos)
|
| 1615 | #define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos)
|
| 1616 | #define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos)
|
| 1617 | #define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos)
|
| 1618 | #define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos)
|
| 1619 | #define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */
|
| 1620 |
|
| 1621 | /* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */
|
| 1622 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1623 | typedef union {
|
| 1624 | struct {
|
| 1625 | uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */
|
| 1626 | uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */
|
| 1627 | uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */
|
| 1628 | uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */
|
| 1629 | uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */
|
| 1630 | uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */
|
| 1631 | uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */
|
| 1632 | uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */
|
| 1633 | uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */
|
| 1634 | uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */
|
| 1635 | uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */
|
| 1636 | uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */
|
| 1637 | uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */
|
| 1638 | uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */
|
| 1639 | uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */
|
| 1640 | uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */
|
| 1641 | uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */
|
| 1642 | uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */
|
| 1643 | uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */
|
| 1644 | uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */
|
| 1645 | uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */
|
| 1646 | uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */
|
| 1647 | uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */
|
| 1648 | uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */
|
| 1649 | uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */
|
| 1650 | uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */
|
| 1651 | uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */
|
| 1652 | uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */
|
| 1653 | uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */
|
| 1654 | uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */
|
| 1655 | uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */
|
| 1656 | uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */
|
| 1657 | } bit; /*!< Structure used for bit access */
|
| 1658 | uint32_t reg; /*!< Type used for register access */
|
| 1659 | } CAN_TXBRP_Type;
|
| 1660 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1661 |
|
| 1662 | #define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */
|
| 1663 | #define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */
|
| 1664 |
|
| 1665 | #define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */
|
| 1666 | #define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos)
|
| 1667 | #define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */
|
| 1668 | #define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos)
|
| 1669 | #define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */
|
| 1670 | #define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos)
|
| 1671 | #define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */
|
| 1672 | #define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos)
|
| 1673 | #define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */
|
| 1674 | #define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos)
|
| 1675 | #define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */
|
| 1676 | #define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos)
|
| 1677 | #define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */
|
| 1678 | #define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos)
|
| 1679 | #define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */
|
| 1680 | #define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos)
|
| 1681 | #define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */
|
| 1682 | #define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos)
|
| 1683 | #define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */
|
| 1684 | #define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos)
|
| 1685 | #define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */
|
| 1686 | #define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos)
|
| 1687 | #define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */
|
| 1688 | #define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos)
|
| 1689 | #define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */
|
| 1690 | #define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos)
|
| 1691 | #define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */
|
| 1692 | #define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos)
|
| 1693 | #define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */
|
| 1694 | #define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos)
|
| 1695 | #define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */
|
| 1696 | #define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos)
|
| 1697 | #define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */
|
| 1698 | #define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos)
|
| 1699 | #define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */
|
| 1700 | #define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos)
|
| 1701 | #define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */
|
| 1702 | #define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos)
|
| 1703 | #define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */
|
| 1704 | #define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos)
|
| 1705 | #define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */
|
| 1706 | #define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos)
|
| 1707 | #define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */
|
| 1708 | #define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos)
|
| 1709 | #define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */
|
| 1710 | #define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos)
|
| 1711 | #define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */
|
| 1712 | #define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos)
|
| 1713 | #define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */
|
| 1714 | #define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos)
|
| 1715 | #define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */
|
| 1716 | #define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos)
|
| 1717 | #define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */
|
| 1718 | #define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos)
|
| 1719 | #define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */
|
| 1720 | #define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos)
|
| 1721 | #define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */
|
| 1722 | #define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos)
|
| 1723 | #define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */
|
| 1724 | #define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos)
|
| 1725 | #define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */
|
| 1726 | #define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos)
|
| 1727 | #define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */
|
| 1728 | #define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos)
|
| 1729 | #define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */
|
| 1730 |
|
| 1731 | /* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */
|
| 1732 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1733 | typedef union {
|
| 1734 | struct {
|
| 1735 | uint32_t AR0:1; /*!< bit: 0 Add Request 0 */
|
| 1736 | uint32_t AR1:1; /*!< bit: 1 Add Request 1 */
|
| 1737 | uint32_t AR2:1; /*!< bit: 2 Add Request 2 */
|
| 1738 | uint32_t AR3:1; /*!< bit: 3 Add Request 3 */
|
| 1739 | uint32_t AR4:1; /*!< bit: 4 Add Request 4 */
|
| 1740 | uint32_t AR5:1; /*!< bit: 5 Add Request 5 */
|
| 1741 | uint32_t AR6:1; /*!< bit: 6 Add Request 6 */
|
| 1742 | uint32_t AR7:1; /*!< bit: 7 Add Request 7 */
|
| 1743 | uint32_t AR8:1; /*!< bit: 8 Add Request 8 */
|
| 1744 | uint32_t AR9:1; /*!< bit: 9 Add Request 9 */
|
| 1745 | uint32_t AR10:1; /*!< bit: 10 Add Request 10 */
|
| 1746 | uint32_t AR11:1; /*!< bit: 11 Add Request 11 */
|
| 1747 | uint32_t AR12:1; /*!< bit: 12 Add Request 12 */
|
| 1748 | uint32_t AR13:1; /*!< bit: 13 Add Request 13 */
|
| 1749 | uint32_t AR14:1; /*!< bit: 14 Add Request 14 */
|
| 1750 | uint32_t AR15:1; /*!< bit: 15 Add Request 15 */
|
| 1751 | uint32_t AR16:1; /*!< bit: 16 Add Request 16 */
|
| 1752 | uint32_t AR17:1; /*!< bit: 17 Add Request 17 */
|
| 1753 | uint32_t AR18:1; /*!< bit: 18 Add Request 18 */
|
| 1754 | uint32_t AR19:1; /*!< bit: 19 Add Request 19 */
|
| 1755 | uint32_t AR20:1; /*!< bit: 20 Add Request 20 */
|
| 1756 | uint32_t AR21:1; /*!< bit: 21 Add Request 21 */
|
| 1757 | uint32_t AR22:1; /*!< bit: 22 Add Request 22 */
|
| 1758 | uint32_t AR23:1; /*!< bit: 23 Add Request 23 */
|
| 1759 | uint32_t AR24:1; /*!< bit: 24 Add Request 24 */
|
| 1760 | uint32_t AR25:1; /*!< bit: 25 Add Request 25 */
|
| 1761 | uint32_t AR26:1; /*!< bit: 26 Add Request 26 */
|
| 1762 | uint32_t AR27:1; /*!< bit: 27 Add Request 27 */
|
| 1763 | uint32_t AR28:1; /*!< bit: 28 Add Request 28 */
|
| 1764 | uint32_t AR29:1; /*!< bit: 29 Add Request 29 */
|
| 1765 | uint32_t AR30:1; /*!< bit: 30 Add Request 30 */
|
| 1766 | uint32_t AR31:1; /*!< bit: 31 Add Request 31 */
|
| 1767 | } bit; /*!< Structure used for bit access */
|
| 1768 | uint32_t reg; /*!< Type used for register access */
|
| 1769 | } CAN_TXBAR_Type;
|
| 1770 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1771 |
|
| 1772 | #define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */
|
| 1773 | #define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */
|
| 1774 |
|
| 1775 | #define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */
|
| 1776 | #define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos)
|
| 1777 | #define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */
|
| 1778 | #define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos)
|
| 1779 | #define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */
|
| 1780 | #define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos)
|
| 1781 | #define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */
|
| 1782 | #define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos)
|
| 1783 | #define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */
|
| 1784 | #define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos)
|
| 1785 | #define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */
|
| 1786 | #define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos)
|
| 1787 | #define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */
|
| 1788 | #define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos)
|
| 1789 | #define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */
|
| 1790 | #define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos)
|
| 1791 | #define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */
|
| 1792 | #define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos)
|
| 1793 | #define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */
|
| 1794 | #define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos)
|
| 1795 | #define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */
|
| 1796 | #define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos)
|
| 1797 | #define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */
|
| 1798 | #define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos)
|
| 1799 | #define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */
|
| 1800 | #define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos)
|
| 1801 | #define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */
|
| 1802 | #define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos)
|
| 1803 | #define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */
|
| 1804 | #define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos)
|
| 1805 | #define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */
|
| 1806 | #define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos)
|
| 1807 | #define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */
|
| 1808 | #define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos)
|
| 1809 | #define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */
|
| 1810 | #define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos)
|
| 1811 | #define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */
|
| 1812 | #define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos)
|
| 1813 | #define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */
|
| 1814 | #define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos)
|
| 1815 | #define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */
|
| 1816 | #define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos)
|
| 1817 | #define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */
|
| 1818 | #define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos)
|
| 1819 | #define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */
|
| 1820 | #define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos)
|
| 1821 | #define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */
|
| 1822 | #define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos)
|
| 1823 | #define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */
|
| 1824 | #define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos)
|
| 1825 | #define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */
|
| 1826 | #define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos)
|
| 1827 | #define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */
|
| 1828 | #define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos)
|
| 1829 | #define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */
|
| 1830 | #define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos)
|
| 1831 | #define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */
|
| 1832 | #define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos)
|
| 1833 | #define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */
|
| 1834 | #define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos)
|
| 1835 | #define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */
|
| 1836 | #define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos)
|
| 1837 | #define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */
|
| 1838 | #define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos)
|
| 1839 | #define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */
|
| 1840 |
|
| 1841 | /* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */
|
| 1842 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1843 | typedef union {
|
| 1844 | struct {
|
| 1845 | uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */
|
| 1846 | uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */
|
| 1847 | uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */
|
| 1848 | uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */
|
| 1849 | uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */
|
| 1850 | uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */
|
| 1851 | uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */
|
| 1852 | uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */
|
| 1853 | uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */
|
| 1854 | uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */
|
| 1855 | uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */
|
| 1856 | uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */
|
| 1857 | uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */
|
| 1858 | uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */
|
| 1859 | uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */
|
| 1860 | uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */
|
| 1861 | uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */
|
| 1862 | uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */
|
| 1863 | uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */
|
| 1864 | uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */
|
| 1865 | uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */
|
| 1866 | uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */
|
| 1867 | uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */
|
| 1868 | uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */
|
| 1869 | uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */
|
| 1870 | uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */
|
| 1871 | uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */
|
| 1872 | uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */
|
| 1873 | uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */
|
| 1874 | uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */
|
| 1875 | uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */
|
| 1876 | uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */
|
| 1877 | } bit; /*!< Structure used for bit access */
|
| 1878 | uint32_t reg; /*!< Type used for register access */
|
| 1879 | } CAN_TXBCR_Type;
|
| 1880 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1881 |
|
| 1882 | #define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */
|
| 1883 | #define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */
|
| 1884 |
|
| 1885 | #define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */
|
| 1886 | #define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos)
|
| 1887 | #define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */
|
| 1888 | #define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos)
|
| 1889 | #define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */
|
| 1890 | #define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos)
|
| 1891 | #define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */
|
| 1892 | #define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos)
|
| 1893 | #define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */
|
| 1894 | #define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos)
|
| 1895 | #define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */
|
| 1896 | #define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos)
|
| 1897 | #define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */
|
| 1898 | #define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos)
|
| 1899 | #define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */
|
| 1900 | #define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos)
|
| 1901 | #define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */
|
| 1902 | #define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos)
|
| 1903 | #define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */
|
| 1904 | #define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos)
|
| 1905 | #define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */
|
| 1906 | #define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos)
|
| 1907 | #define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */
|
| 1908 | #define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos)
|
| 1909 | #define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */
|
| 1910 | #define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos)
|
| 1911 | #define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */
|
| 1912 | #define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos)
|
| 1913 | #define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */
|
| 1914 | #define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos)
|
| 1915 | #define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */
|
| 1916 | #define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos)
|
| 1917 | #define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */
|
| 1918 | #define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos)
|
| 1919 | #define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */
|
| 1920 | #define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos)
|
| 1921 | #define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */
|
| 1922 | #define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos)
|
| 1923 | #define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */
|
| 1924 | #define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos)
|
| 1925 | #define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */
|
| 1926 | #define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos)
|
| 1927 | #define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */
|
| 1928 | #define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos)
|
| 1929 | #define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */
|
| 1930 | #define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos)
|
| 1931 | #define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */
|
| 1932 | #define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos)
|
| 1933 | #define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */
|
| 1934 | #define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos)
|
| 1935 | #define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */
|
| 1936 | #define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos)
|
| 1937 | #define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */
|
| 1938 | #define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos)
|
| 1939 | #define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */
|
| 1940 | #define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos)
|
| 1941 | #define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */
|
| 1942 | #define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos)
|
| 1943 | #define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */
|
| 1944 | #define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos)
|
| 1945 | #define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */
|
| 1946 | #define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos)
|
| 1947 | #define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */
|
| 1948 | #define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos)
|
| 1949 | #define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */
|
| 1950 |
|
| 1951 | /* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */
|
| 1952 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1953 | typedef union {
|
| 1954 | struct {
|
| 1955 | uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */
|
| 1956 | uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */
|
| 1957 | uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */
|
| 1958 | uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */
|
| 1959 | uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */
|
| 1960 | uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */
|
| 1961 | uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */
|
| 1962 | uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */
|
| 1963 | uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */
|
| 1964 | uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */
|
| 1965 | uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */
|
| 1966 | uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */
|
| 1967 | uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */
|
| 1968 | uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */
|
| 1969 | uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */
|
| 1970 | uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */
|
| 1971 | uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */
|
| 1972 | uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */
|
| 1973 | uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */
|
| 1974 | uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */
|
| 1975 | uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */
|
| 1976 | uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */
|
| 1977 | uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */
|
| 1978 | uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */
|
| 1979 | uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */
|
| 1980 | uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */
|
| 1981 | uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */
|
| 1982 | uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */
|
| 1983 | uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */
|
| 1984 | uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */
|
| 1985 | uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */
|
| 1986 | uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */
|
| 1987 | } bit; /*!< Structure used for bit access */
|
| 1988 | uint32_t reg; /*!< Type used for register access */
|
| 1989 | } CAN_TXBTO_Type;
|
| 1990 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1991 |
|
| 1992 | #define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */
|
| 1993 | #define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */
|
| 1994 |
|
| 1995 | #define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */
|
| 1996 | #define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos)
|
| 1997 | #define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */
|
| 1998 | #define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos)
|
| 1999 | #define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */
|
| 2000 | #define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos)
|
| 2001 | #define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */
|
| 2002 | #define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos)
|
| 2003 | #define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */
|
| 2004 | #define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos)
|
| 2005 | #define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */
|
| 2006 | #define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos)
|
| 2007 | #define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */
|
| 2008 | #define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos)
|
| 2009 | #define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */
|
| 2010 | #define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos)
|
| 2011 | #define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */
|
| 2012 | #define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos)
|
| 2013 | #define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */
|
| 2014 | #define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos)
|
| 2015 | #define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */
|
| 2016 | #define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos)
|
| 2017 | #define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */
|
| 2018 | #define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos)
|
| 2019 | #define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */
|
| 2020 | #define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos)
|
| 2021 | #define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */
|
| 2022 | #define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos)
|
| 2023 | #define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */
|
| 2024 | #define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos)
|
| 2025 | #define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */
|
| 2026 | #define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos)
|
| 2027 | #define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */
|
| 2028 | #define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos)
|
| 2029 | #define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */
|
| 2030 | #define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos)
|
| 2031 | #define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */
|
| 2032 | #define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos)
|
| 2033 | #define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */
|
| 2034 | #define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos)
|
| 2035 | #define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */
|
| 2036 | #define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos)
|
| 2037 | #define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */
|
| 2038 | #define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos)
|
| 2039 | #define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */
|
| 2040 | #define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos)
|
| 2041 | #define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */
|
| 2042 | #define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos)
|
| 2043 | #define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */
|
| 2044 | #define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos)
|
| 2045 | #define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */
|
| 2046 | #define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos)
|
| 2047 | #define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */
|
| 2048 | #define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos)
|
| 2049 | #define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */
|
| 2050 | #define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos)
|
| 2051 | #define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */
|
| 2052 | #define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos)
|
| 2053 | #define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */
|
| 2054 | #define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos)
|
| 2055 | #define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */
|
| 2056 | #define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos)
|
| 2057 | #define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */
|
| 2058 | #define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos)
|
| 2059 | #define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */
|
| 2060 |
|
| 2061 | /* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */
|
| 2062 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2063 | typedef union {
|
| 2064 | struct {
|
| 2065 | uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */
|
| 2066 | uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */
|
| 2067 | uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */
|
| 2068 | uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */
|
| 2069 | uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */
|
| 2070 | uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */
|
| 2071 | uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */
|
| 2072 | uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */
|
| 2073 | uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */
|
| 2074 | uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */
|
| 2075 | uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */
|
| 2076 | uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */
|
| 2077 | uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */
|
| 2078 | uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */
|
| 2079 | uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */
|
| 2080 | uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */
|
| 2081 | uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */
|
| 2082 | uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */
|
| 2083 | uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */
|
| 2084 | uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */
|
| 2085 | uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */
|
| 2086 | uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */
|
| 2087 | uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */
|
| 2088 | uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */
|
| 2089 | uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */
|
| 2090 | uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */
|
| 2091 | uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */
|
| 2092 | uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */
|
| 2093 | uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */
|
| 2094 | uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */
|
| 2095 | uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */
|
| 2096 | uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */
|
| 2097 | } bit; /*!< Structure used for bit access */
|
| 2098 | uint32_t reg; /*!< Type used for register access */
|
| 2099 | } CAN_TXBCF_Type;
|
| 2100 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2101 |
|
| 2102 | #define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */
|
| 2103 | #define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */
|
| 2104 |
|
| 2105 | #define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */
|
| 2106 | #define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos)
|
| 2107 | #define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */
|
| 2108 | #define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos)
|
| 2109 | #define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */
|
| 2110 | #define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos)
|
| 2111 | #define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */
|
| 2112 | #define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos)
|
| 2113 | #define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */
|
| 2114 | #define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos)
|
| 2115 | #define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */
|
| 2116 | #define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos)
|
| 2117 | #define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */
|
| 2118 | #define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos)
|
| 2119 | #define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */
|
| 2120 | #define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos)
|
| 2121 | #define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */
|
| 2122 | #define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos)
|
| 2123 | #define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */
|
| 2124 | #define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos)
|
| 2125 | #define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */
|
| 2126 | #define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos)
|
| 2127 | #define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */
|
| 2128 | #define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos)
|
| 2129 | #define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */
|
| 2130 | #define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos)
|
| 2131 | #define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */
|
| 2132 | #define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos)
|
| 2133 | #define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */
|
| 2134 | #define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos)
|
| 2135 | #define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */
|
| 2136 | #define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos)
|
| 2137 | #define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */
|
| 2138 | #define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos)
|
| 2139 | #define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */
|
| 2140 | #define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos)
|
| 2141 | #define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */
|
| 2142 | #define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos)
|
| 2143 | #define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */
|
| 2144 | #define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos)
|
| 2145 | #define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */
|
| 2146 | #define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos)
|
| 2147 | #define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */
|
| 2148 | #define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos)
|
| 2149 | #define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */
|
| 2150 | #define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos)
|
| 2151 | #define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */
|
| 2152 | #define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos)
|
| 2153 | #define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */
|
| 2154 | #define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos)
|
| 2155 | #define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */
|
| 2156 | #define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos)
|
| 2157 | #define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */
|
| 2158 | #define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos)
|
| 2159 | #define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */
|
| 2160 | #define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos)
|
| 2161 | #define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */
|
| 2162 | #define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos)
|
| 2163 | #define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */
|
| 2164 | #define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos)
|
| 2165 | #define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */
|
| 2166 | #define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos)
|
| 2167 | #define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */
|
| 2168 | #define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos)
|
| 2169 | #define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */
|
| 2170 |
|
| 2171 | /* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */
|
| 2172 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2173 | typedef union {
|
| 2174 | struct {
|
| 2175 | uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */
|
| 2176 | uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */
|
| 2177 | uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */
|
| 2178 | uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */
|
| 2179 | uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */
|
| 2180 | uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */
|
| 2181 | uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */
|
| 2182 | uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */
|
| 2183 | uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */
|
| 2184 | uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */
|
| 2185 | uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */
|
| 2186 | uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */
|
| 2187 | uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */
|
| 2188 | uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */
|
| 2189 | uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */
|
| 2190 | uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */
|
| 2191 | uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */
|
| 2192 | uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */
|
| 2193 | uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */
|
| 2194 | uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */
|
| 2195 | uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */
|
| 2196 | uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */
|
| 2197 | uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */
|
| 2198 | uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */
|
| 2199 | uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */
|
| 2200 | uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */
|
| 2201 | uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */
|
| 2202 | uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */
|
| 2203 | uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */
|
| 2204 | uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */
|
| 2205 | uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */
|
| 2206 | uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */
|
| 2207 | } bit; /*!< Structure used for bit access */
|
| 2208 | uint32_t reg; /*!< Type used for register access */
|
| 2209 | } CAN_TXBTIE_Type;
|
| 2210 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2211 |
|
| 2212 | #define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */
|
| 2213 | #define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */
|
| 2214 |
|
| 2215 | #define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */
|
| 2216 | #define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos)
|
| 2217 | #define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */
|
| 2218 | #define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos)
|
| 2219 | #define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */
|
| 2220 | #define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos)
|
| 2221 | #define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */
|
| 2222 | #define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos)
|
| 2223 | #define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */
|
| 2224 | #define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos)
|
| 2225 | #define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */
|
| 2226 | #define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos)
|
| 2227 | #define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */
|
| 2228 | #define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos)
|
| 2229 | #define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */
|
| 2230 | #define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos)
|
| 2231 | #define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */
|
| 2232 | #define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos)
|
| 2233 | #define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */
|
| 2234 | #define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos)
|
| 2235 | #define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */
|
| 2236 | #define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos)
|
| 2237 | #define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */
|
| 2238 | #define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos)
|
| 2239 | #define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */
|
| 2240 | #define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos)
|
| 2241 | #define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */
|
| 2242 | #define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos)
|
| 2243 | #define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */
|
| 2244 | #define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos)
|
| 2245 | #define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */
|
| 2246 | #define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos)
|
| 2247 | #define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */
|
| 2248 | #define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos)
|
| 2249 | #define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */
|
| 2250 | #define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos)
|
| 2251 | #define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */
|
| 2252 | #define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos)
|
| 2253 | #define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */
|
| 2254 | #define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos)
|
| 2255 | #define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */
|
| 2256 | #define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos)
|
| 2257 | #define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */
|
| 2258 | #define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos)
|
| 2259 | #define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */
|
| 2260 | #define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos)
|
| 2261 | #define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */
|
| 2262 | #define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos)
|
| 2263 | #define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */
|
| 2264 | #define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos)
|
| 2265 | #define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */
|
| 2266 | #define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos)
|
| 2267 | #define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */
|
| 2268 | #define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos)
|
| 2269 | #define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */
|
| 2270 | #define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos)
|
| 2271 | #define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */
|
| 2272 | #define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos)
|
| 2273 | #define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */
|
| 2274 | #define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos)
|
| 2275 | #define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */
|
| 2276 | #define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos)
|
| 2277 | #define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */
|
| 2278 | #define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos)
|
| 2279 | #define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */
|
| 2280 |
|
| 2281 | /* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */
|
| 2282 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2283 | typedef union {
|
| 2284 | struct {
|
| 2285 | uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */
|
| 2286 | uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */
|
| 2287 | uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */
|
| 2288 | uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */
|
| 2289 | uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */
|
| 2290 | uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */
|
| 2291 | uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */
|
| 2292 | uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */
|
| 2293 | uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */
|
| 2294 | uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */
|
| 2295 | uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */
|
| 2296 | uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */
|
| 2297 | uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */
|
| 2298 | uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */
|
| 2299 | uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */
|
| 2300 | uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */
|
| 2301 | uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */
|
| 2302 | uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */
|
| 2303 | uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */
|
| 2304 | uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */
|
| 2305 | uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */
|
| 2306 | uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */
|
| 2307 | uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */
|
| 2308 | uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */
|
| 2309 | uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */
|
| 2310 | uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */
|
| 2311 | uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */
|
| 2312 | uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */
|
| 2313 | uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */
|
| 2314 | uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */
|
| 2315 | uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */
|
| 2316 | uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */
|
| 2317 | } bit; /*!< Structure used for bit access */
|
| 2318 | uint32_t reg; /*!< Type used for register access */
|
| 2319 | } CAN_TXBCIE_Type;
|
| 2320 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2321 |
|
| 2322 | #define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */
|
| 2323 | #define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */
|
| 2324 |
|
| 2325 | #define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */
|
| 2326 | #define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos)
|
| 2327 | #define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */
|
| 2328 | #define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos)
|
| 2329 | #define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */
|
| 2330 | #define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos)
|
| 2331 | #define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */
|
| 2332 | #define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos)
|
| 2333 | #define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */
|
| 2334 | #define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos)
|
| 2335 | #define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */
|
| 2336 | #define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos)
|
| 2337 | #define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */
|
| 2338 | #define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos)
|
| 2339 | #define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */
|
| 2340 | #define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos)
|
| 2341 | #define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */
|
| 2342 | #define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos)
|
| 2343 | #define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */
|
| 2344 | #define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos)
|
| 2345 | #define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */
|
| 2346 | #define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos)
|
| 2347 | #define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */
|
| 2348 | #define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos)
|
| 2349 | #define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */
|
| 2350 | #define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos)
|
| 2351 | #define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */
|
| 2352 | #define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos)
|
| 2353 | #define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */
|
| 2354 | #define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos)
|
| 2355 | #define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */
|
| 2356 | #define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos)
|
| 2357 | #define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */
|
| 2358 | #define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos)
|
| 2359 | #define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */
|
| 2360 | #define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos)
|
| 2361 | #define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */
|
| 2362 | #define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos)
|
| 2363 | #define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */
|
| 2364 | #define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos)
|
| 2365 | #define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */
|
| 2366 | #define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos)
|
| 2367 | #define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */
|
| 2368 | #define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos)
|
| 2369 | #define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */
|
| 2370 | #define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos)
|
| 2371 | #define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */
|
| 2372 | #define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos)
|
| 2373 | #define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */
|
| 2374 | #define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos)
|
| 2375 | #define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */
|
| 2376 | #define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos)
|
| 2377 | #define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */
|
| 2378 | #define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos)
|
| 2379 | #define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */
|
| 2380 | #define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos)
|
| 2381 | #define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */
|
| 2382 | #define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos)
|
| 2383 | #define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */
|
| 2384 | #define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos)
|
| 2385 | #define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */
|
| 2386 | #define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos)
|
| 2387 | #define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */
|
| 2388 | #define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos)
|
| 2389 | #define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */
|
| 2390 |
|
| 2391 | /* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */
|
| 2392 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2393 | typedef union {
|
| 2394 | struct {
|
| 2395 | uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */
|
| 2396 | uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */
|
| 2397 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 2398 | uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */
|
| 2399 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 2400 | } bit; /*!< Structure used for bit access */
|
| 2401 | uint32_t reg; /*!< Type used for register access */
|
| 2402 | } CAN_TXEFC_Type;
|
| 2403 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2404 |
|
| 2405 | #define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */
|
| 2406 | #define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */
|
| 2407 |
|
| 2408 | #define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */
|
| 2409 | #define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos)
|
| 2410 | #define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos))
|
| 2411 | #define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */
|
| 2412 | #define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos)
|
| 2413 | #define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos))
|
| 2414 | #define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */
|
| 2415 | #define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos)
|
| 2416 | #define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos))
|
| 2417 | #define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */
|
| 2418 |
|
| 2419 | /* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */
|
| 2420 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2421 | typedef union {
|
| 2422 | struct {
|
| 2423 | uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */
|
| 2424 | uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
| 2425 | uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */
|
| 2426 | uint32_t :3; /*!< bit: 13..15 Reserved */
|
| 2427 | uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */
|
| 2428 | uint32_t :3; /*!< bit: 21..23 Reserved */
|
| 2429 | uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */
|
| 2430 | uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */
|
| 2431 | uint32_t :6; /*!< bit: 26..31 Reserved */
|
| 2432 | } bit; /*!< Structure used for bit access */
|
| 2433 | uint32_t reg; /*!< Type used for register access */
|
| 2434 | } CAN_TXEFS_Type;
|
| 2435 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2436 |
|
| 2437 | #define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */
|
| 2438 | #define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */
|
| 2439 |
|
| 2440 | #define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */
|
| 2441 | #define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos)
|
| 2442 | #define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos))
|
| 2443 | #define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */
|
| 2444 | #define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos)
|
| 2445 | #define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos))
|
| 2446 | #define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */
|
| 2447 | #define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos)
|
| 2448 | #define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos))
|
| 2449 | #define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */
|
| 2450 | #define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos)
|
| 2451 | #define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */
|
| 2452 | #define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos)
|
| 2453 | #define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */
|
| 2454 |
|
| 2455 | /* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */
|
| 2456 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2457 | typedef union {
|
| 2458 | struct {
|
| 2459 | uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */
|
| 2460 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 2461 | } bit; /*!< Structure used for bit access */
|
| 2462 | uint32_t reg; /*!< Type used for register access */
|
| 2463 | } CAN_TXEFA_Type;
|
| 2464 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2465 |
|
| 2466 | #define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */
|
| 2467 | #define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */
|
| 2468 |
|
| 2469 | #define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */
|
| 2470 | #define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos)
|
| 2471 | #define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos))
|
| 2472 | #define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */
|
| 2473 |
|
| 2474 | /* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */
|
| 2475 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2476 | typedef union {
|
| 2477 | struct {
|
| 2478 | uint32_t ID:29; /*!< bit: 0..28 Identifier */
|
| 2479 | uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
|
| 2480 | uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
|
| 2481 | uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
|
| 2482 | } bit; /*!< Structure used for bit access */
|
| 2483 | uint32_t reg; /*!< Type used for register access */
|
| 2484 | } CAN_RXBE_0_Type;
|
| 2485 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2486 |
|
| 2487 | #define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */
|
| 2488 | #define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */
|
| 2489 |
|
| 2490 | #define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */
|
| 2491 | #define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos)
|
| 2492 | #define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos))
|
| 2493 | #define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */
|
| 2494 | #define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos)
|
| 2495 | #define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */
|
| 2496 | #define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos)
|
| 2497 | #define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */
|
| 2498 | #define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos)
|
| 2499 | #define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */
|
| 2500 |
|
| 2501 | /* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */
|
| 2502 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2503 | typedef union {
|
| 2504 | struct {
|
| 2505 | uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
|
| 2506 | uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
|
| 2507 | uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
|
| 2508 | uint32_t FDF:1; /*!< bit: 21 FD Format */
|
| 2509 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 2510 | uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
|
| 2511 | uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
|
| 2512 | } bit; /*!< Structure used for bit access */
|
| 2513 | uint32_t reg; /*!< Type used for register access */
|
| 2514 | } CAN_RXBE_1_Type;
|
| 2515 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2516 |
|
| 2517 | #define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */
|
| 2518 | #define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */
|
| 2519 |
|
| 2520 | #define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */
|
| 2521 | #define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos)
|
| 2522 | #define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos))
|
| 2523 | #define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */
|
| 2524 | #define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos)
|
| 2525 | #define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos))
|
| 2526 | #define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */
|
| 2527 | #define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos)
|
| 2528 | #define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */
|
| 2529 | #define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos)
|
| 2530 | #define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */
|
| 2531 | #define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos)
|
| 2532 | #define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos))
|
| 2533 | #define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */
|
| 2534 | #define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos)
|
| 2535 | #define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */
|
| 2536 |
|
| 2537 | /* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */
|
| 2538 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2539 | typedef union {
|
| 2540 | struct {
|
| 2541 | uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
|
| 2542 | uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
|
| 2543 | uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
|
| 2544 | uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
|
| 2545 | } bit; /*!< Structure used for bit access */
|
| 2546 | uint32_t reg; /*!< Type used for register access */
|
| 2547 | } CAN_RXBE_DATA_Type;
|
| 2548 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2549 |
|
| 2550 | #define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */
|
| 2551 | #define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */
|
| 2552 |
|
| 2553 | #define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */
|
| 2554 | #define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos)
|
| 2555 | #define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos))
|
| 2556 | #define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */
|
| 2557 | #define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos)
|
| 2558 | #define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos))
|
| 2559 | #define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */
|
| 2560 | #define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos)
|
| 2561 | #define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos))
|
| 2562 | #define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */
|
| 2563 | #define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos)
|
| 2564 | #define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos))
|
| 2565 | #define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */
|
| 2566 |
|
| 2567 | /* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */
|
| 2568 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2569 | typedef union {
|
| 2570 | struct {
|
| 2571 | uint32_t ID:29; /*!< bit: 0..28 Identifier */
|
| 2572 | uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
|
| 2573 | uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
|
| 2574 | uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
|
| 2575 | } bit; /*!< Structure used for bit access */
|
| 2576 | uint32_t reg; /*!< Type used for register access */
|
| 2577 | } CAN_RXF0E_0_Type;
|
| 2578 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2579 |
|
| 2580 | #define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */
|
| 2581 | #define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */
|
| 2582 |
|
| 2583 | #define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */
|
| 2584 | #define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos)
|
| 2585 | #define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos))
|
| 2586 | #define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */
|
| 2587 | #define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos)
|
| 2588 | #define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */
|
| 2589 | #define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos)
|
| 2590 | #define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */
|
| 2591 | #define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos)
|
| 2592 | #define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */
|
| 2593 |
|
| 2594 | /* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */
|
| 2595 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2596 | typedef union {
|
| 2597 | struct {
|
| 2598 | uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
|
| 2599 | uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
|
| 2600 | uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
|
| 2601 | uint32_t FDF:1; /*!< bit: 21 FD Format */
|
| 2602 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 2603 | uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
|
| 2604 | uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
|
| 2605 | } bit; /*!< Structure used for bit access */
|
| 2606 | uint32_t reg; /*!< Type used for register access */
|
| 2607 | } CAN_RXF0E_1_Type;
|
| 2608 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2609 |
|
| 2610 | #define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */
|
| 2611 | #define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */
|
| 2612 |
|
| 2613 | #define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */
|
| 2614 | #define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos)
|
| 2615 | #define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos))
|
| 2616 | #define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */
|
| 2617 | #define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos)
|
| 2618 | #define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos))
|
| 2619 | #define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */
|
| 2620 | #define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos)
|
| 2621 | #define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */
|
| 2622 | #define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos)
|
| 2623 | #define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */
|
| 2624 | #define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos)
|
| 2625 | #define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos))
|
| 2626 | #define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */
|
| 2627 | #define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos)
|
| 2628 | #define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */
|
| 2629 |
|
| 2630 | /* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */
|
| 2631 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2632 | typedef union {
|
| 2633 | struct {
|
| 2634 | uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
|
| 2635 | uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
|
| 2636 | uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
|
| 2637 | uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
|
| 2638 | } bit; /*!< Structure used for bit access */
|
| 2639 | uint32_t reg; /*!< Type used for register access */
|
| 2640 | } CAN_RXF0E_DATA_Type;
|
| 2641 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2642 |
|
| 2643 | #define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */
|
| 2644 | #define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */
|
| 2645 |
|
| 2646 | #define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */
|
| 2647 | #define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos)
|
| 2648 | #define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos))
|
| 2649 | #define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */
|
| 2650 | #define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos)
|
| 2651 | #define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos))
|
| 2652 | #define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */
|
| 2653 | #define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos)
|
| 2654 | #define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos))
|
| 2655 | #define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */
|
| 2656 | #define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos)
|
| 2657 | #define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos))
|
| 2658 | #define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */
|
| 2659 |
|
| 2660 | /* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */
|
| 2661 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2662 | typedef union {
|
| 2663 | struct {
|
| 2664 | uint32_t ID:29; /*!< bit: 0..28 Identifier */
|
| 2665 | uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
|
| 2666 | uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
|
| 2667 | uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
|
| 2668 | } bit; /*!< Structure used for bit access */
|
| 2669 | uint32_t reg; /*!< Type used for register access */
|
| 2670 | } CAN_RXF1E_0_Type;
|
| 2671 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2672 |
|
| 2673 | #define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */
|
| 2674 | #define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */
|
| 2675 |
|
| 2676 | #define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */
|
| 2677 | #define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos)
|
| 2678 | #define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos))
|
| 2679 | #define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */
|
| 2680 | #define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos)
|
| 2681 | #define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */
|
| 2682 | #define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos)
|
| 2683 | #define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */
|
| 2684 | #define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos)
|
| 2685 | #define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */
|
| 2686 |
|
| 2687 | /* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */
|
| 2688 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2689 | typedef union {
|
| 2690 | struct {
|
| 2691 | uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
|
| 2692 | uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
|
| 2693 | uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
|
| 2694 | uint32_t FDF:1; /*!< bit: 21 FD Format */
|
| 2695 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 2696 | uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
|
| 2697 | uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
|
| 2698 | } bit; /*!< Structure used for bit access */
|
| 2699 | uint32_t reg; /*!< Type used for register access */
|
| 2700 | } CAN_RXF1E_1_Type;
|
| 2701 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2702 |
|
| 2703 | #define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */
|
| 2704 | #define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */
|
| 2705 |
|
| 2706 | #define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */
|
| 2707 | #define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos)
|
| 2708 | #define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos))
|
| 2709 | #define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */
|
| 2710 | #define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos)
|
| 2711 | #define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos))
|
| 2712 | #define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */
|
| 2713 | #define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos)
|
| 2714 | #define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */
|
| 2715 | #define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos)
|
| 2716 | #define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */
|
| 2717 | #define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos)
|
| 2718 | #define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos))
|
| 2719 | #define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */
|
| 2720 | #define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos)
|
| 2721 | #define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */
|
| 2722 |
|
| 2723 | /* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */
|
| 2724 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2725 | typedef union {
|
| 2726 | struct {
|
| 2727 | uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
|
| 2728 | uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
|
| 2729 | uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
|
| 2730 | uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
|
| 2731 | } bit; /*!< Structure used for bit access */
|
| 2732 | uint32_t reg; /*!< Type used for register access */
|
| 2733 | } CAN_RXF1E_DATA_Type;
|
| 2734 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2735 |
|
| 2736 | #define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */
|
| 2737 | #define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */
|
| 2738 |
|
| 2739 | #define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */
|
| 2740 | #define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos)
|
| 2741 | #define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos))
|
| 2742 | #define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */
|
| 2743 | #define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos)
|
| 2744 | #define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos))
|
| 2745 | #define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */
|
| 2746 | #define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos)
|
| 2747 | #define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos))
|
| 2748 | #define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */
|
| 2749 | #define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos)
|
| 2750 | #define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos))
|
| 2751 | #define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */
|
| 2752 |
|
| 2753 | /* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */
|
| 2754 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2755 | typedef union {
|
| 2756 | struct {
|
| 2757 | uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */
|
| 2758 | uint32_t :5; /*!< bit: 11..15 Reserved */
|
| 2759 | uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */
|
| 2760 | uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */
|
| 2761 | uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */
|
| 2762 | } bit; /*!< Structure used for bit access */
|
| 2763 | uint32_t reg; /*!< Type used for register access */
|
| 2764 | } CAN_SIDFE_0_Type;
|
| 2765 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2766 |
|
| 2767 | #define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */
|
| 2768 | #define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */
|
| 2769 |
|
| 2770 | #define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */
|
| 2771 | #define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos)
|
| 2772 | #define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos))
|
| 2773 | #define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */
|
| 2774 | #define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos)
|
| 2775 | #define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos))
|
| 2776 | #define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */
|
| 2777 | #define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos)
|
| 2778 | #define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos))
|
| 2779 | #define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */
|
| 2780 | #define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */
|
| 2781 | #define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */
|
| 2782 | #define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */
|
| 2783 | #define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */
|
| 2784 | #define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */
|
| 2785 | #define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */
|
| 2786 | #define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */
|
| 2787 | #define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2788 | #define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2789 | #define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2790 | #define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2791 | #define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2792 | #define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2793 | #define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2794 | #define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos)
|
| 2795 | #define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */
|
| 2796 | #define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos)
|
| 2797 | #define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos))
|
| 2798 | #define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */
|
| 2799 | #define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */
|
| 2800 | #define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */
|
| 2801 | #define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos)
|
| 2802 | #define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos)
|
| 2803 | #define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos)
|
| 2804 | #define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */
|
| 2805 |
|
| 2806 | /* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */
|
| 2807 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2808 | typedef union {
|
| 2809 | struct {
|
| 2810 | uint32_t ID:29; /*!< bit: 0..28 Identifier */
|
| 2811 | uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
|
| 2812 | uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
|
| 2813 | uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
|
| 2814 | } bit; /*!< Structure used for bit access */
|
| 2815 | uint32_t reg; /*!< Type used for register access */
|
| 2816 | } CAN_TXBE_0_Type;
|
| 2817 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2818 |
|
| 2819 | #define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */
|
| 2820 | #define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */
|
| 2821 |
|
| 2822 | #define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */
|
| 2823 | #define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos)
|
| 2824 | #define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos))
|
| 2825 | #define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */
|
| 2826 | #define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos)
|
| 2827 | #define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */
|
| 2828 | #define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos)
|
| 2829 | #define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */
|
| 2830 | #define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos)
|
| 2831 | #define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */
|
| 2832 |
|
| 2833 | /* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */
|
| 2834 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2835 | typedef union {
|
| 2836 | struct {
|
| 2837 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
| 2838 | uint32_t DLC:4; /*!< bit: 16..19 Identifier */
|
| 2839 | uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
|
| 2840 | uint32_t FDF:1; /*!< bit: 21 FD Format */
|
| 2841 | uint32_t :1; /*!< bit: 22 Reserved */
|
| 2842 | uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */
|
| 2843 | uint32_t MM:8; /*!< bit: 24..31 Message Marker */
|
| 2844 | } bit; /*!< Structure used for bit access */
|
| 2845 | uint32_t reg; /*!< Type used for register access */
|
| 2846 | } CAN_TXBE_1_Type;
|
| 2847 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2848 |
|
| 2849 | #define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */
|
| 2850 | #define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */
|
| 2851 |
|
| 2852 | #define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */
|
| 2853 | #define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos)
|
| 2854 | #define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos))
|
| 2855 | #define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */
|
| 2856 | #define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos)
|
| 2857 | #define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */
|
| 2858 | #define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos)
|
| 2859 | #define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */
|
| 2860 | #define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos)
|
| 2861 | #define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */
|
| 2862 | #define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos)
|
| 2863 | #define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos))
|
| 2864 | #define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */
|
| 2865 |
|
| 2866 | /* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */
|
| 2867 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2868 | typedef union {
|
| 2869 | struct {
|
| 2870 | uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
|
| 2871 | uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
|
| 2872 | uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
|
| 2873 | uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
|
| 2874 | } bit; /*!< Structure used for bit access */
|
| 2875 | uint32_t reg; /*!< Type used for register access */
|
| 2876 | } CAN_TXBE_DATA_Type;
|
| 2877 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2878 |
|
| 2879 | #define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */
|
| 2880 | #define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */
|
| 2881 |
|
| 2882 | #define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */
|
| 2883 | #define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos)
|
| 2884 | #define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos))
|
| 2885 | #define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */
|
| 2886 | #define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos)
|
| 2887 | #define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos))
|
| 2888 | #define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */
|
| 2889 | #define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos)
|
| 2890 | #define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos))
|
| 2891 | #define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */
|
| 2892 | #define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos)
|
| 2893 | #define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos))
|
| 2894 | #define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */
|
| 2895 |
|
| 2896 | /* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */
|
| 2897 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2898 | typedef union {
|
| 2899 | struct {
|
| 2900 | uint32_t ID:29; /*!< bit: 0..28 Identifier */
|
| 2901 | uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
|
| 2902 | uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */
|
| 2903 | uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
|
| 2904 | } bit; /*!< Structure used for bit access */
|
| 2905 | uint32_t reg; /*!< Type used for register access */
|
| 2906 | } CAN_TXEFE_0_Type;
|
| 2907 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2908 |
|
| 2909 | #define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */
|
| 2910 | #define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */
|
| 2911 |
|
| 2912 | #define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */
|
| 2913 | #define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos)
|
| 2914 | #define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos))
|
| 2915 | #define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */
|
| 2916 | #define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos)
|
| 2917 | #define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */
|
| 2918 | #define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos)
|
| 2919 | #define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */
|
| 2920 | #define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos)
|
| 2921 | #define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */
|
| 2922 |
|
| 2923 | /* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */
|
| 2924 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2925 | typedef union {
|
| 2926 | struct {
|
| 2927 | uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */
|
| 2928 | uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
|
| 2929 | uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
|
| 2930 | uint32_t FDF:1; /*!< bit: 21 FD Format */
|
| 2931 | uint32_t ET:2; /*!< bit: 22..23 Event Type */
|
| 2932 | uint32_t MM:8; /*!< bit: 24..31 Message Marker */
|
| 2933 | } bit; /*!< Structure used for bit access */
|
| 2934 | uint32_t reg; /*!< Type used for register access */
|
| 2935 | } CAN_TXEFE_1_Type;
|
| 2936 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2937 |
|
| 2938 | #define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */
|
| 2939 | #define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */
|
| 2940 |
|
| 2941 | #define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */
|
| 2942 | #define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos)
|
| 2943 | #define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos))
|
| 2944 | #define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */
|
| 2945 | #define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos)
|
| 2946 | #define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos))
|
| 2947 | #define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */
|
| 2948 | #define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos)
|
| 2949 | #define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */
|
| 2950 | #define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos)
|
| 2951 | #define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */
|
| 2952 | #define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos)
|
| 2953 | #define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos))
|
| 2954 | #define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */
|
| 2955 | #define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */
|
| 2956 | #define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos)
|
| 2957 | #define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos)
|
| 2958 | #define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */
|
| 2959 | #define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos)
|
| 2960 | #define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos))
|
| 2961 | #define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */
|
| 2962 |
|
| 2963 | /* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */
|
| 2964 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2965 | typedef union {
|
| 2966 | struct {
|
| 2967 | uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */
|
| 2968 | uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */
|
| 2969 | } bit; /*!< Structure used for bit access */
|
| 2970 | uint32_t reg; /*!< Type used for register access */
|
| 2971 | } CAN_XIDFE_0_Type;
|
| 2972 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2973 |
|
| 2974 | #define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */
|
| 2975 | #define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */
|
| 2976 |
|
| 2977 | #define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */
|
| 2978 | #define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos)
|
| 2979 | #define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos))
|
| 2980 | #define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */
|
| 2981 | #define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos)
|
| 2982 | #define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos))
|
| 2983 | #define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */
|
| 2984 | #define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */
|
| 2985 | #define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */
|
| 2986 | #define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */
|
| 2987 | #define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */
|
| 2988 | #define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */
|
| 2989 | #define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */
|
| 2990 | #define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */
|
| 2991 | #define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2992 | #define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2993 | #define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2994 | #define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2995 | #define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2996 | #define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2997 | #define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2998 | #define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos)
|
| 2999 | #define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */
|
| 3000 |
|
| 3001 | /* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */
|
| 3002 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3003 | typedef union {
|
| 3004 | struct {
|
| 3005 | uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */
|
| 3006 | uint32_t :1; /*!< bit: 29 Reserved */
|
| 3007 | uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */
|
| 3008 | } bit; /*!< Structure used for bit access */
|
| 3009 | uint32_t reg; /*!< Type used for register access */
|
| 3010 | } CAN_XIDFE_1_Type;
|
| 3011 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3012 |
|
| 3013 | #define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */
|
| 3014 | #define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */
|
| 3015 |
|
| 3016 | #define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */
|
| 3017 | #define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos)
|
| 3018 | #define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos))
|
| 3019 | #define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */
|
| 3020 | #define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos)
|
| 3021 | #define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos))
|
| 3022 | #define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */
|
| 3023 | #define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */
|
| 3024 | #define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */
|
| 3025 | #define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */
|
| 3026 | #define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos)
|
| 3027 | #define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos)
|
| 3028 | #define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos)
|
| 3029 | #define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos)
|
| 3030 | #define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */
|
| 3031 |
|
| 3032 | /** \brief CAN APB hardware registers */
|
| 3033 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3034 | typedef struct {
|
| 3035 | __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */
|
| 3036 | __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */
|
| 3037 | __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */
|
| 3038 | __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */
|
| 3039 | __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */
|
| 3040 | __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */
|
| 3041 | __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */
|
| 3042 | __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */
|
| 3043 | __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */
|
| 3044 | __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */
|
| 3045 | __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */
|
| 3046 | __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */
|
| 3047 | RoReg8 Reserved1[0x10];
|
| 3048 | __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */
|
| 3049 | __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */
|
| 3050 | __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */
|
| 3051 | RoReg8 Reserved2[0x4];
|
| 3052 | __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */
|
| 3053 | __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */
|
| 3054 | __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */
|
| 3055 | __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */
|
| 3056 | RoReg8 Reserved3[0x20];
|
| 3057 | __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */
|
| 3058 | __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */
|
| 3059 | __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */
|
| 3060 | RoReg8 Reserved4[0x4];
|
| 3061 | __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */
|
| 3062 | __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */
|
| 3063 | __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */
|
| 3064 | __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */
|
| 3065 | __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */
|
| 3066 | __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */
|
| 3067 | __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */
|
| 3068 | __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */
|
| 3069 | __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */
|
| 3070 | __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */
|
| 3071 | __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */
|
| 3072 | __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */
|
| 3073 | __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */
|
| 3074 | __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */
|
| 3075 | __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */
|
| 3076 | __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */
|
| 3077 | __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */
|
| 3078 | __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */
|
| 3079 | __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */
|
| 3080 | __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */
|
| 3081 | __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */
|
| 3082 | __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */
|
| 3083 | RoReg8 Reserved5[0x8];
|
| 3084 | __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */
|
| 3085 | __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */
|
| 3086 | __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */
|
| 3087 | } Can;
|
| 3088 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3089 |
|
| 3090 | /** \brief CAN Mram_rxbe hardware registers */
|
| 3091 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3092 | typedef struct {
|
| 3093 | __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */
|
| 3094 | __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */
|
| 3095 | __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */
|
| 3096 | } CanMramRxbe
|
| 3097 | #ifdef __GNUC__
|
| 3098 | __attribute__ ((aligned (4)))
|
| 3099 | #endif
|
| 3100 | ;
|
| 3101 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3102 |
|
| 3103 | /** \brief CAN Mram_rxf0e hardware registers */
|
| 3104 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3105 | typedef struct {
|
| 3106 | __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */
|
| 3107 | __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */
|
| 3108 | __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */
|
| 3109 | } CanMramRxf0e
|
| 3110 | #ifdef __GNUC__
|
| 3111 | __attribute__ ((aligned (4)))
|
| 3112 | #endif
|
| 3113 | ;
|
| 3114 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3115 |
|
| 3116 | /** \brief CAN Mram_rxf1e hardware registers */
|
| 3117 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3118 | typedef struct {
|
| 3119 | __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */
|
| 3120 | __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */
|
| 3121 | __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */
|
| 3122 | } CanMramRxf1e
|
| 3123 | #ifdef __GNUC__
|
| 3124 | __attribute__ ((aligned (4)))
|
| 3125 | #endif
|
| 3126 | ;
|
| 3127 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3128 |
|
| 3129 | /** \brief CAN Mram_sidfe hardware registers */
|
| 3130 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3131 | typedef struct {
|
| 3132 | __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */
|
| 3133 | } CanMramSidfe
|
| 3134 | #ifdef __GNUC__
|
| 3135 | __attribute__ ((aligned (4)))
|
| 3136 | #endif
|
| 3137 | ;
|
| 3138 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3139 |
|
| 3140 | /** \brief CAN Mram_txbe hardware registers */
|
| 3141 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3142 | typedef struct {
|
| 3143 | __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */
|
| 3144 | __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */
|
| 3145 | __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */
|
| 3146 | } CanMramTxbe
|
| 3147 | #ifdef __GNUC__
|
| 3148 | __attribute__ ((aligned (4)))
|
| 3149 | #endif
|
| 3150 | ;
|
| 3151 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3152 |
|
| 3153 | /** \brief CAN Mram_txefe hardware registers */
|
| 3154 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3155 | typedef struct {
|
| 3156 | __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */
|
| 3157 | __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */
|
| 3158 | } CanMramTxefe
|
| 3159 | #ifdef __GNUC__
|
| 3160 | __attribute__ ((aligned (4)))
|
| 3161 | #endif
|
| 3162 | ;
|
| 3163 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3164 |
|
| 3165 | /** \brief CAN Mram_xifde hardware registers */
|
| 3166 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 3167 | typedef struct {
|
| 3168 | __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */
|
| 3169 | __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */
|
| 3170 | } CanMramXifde
|
| 3171 | #ifdef __GNUC__
|
| 3172 | __attribute__ ((aligned (4)))
|
| 3173 | #endif
|
| 3174 | ;
|
| 3175 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 3176 |
|
| 3177 | #define SECTION_CAN_MRAM_RXBE
|
| 3178 | #define SECTION_CAN_MRAM_RXF0E
|
| 3179 | #define SECTION_CAN_MRAM_RXF1E
|
| 3180 | #define SECTION_CAN_MRAM_SIDFE
|
| 3181 | #define SECTION_CAN_MRAM_TXBE
|
| 3182 | #define SECTION_CAN_MRAM_TXEFE
|
| 3183 | #define SECTION_CAN_MRAM_XIFDE
|
| 3184 |
|
| 3185 | /*@}*/
|
| 3186 |
|
| 3187 | #endif /* _SAME54_CAN_COMPONENT_ */
|