Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM SUPC |
| 5 | * |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 6 | * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_SUPC_COMPONENT_ |
| 35 | #ifndef _HRI_SUPC_E54_H_INCLUDED_ |
| 36 | #define _HRI_SUPC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_SUPC_CRITICAL_SECTIONS) |
| 46 | #define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define SUPC_CRITICAL_SECTION_ENTER() |
| 50 | #define SUPC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_supc_bbps_reg_t; |
| 54 | typedef uint32_t hri_supc_bkin_reg_t; |
| 55 | typedef uint32_t hri_supc_bkout_reg_t; |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 56 | typedef uint32_t hri_supc_bod33_reg_t; |
| 57 | typedef uint32_t hri_supc_intenset_reg_t; |
| 58 | typedef uint32_t hri_supc_intflag_reg_t; |
| 59 | typedef uint32_t hri_supc_status_reg_t; |
| 60 | typedef uint32_t hri_supc_vref_reg_t; |
| 61 | typedef uint32_t hri_supc_vreg_reg_t; |
| 62 | |
| 63 | static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) |
| 64 | { |
| 65 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; |
| 66 | } |
| 67 | |
| 68 | static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) |
| 69 | { |
| 70 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; |
| 71 | } |
| 72 | |
| 73 | static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) |
| 74 | { |
| 75 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; |
| 76 | } |
| 77 | |
| 78 | static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) |
| 79 | { |
| 80 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; |
| 81 | } |
| 82 | |
| 83 | static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) |
| 84 | { |
| 85 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; |
| 86 | } |
| 87 | |
| 88 | static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) |
| 89 | { |
| 90 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; |
| 91 | } |
| 92 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 93 | static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) |
| 94 | { |
| 95 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; |
| 96 | } |
| 97 | |
| 98 | static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) |
| 99 | { |
| 100 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; |
| 101 | } |
| 102 | |
| 103 | static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) |
| 104 | { |
| 105 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; |
| 106 | } |
| 107 | |
| 108 | static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) |
| 109 | { |
| 110 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; |
| 111 | } |
| 112 | |
| 113 | static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) |
| 114 | { |
| 115 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; |
| 116 | } |
| 117 | |
| 118 | static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) |
| 119 | { |
| 120 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; |
| 121 | } |
| 122 | |
| 123 | static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) |
| 124 | { |
| 125 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; |
| 126 | } |
| 127 | |
| 128 | static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) |
| 129 | { |
| 130 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; |
| 131 | } |
| 132 | |
| 133 | static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) |
| 134 | { |
| 135 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; |
| 136 | } |
| 137 | |
| 138 | static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) |
| 139 | { |
| 140 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; |
| 141 | } |
| 142 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 143 | static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) |
| 144 | { |
| 145 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; |
| 146 | } |
| 147 | |
| 148 | static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) |
| 149 | { |
| 150 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; |
| 151 | } |
| 152 | |
| 153 | static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) |
| 154 | { |
| 155 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; |
| 156 | } |
| 157 | |
| 158 | static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) |
| 159 | { |
| 160 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; |
| 161 | } |
| 162 | |
| 163 | static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) |
| 164 | { |
| 165 | uint32_t tmp; |
| 166 | tmp = ((Supc *)hw)->INTFLAG.reg; |
| 167 | tmp &= mask; |
| 168 | return tmp; |
| 169 | } |
| 170 | |
| 171 | static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) |
| 172 | { |
| 173 | return ((Supc *)hw)->INTFLAG.reg; |
| 174 | } |
| 175 | |
| 176 | static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) |
| 177 | { |
| 178 | ((Supc *)hw)->INTFLAG.reg = mask; |
| 179 | } |
| 180 | |
| 181 | static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) |
| 182 | { |
| 183 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; |
| 184 | } |
| 185 | |
| 186 | static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) |
| 187 | { |
| 188 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; |
| 189 | } |
| 190 | |
| 191 | static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) |
| 192 | { |
| 193 | if (value == 0x0) { |
| 194 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; |
| 195 | } else { |
| 196 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) |
| 201 | { |
| 202 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; |
| 203 | } |
| 204 | |
| 205 | static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) |
| 206 | { |
| 207 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; |
| 208 | } |
| 209 | |
| 210 | static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) |
| 211 | { |
| 212 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; |
| 213 | } |
| 214 | |
| 215 | static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) |
| 216 | { |
| 217 | if (value == 0x0) { |
| 218 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; |
| 219 | } else { |
| 220 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) |
| 225 | { |
| 226 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; |
| 227 | } |
| 228 | |
| 229 | static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) |
| 230 | { |
| 231 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; |
| 232 | } |
| 233 | |
| 234 | static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) |
| 235 | { |
| 236 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; |
| 237 | } |
| 238 | |
| 239 | static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) |
| 240 | { |
| 241 | if (value == 0x0) { |
| 242 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; |
| 243 | } else { |
| 244 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) |
| 249 | { |
| 250 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; |
| 251 | } |
| 252 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 253 | static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) |
| 254 | { |
| 255 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; |
| 256 | } |
| 257 | |
| 258 | static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) |
| 259 | { |
| 260 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; |
| 261 | } |
| 262 | |
| 263 | static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) |
| 264 | { |
| 265 | if (value == 0x0) { |
| 266 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; |
| 267 | } else { |
| 268 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) |
| 273 | { |
| 274 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; |
| 275 | } |
| 276 | |
| 277 | static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) |
| 278 | { |
| 279 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; |
| 280 | } |
| 281 | |
| 282 | static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) |
| 283 | { |
| 284 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; |
| 285 | } |
| 286 | |
| 287 | static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) |
| 288 | { |
| 289 | if (value == 0x0) { |
| 290 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; |
| 291 | } else { |
| 292 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) |
| 297 | { |
| 298 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; |
| 299 | } |
| 300 | |
| 301 | static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) |
| 302 | { |
| 303 | ((Supc *)hw)->INTENSET.reg = mask; |
| 304 | } |
| 305 | |
| 306 | static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) |
| 307 | { |
| 308 | uint32_t tmp; |
| 309 | tmp = ((Supc *)hw)->INTENSET.reg; |
| 310 | tmp &= mask; |
| 311 | return tmp; |
| 312 | } |
| 313 | |
| 314 | static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) |
| 315 | { |
| 316 | return ((Supc *)hw)->INTENSET.reg; |
| 317 | } |
| 318 | |
| 319 | static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) |
| 320 | { |
| 321 | ((Supc *)hw)->INTENSET.reg = data; |
| 322 | ((Supc *)hw)->INTENCLR.reg = ~data; |
| 323 | } |
| 324 | |
| 325 | static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) |
| 326 | { |
| 327 | ((Supc *)hw)->INTENCLR.reg = mask; |
| 328 | } |
| 329 | |
| 330 | static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) |
| 331 | { |
| 332 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; |
| 333 | } |
| 334 | |
| 335 | static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) |
| 336 | { |
| 337 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; |
| 338 | } |
| 339 | |
| 340 | static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) |
| 341 | { |
| 342 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; |
| 343 | } |
| 344 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 345 | static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) |
| 346 | { |
| 347 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; |
| 348 | } |
| 349 | |
| 350 | static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) |
| 351 | { |
| 352 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; |
| 353 | } |
| 354 | |
| 355 | static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) |
| 356 | { |
| 357 | uint32_t tmp; |
| 358 | tmp = ((Supc *)hw)->STATUS.reg; |
| 359 | tmp &= mask; |
| 360 | return tmp; |
| 361 | } |
| 362 | |
| 363 | static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) |
| 364 | { |
| 365 | return ((Supc *)hw)->STATUS.reg; |
| 366 | } |
| 367 | |
| 368 | static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) |
| 369 | { |
| 370 | return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; |
| 371 | } |
| 372 | |
| 373 | static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) |
| 374 | { |
| 375 | return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; |
| 376 | } |
| 377 | |
| 378 | static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) |
| 379 | { |
| 380 | uint32_t tmp; |
| 381 | tmp = ((Supc *)hw)->BKIN.reg; |
| 382 | tmp &= mask; |
| 383 | return tmp; |
| 384 | } |
| 385 | |
| 386 | static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) |
| 387 | { |
| 388 | return ((Supc *)hw)->BKIN.reg; |
| 389 | } |
| 390 | |
| 391 | static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) |
| 392 | { |
| 393 | SUPC_CRITICAL_SECTION_ENTER(); |
| 394 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; |
| 395 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 396 | } |
| 397 | |
| 398 | static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) |
| 399 | { |
| 400 | uint32_t tmp; |
| 401 | tmp = ((Supc *)hw)->BOD33.reg; |
| 402 | tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; |
| 403 | return (bool)tmp; |
| 404 | } |
| 405 | |
| 406 | static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) |
| 407 | { |
| 408 | uint32_t tmp; |
| 409 | SUPC_CRITICAL_SECTION_ENTER(); |
| 410 | tmp = ((Supc *)hw)->BOD33.reg; |
| 411 | tmp &= ~SUPC_BOD33_ENABLE; |
| 412 | tmp |= value << SUPC_BOD33_ENABLE_Pos; |
| 413 | ((Supc *)hw)->BOD33.reg = tmp; |
| 414 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 415 | } |
| 416 | |
| 417 | static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) |
| 418 | { |
| 419 | SUPC_CRITICAL_SECTION_ENTER(); |
| 420 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; |
| 421 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 422 | } |
| 423 | |
| 424 | static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) |
| 425 | { |
| 426 | SUPC_CRITICAL_SECTION_ENTER(); |
| 427 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; |
| 428 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 429 | } |
| 430 | |
| 431 | static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) |
| 432 | { |
| 433 | SUPC_CRITICAL_SECTION_ENTER(); |
| 434 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; |
| 435 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 436 | } |
| 437 | |
| 438 | static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) |
| 439 | { |
| 440 | uint32_t tmp; |
| 441 | tmp = ((Supc *)hw)->BOD33.reg; |
| 442 | tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; |
| 443 | return (bool)tmp; |
| 444 | } |
| 445 | |
| 446 | static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) |
| 447 | { |
| 448 | uint32_t tmp; |
| 449 | SUPC_CRITICAL_SECTION_ENTER(); |
| 450 | tmp = ((Supc *)hw)->BOD33.reg; |
| 451 | tmp &= ~SUPC_BOD33_STDBYCFG; |
| 452 | tmp |= value << SUPC_BOD33_STDBYCFG_Pos; |
| 453 | ((Supc *)hw)->BOD33.reg = tmp; |
| 454 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 455 | } |
| 456 | |
| 457 | static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) |
| 458 | { |
| 459 | SUPC_CRITICAL_SECTION_ENTER(); |
| 460 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; |
| 461 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 462 | } |
| 463 | |
| 464 | static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) |
| 465 | { |
| 466 | SUPC_CRITICAL_SECTION_ENTER(); |
| 467 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; |
| 468 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 469 | } |
| 470 | |
| 471 | static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) |
| 472 | { |
| 473 | SUPC_CRITICAL_SECTION_ENTER(); |
| 474 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; |
| 475 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 476 | } |
| 477 | |
| 478 | static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) |
| 479 | { |
| 480 | uint32_t tmp; |
| 481 | tmp = ((Supc *)hw)->BOD33.reg; |
| 482 | tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; |
| 483 | return (bool)tmp; |
| 484 | } |
| 485 | |
| 486 | static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) |
| 487 | { |
| 488 | uint32_t tmp; |
| 489 | SUPC_CRITICAL_SECTION_ENTER(); |
| 490 | tmp = ((Supc *)hw)->BOD33.reg; |
| 491 | tmp &= ~SUPC_BOD33_RUNSTDBY; |
| 492 | tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; |
| 493 | ((Supc *)hw)->BOD33.reg = tmp; |
| 494 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 495 | } |
| 496 | |
| 497 | static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) |
| 498 | { |
| 499 | SUPC_CRITICAL_SECTION_ENTER(); |
| 500 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; |
| 501 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 502 | } |
| 503 | |
| 504 | static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) |
| 505 | { |
| 506 | SUPC_CRITICAL_SECTION_ENTER(); |
| 507 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; |
| 508 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 509 | } |
| 510 | |
| 511 | static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) |
| 512 | { |
| 513 | SUPC_CRITICAL_SECTION_ENTER(); |
| 514 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; |
| 515 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 516 | } |
| 517 | |
| 518 | static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) |
| 519 | { |
| 520 | uint32_t tmp; |
| 521 | tmp = ((Supc *)hw)->BOD33.reg; |
| 522 | tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; |
| 523 | return (bool)tmp; |
| 524 | } |
| 525 | |
| 526 | static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) |
| 527 | { |
| 528 | uint32_t tmp; |
| 529 | SUPC_CRITICAL_SECTION_ENTER(); |
| 530 | tmp = ((Supc *)hw)->BOD33.reg; |
| 531 | tmp &= ~SUPC_BOD33_RUNHIB; |
| 532 | tmp |= value << SUPC_BOD33_RUNHIB_Pos; |
| 533 | ((Supc *)hw)->BOD33.reg = tmp; |
| 534 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 535 | } |
| 536 | |
| 537 | static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) |
| 538 | { |
| 539 | SUPC_CRITICAL_SECTION_ENTER(); |
| 540 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; |
| 541 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 542 | } |
| 543 | |
| 544 | static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) |
| 545 | { |
| 546 | SUPC_CRITICAL_SECTION_ENTER(); |
| 547 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; |
| 548 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 549 | } |
| 550 | |
| 551 | static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) |
| 552 | { |
| 553 | SUPC_CRITICAL_SECTION_ENTER(); |
| 554 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; |
| 555 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 556 | } |
| 557 | |
| 558 | static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) |
| 559 | { |
| 560 | uint32_t tmp; |
| 561 | tmp = ((Supc *)hw)->BOD33.reg; |
| 562 | tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; |
| 563 | return (bool)tmp; |
| 564 | } |
| 565 | |
| 566 | static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) |
| 567 | { |
| 568 | uint32_t tmp; |
| 569 | SUPC_CRITICAL_SECTION_ENTER(); |
| 570 | tmp = ((Supc *)hw)->BOD33.reg; |
| 571 | tmp &= ~SUPC_BOD33_RUNBKUP; |
| 572 | tmp |= value << SUPC_BOD33_RUNBKUP_Pos; |
| 573 | ((Supc *)hw)->BOD33.reg = tmp; |
| 574 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 575 | } |
| 576 | |
| 577 | static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) |
| 578 | { |
| 579 | SUPC_CRITICAL_SECTION_ENTER(); |
| 580 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; |
| 581 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 582 | } |
| 583 | |
| 584 | static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) |
| 585 | { |
| 586 | SUPC_CRITICAL_SECTION_ENTER(); |
| 587 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; |
| 588 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 589 | } |
| 590 | |
| 591 | static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 592 | { |
| 593 | SUPC_CRITICAL_SECTION_ENTER(); |
| 594 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); |
| 595 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 596 | } |
| 597 | |
| 598 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 599 | { |
| 600 | uint32_t tmp; |
| 601 | tmp = ((Supc *)hw)->BOD33.reg; |
| 602 | tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; |
| 603 | return tmp; |
| 604 | } |
| 605 | |
| 606 | static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 607 | { |
| 608 | uint32_t tmp; |
| 609 | SUPC_CRITICAL_SECTION_ENTER(); |
| 610 | tmp = ((Supc *)hw)->BOD33.reg; |
| 611 | tmp &= ~SUPC_BOD33_ACTION_Msk; |
| 612 | tmp |= SUPC_BOD33_ACTION(data); |
| 613 | ((Supc *)hw)->BOD33.reg = tmp; |
| 614 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 615 | } |
| 616 | |
| 617 | static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 618 | { |
| 619 | SUPC_CRITICAL_SECTION_ENTER(); |
| 620 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); |
| 621 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 622 | } |
| 623 | |
| 624 | static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 625 | { |
| 626 | SUPC_CRITICAL_SECTION_ENTER(); |
| 627 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); |
| 628 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 629 | } |
| 630 | |
| 631 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) |
| 632 | { |
| 633 | uint32_t tmp; |
| 634 | tmp = ((Supc *)hw)->BOD33.reg; |
| 635 | tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; |
| 636 | return tmp; |
| 637 | } |
| 638 | |
| 639 | static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 640 | { |
| 641 | SUPC_CRITICAL_SECTION_ENTER(); |
| 642 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); |
| 643 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 644 | } |
| 645 | |
| 646 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 647 | { |
| 648 | uint32_t tmp; |
| 649 | tmp = ((Supc *)hw)->BOD33.reg; |
| 650 | tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; |
| 651 | return tmp; |
| 652 | } |
| 653 | |
| 654 | static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 655 | { |
| 656 | uint32_t tmp; |
| 657 | SUPC_CRITICAL_SECTION_ENTER(); |
| 658 | tmp = ((Supc *)hw)->BOD33.reg; |
| 659 | tmp &= ~SUPC_BOD33_HYST_Msk; |
| 660 | tmp |= SUPC_BOD33_HYST(data); |
| 661 | ((Supc *)hw)->BOD33.reg = tmp; |
| 662 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 663 | } |
| 664 | |
| 665 | static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 666 | { |
| 667 | SUPC_CRITICAL_SECTION_ENTER(); |
| 668 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); |
| 669 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 670 | } |
| 671 | |
| 672 | static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 673 | { |
| 674 | SUPC_CRITICAL_SECTION_ENTER(); |
| 675 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); |
| 676 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 677 | } |
| 678 | |
| 679 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) |
| 680 | { |
| 681 | uint32_t tmp; |
| 682 | tmp = ((Supc *)hw)->BOD33.reg; |
| 683 | tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; |
| 684 | return tmp; |
| 685 | } |
| 686 | |
| 687 | static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 688 | { |
| 689 | SUPC_CRITICAL_SECTION_ENTER(); |
| 690 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); |
| 691 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 692 | } |
| 693 | |
| 694 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 695 | { |
| 696 | uint32_t tmp; |
| 697 | tmp = ((Supc *)hw)->BOD33.reg; |
| 698 | tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; |
| 699 | return tmp; |
| 700 | } |
| 701 | |
| 702 | static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 703 | { |
| 704 | uint32_t tmp; |
| 705 | SUPC_CRITICAL_SECTION_ENTER(); |
| 706 | tmp = ((Supc *)hw)->BOD33.reg; |
| 707 | tmp &= ~SUPC_BOD33_PSEL_Msk; |
| 708 | tmp |= SUPC_BOD33_PSEL(data); |
| 709 | ((Supc *)hw)->BOD33.reg = tmp; |
| 710 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 711 | } |
| 712 | |
| 713 | static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 714 | { |
| 715 | SUPC_CRITICAL_SECTION_ENTER(); |
| 716 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); |
| 717 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 718 | } |
| 719 | |
| 720 | static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 721 | { |
| 722 | SUPC_CRITICAL_SECTION_ENTER(); |
| 723 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); |
| 724 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 725 | } |
| 726 | |
| 727 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) |
| 728 | { |
| 729 | uint32_t tmp; |
| 730 | tmp = ((Supc *)hw)->BOD33.reg; |
| 731 | tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; |
| 732 | return tmp; |
| 733 | } |
| 734 | |
| 735 | static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 736 | { |
| 737 | SUPC_CRITICAL_SECTION_ENTER(); |
| 738 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); |
| 739 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 740 | } |
| 741 | |
| 742 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 743 | { |
| 744 | uint32_t tmp; |
| 745 | tmp = ((Supc *)hw)->BOD33.reg; |
| 746 | tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; |
| 747 | return tmp; |
| 748 | } |
| 749 | |
| 750 | static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 751 | { |
| 752 | uint32_t tmp; |
| 753 | SUPC_CRITICAL_SECTION_ENTER(); |
| 754 | tmp = ((Supc *)hw)->BOD33.reg; |
| 755 | tmp &= ~SUPC_BOD33_LEVEL_Msk; |
| 756 | tmp |= SUPC_BOD33_LEVEL(data); |
| 757 | ((Supc *)hw)->BOD33.reg = tmp; |
| 758 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 759 | } |
| 760 | |
| 761 | static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 762 | { |
| 763 | SUPC_CRITICAL_SECTION_ENTER(); |
| 764 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); |
| 765 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 766 | } |
| 767 | |
| 768 | static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 769 | { |
| 770 | SUPC_CRITICAL_SECTION_ENTER(); |
| 771 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); |
| 772 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 773 | } |
| 774 | |
| 775 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) |
| 776 | { |
| 777 | uint32_t tmp; |
| 778 | tmp = ((Supc *)hw)->BOD33.reg; |
| 779 | tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; |
| 780 | return tmp; |
| 781 | } |
| 782 | |
| 783 | static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 784 | { |
| 785 | SUPC_CRITICAL_SECTION_ENTER(); |
| 786 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); |
| 787 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 788 | } |
| 789 | |
| 790 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 791 | { |
| 792 | uint32_t tmp; |
| 793 | tmp = ((Supc *)hw)->BOD33.reg; |
| 794 | tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; |
| 795 | return tmp; |
| 796 | } |
| 797 | |
| 798 | static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 799 | { |
| 800 | uint32_t tmp; |
| 801 | SUPC_CRITICAL_SECTION_ENTER(); |
| 802 | tmp = ((Supc *)hw)->BOD33.reg; |
| 803 | tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; |
| 804 | tmp |= SUPC_BOD33_VBATLEVEL(data); |
| 805 | ((Supc *)hw)->BOD33.reg = tmp; |
| 806 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 807 | } |
| 808 | |
| 809 | static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 810 | { |
| 811 | SUPC_CRITICAL_SECTION_ENTER(); |
| 812 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); |
| 813 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 814 | } |
| 815 | |
| 816 | static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 817 | { |
| 818 | SUPC_CRITICAL_SECTION_ENTER(); |
| 819 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); |
| 820 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 821 | } |
| 822 | |
| 823 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) |
| 824 | { |
| 825 | uint32_t tmp; |
| 826 | tmp = ((Supc *)hw)->BOD33.reg; |
| 827 | tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; |
| 828 | return tmp; |
| 829 | } |
| 830 | |
| 831 | static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 832 | { |
| 833 | SUPC_CRITICAL_SECTION_ENTER(); |
| 834 | ((Supc *)hw)->BOD33.reg |= mask; |
| 835 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 836 | } |
| 837 | |
| 838 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 839 | { |
| 840 | uint32_t tmp; |
| 841 | tmp = ((Supc *)hw)->BOD33.reg; |
| 842 | tmp &= mask; |
| 843 | return tmp; |
| 844 | } |
| 845 | |
| 846 | static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) |
| 847 | { |
| 848 | SUPC_CRITICAL_SECTION_ENTER(); |
| 849 | ((Supc *)hw)->BOD33.reg = data; |
| 850 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 851 | } |
| 852 | |
| 853 | static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 854 | { |
| 855 | SUPC_CRITICAL_SECTION_ENTER(); |
| 856 | ((Supc *)hw)->BOD33.reg &= ~mask; |
| 857 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 858 | } |
| 859 | |
| 860 | static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 861 | { |
| 862 | SUPC_CRITICAL_SECTION_ENTER(); |
| 863 | ((Supc *)hw)->BOD33.reg ^= mask; |
| 864 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 865 | } |
| 866 | |
| 867 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) |
| 868 | { |
| 869 | return ((Supc *)hw)->BOD33.reg; |
| 870 | } |
| 871 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 872 | static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) |
| 873 | { |
| 874 | SUPC_CRITICAL_SECTION_ENTER(); |
| 875 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; |
| 876 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 877 | } |
| 878 | |
| 879 | static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) |
| 880 | { |
| 881 | uint32_t tmp; |
| 882 | tmp = ((Supc *)hw)->VREG.reg; |
| 883 | tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; |
| 884 | return (bool)tmp; |
| 885 | } |
| 886 | |
| 887 | static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) |
| 888 | { |
| 889 | uint32_t tmp; |
| 890 | SUPC_CRITICAL_SECTION_ENTER(); |
| 891 | tmp = ((Supc *)hw)->VREG.reg; |
| 892 | tmp &= ~SUPC_VREG_ENABLE; |
| 893 | tmp |= value << SUPC_VREG_ENABLE_Pos; |
| 894 | ((Supc *)hw)->VREG.reg = tmp; |
| 895 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 896 | } |
| 897 | |
| 898 | static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) |
| 899 | { |
| 900 | SUPC_CRITICAL_SECTION_ENTER(); |
| 901 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; |
| 902 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 903 | } |
| 904 | |
| 905 | static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) |
| 906 | { |
| 907 | SUPC_CRITICAL_SECTION_ENTER(); |
| 908 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; |
| 909 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 910 | } |
| 911 | |
| 912 | static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) |
| 913 | { |
| 914 | SUPC_CRITICAL_SECTION_ENTER(); |
| 915 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; |
| 916 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 917 | } |
| 918 | |
| 919 | static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) |
| 920 | { |
| 921 | uint32_t tmp; |
| 922 | tmp = ((Supc *)hw)->VREG.reg; |
| 923 | tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; |
| 924 | return (bool)tmp; |
| 925 | } |
| 926 | |
| 927 | static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) |
| 928 | { |
| 929 | uint32_t tmp; |
| 930 | SUPC_CRITICAL_SECTION_ENTER(); |
| 931 | tmp = ((Supc *)hw)->VREG.reg; |
| 932 | tmp &= ~SUPC_VREG_SEL; |
| 933 | tmp |= value << SUPC_VREG_SEL_Pos; |
| 934 | ((Supc *)hw)->VREG.reg = tmp; |
| 935 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 936 | } |
| 937 | |
| 938 | static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) |
| 939 | { |
| 940 | SUPC_CRITICAL_SECTION_ENTER(); |
| 941 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; |
| 942 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 943 | } |
| 944 | |
| 945 | static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) |
| 946 | { |
| 947 | SUPC_CRITICAL_SECTION_ENTER(); |
| 948 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; |
| 949 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 950 | } |
| 951 | |
| 952 | static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) |
| 953 | { |
| 954 | SUPC_CRITICAL_SECTION_ENTER(); |
| 955 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; |
| 956 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 957 | } |
| 958 | |
| 959 | static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) |
| 960 | { |
| 961 | uint32_t tmp; |
| 962 | tmp = ((Supc *)hw)->VREG.reg; |
| 963 | tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; |
| 964 | return (bool)tmp; |
| 965 | } |
| 966 | |
| 967 | static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) |
| 968 | { |
| 969 | uint32_t tmp; |
| 970 | SUPC_CRITICAL_SECTION_ENTER(); |
| 971 | tmp = ((Supc *)hw)->VREG.reg; |
| 972 | tmp &= ~SUPC_VREG_RUNBKUP; |
| 973 | tmp |= value << SUPC_VREG_RUNBKUP_Pos; |
| 974 | ((Supc *)hw)->VREG.reg = tmp; |
| 975 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 976 | } |
| 977 | |
| 978 | static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) |
| 979 | { |
| 980 | SUPC_CRITICAL_SECTION_ENTER(); |
| 981 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; |
| 982 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 983 | } |
| 984 | |
| 985 | static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) |
| 986 | { |
| 987 | SUPC_CRITICAL_SECTION_ENTER(); |
| 988 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; |
| 989 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 990 | } |
| 991 | |
| 992 | static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) |
| 993 | { |
| 994 | SUPC_CRITICAL_SECTION_ENTER(); |
| 995 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; |
| 996 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 997 | } |
| 998 | |
| 999 | static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) |
| 1000 | { |
| 1001 | uint32_t tmp; |
| 1002 | tmp = ((Supc *)hw)->VREG.reg; |
| 1003 | tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; |
| 1004 | return (bool)tmp; |
| 1005 | } |
| 1006 | |
| 1007 | static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) |
| 1008 | { |
| 1009 | uint32_t tmp; |
| 1010 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1011 | tmp = ((Supc *)hw)->VREG.reg; |
| 1012 | tmp &= ~SUPC_VREG_VSEN; |
| 1013 | tmp |= value << SUPC_VREG_VSEN_Pos; |
| 1014 | ((Supc *)hw)->VREG.reg = tmp; |
| 1015 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1016 | } |
| 1017 | |
| 1018 | static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) |
| 1019 | { |
| 1020 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1021 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; |
| 1022 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1023 | } |
| 1024 | |
| 1025 | static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) |
| 1026 | { |
| 1027 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1028 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; |
| 1029 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1030 | } |
| 1031 | |
| 1032 | static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1033 | { |
| 1034 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1035 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); |
| 1036 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1037 | } |
| 1038 | |
| 1039 | static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1040 | { |
| 1041 | uint32_t tmp; |
| 1042 | tmp = ((Supc *)hw)->VREG.reg; |
| 1043 | tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; |
| 1044 | return tmp; |
| 1045 | } |
| 1046 | |
| 1047 | static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) |
| 1048 | { |
| 1049 | uint32_t tmp; |
| 1050 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1051 | tmp = ((Supc *)hw)->VREG.reg; |
| 1052 | tmp &= ~SUPC_VREG_VSPER_Msk; |
| 1053 | tmp |= SUPC_VREG_VSPER(data); |
| 1054 | ((Supc *)hw)->VREG.reg = tmp; |
| 1055 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1056 | } |
| 1057 | |
| 1058 | static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1059 | { |
| 1060 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1061 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); |
| 1062 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1063 | } |
| 1064 | |
| 1065 | static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1066 | { |
| 1067 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1068 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); |
| 1069 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1070 | } |
| 1071 | |
| 1072 | static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) |
| 1073 | { |
| 1074 | uint32_t tmp; |
| 1075 | tmp = ((Supc *)hw)->VREG.reg; |
| 1076 | tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; |
| 1077 | return tmp; |
| 1078 | } |
| 1079 | |
| 1080 | static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1081 | { |
| 1082 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1083 | ((Supc *)hw)->VREG.reg |= mask; |
| 1084 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1085 | } |
| 1086 | |
| 1087 | static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1088 | { |
| 1089 | uint32_t tmp; |
| 1090 | tmp = ((Supc *)hw)->VREG.reg; |
| 1091 | tmp &= mask; |
| 1092 | return tmp; |
| 1093 | } |
| 1094 | |
| 1095 | static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) |
| 1096 | { |
| 1097 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1098 | ((Supc *)hw)->VREG.reg = data; |
| 1099 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1100 | } |
| 1101 | |
| 1102 | static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1103 | { |
| 1104 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1105 | ((Supc *)hw)->VREG.reg &= ~mask; |
| 1106 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1107 | } |
| 1108 | |
| 1109 | static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1110 | { |
| 1111 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1112 | ((Supc *)hw)->VREG.reg ^= mask; |
| 1113 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1114 | } |
| 1115 | |
| 1116 | static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) |
| 1117 | { |
| 1118 | return ((Supc *)hw)->VREG.reg; |
| 1119 | } |
| 1120 | |
| 1121 | static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) |
| 1122 | { |
| 1123 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1124 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; |
| 1125 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1126 | } |
| 1127 | |
| 1128 | static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) |
| 1129 | { |
| 1130 | uint32_t tmp; |
| 1131 | tmp = ((Supc *)hw)->VREF.reg; |
| 1132 | tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; |
| 1133 | return (bool)tmp; |
| 1134 | } |
| 1135 | |
| 1136 | static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) |
| 1137 | { |
| 1138 | uint32_t tmp; |
| 1139 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1140 | tmp = ((Supc *)hw)->VREF.reg; |
| 1141 | tmp &= ~SUPC_VREF_TSEN; |
| 1142 | tmp |= value << SUPC_VREF_TSEN_Pos; |
| 1143 | ((Supc *)hw)->VREF.reg = tmp; |
| 1144 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1145 | } |
| 1146 | |
| 1147 | static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) |
| 1148 | { |
| 1149 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1150 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; |
| 1151 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1152 | } |
| 1153 | |
| 1154 | static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) |
| 1155 | { |
| 1156 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1157 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; |
| 1158 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1159 | } |
| 1160 | |
| 1161 | static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) |
| 1162 | { |
| 1163 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1164 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; |
| 1165 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1166 | } |
| 1167 | |
| 1168 | static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) |
| 1169 | { |
| 1170 | uint32_t tmp; |
| 1171 | tmp = ((Supc *)hw)->VREF.reg; |
| 1172 | tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; |
| 1173 | return (bool)tmp; |
| 1174 | } |
| 1175 | |
| 1176 | static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) |
| 1177 | { |
| 1178 | uint32_t tmp; |
| 1179 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1180 | tmp = ((Supc *)hw)->VREF.reg; |
| 1181 | tmp &= ~SUPC_VREF_VREFOE; |
| 1182 | tmp |= value << SUPC_VREF_VREFOE_Pos; |
| 1183 | ((Supc *)hw)->VREF.reg = tmp; |
| 1184 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1185 | } |
| 1186 | |
| 1187 | static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) |
| 1188 | { |
| 1189 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1190 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; |
| 1191 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1192 | } |
| 1193 | |
| 1194 | static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) |
| 1195 | { |
| 1196 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1197 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; |
| 1198 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1199 | } |
| 1200 | |
| 1201 | static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) |
| 1202 | { |
| 1203 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1204 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; |
| 1205 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1206 | } |
| 1207 | |
| 1208 | static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) |
| 1209 | { |
| 1210 | uint32_t tmp; |
| 1211 | tmp = ((Supc *)hw)->VREF.reg; |
| 1212 | tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; |
| 1213 | return (bool)tmp; |
| 1214 | } |
| 1215 | |
| 1216 | static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) |
| 1217 | { |
| 1218 | uint32_t tmp; |
| 1219 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1220 | tmp = ((Supc *)hw)->VREF.reg; |
| 1221 | tmp &= ~SUPC_VREF_TSSEL; |
| 1222 | tmp |= value << SUPC_VREF_TSSEL_Pos; |
| 1223 | ((Supc *)hw)->VREF.reg = tmp; |
| 1224 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1225 | } |
| 1226 | |
| 1227 | static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) |
| 1228 | { |
| 1229 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1230 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; |
| 1231 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1232 | } |
| 1233 | |
| 1234 | static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) |
| 1235 | { |
| 1236 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1237 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; |
| 1238 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1239 | } |
| 1240 | |
| 1241 | static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) |
| 1242 | { |
| 1243 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1244 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; |
| 1245 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1246 | } |
| 1247 | |
| 1248 | static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) |
| 1249 | { |
| 1250 | uint32_t tmp; |
| 1251 | tmp = ((Supc *)hw)->VREF.reg; |
| 1252 | tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; |
| 1253 | return (bool)tmp; |
| 1254 | } |
| 1255 | |
| 1256 | static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) |
| 1257 | { |
| 1258 | uint32_t tmp; |
| 1259 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1260 | tmp = ((Supc *)hw)->VREF.reg; |
| 1261 | tmp &= ~SUPC_VREF_RUNSTDBY; |
| 1262 | tmp |= value << SUPC_VREF_RUNSTDBY_Pos; |
| 1263 | ((Supc *)hw)->VREF.reg = tmp; |
| 1264 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1265 | } |
| 1266 | |
| 1267 | static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) |
| 1268 | { |
| 1269 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1270 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; |
| 1271 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1272 | } |
| 1273 | |
| 1274 | static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) |
| 1275 | { |
| 1276 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1277 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; |
| 1278 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1279 | } |
| 1280 | |
| 1281 | static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) |
| 1282 | { |
| 1283 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1284 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; |
| 1285 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1286 | } |
| 1287 | |
| 1288 | static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) |
| 1289 | { |
| 1290 | uint32_t tmp; |
| 1291 | tmp = ((Supc *)hw)->VREF.reg; |
| 1292 | tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; |
| 1293 | return (bool)tmp; |
| 1294 | } |
| 1295 | |
| 1296 | static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) |
| 1297 | { |
| 1298 | uint32_t tmp; |
| 1299 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1300 | tmp = ((Supc *)hw)->VREF.reg; |
| 1301 | tmp &= ~SUPC_VREF_ONDEMAND; |
| 1302 | tmp |= value << SUPC_VREF_ONDEMAND_Pos; |
| 1303 | ((Supc *)hw)->VREF.reg = tmp; |
| 1304 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1305 | } |
| 1306 | |
| 1307 | static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) |
| 1308 | { |
| 1309 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1310 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; |
| 1311 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1312 | } |
| 1313 | |
| 1314 | static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) |
| 1315 | { |
| 1316 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1317 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; |
| 1318 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1319 | } |
| 1320 | |
| 1321 | static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1322 | { |
| 1323 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1324 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); |
| 1325 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1326 | } |
| 1327 | |
| 1328 | static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1329 | { |
| 1330 | uint32_t tmp; |
| 1331 | tmp = ((Supc *)hw)->VREF.reg; |
| 1332 | tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; |
| 1333 | return tmp; |
| 1334 | } |
| 1335 | |
| 1336 | static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) |
| 1337 | { |
| 1338 | uint32_t tmp; |
| 1339 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1340 | tmp = ((Supc *)hw)->VREF.reg; |
| 1341 | tmp &= ~SUPC_VREF_SEL_Msk; |
| 1342 | tmp |= SUPC_VREF_SEL(data); |
| 1343 | ((Supc *)hw)->VREF.reg = tmp; |
| 1344 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1345 | } |
| 1346 | |
| 1347 | static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1348 | { |
| 1349 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1350 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); |
| 1351 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1352 | } |
| 1353 | |
| 1354 | static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1355 | { |
| 1356 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1357 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); |
| 1358 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1359 | } |
| 1360 | |
| 1361 | static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) |
| 1362 | { |
| 1363 | uint32_t tmp; |
| 1364 | tmp = ((Supc *)hw)->VREF.reg; |
| 1365 | tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; |
| 1366 | return tmp; |
| 1367 | } |
| 1368 | |
| 1369 | static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1370 | { |
| 1371 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1372 | ((Supc *)hw)->VREF.reg |= mask; |
| 1373 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1374 | } |
| 1375 | |
| 1376 | static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1377 | { |
| 1378 | uint32_t tmp; |
| 1379 | tmp = ((Supc *)hw)->VREF.reg; |
| 1380 | tmp &= mask; |
| 1381 | return tmp; |
| 1382 | } |
| 1383 | |
| 1384 | static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) |
| 1385 | { |
| 1386 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1387 | ((Supc *)hw)->VREF.reg = data; |
| 1388 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1389 | } |
| 1390 | |
| 1391 | static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1392 | { |
| 1393 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1394 | ((Supc *)hw)->VREF.reg &= ~mask; |
| 1395 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1396 | } |
| 1397 | |
| 1398 | static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1399 | { |
| 1400 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1401 | ((Supc *)hw)->VREF.reg ^= mask; |
| 1402 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1403 | } |
| 1404 | |
| 1405 | static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) |
| 1406 | { |
| 1407 | return ((Supc *)hw)->VREF.reg; |
| 1408 | } |
| 1409 | |
| 1410 | static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) |
| 1411 | { |
| 1412 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1413 | ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; |
| 1414 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1415 | } |
| 1416 | |
| 1417 | static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) |
| 1418 | { |
| 1419 | uint32_t tmp; |
| 1420 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1421 | tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; |
| 1422 | return (bool)tmp; |
| 1423 | } |
| 1424 | |
| 1425 | static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) |
| 1426 | { |
| 1427 | uint32_t tmp; |
| 1428 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1429 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1430 | tmp &= ~SUPC_BBPS_CONF; |
| 1431 | tmp |= value << SUPC_BBPS_CONF_Pos; |
| 1432 | ((Supc *)hw)->BBPS.reg = tmp; |
| 1433 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1434 | } |
| 1435 | |
| 1436 | static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) |
| 1437 | { |
| 1438 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1439 | ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; |
| 1440 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1441 | } |
| 1442 | |
| 1443 | static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) |
| 1444 | { |
| 1445 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1446 | ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; |
| 1447 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1448 | } |
| 1449 | |
| 1450 | static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) |
| 1451 | { |
| 1452 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1453 | ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; |
| 1454 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1455 | } |
| 1456 | |
| 1457 | static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) |
| 1458 | { |
| 1459 | uint32_t tmp; |
| 1460 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1461 | tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; |
| 1462 | return (bool)tmp; |
| 1463 | } |
| 1464 | |
| 1465 | static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) |
| 1466 | { |
| 1467 | uint32_t tmp; |
| 1468 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1469 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1470 | tmp &= ~SUPC_BBPS_WAKEEN; |
| 1471 | tmp |= value << SUPC_BBPS_WAKEEN_Pos; |
| 1472 | ((Supc *)hw)->BBPS.reg = tmp; |
| 1473 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1474 | } |
| 1475 | |
| 1476 | static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) |
| 1477 | { |
| 1478 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1479 | ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; |
| 1480 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1481 | } |
| 1482 | |
| 1483 | static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) |
| 1484 | { |
| 1485 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1486 | ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; |
| 1487 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1488 | } |
| 1489 | |
| 1490 | static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 1491 | { |
| 1492 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1493 | ((Supc *)hw)->BBPS.reg |= mask; |
| 1494 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1495 | } |
| 1496 | |
| 1497 | static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 1498 | { |
| 1499 | uint32_t tmp; |
| 1500 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1501 | tmp &= mask; |
| 1502 | return tmp; |
| 1503 | } |
| 1504 | |
| 1505 | static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) |
| 1506 | { |
| 1507 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1508 | ((Supc *)hw)->BBPS.reg = data; |
| 1509 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1510 | } |
| 1511 | |
| 1512 | static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 1513 | { |
| 1514 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1515 | ((Supc *)hw)->BBPS.reg &= ~mask; |
| 1516 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1517 | } |
| 1518 | |
| 1519 | static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 1520 | { |
| 1521 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1522 | ((Supc *)hw)->BBPS.reg ^= mask; |
| 1523 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1524 | } |
| 1525 | |
| 1526 | static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) |
| 1527 | { |
| 1528 | return ((Supc *)hw)->BBPS.reg; |
| 1529 | } |
| 1530 | |
| 1531 | static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1532 | { |
| 1533 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1534 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); |
| 1535 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1536 | } |
| 1537 | |
| 1538 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1539 | { |
| 1540 | uint32_t tmp; |
| 1541 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1542 | tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; |
| 1543 | return tmp; |
| 1544 | } |
| 1545 | |
| 1546 | static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 1547 | { |
| 1548 | uint32_t tmp; |
| 1549 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1550 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1551 | tmp &= ~SUPC_BKOUT_EN_Msk; |
| 1552 | tmp |= SUPC_BKOUT_EN(data); |
| 1553 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 1554 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1555 | } |
| 1556 | |
| 1557 | static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1558 | { |
| 1559 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1560 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); |
| 1561 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1562 | } |
| 1563 | |
| 1564 | static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1565 | { |
| 1566 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1567 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); |
| 1568 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1569 | } |
| 1570 | |
| 1571 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) |
| 1572 | { |
| 1573 | uint32_t tmp; |
| 1574 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1575 | tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; |
| 1576 | return tmp; |
| 1577 | } |
| 1578 | |
| 1579 | static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1580 | { |
| 1581 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1582 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); |
| 1583 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1584 | } |
| 1585 | |
| 1586 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1587 | { |
| 1588 | uint32_t tmp; |
| 1589 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1590 | tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; |
| 1591 | return tmp; |
| 1592 | } |
| 1593 | |
| 1594 | static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 1595 | { |
| 1596 | uint32_t tmp; |
| 1597 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1598 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1599 | tmp &= ~SUPC_BKOUT_CLR_Msk; |
| 1600 | tmp |= SUPC_BKOUT_CLR(data); |
| 1601 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 1602 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1603 | } |
| 1604 | |
| 1605 | static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1606 | { |
| 1607 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1608 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); |
| 1609 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1610 | } |
| 1611 | |
| 1612 | static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1613 | { |
| 1614 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1615 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); |
| 1616 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1617 | } |
| 1618 | |
| 1619 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) |
| 1620 | { |
| 1621 | uint32_t tmp; |
| 1622 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1623 | tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; |
| 1624 | return tmp; |
| 1625 | } |
| 1626 | |
| 1627 | static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1628 | { |
| 1629 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1630 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); |
| 1631 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1632 | } |
| 1633 | |
| 1634 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1635 | { |
| 1636 | uint32_t tmp; |
| 1637 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1638 | tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; |
| 1639 | return tmp; |
| 1640 | } |
| 1641 | |
| 1642 | static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 1643 | { |
| 1644 | uint32_t tmp; |
| 1645 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1646 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1647 | tmp &= ~SUPC_BKOUT_SET_Msk; |
| 1648 | tmp |= SUPC_BKOUT_SET(data); |
| 1649 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 1650 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1651 | } |
| 1652 | |
| 1653 | static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1654 | { |
| 1655 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1656 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); |
| 1657 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1658 | } |
| 1659 | |
| 1660 | static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1661 | { |
| 1662 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1663 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); |
| 1664 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1665 | } |
| 1666 | |
| 1667 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) |
| 1668 | { |
| 1669 | uint32_t tmp; |
| 1670 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1671 | tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; |
| 1672 | return tmp; |
| 1673 | } |
| 1674 | |
| 1675 | static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1676 | { |
| 1677 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1678 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); |
| 1679 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1680 | } |
| 1681 | |
| 1682 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1683 | { |
| 1684 | uint32_t tmp; |
| 1685 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1686 | tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; |
| 1687 | return tmp; |
| 1688 | } |
| 1689 | |
| 1690 | static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 1691 | { |
| 1692 | uint32_t tmp; |
| 1693 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1694 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1695 | tmp &= ~SUPC_BKOUT_RTCTGL_Msk; |
| 1696 | tmp |= SUPC_BKOUT_RTCTGL(data); |
| 1697 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 1698 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1699 | } |
| 1700 | |
| 1701 | static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1702 | { |
| 1703 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1704 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); |
| 1705 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1706 | } |
| 1707 | |
| 1708 | static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1709 | { |
| 1710 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1711 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); |
| 1712 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1713 | } |
| 1714 | |
| 1715 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) |
| 1716 | { |
| 1717 | uint32_t tmp; |
| 1718 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1719 | tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; |
| 1720 | return tmp; |
| 1721 | } |
| 1722 | |
| 1723 | static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1724 | { |
| 1725 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1726 | ((Supc *)hw)->BKOUT.reg |= mask; |
| 1727 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1728 | } |
| 1729 | |
| 1730 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1731 | { |
| 1732 | uint32_t tmp; |
| 1733 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 1734 | tmp &= mask; |
| 1735 | return tmp; |
| 1736 | } |
| 1737 | |
| 1738 | static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) |
| 1739 | { |
| 1740 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1741 | ((Supc *)hw)->BKOUT.reg = data; |
| 1742 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1743 | } |
| 1744 | |
| 1745 | static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1746 | { |
| 1747 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1748 | ((Supc *)hw)->BKOUT.reg &= ~mask; |
| 1749 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1750 | } |
| 1751 | |
| 1752 | static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 1753 | { |
| 1754 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1755 | ((Supc *)hw)->BKOUT.reg ^= mask; |
| 1756 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1757 | } |
| 1758 | |
| 1759 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) |
| 1760 | { |
| 1761 | return ((Supc *)hw)->BKOUT.reg; |
| 1762 | } |
| 1763 | |
| 1764 | #ifdef __cplusplus |
| 1765 | } |
| 1766 | #endif |
| 1767 | |
| 1768 | #endif /* _HRI_SUPC_E54_H_INCLUDED */ |
| 1769 | #endif /* _SAME54_SUPC_COMPONENT_ */ |