Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM RTC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_RTC_COMPONENT_ |
| 35 | #ifndef _HRI_RTC_E54_H_INCLUDED_ |
| 36 | #define _HRI_RTC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_RTC_CRITICAL_SECTIONS) |
| 46 | #define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define RTC_CRITICAL_SECTION_ENTER() |
| 50 | #define RTC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_rtcmode0_ctrla_reg_t; |
| 54 | typedef uint16_t hri_rtcmode0_ctrlb_reg_t; |
| 55 | typedef uint16_t hri_rtcmode0_intenset_reg_t; |
| 56 | typedef uint16_t hri_rtcmode0_intflag_reg_t; |
| 57 | typedef uint16_t hri_rtcmode1_comp_reg_t; |
| 58 | typedef uint16_t hri_rtcmode1_count_reg_t; |
| 59 | typedef uint16_t hri_rtcmode1_ctrla_reg_t; |
| 60 | typedef uint16_t hri_rtcmode1_ctrlb_reg_t; |
| 61 | typedef uint16_t hri_rtcmode1_intenset_reg_t; |
| 62 | typedef uint16_t hri_rtcmode1_intflag_reg_t; |
| 63 | typedef uint16_t hri_rtcmode1_per_reg_t; |
| 64 | typedef uint16_t hri_rtcmode2_ctrla_reg_t; |
| 65 | typedef uint16_t hri_rtcmode2_ctrlb_reg_t; |
| 66 | typedef uint16_t hri_rtcmode2_intenset_reg_t; |
| 67 | typedef uint16_t hri_rtcmode2_intflag_reg_t; |
| 68 | typedef uint32_t hri_rtc_bkup_reg_t; |
| 69 | typedef uint32_t hri_rtc_gp_reg_t; |
| 70 | typedef uint32_t hri_rtc_tampctrl_reg_t; |
| 71 | typedef uint32_t hri_rtc_tampid_reg_t; |
| 72 | typedef uint32_t hri_rtcalarm_alarm_reg_t; |
| 73 | typedef uint32_t hri_rtcmode0_comp_reg_t; |
| 74 | typedef uint32_t hri_rtcmode0_count_reg_t; |
| 75 | typedef uint32_t hri_rtcmode0_evctrl_reg_t; |
| 76 | typedef uint32_t hri_rtcmode0_syncbusy_reg_t; |
| 77 | typedef uint32_t hri_rtcmode0_timestamp_reg_t; |
| 78 | typedef uint32_t hri_rtcmode1_evctrl_reg_t; |
| 79 | typedef uint32_t hri_rtcmode1_syncbusy_reg_t; |
| 80 | typedef uint32_t hri_rtcmode1_timestamp_reg_t; |
| 81 | typedef uint32_t hri_rtcmode2_alarm_reg_t; |
| 82 | typedef uint32_t hri_rtcmode2_clock_reg_t; |
| 83 | typedef uint32_t hri_rtcmode2_evctrl_reg_t; |
| 84 | typedef uint32_t hri_rtcmode2_syncbusy_reg_t; |
| 85 | typedef uint32_t hri_rtcmode2_timestamp_reg_t; |
| 86 | typedef uint8_t hri_rtc_dbgctrl_reg_t; |
| 87 | typedef uint8_t hri_rtc_freqcorr_reg_t; |
| 88 | typedef uint8_t hri_rtcalarm_mask_reg_t; |
| 89 | typedef uint8_t hri_rtcmode2_mask_reg_t; |
| 90 | |
| 91 | static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) |
| 92 | { |
| 93 | while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { |
| 94 | }; |
| 95 | } |
| 96 | |
| 97 | static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) |
| 98 | { |
| 99 | return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; |
| 100 | } |
| 101 | |
| 102 | static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) |
| 103 | { |
| 104 | while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { |
| 105 | }; |
| 106 | } |
| 107 | |
| 108 | static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) |
| 109 | { |
| 110 | return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; |
| 111 | } |
| 112 | |
| 113 | static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) |
| 114 | { |
| 115 | while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { |
| 116 | }; |
| 117 | } |
| 118 | |
| 119 | static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) |
| 120 | { |
| 121 | return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; |
| 122 | } |
| 123 | |
| 124 | static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 125 | hri_rtcmode2_alarm_reg_t mask) |
| 126 | { |
| 127 | RTC_CRITICAL_SECTION_ENTER(); |
| 128 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); |
| 129 | RTC_CRITICAL_SECTION_LEAVE(); |
| 130 | } |
| 131 | |
| 132 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 133 | hri_rtcmode2_alarm_reg_t mask) |
| 134 | { |
| 135 | uint32_t tmp; |
| 136 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 137 | tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; |
| 138 | return tmp; |
| 139 | } |
| 140 | |
| 141 | static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 142 | hri_rtcmode2_alarm_reg_t data) |
| 143 | { |
| 144 | uint32_t tmp; |
| 145 | RTC_CRITICAL_SECTION_ENTER(); |
| 146 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 147 | tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; |
| 148 | tmp |= RTC_MODE2_ALARM_SECOND(data); |
| 149 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 150 | RTC_CRITICAL_SECTION_LEAVE(); |
| 151 | } |
| 152 | |
| 153 | static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 154 | hri_rtcmode2_alarm_reg_t mask) |
| 155 | { |
| 156 | RTC_CRITICAL_SECTION_ENTER(); |
| 157 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); |
| 158 | RTC_CRITICAL_SECTION_LEAVE(); |
| 159 | } |
| 160 | |
| 161 | static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 162 | hri_rtcmode2_alarm_reg_t mask) |
| 163 | { |
| 164 | RTC_CRITICAL_SECTION_ENTER(); |
| 165 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); |
| 166 | RTC_CRITICAL_SECTION_LEAVE(); |
| 167 | } |
| 168 | |
| 169 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) |
| 170 | { |
| 171 | uint32_t tmp; |
| 172 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 173 | tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; |
| 174 | return tmp; |
| 175 | } |
| 176 | |
| 177 | static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 178 | hri_rtcmode2_alarm_reg_t mask) |
| 179 | { |
| 180 | RTC_CRITICAL_SECTION_ENTER(); |
| 181 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); |
| 182 | RTC_CRITICAL_SECTION_LEAVE(); |
| 183 | } |
| 184 | |
| 185 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 186 | hri_rtcmode2_alarm_reg_t mask) |
| 187 | { |
| 188 | uint32_t tmp; |
| 189 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 190 | tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; |
| 191 | return tmp; |
| 192 | } |
| 193 | |
| 194 | static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 195 | hri_rtcmode2_alarm_reg_t data) |
| 196 | { |
| 197 | uint32_t tmp; |
| 198 | RTC_CRITICAL_SECTION_ENTER(); |
| 199 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 200 | tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; |
| 201 | tmp |= RTC_MODE2_ALARM_MINUTE(data); |
| 202 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 203 | RTC_CRITICAL_SECTION_LEAVE(); |
| 204 | } |
| 205 | |
| 206 | static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 207 | hri_rtcmode2_alarm_reg_t mask) |
| 208 | { |
| 209 | RTC_CRITICAL_SECTION_ENTER(); |
| 210 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); |
| 211 | RTC_CRITICAL_SECTION_LEAVE(); |
| 212 | } |
| 213 | |
| 214 | static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 215 | hri_rtcmode2_alarm_reg_t mask) |
| 216 | { |
| 217 | RTC_CRITICAL_SECTION_ENTER(); |
| 218 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); |
| 219 | RTC_CRITICAL_SECTION_LEAVE(); |
| 220 | } |
| 221 | |
| 222 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) |
| 223 | { |
| 224 | uint32_t tmp; |
| 225 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 226 | tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; |
| 227 | return tmp; |
| 228 | } |
| 229 | |
| 230 | static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 231 | hri_rtcmode2_alarm_reg_t mask) |
| 232 | { |
| 233 | RTC_CRITICAL_SECTION_ENTER(); |
| 234 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); |
| 235 | RTC_CRITICAL_SECTION_LEAVE(); |
| 236 | } |
| 237 | |
| 238 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 239 | hri_rtcmode2_alarm_reg_t mask) |
| 240 | { |
| 241 | uint32_t tmp; |
| 242 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 243 | tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; |
| 244 | return tmp; |
| 245 | } |
| 246 | |
| 247 | static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 248 | hri_rtcmode2_alarm_reg_t data) |
| 249 | { |
| 250 | uint32_t tmp; |
| 251 | RTC_CRITICAL_SECTION_ENTER(); |
| 252 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 253 | tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; |
| 254 | tmp |= RTC_MODE2_ALARM_HOUR(data); |
| 255 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 256 | RTC_CRITICAL_SECTION_LEAVE(); |
| 257 | } |
| 258 | |
| 259 | static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 260 | hri_rtcmode2_alarm_reg_t mask) |
| 261 | { |
| 262 | RTC_CRITICAL_SECTION_ENTER(); |
| 263 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); |
| 264 | RTC_CRITICAL_SECTION_LEAVE(); |
| 265 | } |
| 266 | |
| 267 | static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 268 | hri_rtcmode2_alarm_reg_t mask) |
| 269 | { |
| 270 | RTC_CRITICAL_SECTION_ENTER(); |
| 271 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); |
| 272 | RTC_CRITICAL_SECTION_LEAVE(); |
| 273 | } |
| 274 | |
| 275 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) |
| 276 | { |
| 277 | uint32_t tmp; |
| 278 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 279 | tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; |
| 280 | return tmp; |
| 281 | } |
| 282 | |
| 283 | static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 284 | hri_rtcmode2_alarm_reg_t mask) |
| 285 | { |
| 286 | RTC_CRITICAL_SECTION_ENTER(); |
| 287 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); |
| 288 | RTC_CRITICAL_SECTION_LEAVE(); |
| 289 | } |
| 290 | |
| 291 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 292 | hri_rtcmode2_alarm_reg_t mask) |
| 293 | { |
| 294 | uint32_t tmp; |
| 295 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 296 | tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; |
| 297 | return tmp; |
| 298 | } |
| 299 | |
| 300 | static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 301 | hri_rtcmode2_alarm_reg_t data) |
| 302 | { |
| 303 | uint32_t tmp; |
| 304 | RTC_CRITICAL_SECTION_ENTER(); |
| 305 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 306 | tmp &= ~RTC_MODE2_ALARM_DAY_Msk; |
| 307 | tmp |= RTC_MODE2_ALARM_DAY(data); |
| 308 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 309 | RTC_CRITICAL_SECTION_LEAVE(); |
| 310 | } |
| 311 | |
| 312 | static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 313 | hri_rtcmode2_alarm_reg_t mask) |
| 314 | { |
| 315 | RTC_CRITICAL_SECTION_ENTER(); |
| 316 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); |
| 317 | RTC_CRITICAL_SECTION_LEAVE(); |
| 318 | } |
| 319 | |
| 320 | static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 321 | hri_rtcmode2_alarm_reg_t mask) |
| 322 | { |
| 323 | RTC_CRITICAL_SECTION_ENTER(); |
| 324 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); |
| 325 | RTC_CRITICAL_SECTION_LEAVE(); |
| 326 | } |
| 327 | |
| 328 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) |
| 329 | { |
| 330 | uint32_t tmp; |
| 331 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 332 | tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; |
| 333 | return tmp; |
| 334 | } |
| 335 | |
| 336 | static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 337 | hri_rtcmode2_alarm_reg_t mask) |
| 338 | { |
| 339 | RTC_CRITICAL_SECTION_ENTER(); |
| 340 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); |
| 341 | RTC_CRITICAL_SECTION_LEAVE(); |
| 342 | } |
| 343 | |
| 344 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 345 | hri_rtcmode2_alarm_reg_t mask) |
| 346 | { |
| 347 | uint32_t tmp; |
| 348 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 349 | tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; |
| 350 | return tmp; |
| 351 | } |
| 352 | |
| 353 | static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 354 | hri_rtcmode2_alarm_reg_t data) |
| 355 | { |
| 356 | uint32_t tmp; |
| 357 | RTC_CRITICAL_SECTION_ENTER(); |
| 358 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 359 | tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; |
| 360 | tmp |= RTC_MODE2_ALARM_MONTH(data); |
| 361 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 362 | RTC_CRITICAL_SECTION_LEAVE(); |
| 363 | } |
| 364 | |
| 365 | static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 366 | hri_rtcmode2_alarm_reg_t mask) |
| 367 | { |
| 368 | RTC_CRITICAL_SECTION_ENTER(); |
| 369 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); |
| 370 | RTC_CRITICAL_SECTION_LEAVE(); |
| 371 | } |
| 372 | |
| 373 | static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 374 | hri_rtcmode2_alarm_reg_t mask) |
| 375 | { |
| 376 | RTC_CRITICAL_SECTION_ENTER(); |
| 377 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); |
| 378 | RTC_CRITICAL_SECTION_LEAVE(); |
| 379 | } |
| 380 | |
| 381 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) |
| 382 | { |
| 383 | uint32_t tmp; |
| 384 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 385 | tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; |
| 386 | return tmp; |
| 387 | } |
| 388 | |
| 389 | static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 390 | hri_rtcmode2_alarm_reg_t mask) |
| 391 | { |
| 392 | RTC_CRITICAL_SECTION_ENTER(); |
| 393 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); |
| 394 | RTC_CRITICAL_SECTION_LEAVE(); |
| 395 | } |
| 396 | |
| 397 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 398 | hri_rtcmode2_alarm_reg_t mask) |
| 399 | { |
| 400 | uint32_t tmp; |
| 401 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 402 | tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; |
| 403 | return tmp; |
| 404 | } |
| 405 | |
| 406 | static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 407 | hri_rtcmode2_alarm_reg_t data) |
| 408 | { |
| 409 | uint32_t tmp; |
| 410 | RTC_CRITICAL_SECTION_ENTER(); |
| 411 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 412 | tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; |
| 413 | tmp |= RTC_MODE2_ALARM_YEAR(data); |
| 414 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 415 | RTC_CRITICAL_SECTION_LEAVE(); |
| 416 | } |
| 417 | |
| 418 | static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 419 | hri_rtcmode2_alarm_reg_t mask) |
| 420 | { |
| 421 | RTC_CRITICAL_SECTION_ENTER(); |
| 422 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); |
| 423 | RTC_CRITICAL_SECTION_LEAVE(); |
| 424 | } |
| 425 | |
| 426 | static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 427 | hri_rtcmode2_alarm_reg_t mask) |
| 428 | { |
| 429 | RTC_CRITICAL_SECTION_ENTER(); |
| 430 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); |
| 431 | RTC_CRITICAL_SECTION_LEAVE(); |
| 432 | } |
| 433 | |
| 434 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) |
| 435 | { |
| 436 | uint32_t tmp; |
| 437 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 438 | tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; |
| 439 | return tmp; |
| 440 | } |
| 441 | |
| 442 | static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 443 | hri_rtcmode2_alarm_reg_t mask) |
| 444 | { |
| 445 | RTC_CRITICAL_SECTION_ENTER(); |
| 446 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; |
| 447 | RTC_CRITICAL_SECTION_LEAVE(); |
| 448 | } |
| 449 | |
| 450 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 451 | hri_rtcmode2_alarm_reg_t mask) |
| 452 | { |
| 453 | uint32_t tmp; |
| 454 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 455 | tmp &= mask; |
| 456 | return tmp; |
| 457 | } |
| 458 | |
| 459 | static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 460 | hri_rtcmode2_alarm_reg_t data) |
| 461 | { |
| 462 | RTC_CRITICAL_SECTION_ENTER(); |
| 463 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; |
| 464 | RTC_CRITICAL_SECTION_LEAVE(); |
| 465 | } |
| 466 | |
| 467 | static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 468 | hri_rtcmode2_alarm_reg_t mask) |
| 469 | { |
| 470 | RTC_CRITICAL_SECTION_ENTER(); |
| 471 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; |
| 472 | RTC_CRITICAL_SECTION_LEAVE(); |
| 473 | } |
| 474 | |
| 475 | static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 476 | hri_rtcmode2_alarm_reg_t mask) |
| 477 | { |
| 478 | RTC_CRITICAL_SECTION_ENTER(); |
| 479 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; |
| 480 | RTC_CRITICAL_SECTION_LEAVE(); |
| 481 | } |
| 482 | |
| 483 | static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) |
| 484 | { |
| 485 | return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; |
| 486 | } |
| 487 | |
| 488 | static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 489 | hri_rtcmode2_mask_reg_t mask) |
| 490 | { |
| 491 | RTC_CRITICAL_SECTION_ENTER(); |
| 492 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); |
| 493 | RTC_CRITICAL_SECTION_LEAVE(); |
| 494 | } |
| 495 | |
| 496 | static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 497 | hri_rtcmode2_mask_reg_t mask) |
| 498 | { |
| 499 | uint8_t tmp; |
| 500 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; |
| 501 | tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; |
| 502 | return tmp; |
| 503 | } |
| 504 | |
| 505 | static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 506 | hri_rtcmode2_mask_reg_t data) |
| 507 | { |
| 508 | uint8_t tmp; |
| 509 | RTC_CRITICAL_SECTION_ENTER(); |
| 510 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; |
| 511 | tmp &= ~RTC_MODE2_MASK_SEL_Msk; |
| 512 | tmp |= RTC_MODE2_MASK_SEL(data); |
| 513 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; |
| 514 | RTC_CRITICAL_SECTION_LEAVE(); |
| 515 | } |
| 516 | |
| 517 | static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 518 | hri_rtcmode2_mask_reg_t mask) |
| 519 | { |
| 520 | RTC_CRITICAL_SECTION_ENTER(); |
| 521 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); |
| 522 | RTC_CRITICAL_SECTION_LEAVE(); |
| 523 | } |
| 524 | |
| 525 | static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 526 | hri_rtcmode2_mask_reg_t mask) |
| 527 | { |
| 528 | RTC_CRITICAL_SECTION_ENTER(); |
| 529 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); |
| 530 | RTC_CRITICAL_SECTION_LEAVE(); |
| 531 | } |
| 532 | |
| 533 | static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) |
| 534 | { |
| 535 | uint8_t tmp; |
| 536 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; |
| 537 | tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; |
| 538 | return tmp; |
| 539 | } |
| 540 | |
| 541 | static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 542 | hri_rtcmode2_mask_reg_t mask) |
| 543 | { |
| 544 | RTC_CRITICAL_SECTION_ENTER(); |
| 545 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; |
| 546 | RTC_CRITICAL_SECTION_LEAVE(); |
| 547 | } |
| 548 | |
| 549 | static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 550 | hri_rtcmode2_mask_reg_t mask) |
| 551 | { |
| 552 | uint8_t tmp; |
| 553 | tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; |
| 554 | tmp &= mask; |
| 555 | return tmp; |
| 556 | } |
| 557 | |
| 558 | static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 559 | hri_rtcmode2_mask_reg_t data) |
| 560 | { |
| 561 | RTC_CRITICAL_SECTION_ENTER(); |
| 562 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; |
| 563 | RTC_CRITICAL_SECTION_LEAVE(); |
| 564 | } |
| 565 | |
| 566 | static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 567 | hri_rtcmode2_mask_reg_t mask) |
| 568 | { |
| 569 | RTC_CRITICAL_SECTION_ENTER(); |
| 570 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; |
| 571 | RTC_CRITICAL_SECTION_LEAVE(); |
| 572 | } |
| 573 | |
| 574 | static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 575 | hri_rtcmode2_mask_reg_t mask) |
| 576 | { |
| 577 | RTC_CRITICAL_SECTION_ENTER(); |
| 578 | ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; |
| 579 | RTC_CRITICAL_SECTION_LEAVE(); |
| 580 | } |
| 581 | |
| 582 | static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) |
| 583 | { |
| 584 | return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; |
| 585 | } |
| 586 | |
| 587 | static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 588 | hri_rtcmode2_alarm_reg_t mask) |
| 589 | { |
| 590 | RTC_CRITICAL_SECTION_ENTER(); |
| 591 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); |
| 592 | RTC_CRITICAL_SECTION_LEAVE(); |
| 593 | } |
| 594 | |
| 595 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 596 | hri_rtcmode2_alarm_reg_t mask) |
| 597 | { |
| 598 | uint32_t tmp; |
| 599 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 600 | tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; |
| 601 | return tmp; |
| 602 | } |
| 603 | |
| 604 | static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 605 | hri_rtcmode2_alarm_reg_t data) |
| 606 | { |
| 607 | uint32_t tmp; |
| 608 | RTC_CRITICAL_SECTION_ENTER(); |
| 609 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 610 | tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; |
| 611 | tmp |= RTC_MODE2_ALARM_SECOND(data); |
| 612 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 613 | RTC_CRITICAL_SECTION_LEAVE(); |
| 614 | } |
| 615 | |
| 616 | static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 617 | hri_rtcmode2_alarm_reg_t mask) |
| 618 | { |
| 619 | RTC_CRITICAL_SECTION_ENTER(); |
| 620 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); |
| 621 | RTC_CRITICAL_SECTION_LEAVE(); |
| 622 | } |
| 623 | |
| 624 | static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, |
| 625 | hri_rtcmode2_alarm_reg_t mask) |
| 626 | { |
| 627 | RTC_CRITICAL_SECTION_ENTER(); |
| 628 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); |
| 629 | RTC_CRITICAL_SECTION_LEAVE(); |
| 630 | } |
| 631 | |
| 632 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) |
| 633 | { |
| 634 | uint32_t tmp; |
| 635 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 636 | tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; |
| 637 | return tmp; |
| 638 | } |
| 639 | |
| 640 | static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 641 | hri_rtcmode2_alarm_reg_t mask) |
| 642 | { |
| 643 | RTC_CRITICAL_SECTION_ENTER(); |
| 644 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); |
| 645 | RTC_CRITICAL_SECTION_LEAVE(); |
| 646 | } |
| 647 | |
| 648 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 649 | hri_rtcmode2_alarm_reg_t mask) |
| 650 | { |
| 651 | uint32_t tmp; |
| 652 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 653 | tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; |
| 654 | return tmp; |
| 655 | } |
| 656 | |
| 657 | static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 658 | hri_rtcmode2_alarm_reg_t data) |
| 659 | { |
| 660 | uint32_t tmp; |
| 661 | RTC_CRITICAL_SECTION_ENTER(); |
| 662 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 663 | tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; |
| 664 | tmp |= RTC_MODE2_ALARM_MINUTE(data); |
| 665 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 666 | RTC_CRITICAL_SECTION_LEAVE(); |
| 667 | } |
| 668 | |
| 669 | static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 670 | hri_rtcmode2_alarm_reg_t mask) |
| 671 | { |
| 672 | RTC_CRITICAL_SECTION_ENTER(); |
| 673 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); |
| 674 | RTC_CRITICAL_SECTION_LEAVE(); |
| 675 | } |
| 676 | |
| 677 | static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, |
| 678 | hri_rtcmode2_alarm_reg_t mask) |
| 679 | { |
| 680 | RTC_CRITICAL_SECTION_ENTER(); |
| 681 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); |
| 682 | RTC_CRITICAL_SECTION_LEAVE(); |
| 683 | } |
| 684 | |
| 685 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) |
| 686 | { |
| 687 | uint32_t tmp; |
| 688 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 689 | tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; |
| 690 | return tmp; |
| 691 | } |
| 692 | |
| 693 | static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 694 | hri_rtcmode2_alarm_reg_t mask) |
| 695 | { |
| 696 | RTC_CRITICAL_SECTION_ENTER(); |
| 697 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); |
| 698 | RTC_CRITICAL_SECTION_LEAVE(); |
| 699 | } |
| 700 | |
| 701 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 702 | hri_rtcmode2_alarm_reg_t mask) |
| 703 | { |
| 704 | uint32_t tmp; |
| 705 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 706 | tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; |
| 707 | return tmp; |
| 708 | } |
| 709 | |
| 710 | static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 711 | hri_rtcmode2_alarm_reg_t data) |
| 712 | { |
| 713 | uint32_t tmp; |
| 714 | RTC_CRITICAL_SECTION_ENTER(); |
| 715 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 716 | tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; |
| 717 | tmp |= RTC_MODE2_ALARM_HOUR(data); |
| 718 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 719 | RTC_CRITICAL_SECTION_LEAVE(); |
| 720 | } |
| 721 | |
| 722 | static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 723 | hri_rtcmode2_alarm_reg_t mask) |
| 724 | { |
| 725 | RTC_CRITICAL_SECTION_ENTER(); |
| 726 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); |
| 727 | RTC_CRITICAL_SECTION_LEAVE(); |
| 728 | } |
| 729 | |
| 730 | static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, |
| 731 | hri_rtcmode2_alarm_reg_t mask) |
| 732 | { |
| 733 | RTC_CRITICAL_SECTION_ENTER(); |
| 734 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); |
| 735 | RTC_CRITICAL_SECTION_LEAVE(); |
| 736 | } |
| 737 | |
| 738 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) |
| 739 | { |
| 740 | uint32_t tmp; |
| 741 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 742 | tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; |
| 743 | return tmp; |
| 744 | } |
| 745 | |
| 746 | static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 747 | hri_rtcmode2_alarm_reg_t mask) |
| 748 | { |
| 749 | RTC_CRITICAL_SECTION_ENTER(); |
| 750 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); |
| 751 | RTC_CRITICAL_SECTION_LEAVE(); |
| 752 | } |
| 753 | |
| 754 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 755 | hri_rtcmode2_alarm_reg_t mask) |
| 756 | { |
| 757 | uint32_t tmp; |
| 758 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 759 | tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; |
| 760 | return tmp; |
| 761 | } |
| 762 | |
| 763 | static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 764 | hri_rtcmode2_alarm_reg_t data) |
| 765 | { |
| 766 | uint32_t tmp; |
| 767 | RTC_CRITICAL_SECTION_ENTER(); |
| 768 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 769 | tmp &= ~RTC_MODE2_ALARM_DAY_Msk; |
| 770 | tmp |= RTC_MODE2_ALARM_DAY(data); |
| 771 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 772 | RTC_CRITICAL_SECTION_LEAVE(); |
| 773 | } |
| 774 | |
| 775 | static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 776 | hri_rtcmode2_alarm_reg_t mask) |
| 777 | { |
| 778 | RTC_CRITICAL_SECTION_ENTER(); |
| 779 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); |
| 780 | RTC_CRITICAL_SECTION_LEAVE(); |
| 781 | } |
| 782 | |
| 783 | static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, |
| 784 | hri_rtcmode2_alarm_reg_t mask) |
| 785 | { |
| 786 | RTC_CRITICAL_SECTION_ENTER(); |
| 787 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); |
| 788 | RTC_CRITICAL_SECTION_LEAVE(); |
| 789 | } |
| 790 | |
| 791 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) |
| 792 | { |
| 793 | uint32_t tmp; |
| 794 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 795 | tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; |
| 796 | return tmp; |
| 797 | } |
| 798 | |
| 799 | static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 800 | hri_rtcmode2_alarm_reg_t mask) |
| 801 | { |
| 802 | RTC_CRITICAL_SECTION_ENTER(); |
| 803 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); |
| 804 | RTC_CRITICAL_SECTION_LEAVE(); |
| 805 | } |
| 806 | |
| 807 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 808 | hri_rtcmode2_alarm_reg_t mask) |
| 809 | { |
| 810 | uint32_t tmp; |
| 811 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 812 | tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; |
| 813 | return tmp; |
| 814 | } |
| 815 | |
| 816 | static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 817 | hri_rtcmode2_alarm_reg_t data) |
| 818 | { |
| 819 | uint32_t tmp; |
| 820 | RTC_CRITICAL_SECTION_ENTER(); |
| 821 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 822 | tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; |
| 823 | tmp |= RTC_MODE2_ALARM_MONTH(data); |
| 824 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 825 | RTC_CRITICAL_SECTION_LEAVE(); |
| 826 | } |
| 827 | |
| 828 | static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 829 | hri_rtcmode2_alarm_reg_t mask) |
| 830 | { |
| 831 | RTC_CRITICAL_SECTION_ENTER(); |
| 832 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); |
| 833 | RTC_CRITICAL_SECTION_LEAVE(); |
| 834 | } |
| 835 | |
| 836 | static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, |
| 837 | hri_rtcmode2_alarm_reg_t mask) |
| 838 | { |
| 839 | RTC_CRITICAL_SECTION_ENTER(); |
| 840 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); |
| 841 | RTC_CRITICAL_SECTION_LEAVE(); |
| 842 | } |
| 843 | |
| 844 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) |
| 845 | { |
| 846 | uint32_t tmp; |
| 847 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 848 | tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; |
| 849 | return tmp; |
| 850 | } |
| 851 | |
| 852 | static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 853 | hri_rtcmode2_alarm_reg_t mask) |
| 854 | { |
| 855 | RTC_CRITICAL_SECTION_ENTER(); |
| 856 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); |
| 857 | RTC_CRITICAL_SECTION_LEAVE(); |
| 858 | } |
| 859 | |
| 860 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 861 | hri_rtcmode2_alarm_reg_t mask) |
| 862 | { |
| 863 | uint32_t tmp; |
| 864 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 865 | tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; |
| 866 | return tmp; |
| 867 | } |
| 868 | |
| 869 | static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 870 | hri_rtcmode2_alarm_reg_t data) |
| 871 | { |
| 872 | uint32_t tmp; |
| 873 | RTC_CRITICAL_SECTION_ENTER(); |
| 874 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 875 | tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; |
| 876 | tmp |= RTC_MODE2_ALARM_YEAR(data); |
| 877 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; |
| 878 | RTC_CRITICAL_SECTION_LEAVE(); |
| 879 | } |
| 880 | |
| 881 | static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 882 | hri_rtcmode2_alarm_reg_t mask) |
| 883 | { |
| 884 | RTC_CRITICAL_SECTION_ENTER(); |
| 885 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); |
| 886 | RTC_CRITICAL_SECTION_LEAVE(); |
| 887 | } |
| 888 | |
| 889 | static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, |
| 890 | hri_rtcmode2_alarm_reg_t mask) |
| 891 | { |
| 892 | RTC_CRITICAL_SECTION_ENTER(); |
| 893 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); |
| 894 | RTC_CRITICAL_SECTION_LEAVE(); |
| 895 | } |
| 896 | |
| 897 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) |
| 898 | { |
| 899 | uint32_t tmp; |
| 900 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 901 | tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; |
| 902 | return tmp; |
| 903 | } |
| 904 | |
| 905 | static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 906 | hri_rtcmode2_alarm_reg_t mask) |
| 907 | { |
| 908 | RTC_CRITICAL_SECTION_ENTER(); |
| 909 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; |
| 910 | RTC_CRITICAL_SECTION_LEAVE(); |
| 911 | } |
| 912 | |
| 913 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 914 | hri_rtcmode2_alarm_reg_t mask) |
| 915 | { |
| 916 | uint32_t tmp; |
| 917 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 918 | tmp &= mask; |
| 919 | return tmp; |
| 920 | } |
| 921 | |
| 922 | static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 923 | hri_rtcmode2_alarm_reg_t data) |
| 924 | { |
| 925 | RTC_CRITICAL_SECTION_ENTER(); |
| 926 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; |
| 927 | RTC_CRITICAL_SECTION_LEAVE(); |
| 928 | } |
| 929 | |
| 930 | static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 931 | hri_rtcmode2_alarm_reg_t mask) |
| 932 | { |
| 933 | RTC_CRITICAL_SECTION_ENTER(); |
| 934 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; |
| 935 | RTC_CRITICAL_SECTION_LEAVE(); |
| 936 | } |
| 937 | |
| 938 | static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, |
| 939 | hri_rtcmode2_alarm_reg_t mask) |
| 940 | { |
| 941 | RTC_CRITICAL_SECTION_ENTER(); |
| 942 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; |
| 943 | RTC_CRITICAL_SECTION_LEAVE(); |
| 944 | } |
| 945 | |
| 946 | static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) |
| 947 | { |
| 948 | return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; |
| 949 | } |
| 950 | |
| 951 | static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 952 | hri_rtcmode2_mask_reg_t mask) |
| 953 | { |
| 954 | RTC_CRITICAL_SECTION_ENTER(); |
| 955 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); |
| 956 | RTC_CRITICAL_SECTION_LEAVE(); |
| 957 | } |
| 958 | |
| 959 | static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 960 | hri_rtcmode2_mask_reg_t mask) |
| 961 | { |
| 962 | uint8_t tmp; |
| 963 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; |
| 964 | tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; |
| 965 | return tmp; |
| 966 | } |
| 967 | |
| 968 | static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 969 | hri_rtcmode2_mask_reg_t data) |
| 970 | { |
| 971 | uint8_t tmp; |
| 972 | RTC_CRITICAL_SECTION_ENTER(); |
| 973 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; |
| 974 | tmp &= ~RTC_MODE2_MASK_SEL_Msk; |
| 975 | tmp |= RTC_MODE2_MASK_SEL(data); |
| 976 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; |
| 977 | RTC_CRITICAL_SECTION_LEAVE(); |
| 978 | } |
| 979 | |
| 980 | static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 981 | hri_rtcmode2_mask_reg_t mask) |
| 982 | { |
| 983 | RTC_CRITICAL_SECTION_ENTER(); |
| 984 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); |
| 985 | RTC_CRITICAL_SECTION_LEAVE(); |
| 986 | } |
| 987 | |
| 988 | static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, |
| 989 | hri_rtcmode2_mask_reg_t mask) |
| 990 | { |
| 991 | RTC_CRITICAL_SECTION_ENTER(); |
| 992 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); |
| 993 | RTC_CRITICAL_SECTION_LEAVE(); |
| 994 | } |
| 995 | |
| 996 | static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) |
| 997 | { |
| 998 | uint8_t tmp; |
| 999 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; |
| 1000 | tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; |
| 1001 | return tmp; |
| 1002 | } |
| 1003 | |
| 1004 | static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 1005 | hri_rtcmode2_mask_reg_t mask) |
| 1006 | { |
| 1007 | RTC_CRITICAL_SECTION_ENTER(); |
| 1008 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; |
| 1009 | RTC_CRITICAL_SECTION_LEAVE(); |
| 1010 | } |
| 1011 | |
| 1012 | static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 1013 | hri_rtcmode2_mask_reg_t mask) |
| 1014 | { |
| 1015 | uint8_t tmp; |
| 1016 | tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; |
| 1017 | tmp &= mask; |
| 1018 | return tmp; |
| 1019 | } |
| 1020 | |
| 1021 | static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 1022 | hri_rtcmode2_mask_reg_t data) |
| 1023 | { |
| 1024 | RTC_CRITICAL_SECTION_ENTER(); |
| 1025 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; |
| 1026 | RTC_CRITICAL_SECTION_LEAVE(); |
| 1027 | } |
| 1028 | |
| 1029 | static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 1030 | hri_rtcmode2_mask_reg_t mask) |
| 1031 | { |
| 1032 | RTC_CRITICAL_SECTION_ENTER(); |
| 1033 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; |
| 1034 | RTC_CRITICAL_SECTION_LEAVE(); |
| 1035 | } |
| 1036 | |
| 1037 | static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, |
| 1038 | hri_rtcmode2_mask_reg_t mask) |
| 1039 | { |
| 1040 | RTC_CRITICAL_SECTION_ENTER(); |
| 1041 | ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; |
| 1042 | RTC_CRITICAL_SECTION_LEAVE(); |
| 1043 | } |
| 1044 | |
| 1045 | static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) |
| 1046 | { |
| 1047 | return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; |
| 1048 | } |
| 1049 | |
| 1050 | static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) |
| 1051 | { |
| 1052 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; |
| 1053 | } |
| 1054 | |
| 1055 | static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) |
| 1056 | { |
| 1057 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; |
| 1058 | } |
| 1059 | |
| 1060 | static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) |
| 1061 | { |
| 1062 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; |
| 1063 | } |
| 1064 | |
| 1065 | static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) |
| 1066 | { |
| 1067 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; |
| 1068 | } |
| 1069 | |
| 1070 | static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) |
| 1071 | { |
| 1072 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; |
| 1073 | } |
| 1074 | |
| 1075 | static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) |
| 1076 | { |
| 1077 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; |
| 1078 | } |
| 1079 | |
| 1080 | static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) |
| 1081 | { |
| 1082 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; |
| 1083 | } |
| 1084 | |
| 1085 | static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) |
| 1086 | { |
| 1087 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; |
| 1088 | } |
| 1089 | |
| 1090 | static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) |
| 1091 | { |
| 1092 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; |
| 1093 | } |
| 1094 | |
| 1095 | static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) |
| 1096 | { |
| 1097 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; |
| 1098 | } |
| 1099 | |
| 1100 | static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) |
| 1101 | { |
| 1102 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; |
| 1103 | } |
| 1104 | |
| 1105 | static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) |
| 1106 | { |
| 1107 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; |
| 1108 | } |
| 1109 | |
| 1110 | static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) |
| 1111 | { |
| 1112 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; |
| 1113 | } |
| 1114 | |
| 1115 | static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) |
| 1116 | { |
| 1117 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; |
| 1118 | } |
| 1119 | |
| 1120 | static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) |
| 1121 | { |
| 1122 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; |
| 1123 | } |
| 1124 | |
| 1125 | static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) |
| 1126 | { |
| 1127 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; |
| 1128 | } |
| 1129 | |
| 1130 | static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) |
| 1131 | { |
| 1132 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; |
| 1133 | } |
| 1134 | |
| 1135 | static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) |
| 1136 | { |
| 1137 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; |
| 1138 | } |
| 1139 | |
| 1140 | static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) |
| 1141 | { |
| 1142 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; |
| 1143 | } |
| 1144 | |
| 1145 | static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) |
| 1146 | { |
| 1147 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; |
| 1148 | } |
| 1149 | |
| 1150 | static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) |
| 1151 | { |
| 1152 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; |
| 1153 | } |
| 1154 | |
| 1155 | static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) |
| 1156 | { |
| 1157 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; |
| 1158 | } |
| 1159 | |
| 1160 | static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) |
| 1161 | { |
| 1162 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; |
| 1163 | } |
| 1164 | |
| 1165 | static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) |
| 1166 | { |
| 1167 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; |
| 1168 | } |
| 1169 | |
| 1170 | static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) |
| 1171 | { |
| 1172 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; |
| 1173 | } |
| 1174 | |
| 1175 | static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) |
| 1176 | { |
| 1177 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; |
| 1178 | } |
| 1179 | |
| 1180 | static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) |
| 1181 | { |
| 1182 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; |
| 1183 | } |
| 1184 | |
| 1185 | static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) |
| 1186 | { |
| 1187 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; |
| 1188 | } |
| 1189 | |
| 1190 | static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) |
| 1191 | { |
| 1192 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; |
| 1193 | } |
| 1194 | |
| 1195 | static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) |
| 1196 | { |
| 1197 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; |
| 1198 | } |
| 1199 | |
| 1200 | static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) |
| 1201 | { |
| 1202 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; |
| 1203 | } |
| 1204 | |
| 1205 | static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) |
| 1206 | { |
| 1207 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; |
| 1208 | } |
| 1209 | |
| 1210 | static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) |
| 1211 | { |
| 1212 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; |
| 1213 | } |
| 1214 | |
| 1215 | static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) |
| 1216 | { |
| 1217 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; |
| 1218 | } |
| 1219 | |
| 1220 | static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) |
| 1221 | { |
| 1222 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; |
| 1223 | } |
| 1224 | |
| 1225 | static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) |
| 1226 | { |
| 1227 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; |
| 1228 | } |
| 1229 | |
| 1230 | static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) |
| 1231 | { |
| 1232 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; |
| 1233 | } |
| 1234 | |
| 1235 | static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) |
| 1236 | { |
| 1237 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; |
| 1238 | } |
| 1239 | |
| 1240 | static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) |
| 1241 | { |
| 1242 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; |
| 1243 | } |
| 1244 | |
| 1245 | static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) |
| 1246 | { |
| 1247 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; |
| 1248 | } |
| 1249 | |
| 1250 | static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) |
| 1251 | { |
| 1252 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; |
| 1253 | } |
| 1254 | |
| 1255 | static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) |
| 1256 | { |
| 1257 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; |
| 1258 | } |
| 1259 | |
| 1260 | static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) |
| 1261 | { |
| 1262 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; |
| 1263 | } |
| 1264 | |
| 1265 | static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) |
| 1266 | { |
| 1267 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; |
| 1268 | } |
| 1269 | |
| 1270 | static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) |
| 1271 | { |
| 1272 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; |
| 1273 | } |
| 1274 | |
| 1275 | static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) |
| 1276 | { |
| 1277 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; |
| 1278 | } |
| 1279 | |
| 1280 | static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) |
| 1281 | { |
| 1282 | return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; |
| 1283 | } |
| 1284 | |
| 1285 | static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) |
| 1286 | { |
| 1287 | ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; |
| 1288 | } |
| 1289 | |
| 1290 | static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, |
| 1291 | hri_rtcmode0_intflag_reg_t mask) |
| 1292 | { |
| 1293 | uint16_t tmp; |
| 1294 | tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; |
| 1295 | tmp &= mask; |
| 1296 | return tmp; |
| 1297 | } |
| 1298 | |
| 1299 | static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) |
| 1300 | { |
| 1301 | return ((Rtc *)hw)->MODE0.INTFLAG.reg; |
| 1302 | } |
| 1303 | |
| 1304 | static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) |
| 1305 | { |
| 1306 | ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; |
| 1307 | } |
| 1308 | |
| 1309 | static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) |
| 1310 | { |
| 1311 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; |
| 1312 | } |
| 1313 | |
| 1314 | static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) |
| 1315 | { |
| 1316 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; |
| 1317 | } |
| 1318 | |
| 1319 | static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) |
| 1320 | { |
| 1321 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; |
| 1322 | } |
| 1323 | |
| 1324 | static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) |
| 1325 | { |
| 1326 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; |
| 1327 | } |
| 1328 | |
| 1329 | static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) |
| 1330 | { |
| 1331 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; |
| 1332 | } |
| 1333 | |
| 1334 | static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) |
| 1335 | { |
| 1336 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; |
| 1337 | } |
| 1338 | |
| 1339 | static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) |
| 1340 | { |
| 1341 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; |
| 1342 | } |
| 1343 | |
| 1344 | static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) |
| 1345 | { |
| 1346 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; |
| 1347 | } |
| 1348 | |
| 1349 | static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) |
| 1350 | { |
| 1351 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; |
| 1352 | } |
| 1353 | |
| 1354 | static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) |
| 1355 | { |
| 1356 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; |
| 1357 | } |
| 1358 | |
| 1359 | static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) |
| 1360 | { |
| 1361 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; |
| 1362 | } |
| 1363 | |
| 1364 | static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) |
| 1365 | { |
| 1366 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; |
| 1367 | } |
| 1368 | |
| 1369 | static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) |
| 1370 | { |
| 1371 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; |
| 1372 | } |
| 1373 | |
| 1374 | static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) |
| 1375 | { |
| 1376 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; |
| 1377 | } |
| 1378 | |
| 1379 | static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) |
| 1380 | { |
| 1381 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; |
| 1382 | } |
| 1383 | |
| 1384 | static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) |
| 1385 | { |
| 1386 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; |
| 1387 | } |
| 1388 | |
| 1389 | static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) |
| 1390 | { |
| 1391 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; |
| 1392 | } |
| 1393 | |
| 1394 | static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) |
| 1395 | { |
| 1396 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; |
| 1397 | } |
| 1398 | |
| 1399 | static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) |
| 1400 | { |
| 1401 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; |
| 1402 | } |
| 1403 | |
| 1404 | static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) |
| 1405 | { |
| 1406 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; |
| 1407 | } |
| 1408 | |
| 1409 | static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) |
| 1410 | { |
| 1411 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; |
| 1412 | } |
| 1413 | |
| 1414 | static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) |
| 1415 | { |
| 1416 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; |
| 1417 | } |
| 1418 | |
| 1419 | static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) |
| 1420 | { |
| 1421 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; |
| 1422 | } |
| 1423 | |
| 1424 | static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) |
| 1425 | { |
| 1426 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; |
| 1427 | } |
| 1428 | |
| 1429 | static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) |
| 1430 | { |
| 1431 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; |
| 1432 | } |
| 1433 | |
| 1434 | static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) |
| 1435 | { |
| 1436 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; |
| 1437 | } |
| 1438 | |
| 1439 | static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) |
| 1440 | { |
| 1441 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; |
| 1442 | } |
| 1443 | |
| 1444 | static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) |
| 1445 | { |
| 1446 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; |
| 1447 | } |
| 1448 | |
| 1449 | static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) |
| 1450 | { |
| 1451 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; |
| 1452 | } |
| 1453 | |
| 1454 | static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) |
| 1455 | { |
| 1456 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; |
| 1457 | } |
| 1458 | |
| 1459 | static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) |
| 1460 | { |
| 1461 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; |
| 1462 | } |
| 1463 | |
| 1464 | static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) |
| 1465 | { |
| 1466 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; |
| 1467 | } |
| 1468 | |
| 1469 | static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) |
| 1470 | { |
| 1471 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; |
| 1472 | } |
| 1473 | |
| 1474 | static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) |
| 1475 | { |
| 1476 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; |
| 1477 | } |
| 1478 | |
| 1479 | static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) |
| 1480 | { |
| 1481 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; |
| 1482 | } |
| 1483 | |
| 1484 | static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) |
| 1485 | { |
| 1486 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; |
| 1487 | } |
| 1488 | |
| 1489 | static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) |
| 1490 | { |
| 1491 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; |
| 1492 | } |
| 1493 | |
| 1494 | static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) |
| 1495 | { |
| 1496 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; |
| 1497 | } |
| 1498 | |
| 1499 | static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) |
| 1500 | { |
| 1501 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; |
| 1502 | } |
| 1503 | |
| 1504 | static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) |
| 1505 | { |
| 1506 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; |
| 1507 | } |
| 1508 | |
| 1509 | static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) |
| 1510 | { |
| 1511 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; |
| 1512 | } |
| 1513 | |
| 1514 | static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) |
| 1515 | { |
| 1516 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; |
| 1517 | } |
| 1518 | |
| 1519 | static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) |
| 1520 | { |
| 1521 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; |
| 1522 | } |
| 1523 | |
| 1524 | static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) |
| 1525 | { |
| 1526 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; |
| 1527 | } |
| 1528 | |
| 1529 | static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) |
| 1530 | { |
| 1531 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; |
| 1532 | } |
| 1533 | |
| 1534 | static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) |
| 1535 | { |
| 1536 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; |
| 1537 | } |
| 1538 | |
| 1539 | static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) |
| 1540 | { |
| 1541 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; |
| 1542 | } |
| 1543 | |
| 1544 | static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) |
| 1545 | { |
| 1546 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; |
| 1547 | } |
| 1548 | |
| 1549 | static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) |
| 1550 | { |
| 1551 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; |
| 1552 | } |
| 1553 | |
| 1554 | static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) |
| 1555 | { |
| 1556 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; |
| 1557 | } |
| 1558 | |
| 1559 | static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) |
| 1560 | { |
| 1561 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; |
| 1562 | } |
| 1563 | |
| 1564 | static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) |
| 1565 | { |
| 1566 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; |
| 1567 | } |
| 1568 | |
| 1569 | static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) |
| 1570 | { |
| 1571 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; |
| 1572 | } |
| 1573 | |
| 1574 | static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) |
| 1575 | { |
| 1576 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; |
| 1577 | } |
| 1578 | |
| 1579 | static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) |
| 1580 | { |
| 1581 | return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; |
| 1582 | } |
| 1583 | |
| 1584 | static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) |
| 1585 | { |
| 1586 | ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; |
| 1587 | } |
| 1588 | |
| 1589 | static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, |
| 1590 | hri_rtcmode1_intflag_reg_t mask) |
| 1591 | { |
| 1592 | uint16_t tmp; |
| 1593 | tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; |
| 1594 | tmp &= mask; |
| 1595 | return tmp; |
| 1596 | } |
| 1597 | |
| 1598 | static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) |
| 1599 | { |
| 1600 | return ((Rtc *)hw)->MODE1.INTFLAG.reg; |
| 1601 | } |
| 1602 | |
| 1603 | static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) |
| 1604 | { |
| 1605 | ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; |
| 1606 | } |
| 1607 | |
| 1608 | static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) |
| 1609 | { |
| 1610 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; |
| 1611 | } |
| 1612 | |
| 1613 | static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) |
| 1614 | { |
| 1615 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; |
| 1616 | } |
| 1617 | |
| 1618 | static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) |
| 1619 | { |
| 1620 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; |
| 1621 | } |
| 1622 | |
| 1623 | static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) |
| 1624 | { |
| 1625 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; |
| 1626 | } |
| 1627 | |
| 1628 | static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) |
| 1629 | { |
| 1630 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; |
| 1631 | } |
| 1632 | |
| 1633 | static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) |
| 1634 | { |
| 1635 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; |
| 1636 | } |
| 1637 | |
| 1638 | static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) |
| 1639 | { |
| 1640 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; |
| 1641 | } |
| 1642 | |
| 1643 | static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) |
| 1644 | { |
| 1645 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; |
| 1646 | } |
| 1647 | |
| 1648 | static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) |
| 1649 | { |
| 1650 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; |
| 1651 | } |
| 1652 | |
| 1653 | static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) |
| 1654 | { |
| 1655 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; |
| 1656 | } |
| 1657 | |
| 1658 | static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) |
| 1659 | { |
| 1660 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; |
| 1661 | } |
| 1662 | |
| 1663 | static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) |
| 1664 | { |
| 1665 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; |
| 1666 | } |
| 1667 | |
| 1668 | static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) |
| 1669 | { |
| 1670 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; |
| 1671 | } |
| 1672 | |
| 1673 | static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) |
| 1674 | { |
| 1675 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; |
| 1676 | } |
| 1677 | |
| 1678 | static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) |
| 1679 | { |
| 1680 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; |
| 1681 | } |
| 1682 | |
| 1683 | static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) |
| 1684 | { |
| 1685 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; |
| 1686 | } |
| 1687 | |
| 1688 | static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) |
| 1689 | { |
| 1690 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; |
| 1691 | } |
| 1692 | |
| 1693 | static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) |
| 1694 | { |
| 1695 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; |
| 1696 | } |
| 1697 | |
| 1698 | static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) |
| 1699 | { |
| 1700 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; |
| 1701 | } |
| 1702 | |
| 1703 | static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) |
| 1704 | { |
| 1705 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; |
| 1706 | } |
| 1707 | |
| 1708 | static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) |
| 1709 | { |
| 1710 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; |
| 1711 | } |
| 1712 | |
| 1713 | static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) |
| 1714 | { |
| 1715 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; |
| 1716 | } |
| 1717 | |
| 1718 | static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) |
| 1719 | { |
| 1720 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; |
| 1721 | } |
| 1722 | |
| 1723 | static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) |
| 1724 | { |
| 1725 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; |
| 1726 | } |
| 1727 | |
| 1728 | static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) |
| 1729 | { |
| 1730 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; |
| 1731 | } |
| 1732 | |
| 1733 | static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) |
| 1734 | { |
| 1735 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; |
| 1736 | } |
| 1737 | |
| 1738 | static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) |
| 1739 | { |
| 1740 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; |
| 1741 | } |
| 1742 | |
| 1743 | static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) |
| 1744 | { |
| 1745 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; |
| 1746 | } |
| 1747 | |
| 1748 | static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) |
| 1749 | { |
| 1750 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; |
| 1751 | } |
| 1752 | |
| 1753 | static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) |
| 1754 | { |
| 1755 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; |
| 1756 | } |
| 1757 | |
| 1758 | static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) |
| 1759 | { |
| 1760 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; |
| 1761 | } |
| 1762 | |
| 1763 | static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) |
| 1764 | { |
| 1765 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; |
| 1766 | } |
| 1767 | |
| 1768 | static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) |
| 1769 | { |
| 1770 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; |
| 1771 | } |
| 1772 | |
| 1773 | static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) |
| 1774 | { |
| 1775 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; |
| 1776 | } |
| 1777 | |
| 1778 | static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) |
| 1779 | { |
| 1780 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; |
| 1781 | } |
| 1782 | |
| 1783 | static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) |
| 1784 | { |
| 1785 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; |
| 1786 | } |
| 1787 | |
| 1788 | static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) |
| 1789 | { |
| 1790 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; |
| 1791 | } |
| 1792 | |
| 1793 | static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) |
| 1794 | { |
| 1795 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; |
| 1796 | } |
| 1797 | |
| 1798 | static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) |
| 1799 | { |
| 1800 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; |
| 1801 | } |
| 1802 | |
| 1803 | static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) |
| 1804 | { |
| 1805 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; |
| 1806 | } |
| 1807 | |
| 1808 | static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) |
| 1809 | { |
| 1810 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; |
| 1811 | } |
| 1812 | |
| 1813 | static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) |
| 1814 | { |
| 1815 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; |
| 1816 | } |
| 1817 | |
| 1818 | static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) |
| 1819 | { |
| 1820 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; |
| 1821 | } |
| 1822 | |
| 1823 | static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) |
| 1824 | { |
| 1825 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; |
| 1826 | } |
| 1827 | |
| 1828 | static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) |
| 1829 | { |
| 1830 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; |
| 1831 | } |
| 1832 | |
| 1833 | static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) |
| 1834 | { |
| 1835 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; |
| 1836 | } |
| 1837 | |
| 1838 | static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) |
| 1839 | { |
| 1840 | return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; |
| 1841 | } |
| 1842 | |
| 1843 | static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) |
| 1844 | { |
| 1845 | ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; |
| 1846 | } |
| 1847 | |
| 1848 | static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, |
| 1849 | hri_rtcmode2_intflag_reg_t mask) |
| 1850 | { |
| 1851 | uint16_t tmp; |
| 1852 | tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; |
| 1853 | tmp &= mask; |
| 1854 | return tmp; |
| 1855 | } |
| 1856 | |
| 1857 | static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) |
| 1858 | { |
| 1859 | return ((Rtc *)hw)->MODE2.INTFLAG.reg; |
| 1860 | } |
| 1861 | |
| 1862 | static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) |
| 1863 | { |
| 1864 | ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; |
| 1865 | } |
| 1866 | |
| 1867 | static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) |
| 1868 | { |
| 1869 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; |
| 1870 | } |
| 1871 | |
| 1872 | static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) |
| 1873 | { |
| 1874 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; |
| 1875 | } |
| 1876 | |
| 1877 | static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) |
| 1878 | { |
| 1879 | if (value == 0x0) { |
| 1880 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; |
| 1881 | } else { |
| 1882 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; |
| 1883 | } |
| 1884 | } |
| 1885 | |
| 1886 | static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) |
| 1887 | { |
| 1888 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; |
| 1889 | } |
| 1890 | |
| 1891 | static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) |
| 1892 | { |
| 1893 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; |
| 1894 | } |
| 1895 | |
| 1896 | static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) |
| 1897 | { |
| 1898 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; |
| 1899 | } |
| 1900 | |
| 1901 | static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) |
| 1902 | { |
| 1903 | if (value == 0x0) { |
| 1904 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; |
| 1905 | } else { |
| 1906 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; |
| 1907 | } |
| 1908 | } |
| 1909 | |
| 1910 | static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) |
| 1911 | { |
| 1912 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; |
| 1913 | } |
| 1914 | |
| 1915 | static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) |
| 1916 | { |
| 1917 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; |
| 1918 | } |
| 1919 | |
| 1920 | static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) |
| 1921 | { |
| 1922 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; |
| 1923 | } |
| 1924 | |
| 1925 | static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) |
| 1926 | { |
| 1927 | if (value == 0x0) { |
| 1928 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; |
| 1929 | } else { |
| 1930 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; |
| 1931 | } |
| 1932 | } |
| 1933 | |
| 1934 | static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) |
| 1935 | { |
| 1936 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; |
| 1937 | } |
| 1938 | |
| 1939 | static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) |
| 1940 | { |
| 1941 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; |
| 1942 | } |
| 1943 | |
| 1944 | static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) |
| 1945 | { |
| 1946 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; |
| 1947 | } |
| 1948 | |
| 1949 | static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) |
| 1950 | { |
| 1951 | if (value == 0x0) { |
| 1952 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; |
| 1953 | } else { |
| 1954 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; |
| 1955 | } |
| 1956 | } |
| 1957 | |
| 1958 | static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) |
| 1959 | { |
| 1960 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; |
| 1961 | } |
| 1962 | |
| 1963 | static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) |
| 1964 | { |
| 1965 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; |
| 1966 | } |
| 1967 | |
| 1968 | static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) |
| 1969 | { |
| 1970 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; |
| 1971 | } |
| 1972 | |
| 1973 | static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) |
| 1974 | { |
| 1975 | if (value == 0x0) { |
| 1976 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; |
| 1977 | } else { |
| 1978 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; |
| 1979 | } |
| 1980 | } |
| 1981 | |
| 1982 | static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) |
| 1983 | { |
| 1984 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; |
| 1985 | } |
| 1986 | |
| 1987 | static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) |
| 1988 | { |
| 1989 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; |
| 1990 | } |
| 1991 | |
| 1992 | static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) |
| 1993 | { |
| 1994 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; |
| 1995 | } |
| 1996 | |
| 1997 | static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) |
| 1998 | { |
| 1999 | if (value == 0x0) { |
| 2000 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; |
| 2001 | } else { |
| 2002 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; |
| 2003 | } |
| 2004 | } |
| 2005 | |
| 2006 | static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) |
| 2007 | { |
| 2008 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; |
| 2009 | } |
| 2010 | |
| 2011 | static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) |
| 2012 | { |
| 2013 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; |
| 2014 | } |
| 2015 | |
| 2016 | static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) |
| 2017 | { |
| 2018 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; |
| 2019 | } |
| 2020 | |
| 2021 | static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) |
| 2022 | { |
| 2023 | if (value == 0x0) { |
| 2024 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; |
| 2025 | } else { |
| 2026 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; |
| 2027 | } |
| 2028 | } |
| 2029 | |
| 2030 | static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) |
| 2031 | { |
| 2032 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; |
| 2033 | } |
| 2034 | |
| 2035 | static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) |
| 2036 | { |
| 2037 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; |
| 2038 | } |
| 2039 | |
| 2040 | static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) |
| 2041 | { |
| 2042 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; |
| 2043 | } |
| 2044 | |
| 2045 | static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) |
| 2046 | { |
| 2047 | if (value == 0x0) { |
| 2048 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; |
| 2049 | } else { |
| 2050 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; |
| 2051 | } |
| 2052 | } |
| 2053 | |
| 2054 | static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) |
| 2055 | { |
| 2056 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; |
| 2057 | } |
| 2058 | |
| 2059 | static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) |
| 2060 | { |
| 2061 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; |
| 2062 | } |
| 2063 | |
| 2064 | static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) |
| 2065 | { |
| 2066 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; |
| 2067 | } |
| 2068 | |
| 2069 | static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) |
| 2070 | { |
| 2071 | if (value == 0x0) { |
| 2072 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; |
| 2073 | } else { |
| 2074 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; |
| 2075 | } |
| 2076 | } |
| 2077 | |
| 2078 | static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) |
| 2079 | { |
| 2080 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; |
| 2081 | } |
| 2082 | |
| 2083 | static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) |
| 2084 | { |
| 2085 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; |
| 2086 | } |
| 2087 | |
| 2088 | static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) |
| 2089 | { |
| 2090 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; |
| 2091 | } |
| 2092 | |
| 2093 | static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) |
| 2094 | { |
| 2095 | if (value == 0x0) { |
| 2096 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; |
| 2097 | } else { |
| 2098 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; |
| 2099 | } |
| 2100 | } |
| 2101 | |
| 2102 | static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) |
| 2103 | { |
| 2104 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; |
| 2105 | } |
| 2106 | |
| 2107 | static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) |
| 2108 | { |
| 2109 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; |
| 2110 | } |
| 2111 | |
| 2112 | static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) |
| 2113 | { |
| 2114 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; |
| 2115 | } |
| 2116 | |
| 2117 | static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) |
| 2118 | { |
| 2119 | if (value == 0x0) { |
| 2120 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; |
| 2121 | } else { |
| 2122 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; |
| 2123 | } |
| 2124 | } |
| 2125 | |
| 2126 | static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) |
| 2127 | { |
| 2128 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; |
| 2129 | } |
| 2130 | |
| 2131 | static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) |
| 2132 | { |
| 2133 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; |
| 2134 | } |
| 2135 | |
| 2136 | static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) |
| 2137 | { |
| 2138 | return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; |
| 2139 | } |
| 2140 | |
| 2141 | static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) |
| 2142 | { |
| 2143 | if (value == 0x0) { |
| 2144 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; |
| 2145 | } else { |
| 2146 | ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; |
| 2147 | } |
| 2148 | } |
| 2149 | |
| 2150 | static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) |
| 2151 | { |
| 2152 | ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; |
| 2153 | } |
| 2154 | |
| 2155 | static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) |
| 2156 | { |
| 2157 | ((Rtc *)hw)->MODE0.INTENSET.reg = mask; |
| 2158 | } |
| 2159 | |
| 2160 | static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, |
| 2161 | hri_rtcmode0_intenset_reg_t mask) |
| 2162 | { |
| 2163 | uint16_t tmp; |
| 2164 | tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; |
| 2165 | tmp &= mask; |
| 2166 | return tmp; |
| 2167 | } |
| 2168 | |
| 2169 | static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) |
| 2170 | { |
| 2171 | return ((Rtc *)hw)->MODE0.INTENSET.reg; |
| 2172 | } |
| 2173 | |
| 2174 | static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) |
| 2175 | { |
| 2176 | ((Rtc *)hw)->MODE0.INTENSET.reg = data; |
| 2177 | ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; |
| 2178 | } |
| 2179 | |
| 2180 | static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) |
| 2181 | { |
| 2182 | ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; |
| 2183 | } |
| 2184 | |
| 2185 | static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) |
| 2186 | { |
| 2187 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; |
| 2188 | } |
| 2189 | |
| 2190 | static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) |
| 2191 | { |
| 2192 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; |
| 2193 | } |
| 2194 | |
| 2195 | static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) |
| 2196 | { |
| 2197 | if (value == 0x0) { |
| 2198 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; |
| 2199 | } else { |
| 2200 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; |
| 2201 | } |
| 2202 | } |
| 2203 | |
| 2204 | static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) |
| 2205 | { |
| 2206 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; |
| 2207 | } |
| 2208 | |
| 2209 | static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) |
| 2210 | { |
| 2211 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; |
| 2212 | } |
| 2213 | |
| 2214 | static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) |
| 2215 | { |
| 2216 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; |
| 2217 | } |
| 2218 | |
| 2219 | static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) |
| 2220 | { |
| 2221 | if (value == 0x0) { |
| 2222 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; |
| 2223 | } else { |
| 2224 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; |
| 2225 | } |
| 2226 | } |
| 2227 | |
| 2228 | static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) |
| 2229 | { |
| 2230 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; |
| 2231 | } |
| 2232 | |
| 2233 | static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) |
| 2234 | { |
| 2235 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; |
| 2236 | } |
| 2237 | |
| 2238 | static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) |
| 2239 | { |
| 2240 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; |
| 2241 | } |
| 2242 | |
| 2243 | static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) |
| 2244 | { |
| 2245 | if (value == 0x0) { |
| 2246 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; |
| 2247 | } else { |
| 2248 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; |
| 2249 | } |
| 2250 | } |
| 2251 | |
| 2252 | static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) |
| 2253 | { |
| 2254 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; |
| 2255 | } |
| 2256 | |
| 2257 | static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) |
| 2258 | { |
| 2259 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; |
| 2260 | } |
| 2261 | |
| 2262 | static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) |
| 2263 | { |
| 2264 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; |
| 2265 | } |
| 2266 | |
| 2267 | static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) |
| 2268 | { |
| 2269 | if (value == 0x0) { |
| 2270 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; |
| 2271 | } else { |
| 2272 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; |
| 2273 | } |
| 2274 | } |
| 2275 | |
| 2276 | static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) |
| 2277 | { |
| 2278 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; |
| 2279 | } |
| 2280 | |
| 2281 | static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) |
| 2282 | { |
| 2283 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; |
| 2284 | } |
| 2285 | |
| 2286 | static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) |
| 2287 | { |
| 2288 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; |
| 2289 | } |
| 2290 | |
| 2291 | static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) |
| 2292 | { |
| 2293 | if (value == 0x0) { |
| 2294 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; |
| 2295 | } else { |
| 2296 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; |
| 2297 | } |
| 2298 | } |
| 2299 | |
| 2300 | static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) |
| 2301 | { |
| 2302 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; |
| 2303 | } |
| 2304 | |
| 2305 | static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) |
| 2306 | { |
| 2307 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; |
| 2308 | } |
| 2309 | |
| 2310 | static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) |
| 2311 | { |
| 2312 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; |
| 2313 | } |
| 2314 | |
| 2315 | static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) |
| 2316 | { |
| 2317 | if (value == 0x0) { |
| 2318 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; |
| 2319 | } else { |
| 2320 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; |
| 2321 | } |
| 2322 | } |
| 2323 | |
| 2324 | static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) |
| 2325 | { |
| 2326 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; |
| 2327 | } |
| 2328 | |
| 2329 | static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) |
| 2330 | { |
| 2331 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; |
| 2332 | } |
| 2333 | |
| 2334 | static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) |
| 2335 | { |
| 2336 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; |
| 2337 | } |
| 2338 | |
| 2339 | static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) |
| 2340 | { |
| 2341 | if (value == 0x0) { |
| 2342 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; |
| 2343 | } else { |
| 2344 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; |
| 2345 | } |
| 2346 | } |
| 2347 | |
| 2348 | static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) |
| 2349 | { |
| 2350 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; |
| 2351 | } |
| 2352 | |
| 2353 | static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) |
| 2354 | { |
| 2355 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; |
| 2356 | } |
| 2357 | |
| 2358 | static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) |
| 2359 | { |
| 2360 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; |
| 2361 | } |
| 2362 | |
| 2363 | static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) |
| 2364 | { |
| 2365 | if (value == 0x0) { |
| 2366 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; |
| 2367 | } else { |
| 2368 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; |
| 2369 | } |
| 2370 | } |
| 2371 | |
| 2372 | static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) |
| 2373 | { |
| 2374 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; |
| 2375 | } |
| 2376 | |
| 2377 | static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) |
| 2378 | { |
| 2379 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; |
| 2380 | } |
| 2381 | |
| 2382 | static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) |
| 2383 | { |
| 2384 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; |
| 2385 | } |
| 2386 | |
| 2387 | static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) |
| 2388 | { |
| 2389 | if (value == 0x0) { |
| 2390 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; |
| 2391 | } else { |
| 2392 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; |
| 2393 | } |
| 2394 | } |
| 2395 | |
| 2396 | static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) |
| 2397 | { |
| 2398 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; |
| 2399 | } |
| 2400 | |
| 2401 | static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) |
| 2402 | { |
| 2403 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; |
| 2404 | } |
| 2405 | |
| 2406 | static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) |
| 2407 | { |
| 2408 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; |
| 2409 | } |
| 2410 | |
| 2411 | static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) |
| 2412 | { |
| 2413 | if (value == 0x0) { |
| 2414 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; |
| 2415 | } else { |
| 2416 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; |
| 2417 | } |
| 2418 | } |
| 2419 | |
| 2420 | static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) |
| 2421 | { |
| 2422 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; |
| 2423 | } |
| 2424 | |
| 2425 | static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) |
| 2426 | { |
| 2427 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; |
| 2428 | } |
| 2429 | |
| 2430 | static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) |
| 2431 | { |
| 2432 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; |
| 2433 | } |
| 2434 | |
| 2435 | static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) |
| 2436 | { |
| 2437 | if (value == 0x0) { |
| 2438 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; |
| 2439 | } else { |
| 2440 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; |
| 2441 | } |
| 2442 | } |
| 2443 | |
| 2444 | static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) |
| 2445 | { |
| 2446 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; |
| 2447 | } |
| 2448 | |
| 2449 | static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) |
| 2450 | { |
| 2451 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; |
| 2452 | } |
| 2453 | |
| 2454 | static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) |
| 2455 | { |
| 2456 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; |
| 2457 | } |
| 2458 | |
| 2459 | static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) |
| 2460 | { |
| 2461 | if (value == 0x0) { |
| 2462 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; |
| 2463 | } else { |
| 2464 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; |
| 2465 | } |
| 2466 | } |
| 2467 | |
| 2468 | static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) |
| 2469 | { |
| 2470 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; |
| 2471 | } |
| 2472 | |
| 2473 | static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) |
| 2474 | { |
| 2475 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; |
| 2476 | } |
| 2477 | |
| 2478 | static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) |
| 2479 | { |
| 2480 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; |
| 2481 | } |
| 2482 | |
| 2483 | static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) |
| 2484 | { |
| 2485 | if (value == 0x0) { |
| 2486 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; |
| 2487 | } else { |
| 2488 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; |
| 2489 | } |
| 2490 | } |
| 2491 | |
| 2492 | static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) |
| 2493 | { |
| 2494 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; |
| 2495 | } |
| 2496 | |
| 2497 | static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) |
| 2498 | { |
| 2499 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; |
| 2500 | } |
| 2501 | |
| 2502 | static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) |
| 2503 | { |
| 2504 | return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; |
| 2505 | } |
| 2506 | |
| 2507 | static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) |
| 2508 | { |
| 2509 | if (value == 0x0) { |
| 2510 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; |
| 2511 | } else { |
| 2512 | ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; |
| 2513 | } |
| 2514 | } |
| 2515 | |
| 2516 | static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) |
| 2517 | { |
| 2518 | ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; |
| 2519 | } |
| 2520 | |
| 2521 | static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) |
| 2522 | { |
| 2523 | ((Rtc *)hw)->MODE1.INTENSET.reg = mask; |
| 2524 | } |
| 2525 | |
| 2526 | static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, |
| 2527 | hri_rtcmode1_intenset_reg_t mask) |
| 2528 | { |
| 2529 | uint16_t tmp; |
| 2530 | tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; |
| 2531 | tmp &= mask; |
| 2532 | return tmp; |
| 2533 | } |
| 2534 | |
| 2535 | static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) |
| 2536 | { |
| 2537 | return ((Rtc *)hw)->MODE1.INTENSET.reg; |
| 2538 | } |
| 2539 | |
| 2540 | static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) |
| 2541 | { |
| 2542 | ((Rtc *)hw)->MODE1.INTENSET.reg = data; |
| 2543 | ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; |
| 2544 | } |
| 2545 | |
| 2546 | static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) |
| 2547 | { |
| 2548 | ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; |
| 2549 | } |
| 2550 | |
| 2551 | static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) |
| 2552 | { |
| 2553 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; |
| 2554 | } |
| 2555 | |
| 2556 | static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) |
| 2557 | { |
| 2558 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; |
| 2559 | } |
| 2560 | |
| 2561 | static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) |
| 2562 | { |
| 2563 | if (value == 0x0) { |
| 2564 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; |
| 2565 | } else { |
| 2566 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; |
| 2567 | } |
| 2568 | } |
| 2569 | |
| 2570 | static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) |
| 2571 | { |
| 2572 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; |
| 2573 | } |
| 2574 | |
| 2575 | static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) |
| 2576 | { |
| 2577 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; |
| 2578 | } |
| 2579 | |
| 2580 | static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) |
| 2581 | { |
| 2582 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; |
| 2583 | } |
| 2584 | |
| 2585 | static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) |
| 2586 | { |
| 2587 | if (value == 0x0) { |
| 2588 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; |
| 2589 | } else { |
| 2590 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; |
| 2591 | } |
| 2592 | } |
| 2593 | |
| 2594 | static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) |
| 2595 | { |
| 2596 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; |
| 2597 | } |
| 2598 | |
| 2599 | static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) |
| 2600 | { |
| 2601 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; |
| 2602 | } |
| 2603 | |
| 2604 | static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) |
| 2605 | { |
| 2606 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; |
| 2607 | } |
| 2608 | |
| 2609 | static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) |
| 2610 | { |
| 2611 | if (value == 0x0) { |
| 2612 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; |
| 2613 | } else { |
| 2614 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; |
| 2615 | } |
| 2616 | } |
| 2617 | |
| 2618 | static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) |
| 2619 | { |
| 2620 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; |
| 2621 | } |
| 2622 | |
| 2623 | static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) |
| 2624 | { |
| 2625 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; |
| 2626 | } |
| 2627 | |
| 2628 | static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) |
| 2629 | { |
| 2630 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; |
| 2631 | } |
| 2632 | |
| 2633 | static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) |
| 2634 | { |
| 2635 | if (value == 0x0) { |
| 2636 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; |
| 2637 | } else { |
| 2638 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; |
| 2639 | } |
| 2640 | } |
| 2641 | |
| 2642 | static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) |
| 2643 | { |
| 2644 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; |
| 2645 | } |
| 2646 | |
| 2647 | static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) |
| 2648 | { |
| 2649 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; |
| 2650 | } |
| 2651 | |
| 2652 | static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) |
| 2653 | { |
| 2654 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; |
| 2655 | } |
| 2656 | |
| 2657 | static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) |
| 2658 | { |
| 2659 | if (value == 0x0) { |
| 2660 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; |
| 2661 | } else { |
| 2662 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; |
| 2663 | } |
| 2664 | } |
| 2665 | |
| 2666 | static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) |
| 2667 | { |
| 2668 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; |
| 2669 | } |
| 2670 | |
| 2671 | static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) |
| 2672 | { |
| 2673 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; |
| 2674 | } |
| 2675 | |
| 2676 | static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) |
| 2677 | { |
| 2678 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; |
| 2679 | } |
| 2680 | |
| 2681 | static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) |
| 2682 | { |
| 2683 | if (value == 0x0) { |
| 2684 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; |
| 2685 | } else { |
| 2686 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; |
| 2687 | } |
| 2688 | } |
| 2689 | |
| 2690 | static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) |
| 2691 | { |
| 2692 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; |
| 2693 | } |
| 2694 | |
| 2695 | static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) |
| 2696 | { |
| 2697 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; |
| 2698 | } |
| 2699 | |
| 2700 | static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) |
| 2701 | { |
| 2702 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; |
| 2703 | } |
| 2704 | |
| 2705 | static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) |
| 2706 | { |
| 2707 | if (value == 0x0) { |
| 2708 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; |
| 2709 | } else { |
| 2710 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; |
| 2711 | } |
| 2712 | } |
| 2713 | |
| 2714 | static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) |
| 2715 | { |
| 2716 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; |
| 2717 | } |
| 2718 | |
| 2719 | static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) |
| 2720 | { |
| 2721 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; |
| 2722 | } |
| 2723 | |
| 2724 | static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) |
| 2725 | { |
| 2726 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; |
| 2727 | } |
| 2728 | |
| 2729 | static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) |
| 2730 | { |
| 2731 | if (value == 0x0) { |
| 2732 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; |
| 2733 | } else { |
| 2734 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; |
| 2735 | } |
| 2736 | } |
| 2737 | |
| 2738 | static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) |
| 2739 | { |
| 2740 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; |
| 2741 | } |
| 2742 | |
| 2743 | static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) |
| 2744 | { |
| 2745 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; |
| 2746 | } |
| 2747 | |
| 2748 | static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) |
| 2749 | { |
| 2750 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; |
| 2751 | } |
| 2752 | |
| 2753 | static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) |
| 2754 | { |
| 2755 | if (value == 0x0) { |
| 2756 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; |
| 2757 | } else { |
| 2758 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; |
| 2759 | } |
| 2760 | } |
| 2761 | |
| 2762 | static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) |
| 2763 | { |
| 2764 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; |
| 2765 | } |
| 2766 | |
| 2767 | static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) |
| 2768 | { |
| 2769 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; |
| 2770 | } |
| 2771 | |
| 2772 | static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) |
| 2773 | { |
| 2774 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; |
| 2775 | } |
| 2776 | |
| 2777 | static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) |
| 2778 | { |
| 2779 | if (value == 0x0) { |
| 2780 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; |
| 2781 | } else { |
| 2782 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; |
| 2783 | } |
| 2784 | } |
| 2785 | |
| 2786 | static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) |
| 2787 | { |
| 2788 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; |
| 2789 | } |
| 2790 | |
| 2791 | static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) |
| 2792 | { |
| 2793 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; |
| 2794 | } |
| 2795 | |
| 2796 | static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) |
| 2797 | { |
| 2798 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; |
| 2799 | } |
| 2800 | |
| 2801 | static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) |
| 2802 | { |
| 2803 | if (value == 0x0) { |
| 2804 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; |
| 2805 | } else { |
| 2806 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; |
| 2807 | } |
| 2808 | } |
| 2809 | |
| 2810 | static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) |
| 2811 | { |
| 2812 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; |
| 2813 | } |
| 2814 | |
| 2815 | static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) |
| 2816 | { |
| 2817 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; |
| 2818 | } |
| 2819 | |
| 2820 | static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) |
| 2821 | { |
| 2822 | return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; |
| 2823 | } |
| 2824 | |
| 2825 | static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) |
| 2826 | { |
| 2827 | if (value == 0x0) { |
| 2828 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; |
| 2829 | } else { |
| 2830 | ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; |
| 2831 | } |
| 2832 | } |
| 2833 | |
| 2834 | static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) |
| 2835 | { |
| 2836 | ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; |
| 2837 | } |
| 2838 | |
| 2839 | static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) |
| 2840 | { |
| 2841 | ((Rtc *)hw)->MODE2.INTENSET.reg = mask; |
| 2842 | } |
| 2843 | |
| 2844 | static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, |
| 2845 | hri_rtcmode2_intenset_reg_t mask) |
| 2846 | { |
| 2847 | uint16_t tmp; |
| 2848 | tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; |
| 2849 | tmp &= mask; |
| 2850 | return tmp; |
| 2851 | } |
| 2852 | |
| 2853 | static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) |
| 2854 | { |
| 2855 | return ((Rtc *)hw)->MODE2.INTENSET.reg; |
| 2856 | } |
| 2857 | |
| 2858 | static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) |
| 2859 | { |
| 2860 | ((Rtc *)hw)->MODE2.INTENSET.reg = data; |
| 2861 | ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; |
| 2862 | } |
| 2863 | |
| 2864 | static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) |
| 2865 | { |
| 2866 | ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; |
| 2867 | } |
| 2868 | |
| 2869 | static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 2870 | { |
| 2871 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; |
| 2872 | } |
| 2873 | |
| 2874 | static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 2875 | { |
| 2876 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; |
| 2877 | } |
| 2878 | |
| 2879 | static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) |
| 2880 | { |
| 2881 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; |
| 2882 | } |
| 2883 | |
| 2884 | static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) |
| 2885 | { |
| 2886 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; |
| 2887 | } |
| 2888 | |
| 2889 | static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) |
| 2890 | { |
| 2891 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; |
| 2892 | } |
| 2893 | |
| 2894 | static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) |
| 2895 | { |
| 2896 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; |
| 2897 | } |
| 2898 | |
| 2899 | static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) |
| 2900 | { |
| 2901 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; |
| 2902 | } |
| 2903 | |
| 2904 | static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) |
| 2905 | { |
| 2906 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; |
| 2907 | } |
| 2908 | |
| 2909 | static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) |
| 2910 | { |
| 2911 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; |
| 2912 | } |
| 2913 | |
| 2914 | static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) |
| 2915 | { |
| 2916 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; |
| 2917 | } |
| 2918 | |
| 2919 | static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) |
| 2920 | { |
| 2921 | return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; |
| 2922 | } |
| 2923 | |
| 2924 | static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, |
| 2925 | hri_rtcmode0_syncbusy_reg_t mask) |
| 2926 | { |
| 2927 | uint32_t tmp; |
| 2928 | tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; |
| 2929 | tmp &= mask; |
| 2930 | return tmp; |
| 2931 | } |
| 2932 | |
| 2933 | static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) |
| 2934 | { |
| 2935 | return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; |
| 2936 | } |
| 2937 | |
| 2938 | static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 2939 | { |
| 2940 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; |
| 2941 | } |
| 2942 | |
| 2943 | static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 2944 | { |
| 2945 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; |
| 2946 | } |
| 2947 | |
| 2948 | static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) |
| 2949 | { |
| 2950 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; |
| 2951 | } |
| 2952 | |
| 2953 | static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) |
| 2954 | { |
| 2955 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; |
| 2956 | } |
| 2957 | |
| 2958 | static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) |
| 2959 | { |
| 2960 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; |
| 2961 | } |
| 2962 | |
| 2963 | static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) |
| 2964 | { |
| 2965 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; |
| 2966 | } |
| 2967 | |
| 2968 | static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) |
| 2969 | { |
| 2970 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; |
| 2971 | } |
| 2972 | |
| 2973 | static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) |
| 2974 | { |
| 2975 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; |
| 2976 | } |
| 2977 | |
| 2978 | static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) |
| 2979 | { |
| 2980 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; |
| 2981 | } |
| 2982 | |
| 2983 | static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) |
| 2984 | { |
| 2985 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; |
| 2986 | } |
| 2987 | |
| 2988 | static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) |
| 2989 | { |
| 2990 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; |
| 2991 | } |
| 2992 | |
| 2993 | static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) |
| 2994 | { |
| 2995 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; |
| 2996 | } |
| 2997 | |
| 2998 | static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) |
| 2999 | { |
| 3000 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; |
| 3001 | } |
| 3002 | |
| 3003 | static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) |
| 3004 | { |
| 3005 | return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; |
| 3006 | } |
| 3007 | |
| 3008 | static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, |
| 3009 | hri_rtcmode1_syncbusy_reg_t mask) |
| 3010 | { |
| 3011 | uint32_t tmp; |
| 3012 | tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; |
| 3013 | tmp &= mask; |
| 3014 | return tmp; |
| 3015 | } |
| 3016 | |
| 3017 | static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) |
| 3018 | { |
| 3019 | return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; |
| 3020 | } |
| 3021 | |
| 3022 | static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 3023 | { |
| 3024 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; |
| 3025 | } |
| 3026 | |
| 3027 | static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 3028 | { |
| 3029 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; |
| 3030 | } |
| 3031 | |
| 3032 | static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) |
| 3033 | { |
| 3034 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; |
| 3035 | } |
| 3036 | |
| 3037 | static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) |
| 3038 | { |
| 3039 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; |
| 3040 | } |
| 3041 | |
| 3042 | static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) |
| 3043 | { |
| 3044 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; |
| 3045 | } |
| 3046 | |
| 3047 | static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) |
| 3048 | { |
| 3049 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; |
| 3050 | } |
| 3051 | |
| 3052 | static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) |
| 3053 | { |
| 3054 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; |
| 3055 | } |
| 3056 | |
| 3057 | static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) |
| 3058 | { |
| 3059 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; |
| 3060 | } |
| 3061 | |
| 3062 | static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) |
| 3063 | { |
| 3064 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; |
| 3065 | } |
| 3066 | |
| 3067 | static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) |
| 3068 | { |
| 3069 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; |
| 3070 | } |
| 3071 | |
| 3072 | static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) |
| 3073 | { |
| 3074 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; |
| 3075 | } |
| 3076 | |
| 3077 | static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) |
| 3078 | { |
| 3079 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; |
| 3080 | } |
| 3081 | |
| 3082 | static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) |
| 3083 | { |
| 3084 | return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; |
| 3085 | } |
| 3086 | |
| 3087 | static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, |
| 3088 | hri_rtcmode2_syncbusy_reg_t mask) |
| 3089 | { |
| 3090 | uint32_t tmp; |
| 3091 | tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; |
| 3092 | tmp &= mask; |
| 3093 | return tmp; |
| 3094 | } |
| 3095 | |
| 3096 | static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) |
| 3097 | { |
| 3098 | return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; |
| 3099 | } |
| 3100 | |
| 3101 | static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, |
| 3102 | hri_rtcmode0_timestamp_reg_t mask) |
| 3103 | { |
| 3104 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 3105 | return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; |
| 3106 | } |
| 3107 | |
| 3108 | static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) |
| 3109 | { |
| 3110 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 3111 | return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; |
| 3112 | } |
| 3113 | |
| 3114 | static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, |
| 3115 | hri_rtcmode0_timestamp_reg_t mask) |
| 3116 | { |
| 3117 | uint32_t tmp; |
| 3118 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 3119 | tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; |
| 3120 | tmp &= mask; |
| 3121 | return tmp; |
| 3122 | } |
| 3123 | |
| 3124 | static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) |
| 3125 | { |
| 3126 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 3127 | return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; |
| 3128 | } |
| 3129 | |
| 3130 | static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, |
| 3131 | hri_rtcmode1_timestamp_reg_t mask) |
| 3132 | { |
| 3133 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 3134 | return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; |
| 3135 | } |
| 3136 | |
| 3137 | static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) |
| 3138 | { |
| 3139 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 3140 | return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; |
| 3141 | } |
| 3142 | |
| 3143 | static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, |
| 3144 | hri_rtcmode1_timestamp_reg_t mask) |
| 3145 | { |
| 3146 | uint32_t tmp; |
| 3147 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 3148 | tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; |
| 3149 | tmp &= mask; |
| 3150 | return tmp; |
| 3151 | } |
| 3152 | |
| 3153 | static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) |
| 3154 | { |
| 3155 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 3156 | return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; |
| 3157 | } |
| 3158 | |
| 3159 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, |
| 3160 | hri_rtcmode2_timestamp_reg_t mask) |
| 3161 | { |
| 3162 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3163 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; |
| 3164 | } |
| 3165 | |
| 3166 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) |
| 3167 | { |
| 3168 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3169 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; |
| 3170 | } |
| 3171 | |
| 3172 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, |
| 3173 | hri_rtcmode2_timestamp_reg_t mask) |
| 3174 | { |
| 3175 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3176 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; |
| 3177 | } |
| 3178 | |
| 3179 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) |
| 3180 | { |
| 3181 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3182 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; |
| 3183 | } |
| 3184 | |
| 3185 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, |
| 3186 | hri_rtcmode2_timestamp_reg_t mask) |
| 3187 | { |
| 3188 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3189 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; |
| 3190 | } |
| 3191 | |
| 3192 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) |
| 3193 | { |
| 3194 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3195 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; |
| 3196 | } |
| 3197 | |
| 3198 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, |
| 3199 | hri_rtcmode2_timestamp_reg_t mask) |
| 3200 | { |
| 3201 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3202 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; |
| 3203 | } |
| 3204 | |
| 3205 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) |
| 3206 | { |
| 3207 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3208 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; |
| 3209 | } |
| 3210 | |
| 3211 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, |
| 3212 | hri_rtcmode2_timestamp_reg_t mask) |
| 3213 | { |
| 3214 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3215 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; |
| 3216 | } |
| 3217 | |
| 3218 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) |
| 3219 | { |
| 3220 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3221 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; |
| 3222 | } |
| 3223 | |
| 3224 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, |
| 3225 | hri_rtcmode2_timestamp_reg_t mask) |
| 3226 | { |
| 3227 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3228 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; |
| 3229 | } |
| 3230 | |
| 3231 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) |
| 3232 | { |
| 3233 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3234 | return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; |
| 3235 | } |
| 3236 | |
| 3237 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, |
| 3238 | hri_rtcmode2_timestamp_reg_t mask) |
| 3239 | { |
| 3240 | uint32_t tmp; |
| 3241 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3242 | tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; |
| 3243 | tmp &= mask; |
| 3244 | return tmp; |
| 3245 | } |
| 3246 | |
| 3247 | static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) |
| 3248 | { |
| 3249 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 3250 | return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; |
| 3251 | } |
| 3252 | |
| 3253 | static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) |
| 3254 | { |
| 3255 | RTC_CRITICAL_SECTION_ENTER(); |
| 3256 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; |
| 3257 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); |
| 3258 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3259 | } |
| 3260 | |
| 3261 | static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) |
| 3262 | { |
| 3263 | uint16_t tmp; |
| 3264 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); |
| 3265 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3266 | tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; |
| 3267 | return (bool)tmp; |
| 3268 | } |
| 3269 | |
| 3270 | static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) |
| 3271 | { |
| 3272 | RTC_CRITICAL_SECTION_ENTER(); |
| 3273 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; |
| 3274 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3275 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3276 | } |
| 3277 | |
| 3278 | static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) |
| 3279 | { |
| 3280 | uint16_t tmp; |
| 3281 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3282 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3283 | tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; |
| 3284 | return (bool)tmp; |
| 3285 | } |
| 3286 | |
| 3287 | static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 3288 | { |
| 3289 | uint16_t tmp; |
| 3290 | RTC_CRITICAL_SECTION_ENTER(); |
| 3291 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3292 | tmp &= ~RTC_MODE0_CTRLA_ENABLE; |
| 3293 | tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; |
| 3294 | ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; |
| 3295 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3296 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3297 | } |
| 3298 | |
| 3299 | static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 3300 | { |
| 3301 | RTC_CRITICAL_SECTION_ENTER(); |
| 3302 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; |
| 3303 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3304 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3305 | } |
| 3306 | |
| 3307 | static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 3308 | { |
| 3309 | RTC_CRITICAL_SECTION_ENTER(); |
| 3310 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; |
| 3311 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3312 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3313 | } |
| 3314 | |
| 3315 | static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) |
| 3316 | { |
| 3317 | RTC_CRITICAL_SECTION_ENTER(); |
| 3318 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; |
| 3319 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3320 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3321 | } |
| 3322 | |
| 3323 | static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) |
| 3324 | { |
| 3325 | uint16_t tmp; |
| 3326 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3327 | tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; |
| 3328 | return (bool)tmp; |
| 3329 | } |
| 3330 | |
| 3331 | static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) |
| 3332 | { |
| 3333 | uint16_t tmp; |
| 3334 | RTC_CRITICAL_SECTION_ENTER(); |
| 3335 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3336 | tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; |
| 3337 | tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; |
| 3338 | ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; |
| 3339 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3340 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3341 | } |
| 3342 | |
| 3343 | static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) |
| 3344 | { |
| 3345 | RTC_CRITICAL_SECTION_ENTER(); |
| 3346 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; |
| 3347 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3348 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3349 | } |
| 3350 | |
| 3351 | static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) |
| 3352 | { |
| 3353 | RTC_CRITICAL_SECTION_ENTER(); |
| 3354 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; |
| 3355 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3356 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3357 | } |
| 3358 | |
| 3359 | static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) |
| 3360 | { |
| 3361 | RTC_CRITICAL_SECTION_ENTER(); |
| 3362 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; |
| 3363 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3364 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3365 | } |
| 3366 | |
| 3367 | static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) |
| 3368 | { |
| 3369 | uint16_t tmp; |
| 3370 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3371 | tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; |
| 3372 | return (bool)tmp; |
| 3373 | } |
| 3374 | |
| 3375 | static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) |
| 3376 | { |
| 3377 | uint16_t tmp; |
| 3378 | RTC_CRITICAL_SECTION_ENTER(); |
| 3379 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3380 | tmp &= ~RTC_MODE0_CTRLA_BKTRST; |
| 3381 | tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; |
| 3382 | ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; |
| 3383 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3384 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3385 | } |
| 3386 | |
| 3387 | static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) |
| 3388 | { |
| 3389 | RTC_CRITICAL_SECTION_ENTER(); |
| 3390 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; |
| 3391 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3392 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3393 | } |
| 3394 | |
| 3395 | static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) |
| 3396 | { |
| 3397 | RTC_CRITICAL_SECTION_ENTER(); |
| 3398 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; |
| 3399 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3400 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3401 | } |
| 3402 | |
| 3403 | static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) |
| 3404 | { |
| 3405 | RTC_CRITICAL_SECTION_ENTER(); |
| 3406 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; |
| 3407 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3408 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3409 | } |
| 3410 | |
| 3411 | static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) |
| 3412 | { |
| 3413 | uint16_t tmp; |
| 3414 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3415 | tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; |
| 3416 | return (bool)tmp; |
| 3417 | } |
| 3418 | |
| 3419 | static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) |
| 3420 | { |
| 3421 | uint16_t tmp; |
| 3422 | RTC_CRITICAL_SECTION_ENTER(); |
| 3423 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3424 | tmp &= ~RTC_MODE0_CTRLA_GPTRST; |
| 3425 | tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; |
| 3426 | ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; |
| 3427 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3428 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3429 | } |
| 3430 | |
| 3431 | static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) |
| 3432 | { |
| 3433 | RTC_CRITICAL_SECTION_ENTER(); |
| 3434 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; |
| 3435 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3436 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3437 | } |
| 3438 | |
| 3439 | static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) |
| 3440 | { |
| 3441 | RTC_CRITICAL_SECTION_ENTER(); |
| 3442 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; |
| 3443 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3444 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3445 | } |
| 3446 | |
| 3447 | static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3448 | { |
| 3449 | RTC_CRITICAL_SECTION_ENTER(); |
| 3450 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; |
| 3451 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3452 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3453 | } |
| 3454 | |
| 3455 | static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3456 | { |
| 3457 | uint16_t tmp; |
| 3458 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3459 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3460 | tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; |
| 3461 | return (bool)tmp; |
| 3462 | } |
| 3463 | |
| 3464 | static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) |
| 3465 | { |
| 3466 | uint16_t tmp; |
| 3467 | RTC_CRITICAL_SECTION_ENTER(); |
| 3468 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3469 | tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; |
| 3470 | tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; |
| 3471 | ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; |
| 3472 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3473 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3474 | } |
| 3475 | |
| 3476 | static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3477 | { |
| 3478 | RTC_CRITICAL_SECTION_ENTER(); |
| 3479 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; |
| 3480 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3481 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3482 | } |
| 3483 | |
| 3484 | static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3485 | { |
| 3486 | RTC_CRITICAL_SECTION_ENTER(); |
| 3487 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; |
| 3488 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3489 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3490 | } |
| 3491 | |
| 3492 | static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3493 | { |
| 3494 | RTC_CRITICAL_SECTION_ENTER(); |
| 3495 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); |
| 3496 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3497 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3498 | } |
| 3499 | |
| 3500 | static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, |
| 3501 | hri_rtcmode0_ctrla_reg_t mask) |
| 3502 | { |
| 3503 | uint16_t tmp; |
| 3504 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3505 | tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; |
| 3506 | return tmp; |
| 3507 | } |
| 3508 | |
| 3509 | static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) |
| 3510 | { |
| 3511 | uint16_t tmp; |
| 3512 | RTC_CRITICAL_SECTION_ENTER(); |
| 3513 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3514 | tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; |
| 3515 | tmp |= RTC_MODE0_CTRLA_MODE(data); |
| 3516 | ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; |
| 3517 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3518 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3519 | } |
| 3520 | |
| 3521 | static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3522 | { |
| 3523 | RTC_CRITICAL_SECTION_ENTER(); |
| 3524 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); |
| 3525 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3526 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3527 | } |
| 3528 | |
| 3529 | static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3530 | { |
| 3531 | RTC_CRITICAL_SECTION_ENTER(); |
| 3532 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); |
| 3533 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3534 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3535 | } |
| 3536 | |
| 3537 | static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) |
| 3538 | { |
| 3539 | uint16_t tmp; |
| 3540 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3541 | tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; |
| 3542 | return tmp; |
| 3543 | } |
| 3544 | |
| 3545 | static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3546 | { |
| 3547 | RTC_CRITICAL_SECTION_ENTER(); |
| 3548 | ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); |
| 3549 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3550 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3551 | } |
| 3552 | |
| 3553 | static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, |
| 3554 | hri_rtcmode0_ctrla_reg_t mask) |
| 3555 | { |
| 3556 | uint16_t tmp; |
| 3557 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3558 | tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; |
| 3559 | return tmp; |
| 3560 | } |
| 3561 | |
| 3562 | static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) |
| 3563 | { |
| 3564 | uint16_t tmp; |
| 3565 | RTC_CRITICAL_SECTION_ENTER(); |
| 3566 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3567 | tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; |
| 3568 | tmp |= RTC_MODE0_CTRLA_PRESCALER(data); |
| 3569 | ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; |
| 3570 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3571 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3572 | } |
| 3573 | |
| 3574 | static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3575 | { |
| 3576 | RTC_CRITICAL_SECTION_ENTER(); |
| 3577 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); |
| 3578 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3579 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3580 | } |
| 3581 | |
| 3582 | static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3583 | { |
| 3584 | RTC_CRITICAL_SECTION_ENTER(); |
| 3585 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); |
| 3586 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 3587 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3588 | } |
| 3589 | |
| 3590 | static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) |
| 3591 | { |
| 3592 | uint16_t tmp; |
| 3593 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3594 | tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; |
| 3595 | return tmp; |
| 3596 | } |
| 3597 | |
| 3598 | static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3599 | { |
| 3600 | RTC_CRITICAL_SECTION_ENTER(); |
| 3601 | ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; |
| 3602 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3603 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3604 | } |
| 3605 | |
| 3606 | static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3607 | { |
| 3608 | uint16_t tmp; |
| 3609 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3610 | tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3611 | tmp &= mask; |
| 3612 | return tmp; |
| 3613 | } |
| 3614 | |
| 3615 | static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) |
| 3616 | { |
| 3617 | RTC_CRITICAL_SECTION_ENTER(); |
| 3618 | ((Rtc *)hw)->MODE0.CTRLA.reg = data; |
| 3619 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3620 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3621 | } |
| 3622 | |
| 3623 | static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3624 | { |
| 3625 | RTC_CRITICAL_SECTION_ENTER(); |
| 3626 | ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; |
| 3627 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3628 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3629 | } |
| 3630 | |
| 3631 | static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) |
| 3632 | { |
| 3633 | RTC_CRITICAL_SECTION_ENTER(); |
| 3634 | ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; |
| 3635 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3636 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3637 | } |
| 3638 | |
| 3639 | static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) |
| 3640 | { |
| 3641 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); |
| 3642 | return ((Rtc *)hw)->MODE0.CTRLA.reg; |
| 3643 | } |
| 3644 | |
| 3645 | static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) |
| 3646 | { |
| 3647 | RTC_CRITICAL_SECTION_ENTER(); |
| 3648 | ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; |
| 3649 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); |
| 3650 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3651 | } |
| 3652 | |
| 3653 | static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) |
| 3654 | { |
| 3655 | uint16_t tmp; |
| 3656 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); |
| 3657 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3658 | tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; |
| 3659 | return (bool)tmp; |
| 3660 | } |
| 3661 | |
| 3662 | static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) |
| 3663 | { |
| 3664 | RTC_CRITICAL_SECTION_ENTER(); |
| 3665 | ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; |
| 3666 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3667 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3668 | } |
| 3669 | |
| 3670 | static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) |
| 3671 | { |
| 3672 | uint16_t tmp; |
| 3673 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3674 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3675 | tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; |
| 3676 | return (bool)tmp; |
| 3677 | } |
| 3678 | |
| 3679 | static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 3680 | { |
| 3681 | uint16_t tmp; |
| 3682 | RTC_CRITICAL_SECTION_ENTER(); |
| 3683 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3684 | tmp &= ~RTC_MODE1_CTRLA_ENABLE; |
| 3685 | tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; |
| 3686 | ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; |
| 3687 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3688 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3689 | } |
| 3690 | |
| 3691 | static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 3692 | { |
| 3693 | RTC_CRITICAL_SECTION_ENTER(); |
| 3694 | ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; |
| 3695 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3696 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3697 | } |
| 3698 | |
| 3699 | static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 3700 | { |
| 3701 | RTC_CRITICAL_SECTION_ENTER(); |
| 3702 | ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; |
| 3703 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3704 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3705 | } |
| 3706 | |
| 3707 | static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) |
| 3708 | { |
| 3709 | RTC_CRITICAL_SECTION_ENTER(); |
| 3710 | ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; |
| 3711 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3712 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3713 | } |
| 3714 | |
| 3715 | static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) |
| 3716 | { |
| 3717 | uint16_t tmp; |
| 3718 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3719 | tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; |
| 3720 | return (bool)tmp; |
| 3721 | } |
| 3722 | |
| 3723 | static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) |
| 3724 | { |
| 3725 | uint16_t tmp; |
| 3726 | RTC_CRITICAL_SECTION_ENTER(); |
| 3727 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3728 | tmp &= ~RTC_MODE1_CTRLA_BKTRST; |
| 3729 | tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; |
| 3730 | ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; |
| 3731 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3732 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3733 | } |
| 3734 | |
| 3735 | static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) |
| 3736 | { |
| 3737 | RTC_CRITICAL_SECTION_ENTER(); |
| 3738 | ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; |
| 3739 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3740 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3741 | } |
| 3742 | |
| 3743 | static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) |
| 3744 | { |
| 3745 | RTC_CRITICAL_SECTION_ENTER(); |
| 3746 | ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; |
| 3747 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3748 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3749 | } |
| 3750 | |
| 3751 | static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) |
| 3752 | { |
| 3753 | RTC_CRITICAL_SECTION_ENTER(); |
| 3754 | ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; |
| 3755 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3756 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3757 | } |
| 3758 | |
| 3759 | static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) |
| 3760 | { |
| 3761 | uint16_t tmp; |
| 3762 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3763 | tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; |
| 3764 | return (bool)tmp; |
| 3765 | } |
| 3766 | |
| 3767 | static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) |
| 3768 | { |
| 3769 | uint16_t tmp; |
| 3770 | RTC_CRITICAL_SECTION_ENTER(); |
| 3771 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3772 | tmp &= ~RTC_MODE1_CTRLA_GPTRST; |
| 3773 | tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; |
| 3774 | ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; |
| 3775 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3776 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3777 | } |
| 3778 | |
| 3779 | static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) |
| 3780 | { |
| 3781 | RTC_CRITICAL_SECTION_ENTER(); |
| 3782 | ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; |
| 3783 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3784 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3785 | } |
| 3786 | |
| 3787 | static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) |
| 3788 | { |
| 3789 | RTC_CRITICAL_SECTION_ENTER(); |
| 3790 | ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; |
| 3791 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3792 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3793 | } |
| 3794 | |
| 3795 | static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3796 | { |
| 3797 | RTC_CRITICAL_SECTION_ENTER(); |
| 3798 | ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; |
| 3799 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3800 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3801 | } |
| 3802 | |
| 3803 | static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3804 | { |
| 3805 | uint16_t tmp; |
| 3806 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3807 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3808 | tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; |
| 3809 | return (bool)tmp; |
| 3810 | } |
| 3811 | |
| 3812 | static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) |
| 3813 | { |
| 3814 | uint16_t tmp; |
| 3815 | RTC_CRITICAL_SECTION_ENTER(); |
| 3816 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3817 | tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; |
| 3818 | tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; |
| 3819 | ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; |
| 3820 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3821 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3822 | } |
| 3823 | |
| 3824 | static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3825 | { |
| 3826 | RTC_CRITICAL_SECTION_ENTER(); |
| 3827 | ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; |
| 3828 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3829 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3830 | } |
| 3831 | |
| 3832 | static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) |
| 3833 | { |
| 3834 | RTC_CRITICAL_SECTION_ENTER(); |
| 3835 | ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; |
| 3836 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3837 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3838 | } |
| 3839 | |
| 3840 | static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3841 | { |
| 3842 | RTC_CRITICAL_SECTION_ENTER(); |
| 3843 | ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); |
| 3844 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3845 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3846 | } |
| 3847 | |
| 3848 | static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, |
| 3849 | hri_rtcmode1_ctrla_reg_t mask) |
| 3850 | { |
| 3851 | uint16_t tmp; |
| 3852 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3853 | tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; |
| 3854 | return tmp; |
| 3855 | } |
| 3856 | |
| 3857 | static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) |
| 3858 | { |
| 3859 | uint16_t tmp; |
| 3860 | RTC_CRITICAL_SECTION_ENTER(); |
| 3861 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3862 | tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; |
| 3863 | tmp |= RTC_MODE1_CTRLA_MODE(data); |
| 3864 | ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; |
| 3865 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3866 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3867 | } |
| 3868 | |
| 3869 | static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3870 | { |
| 3871 | RTC_CRITICAL_SECTION_ENTER(); |
| 3872 | ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); |
| 3873 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3874 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3875 | } |
| 3876 | |
| 3877 | static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3878 | { |
| 3879 | RTC_CRITICAL_SECTION_ENTER(); |
| 3880 | ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); |
| 3881 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3882 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3883 | } |
| 3884 | |
| 3885 | static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) |
| 3886 | { |
| 3887 | uint16_t tmp; |
| 3888 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3889 | tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; |
| 3890 | return tmp; |
| 3891 | } |
| 3892 | |
| 3893 | static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3894 | { |
| 3895 | RTC_CRITICAL_SECTION_ENTER(); |
| 3896 | ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); |
| 3897 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3898 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3899 | } |
| 3900 | |
| 3901 | static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, |
| 3902 | hri_rtcmode1_ctrla_reg_t mask) |
| 3903 | { |
| 3904 | uint16_t tmp; |
| 3905 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3906 | tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; |
| 3907 | return tmp; |
| 3908 | } |
| 3909 | |
| 3910 | static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) |
| 3911 | { |
| 3912 | uint16_t tmp; |
| 3913 | RTC_CRITICAL_SECTION_ENTER(); |
| 3914 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3915 | tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; |
| 3916 | tmp |= RTC_MODE1_CTRLA_PRESCALER(data); |
| 3917 | ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; |
| 3918 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3919 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3920 | } |
| 3921 | |
| 3922 | static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3923 | { |
| 3924 | RTC_CRITICAL_SECTION_ENTER(); |
| 3925 | ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); |
| 3926 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3927 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3928 | } |
| 3929 | |
| 3930 | static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3931 | { |
| 3932 | RTC_CRITICAL_SECTION_ENTER(); |
| 3933 | ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); |
| 3934 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); |
| 3935 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3936 | } |
| 3937 | |
| 3938 | static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) |
| 3939 | { |
| 3940 | uint16_t tmp; |
| 3941 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3942 | tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; |
| 3943 | return tmp; |
| 3944 | } |
| 3945 | |
| 3946 | static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3947 | { |
| 3948 | RTC_CRITICAL_SECTION_ENTER(); |
| 3949 | ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; |
| 3950 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3951 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3952 | } |
| 3953 | |
| 3954 | static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3955 | { |
| 3956 | uint16_t tmp; |
| 3957 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3958 | tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3959 | tmp &= mask; |
| 3960 | return tmp; |
| 3961 | } |
| 3962 | |
| 3963 | static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) |
| 3964 | { |
| 3965 | RTC_CRITICAL_SECTION_ENTER(); |
| 3966 | ((Rtc *)hw)->MODE1.CTRLA.reg = data; |
| 3967 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3968 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3969 | } |
| 3970 | |
| 3971 | static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3972 | { |
| 3973 | RTC_CRITICAL_SECTION_ENTER(); |
| 3974 | ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; |
| 3975 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3976 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3977 | } |
| 3978 | |
| 3979 | static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) |
| 3980 | { |
| 3981 | RTC_CRITICAL_SECTION_ENTER(); |
| 3982 | ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; |
| 3983 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3984 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3985 | } |
| 3986 | |
| 3987 | static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) |
| 3988 | { |
| 3989 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); |
| 3990 | return ((Rtc *)hw)->MODE1.CTRLA.reg; |
| 3991 | } |
| 3992 | |
| 3993 | static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) |
| 3994 | { |
| 3995 | RTC_CRITICAL_SECTION_ENTER(); |
| 3996 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; |
| 3997 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); |
| 3998 | RTC_CRITICAL_SECTION_LEAVE(); |
| 3999 | } |
| 4000 | |
| 4001 | static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) |
| 4002 | { |
| 4003 | uint16_t tmp; |
| 4004 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); |
| 4005 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4006 | tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; |
| 4007 | return (bool)tmp; |
| 4008 | } |
| 4009 | |
| 4010 | static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) |
| 4011 | { |
| 4012 | RTC_CRITICAL_SECTION_ENTER(); |
| 4013 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; |
| 4014 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4015 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4016 | } |
| 4017 | |
| 4018 | static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) |
| 4019 | { |
| 4020 | uint16_t tmp; |
| 4021 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4022 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4023 | tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; |
| 4024 | return (bool)tmp; |
| 4025 | } |
| 4026 | |
| 4027 | static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 4028 | { |
| 4029 | uint16_t tmp; |
| 4030 | RTC_CRITICAL_SECTION_ENTER(); |
| 4031 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4032 | tmp &= ~RTC_MODE2_CTRLA_ENABLE; |
| 4033 | tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; |
| 4034 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4035 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4036 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4037 | } |
| 4038 | |
| 4039 | static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 4040 | { |
| 4041 | RTC_CRITICAL_SECTION_ENTER(); |
| 4042 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; |
| 4043 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4044 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4045 | } |
| 4046 | |
| 4047 | static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 4048 | { |
| 4049 | RTC_CRITICAL_SECTION_ENTER(); |
| 4050 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; |
| 4051 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4052 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4053 | } |
| 4054 | |
| 4055 | static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) |
| 4056 | { |
| 4057 | RTC_CRITICAL_SECTION_ENTER(); |
| 4058 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; |
| 4059 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4060 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4061 | } |
| 4062 | |
| 4063 | static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) |
| 4064 | { |
| 4065 | uint16_t tmp; |
| 4066 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4067 | tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; |
| 4068 | return (bool)tmp; |
| 4069 | } |
| 4070 | |
| 4071 | static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) |
| 4072 | { |
| 4073 | uint16_t tmp; |
| 4074 | RTC_CRITICAL_SECTION_ENTER(); |
| 4075 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4076 | tmp &= ~RTC_MODE2_CTRLA_CLKREP; |
| 4077 | tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; |
| 4078 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4079 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4080 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4081 | } |
| 4082 | |
| 4083 | static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) |
| 4084 | { |
| 4085 | RTC_CRITICAL_SECTION_ENTER(); |
| 4086 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; |
| 4087 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4088 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4089 | } |
| 4090 | |
| 4091 | static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) |
| 4092 | { |
| 4093 | RTC_CRITICAL_SECTION_ENTER(); |
| 4094 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; |
| 4095 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4096 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4097 | } |
| 4098 | |
| 4099 | static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) |
| 4100 | { |
| 4101 | RTC_CRITICAL_SECTION_ENTER(); |
| 4102 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; |
| 4103 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4104 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4105 | } |
| 4106 | |
| 4107 | static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) |
| 4108 | { |
| 4109 | uint16_t tmp; |
| 4110 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4111 | tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; |
| 4112 | return (bool)tmp; |
| 4113 | } |
| 4114 | |
| 4115 | static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) |
| 4116 | { |
| 4117 | uint16_t tmp; |
| 4118 | RTC_CRITICAL_SECTION_ENTER(); |
| 4119 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4120 | tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; |
| 4121 | tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; |
| 4122 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4123 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4124 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4125 | } |
| 4126 | |
| 4127 | static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) |
| 4128 | { |
| 4129 | RTC_CRITICAL_SECTION_ENTER(); |
| 4130 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; |
| 4131 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4132 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4133 | } |
| 4134 | |
| 4135 | static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) |
| 4136 | { |
| 4137 | RTC_CRITICAL_SECTION_ENTER(); |
| 4138 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; |
| 4139 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4140 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4141 | } |
| 4142 | |
| 4143 | static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) |
| 4144 | { |
| 4145 | RTC_CRITICAL_SECTION_ENTER(); |
| 4146 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; |
| 4147 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4148 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4149 | } |
| 4150 | |
| 4151 | static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) |
| 4152 | { |
| 4153 | uint16_t tmp; |
| 4154 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4155 | tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; |
| 4156 | return (bool)tmp; |
| 4157 | } |
| 4158 | |
| 4159 | static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) |
| 4160 | { |
| 4161 | uint16_t tmp; |
| 4162 | RTC_CRITICAL_SECTION_ENTER(); |
| 4163 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4164 | tmp &= ~RTC_MODE2_CTRLA_BKTRST; |
| 4165 | tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; |
| 4166 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4167 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4168 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4169 | } |
| 4170 | |
| 4171 | static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) |
| 4172 | { |
| 4173 | RTC_CRITICAL_SECTION_ENTER(); |
| 4174 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; |
| 4175 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4176 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4177 | } |
| 4178 | |
| 4179 | static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) |
| 4180 | { |
| 4181 | RTC_CRITICAL_SECTION_ENTER(); |
| 4182 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; |
| 4183 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4184 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4185 | } |
| 4186 | |
| 4187 | static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) |
| 4188 | { |
| 4189 | RTC_CRITICAL_SECTION_ENTER(); |
| 4190 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; |
| 4191 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4192 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4193 | } |
| 4194 | |
| 4195 | static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) |
| 4196 | { |
| 4197 | uint16_t tmp; |
| 4198 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4199 | tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; |
| 4200 | return (bool)tmp; |
| 4201 | } |
| 4202 | |
| 4203 | static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) |
| 4204 | { |
| 4205 | uint16_t tmp; |
| 4206 | RTC_CRITICAL_SECTION_ENTER(); |
| 4207 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4208 | tmp &= ~RTC_MODE2_CTRLA_GPTRST; |
| 4209 | tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; |
| 4210 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4211 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4212 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4213 | } |
| 4214 | |
| 4215 | static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) |
| 4216 | { |
| 4217 | RTC_CRITICAL_SECTION_ENTER(); |
| 4218 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; |
| 4219 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4220 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4221 | } |
| 4222 | |
| 4223 | static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) |
| 4224 | { |
| 4225 | RTC_CRITICAL_SECTION_ENTER(); |
| 4226 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; |
| 4227 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4228 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4229 | } |
| 4230 | |
| 4231 | static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) |
| 4232 | { |
| 4233 | RTC_CRITICAL_SECTION_ENTER(); |
| 4234 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; |
| 4235 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4236 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4237 | } |
| 4238 | |
| 4239 | static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) |
| 4240 | { |
| 4241 | uint16_t tmp; |
| 4242 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4243 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4244 | tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; |
| 4245 | return (bool)tmp; |
| 4246 | } |
| 4247 | |
| 4248 | static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) |
| 4249 | { |
| 4250 | uint16_t tmp; |
| 4251 | RTC_CRITICAL_SECTION_ENTER(); |
| 4252 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4253 | tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; |
| 4254 | tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; |
| 4255 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4256 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4257 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4258 | } |
| 4259 | |
| 4260 | static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) |
| 4261 | { |
| 4262 | RTC_CRITICAL_SECTION_ENTER(); |
| 4263 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; |
| 4264 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4265 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4266 | } |
| 4267 | |
| 4268 | static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) |
| 4269 | { |
| 4270 | RTC_CRITICAL_SECTION_ENTER(); |
| 4271 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; |
| 4272 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4273 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4274 | } |
| 4275 | |
| 4276 | static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4277 | { |
| 4278 | RTC_CRITICAL_SECTION_ENTER(); |
| 4279 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); |
| 4280 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4281 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4282 | } |
| 4283 | |
| 4284 | static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, |
| 4285 | hri_rtcmode2_ctrla_reg_t mask) |
| 4286 | { |
| 4287 | uint16_t tmp; |
| 4288 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4289 | tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; |
| 4290 | return tmp; |
| 4291 | } |
| 4292 | |
| 4293 | static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) |
| 4294 | { |
| 4295 | uint16_t tmp; |
| 4296 | RTC_CRITICAL_SECTION_ENTER(); |
| 4297 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4298 | tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; |
| 4299 | tmp |= RTC_MODE2_CTRLA_MODE(data); |
| 4300 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4301 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4302 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4303 | } |
| 4304 | |
| 4305 | static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4306 | { |
| 4307 | RTC_CRITICAL_SECTION_ENTER(); |
| 4308 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); |
| 4309 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4310 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4311 | } |
| 4312 | |
| 4313 | static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4314 | { |
| 4315 | RTC_CRITICAL_SECTION_ENTER(); |
| 4316 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); |
| 4317 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4318 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4319 | } |
| 4320 | |
| 4321 | static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) |
| 4322 | { |
| 4323 | uint16_t tmp; |
| 4324 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4325 | tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; |
| 4326 | return tmp; |
| 4327 | } |
| 4328 | |
| 4329 | static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4330 | { |
| 4331 | RTC_CRITICAL_SECTION_ENTER(); |
| 4332 | ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); |
| 4333 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4334 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4335 | } |
| 4336 | |
| 4337 | static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, |
| 4338 | hri_rtcmode2_ctrla_reg_t mask) |
| 4339 | { |
| 4340 | uint16_t tmp; |
| 4341 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4342 | tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; |
| 4343 | return tmp; |
| 4344 | } |
| 4345 | |
| 4346 | static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) |
| 4347 | { |
| 4348 | uint16_t tmp; |
| 4349 | RTC_CRITICAL_SECTION_ENTER(); |
| 4350 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4351 | tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; |
| 4352 | tmp |= RTC_MODE2_CTRLA_PRESCALER(data); |
| 4353 | ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; |
| 4354 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4355 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4356 | } |
| 4357 | |
| 4358 | static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4359 | { |
| 4360 | RTC_CRITICAL_SECTION_ENTER(); |
| 4361 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); |
| 4362 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4363 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4364 | } |
| 4365 | |
| 4366 | static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4367 | { |
| 4368 | RTC_CRITICAL_SECTION_ENTER(); |
| 4369 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); |
| 4370 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 4371 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4372 | } |
| 4373 | |
| 4374 | static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) |
| 4375 | { |
| 4376 | uint16_t tmp; |
| 4377 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4378 | tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; |
| 4379 | return tmp; |
| 4380 | } |
| 4381 | |
| 4382 | static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4383 | { |
| 4384 | RTC_CRITICAL_SECTION_ENTER(); |
| 4385 | ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; |
| 4386 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4387 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4388 | } |
| 4389 | |
| 4390 | static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4391 | { |
| 4392 | uint16_t tmp; |
| 4393 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4394 | tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4395 | tmp &= mask; |
| 4396 | return tmp; |
| 4397 | } |
| 4398 | |
| 4399 | static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) |
| 4400 | { |
| 4401 | RTC_CRITICAL_SECTION_ENTER(); |
| 4402 | ((Rtc *)hw)->MODE2.CTRLA.reg = data; |
| 4403 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4404 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4405 | } |
| 4406 | |
| 4407 | static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4408 | { |
| 4409 | RTC_CRITICAL_SECTION_ENTER(); |
| 4410 | ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; |
| 4411 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4412 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4413 | } |
| 4414 | |
| 4415 | static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) |
| 4416 | { |
| 4417 | RTC_CRITICAL_SECTION_ENTER(); |
| 4418 | ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; |
| 4419 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4420 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4421 | } |
| 4422 | |
| 4423 | static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) |
| 4424 | { |
| 4425 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); |
| 4426 | return ((Rtc *)hw)->MODE2.CTRLA.reg; |
| 4427 | } |
| 4428 | |
| 4429 | static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) |
| 4430 | { |
| 4431 | RTC_CRITICAL_SECTION_ENTER(); |
| 4432 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; |
| 4433 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4434 | } |
| 4435 | |
| 4436 | static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) |
| 4437 | { |
| 4438 | uint16_t tmp; |
| 4439 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4440 | tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; |
| 4441 | return (bool)tmp; |
| 4442 | } |
| 4443 | |
| 4444 | static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) |
| 4445 | { |
| 4446 | uint16_t tmp; |
| 4447 | RTC_CRITICAL_SECTION_ENTER(); |
| 4448 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4449 | tmp &= ~RTC_MODE0_CTRLB_GP0EN; |
| 4450 | tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; |
| 4451 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4452 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4453 | } |
| 4454 | |
| 4455 | static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) |
| 4456 | { |
| 4457 | RTC_CRITICAL_SECTION_ENTER(); |
| 4458 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; |
| 4459 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4460 | } |
| 4461 | |
| 4462 | static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) |
| 4463 | { |
| 4464 | RTC_CRITICAL_SECTION_ENTER(); |
| 4465 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; |
| 4466 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4467 | } |
| 4468 | |
| 4469 | static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) |
| 4470 | { |
| 4471 | RTC_CRITICAL_SECTION_ENTER(); |
| 4472 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; |
| 4473 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4474 | } |
| 4475 | |
| 4476 | static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) |
| 4477 | { |
| 4478 | uint16_t tmp; |
| 4479 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4480 | tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; |
| 4481 | return (bool)tmp; |
| 4482 | } |
| 4483 | |
| 4484 | static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) |
| 4485 | { |
| 4486 | uint16_t tmp; |
| 4487 | RTC_CRITICAL_SECTION_ENTER(); |
| 4488 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4489 | tmp &= ~RTC_MODE0_CTRLB_GP2EN; |
| 4490 | tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; |
| 4491 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4492 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4493 | } |
| 4494 | |
| 4495 | static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) |
| 4496 | { |
| 4497 | RTC_CRITICAL_SECTION_ENTER(); |
| 4498 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; |
| 4499 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4500 | } |
| 4501 | |
| 4502 | static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) |
| 4503 | { |
| 4504 | RTC_CRITICAL_SECTION_ENTER(); |
| 4505 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; |
| 4506 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4507 | } |
| 4508 | |
| 4509 | static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4510 | { |
| 4511 | RTC_CRITICAL_SECTION_ENTER(); |
| 4512 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; |
| 4513 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4514 | } |
| 4515 | |
| 4516 | static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4517 | { |
| 4518 | uint16_t tmp; |
| 4519 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4520 | tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; |
| 4521 | return (bool)tmp; |
| 4522 | } |
| 4523 | |
| 4524 | static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) |
| 4525 | { |
| 4526 | uint16_t tmp; |
| 4527 | RTC_CRITICAL_SECTION_ENTER(); |
| 4528 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4529 | tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; |
| 4530 | tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; |
| 4531 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4532 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4533 | } |
| 4534 | |
| 4535 | static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4536 | { |
| 4537 | RTC_CRITICAL_SECTION_ENTER(); |
| 4538 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; |
| 4539 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4540 | } |
| 4541 | |
| 4542 | static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4543 | { |
| 4544 | RTC_CRITICAL_SECTION_ENTER(); |
| 4545 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; |
| 4546 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4547 | } |
| 4548 | |
| 4549 | static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4550 | { |
| 4551 | RTC_CRITICAL_SECTION_ENTER(); |
| 4552 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; |
| 4553 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4554 | } |
| 4555 | |
| 4556 | static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4557 | { |
| 4558 | uint16_t tmp; |
| 4559 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4560 | tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; |
| 4561 | return (bool)tmp; |
| 4562 | } |
| 4563 | |
| 4564 | static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) |
| 4565 | { |
| 4566 | uint16_t tmp; |
| 4567 | RTC_CRITICAL_SECTION_ENTER(); |
| 4568 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4569 | tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; |
| 4570 | tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; |
| 4571 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4572 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4573 | } |
| 4574 | |
| 4575 | static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4576 | { |
| 4577 | RTC_CRITICAL_SECTION_ENTER(); |
| 4578 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; |
| 4579 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4580 | } |
| 4581 | |
| 4582 | static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4583 | { |
| 4584 | RTC_CRITICAL_SECTION_ENTER(); |
| 4585 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; |
| 4586 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4587 | } |
| 4588 | |
| 4589 | static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) |
| 4590 | { |
| 4591 | RTC_CRITICAL_SECTION_ENTER(); |
| 4592 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; |
| 4593 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4594 | } |
| 4595 | |
| 4596 | static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) |
| 4597 | { |
| 4598 | uint16_t tmp; |
| 4599 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4600 | tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; |
| 4601 | return (bool)tmp; |
| 4602 | } |
| 4603 | |
| 4604 | static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) |
| 4605 | { |
| 4606 | uint16_t tmp; |
| 4607 | RTC_CRITICAL_SECTION_ENTER(); |
| 4608 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4609 | tmp &= ~RTC_MODE0_CTRLB_RTCOUT; |
| 4610 | tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; |
| 4611 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4612 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4613 | } |
| 4614 | |
| 4615 | static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) |
| 4616 | { |
| 4617 | RTC_CRITICAL_SECTION_ENTER(); |
| 4618 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; |
| 4619 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4620 | } |
| 4621 | |
| 4622 | static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) |
| 4623 | { |
| 4624 | RTC_CRITICAL_SECTION_ENTER(); |
| 4625 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; |
| 4626 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4627 | } |
| 4628 | |
| 4629 | static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) |
| 4630 | { |
| 4631 | RTC_CRITICAL_SECTION_ENTER(); |
| 4632 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; |
| 4633 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4634 | } |
| 4635 | |
| 4636 | static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) |
| 4637 | { |
| 4638 | uint16_t tmp; |
| 4639 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4640 | tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; |
| 4641 | return (bool)tmp; |
| 4642 | } |
| 4643 | |
| 4644 | static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) |
| 4645 | { |
| 4646 | uint16_t tmp; |
| 4647 | RTC_CRITICAL_SECTION_ENTER(); |
| 4648 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4649 | tmp &= ~RTC_MODE0_CTRLB_DMAEN; |
| 4650 | tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; |
| 4651 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4652 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4653 | } |
| 4654 | |
| 4655 | static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) |
| 4656 | { |
| 4657 | RTC_CRITICAL_SECTION_ENTER(); |
| 4658 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; |
| 4659 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4660 | } |
| 4661 | |
| 4662 | static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) |
| 4663 | { |
| 4664 | RTC_CRITICAL_SECTION_ENTER(); |
| 4665 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; |
| 4666 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4667 | } |
| 4668 | |
| 4669 | static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4670 | { |
| 4671 | RTC_CRITICAL_SECTION_ENTER(); |
| 4672 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); |
| 4673 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4674 | } |
| 4675 | |
| 4676 | static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, |
| 4677 | hri_rtcmode0_ctrlb_reg_t mask) |
| 4678 | { |
| 4679 | uint16_t tmp; |
| 4680 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4681 | tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; |
| 4682 | return tmp; |
| 4683 | } |
| 4684 | |
| 4685 | static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) |
| 4686 | { |
| 4687 | uint16_t tmp; |
| 4688 | RTC_CRITICAL_SECTION_ENTER(); |
| 4689 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4690 | tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; |
| 4691 | tmp |= RTC_MODE0_CTRLB_DEBF(data); |
| 4692 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4693 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4694 | } |
| 4695 | |
| 4696 | static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4697 | { |
| 4698 | RTC_CRITICAL_SECTION_ENTER(); |
| 4699 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); |
| 4700 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4701 | } |
| 4702 | |
| 4703 | static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4704 | { |
| 4705 | RTC_CRITICAL_SECTION_ENTER(); |
| 4706 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); |
| 4707 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4708 | } |
| 4709 | |
| 4710 | static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) |
| 4711 | { |
| 4712 | uint16_t tmp; |
| 4713 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4714 | tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; |
| 4715 | return tmp; |
| 4716 | } |
| 4717 | |
| 4718 | static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4719 | { |
| 4720 | RTC_CRITICAL_SECTION_ENTER(); |
| 4721 | ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); |
| 4722 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4723 | } |
| 4724 | |
| 4725 | static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, |
| 4726 | hri_rtcmode0_ctrlb_reg_t mask) |
| 4727 | { |
| 4728 | uint16_t tmp; |
| 4729 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4730 | tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; |
| 4731 | return tmp; |
| 4732 | } |
| 4733 | |
| 4734 | static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) |
| 4735 | { |
| 4736 | uint16_t tmp; |
| 4737 | RTC_CRITICAL_SECTION_ENTER(); |
| 4738 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4739 | tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; |
| 4740 | tmp |= RTC_MODE0_CTRLB_ACTF(data); |
| 4741 | ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; |
| 4742 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4743 | } |
| 4744 | |
| 4745 | static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4746 | { |
| 4747 | RTC_CRITICAL_SECTION_ENTER(); |
| 4748 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); |
| 4749 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4750 | } |
| 4751 | |
| 4752 | static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4753 | { |
| 4754 | RTC_CRITICAL_SECTION_ENTER(); |
| 4755 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); |
| 4756 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4757 | } |
| 4758 | |
| 4759 | static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) |
| 4760 | { |
| 4761 | uint16_t tmp; |
| 4762 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4763 | tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; |
| 4764 | return tmp; |
| 4765 | } |
| 4766 | |
| 4767 | static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4768 | { |
| 4769 | RTC_CRITICAL_SECTION_ENTER(); |
| 4770 | ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; |
| 4771 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4772 | } |
| 4773 | |
| 4774 | static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4775 | { |
| 4776 | uint16_t tmp; |
| 4777 | tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4778 | tmp &= mask; |
| 4779 | return tmp; |
| 4780 | } |
| 4781 | |
| 4782 | static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) |
| 4783 | { |
| 4784 | RTC_CRITICAL_SECTION_ENTER(); |
| 4785 | ((Rtc *)hw)->MODE0.CTRLB.reg = data; |
| 4786 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4787 | } |
| 4788 | |
| 4789 | static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4790 | { |
| 4791 | RTC_CRITICAL_SECTION_ENTER(); |
| 4792 | ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; |
| 4793 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4794 | } |
| 4795 | |
| 4796 | static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) |
| 4797 | { |
| 4798 | RTC_CRITICAL_SECTION_ENTER(); |
| 4799 | ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; |
| 4800 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4801 | } |
| 4802 | |
| 4803 | static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) |
| 4804 | { |
| 4805 | return ((Rtc *)hw)->MODE0.CTRLB.reg; |
| 4806 | } |
| 4807 | |
| 4808 | static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) |
| 4809 | { |
| 4810 | RTC_CRITICAL_SECTION_ENTER(); |
| 4811 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; |
| 4812 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4813 | } |
| 4814 | |
| 4815 | static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) |
| 4816 | { |
| 4817 | uint16_t tmp; |
| 4818 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4819 | tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; |
| 4820 | return (bool)tmp; |
| 4821 | } |
| 4822 | |
| 4823 | static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) |
| 4824 | { |
| 4825 | uint16_t tmp; |
| 4826 | RTC_CRITICAL_SECTION_ENTER(); |
| 4827 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4828 | tmp &= ~RTC_MODE1_CTRLB_GP0EN; |
| 4829 | tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; |
| 4830 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 4831 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4832 | } |
| 4833 | |
| 4834 | static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) |
| 4835 | { |
| 4836 | RTC_CRITICAL_SECTION_ENTER(); |
| 4837 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; |
| 4838 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4839 | } |
| 4840 | |
| 4841 | static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) |
| 4842 | { |
| 4843 | RTC_CRITICAL_SECTION_ENTER(); |
| 4844 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; |
| 4845 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4846 | } |
| 4847 | |
| 4848 | static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) |
| 4849 | { |
| 4850 | RTC_CRITICAL_SECTION_ENTER(); |
| 4851 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; |
| 4852 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4853 | } |
| 4854 | |
| 4855 | static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) |
| 4856 | { |
| 4857 | uint16_t tmp; |
| 4858 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4859 | tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; |
| 4860 | return (bool)tmp; |
| 4861 | } |
| 4862 | |
| 4863 | static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) |
| 4864 | { |
| 4865 | uint16_t tmp; |
| 4866 | RTC_CRITICAL_SECTION_ENTER(); |
| 4867 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4868 | tmp &= ~RTC_MODE1_CTRLB_GP2EN; |
| 4869 | tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; |
| 4870 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 4871 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4872 | } |
| 4873 | |
| 4874 | static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) |
| 4875 | { |
| 4876 | RTC_CRITICAL_SECTION_ENTER(); |
| 4877 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; |
| 4878 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4879 | } |
| 4880 | |
| 4881 | static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) |
| 4882 | { |
| 4883 | RTC_CRITICAL_SECTION_ENTER(); |
| 4884 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; |
| 4885 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4886 | } |
| 4887 | |
| 4888 | static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4889 | { |
| 4890 | RTC_CRITICAL_SECTION_ENTER(); |
| 4891 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; |
| 4892 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4893 | } |
| 4894 | |
| 4895 | static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4896 | { |
| 4897 | uint16_t tmp; |
| 4898 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4899 | tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; |
| 4900 | return (bool)tmp; |
| 4901 | } |
| 4902 | |
| 4903 | static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) |
| 4904 | { |
| 4905 | uint16_t tmp; |
| 4906 | RTC_CRITICAL_SECTION_ENTER(); |
| 4907 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4908 | tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; |
| 4909 | tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; |
| 4910 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 4911 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4912 | } |
| 4913 | |
| 4914 | static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4915 | { |
| 4916 | RTC_CRITICAL_SECTION_ENTER(); |
| 4917 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; |
| 4918 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4919 | } |
| 4920 | |
| 4921 | static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) |
| 4922 | { |
| 4923 | RTC_CRITICAL_SECTION_ENTER(); |
| 4924 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; |
| 4925 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4926 | } |
| 4927 | |
| 4928 | static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4929 | { |
| 4930 | RTC_CRITICAL_SECTION_ENTER(); |
| 4931 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; |
| 4932 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4933 | } |
| 4934 | |
| 4935 | static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4936 | { |
| 4937 | uint16_t tmp; |
| 4938 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4939 | tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; |
| 4940 | return (bool)tmp; |
| 4941 | } |
| 4942 | |
| 4943 | static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) |
| 4944 | { |
| 4945 | uint16_t tmp; |
| 4946 | RTC_CRITICAL_SECTION_ENTER(); |
| 4947 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4948 | tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; |
| 4949 | tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; |
| 4950 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 4951 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4952 | } |
| 4953 | |
| 4954 | static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4955 | { |
| 4956 | RTC_CRITICAL_SECTION_ENTER(); |
| 4957 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; |
| 4958 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4959 | } |
| 4960 | |
| 4961 | static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) |
| 4962 | { |
| 4963 | RTC_CRITICAL_SECTION_ENTER(); |
| 4964 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; |
| 4965 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4966 | } |
| 4967 | |
| 4968 | static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) |
| 4969 | { |
| 4970 | RTC_CRITICAL_SECTION_ENTER(); |
| 4971 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; |
| 4972 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4973 | } |
| 4974 | |
| 4975 | static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) |
| 4976 | { |
| 4977 | uint16_t tmp; |
| 4978 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4979 | tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; |
| 4980 | return (bool)tmp; |
| 4981 | } |
| 4982 | |
| 4983 | static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) |
| 4984 | { |
| 4985 | uint16_t tmp; |
| 4986 | RTC_CRITICAL_SECTION_ENTER(); |
| 4987 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 4988 | tmp &= ~RTC_MODE1_CTRLB_RTCOUT; |
| 4989 | tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; |
| 4990 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 4991 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4992 | } |
| 4993 | |
| 4994 | static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) |
| 4995 | { |
| 4996 | RTC_CRITICAL_SECTION_ENTER(); |
| 4997 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; |
| 4998 | RTC_CRITICAL_SECTION_LEAVE(); |
| 4999 | } |
| 5000 | |
| 5001 | static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) |
| 5002 | { |
| 5003 | RTC_CRITICAL_SECTION_ENTER(); |
| 5004 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; |
| 5005 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5006 | } |
| 5007 | |
| 5008 | static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) |
| 5009 | { |
| 5010 | RTC_CRITICAL_SECTION_ENTER(); |
| 5011 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; |
| 5012 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5013 | } |
| 5014 | |
| 5015 | static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) |
| 5016 | { |
| 5017 | uint16_t tmp; |
| 5018 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5019 | tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; |
| 5020 | return (bool)tmp; |
| 5021 | } |
| 5022 | |
| 5023 | static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) |
| 5024 | { |
| 5025 | uint16_t tmp; |
| 5026 | RTC_CRITICAL_SECTION_ENTER(); |
| 5027 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5028 | tmp &= ~RTC_MODE1_CTRLB_DMAEN; |
| 5029 | tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; |
| 5030 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 5031 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5032 | } |
| 5033 | |
| 5034 | static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) |
| 5035 | { |
| 5036 | RTC_CRITICAL_SECTION_ENTER(); |
| 5037 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; |
| 5038 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5039 | } |
| 5040 | |
| 5041 | static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) |
| 5042 | { |
| 5043 | RTC_CRITICAL_SECTION_ENTER(); |
| 5044 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; |
| 5045 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5046 | } |
| 5047 | |
| 5048 | static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5049 | { |
| 5050 | RTC_CRITICAL_SECTION_ENTER(); |
| 5051 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); |
| 5052 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5053 | } |
| 5054 | |
| 5055 | static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, |
| 5056 | hri_rtcmode1_ctrlb_reg_t mask) |
| 5057 | { |
| 5058 | uint16_t tmp; |
| 5059 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5060 | tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; |
| 5061 | return tmp; |
| 5062 | } |
| 5063 | |
| 5064 | static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) |
| 5065 | { |
| 5066 | uint16_t tmp; |
| 5067 | RTC_CRITICAL_SECTION_ENTER(); |
| 5068 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5069 | tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; |
| 5070 | tmp |= RTC_MODE1_CTRLB_DEBF(data); |
| 5071 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 5072 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5073 | } |
| 5074 | |
| 5075 | static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5076 | { |
| 5077 | RTC_CRITICAL_SECTION_ENTER(); |
| 5078 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); |
| 5079 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5080 | } |
| 5081 | |
| 5082 | static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5083 | { |
| 5084 | RTC_CRITICAL_SECTION_ENTER(); |
| 5085 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); |
| 5086 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5087 | } |
| 5088 | |
| 5089 | static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) |
| 5090 | { |
| 5091 | uint16_t tmp; |
| 5092 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5093 | tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; |
| 5094 | return tmp; |
| 5095 | } |
| 5096 | |
| 5097 | static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5098 | { |
| 5099 | RTC_CRITICAL_SECTION_ENTER(); |
| 5100 | ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); |
| 5101 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5102 | } |
| 5103 | |
| 5104 | static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, |
| 5105 | hri_rtcmode1_ctrlb_reg_t mask) |
| 5106 | { |
| 5107 | uint16_t tmp; |
| 5108 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5109 | tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; |
| 5110 | return tmp; |
| 5111 | } |
| 5112 | |
| 5113 | static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) |
| 5114 | { |
| 5115 | uint16_t tmp; |
| 5116 | RTC_CRITICAL_SECTION_ENTER(); |
| 5117 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5118 | tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; |
| 5119 | tmp |= RTC_MODE1_CTRLB_ACTF(data); |
| 5120 | ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; |
| 5121 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5122 | } |
| 5123 | |
| 5124 | static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5125 | { |
| 5126 | RTC_CRITICAL_SECTION_ENTER(); |
| 5127 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); |
| 5128 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5129 | } |
| 5130 | |
| 5131 | static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5132 | { |
| 5133 | RTC_CRITICAL_SECTION_ENTER(); |
| 5134 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); |
| 5135 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5136 | } |
| 5137 | |
| 5138 | static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) |
| 5139 | { |
| 5140 | uint16_t tmp; |
| 5141 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5142 | tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; |
| 5143 | return tmp; |
| 5144 | } |
| 5145 | |
| 5146 | static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5147 | { |
| 5148 | RTC_CRITICAL_SECTION_ENTER(); |
| 5149 | ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; |
| 5150 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5151 | } |
| 5152 | |
| 5153 | static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5154 | { |
| 5155 | uint16_t tmp; |
| 5156 | tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5157 | tmp &= mask; |
| 5158 | return tmp; |
| 5159 | } |
| 5160 | |
| 5161 | static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) |
| 5162 | { |
| 5163 | RTC_CRITICAL_SECTION_ENTER(); |
| 5164 | ((Rtc *)hw)->MODE1.CTRLB.reg = data; |
| 5165 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5166 | } |
| 5167 | |
| 5168 | static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5169 | { |
| 5170 | RTC_CRITICAL_SECTION_ENTER(); |
| 5171 | ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; |
| 5172 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5173 | } |
| 5174 | |
| 5175 | static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) |
| 5176 | { |
| 5177 | RTC_CRITICAL_SECTION_ENTER(); |
| 5178 | ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; |
| 5179 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5180 | } |
| 5181 | |
| 5182 | static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) |
| 5183 | { |
| 5184 | return ((Rtc *)hw)->MODE1.CTRLB.reg; |
| 5185 | } |
| 5186 | |
| 5187 | static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) |
| 5188 | { |
| 5189 | RTC_CRITICAL_SECTION_ENTER(); |
| 5190 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; |
| 5191 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5192 | } |
| 5193 | |
| 5194 | static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) |
| 5195 | { |
| 5196 | uint16_t tmp; |
| 5197 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5198 | tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; |
| 5199 | return (bool)tmp; |
| 5200 | } |
| 5201 | |
| 5202 | static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) |
| 5203 | { |
| 5204 | uint16_t tmp; |
| 5205 | RTC_CRITICAL_SECTION_ENTER(); |
| 5206 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5207 | tmp &= ~RTC_MODE2_CTRLB_GP0EN; |
| 5208 | tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; |
| 5209 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5210 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5211 | } |
| 5212 | |
| 5213 | static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) |
| 5214 | { |
| 5215 | RTC_CRITICAL_SECTION_ENTER(); |
| 5216 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; |
| 5217 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5218 | } |
| 5219 | |
| 5220 | static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) |
| 5221 | { |
| 5222 | RTC_CRITICAL_SECTION_ENTER(); |
| 5223 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; |
| 5224 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5225 | } |
| 5226 | |
| 5227 | static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) |
| 5228 | { |
| 5229 | RTC_CRITICAL_SECTION_ENTER(); |
| 5230 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; |
| 5231 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5232 | } |
| 5233 | |
| 5234 | static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) |
| 5235 | { |
| 5236 | uint16_t tmp; |
| 5237 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5238 | tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; |
| 5239 | return (bool)tmp; |
| 5240 | } |
| 5241 | |
| 5242 | static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) |
| 5243 | { |
| 5244 | uint16_t tmp; |
| 5245 | RTC_CRITICAL_SECTION_ENTER(); |
| 5246 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5247 | tmp &= ~RTC_MODE2_CTRLB_GP2EN; |
| 5248 | tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; |
| 5249 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5250 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5251 | } |
| 5252 | |
| 5253 | static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) |
| 5254 | { |
| 5255 | RTC_CRITICAL_SECTION_ENTER(); |
| 5256 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; |
| 5257 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5258 | } |
| 5259 | |
| 5260 | static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) |
| 5261 | { |
| 5262 | RTC_CRITICAL_SECTION_ENTER(); |
| 5263 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; |
| 5264 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5265 | } |
| 5266 | |
| 5267 | static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) |
| 5268 | { |
| 5269 | RTC_CRITICAL_SECTION_ENTER(); |
| 5270 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; |
| 5271 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5272 | } |
| 5273 | |
| 5274 | static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) |
| 5275 | { |
| 5276 | uint16_t tmp; |
| 5277 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5278 | tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; |
| 5279 | return (bool)tmp; |
| 5280 | } |
| 5281 | |
| 5282 | static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) |
| 5283 | { |
| 5284 | uint16_t tmp; |
| 5285 | RTC_CRITICAL_SECTION_ENTER(); |
| 5286 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5287 | tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; |
| 5288 | tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; |
| 5289 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5290 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5291 | } |
| 5292 | |
| 5293 | static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) |
| 5294 | { |
| 5295 | RTC_CRITICAL_SECTION_ENTER(); |
| 5296 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; |
| 5297 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5298 | } |
| 5299 | |
| 5300 | static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) |
| 5301 | { |
| 5302 | RTC_CRITICAL_SECTION_ENTER(); |
| 5303 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; |
| 5304 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5305 | } |
| 5306 | |
| 5307 | static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) |
| 5308 | { |
| 5309 | RTC_CRITICAL_SECTION_ENTER(); |
| 5310 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; |
| 5311 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5312 | } |
| 5313 | |
| 5314 | static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) |
| 5315 | { |
| 5316 | uint16_t tmp; |
| 5317 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5318 | tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; |
| 5319 | return (bool)tmp; |
| 5320 | } |
| 5321 | |
| 5322 | static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) |
| 5323 | { |
| 5324 | uint16_t tmp; |
| 5325 | RTC_CRITICAL_SECTION_ENTER(); |
| 5326 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5327 | tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; |
| 5328 | tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; |
| 5329 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5330 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5331 | } |
| 5332 | |
| 5333 | static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) |
| 5334 | { |
| 5335 | RTC_CRITICAL_SECTION_ENTER(); |
| 5336 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; |
| 5337 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5338 | } |
| 5339 | |
| 5340 | static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) |
| 5341 | { |
| 5342 | RTC_CRITICAL_SECTION_ENTER(); |
| 5343 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; |
| 5344 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5345 | } |
| 5346 | |
| 5347 | static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) |
| 5348 | { |
| 5349 | RTC_CRITICAL_SECTION_ENTER(); |
| 5350 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; |
| 5351 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5352 | } |
| 5353 | |
| 5354 | static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) |
| 5355 | { |
| 5356 | uint16_t tmp; |
| 5357 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5358 | tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; |
| 5359 | return (bool)tmp; |
| 5360 | } |
| 5361 | |
| 5362 | static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) |
| 5363 | { |
| 5364 | uint16_t tmp; |
| 5365 | RTC_CRITICAL_SECTION_ENTER(); |
| 5366 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5367 | tmp &= ~RTC_MODE2_CTRLB_RTCOUT; |
| 5368 | tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; |
| 5369 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5370 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5371 | } |
| 5372 | |
| 5373 | static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) |
| 5374 | { |
| 5375 | RTC_CRITICAL_SECTION_ENTER(); |
| 5376 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; |
| 5377 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5378 | } |
| 5379 | |
| 5380 | static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) |
| 5381 | { |
| 5382 | RTC_CRITICAL_SECTION_ENTER(); |
| 5383 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; |
| 5384 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5385 | } |
| 5386 | |
| 5387 | static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) |
| 5388 | { |
| 5389 | RTC_CRITICAL_SECTION_ENTER(); |
| 5390 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; |
| 5391 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5392 | } |
| 5393 | |
| 5394 | static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) |
| 5395 | { |
| 5396 | uint16_t tmp; |
| 5397 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5398 | tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; |
| 5399 | return (bool)tmp; |
| 5400 | } |
| 5401 | |
| 5402 | static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) |
| 5403 | { |
| 5404 | uint16_t tmp; |
| 5405 | RTC_CRITICAL_SECTION_ENTER(); |
| 5406 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5407 | tmp &= ~RTC_MODE2_CTRLB_DMAEN; |
| 5408 | tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; |
| 5409 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5410 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5411 | } |
| 5412 | |
| 5413 | static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) |
| 5414 | { |
| 5415 | RTC_CRITICAL_SECTION_ENTER(); |
| 5416 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; |
| 5417 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5418 | } |
| 5419 | |
| 5420 | static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) |
| 5421 | { |
| 5422 | RTC_CRITICAL_SECTION_ENTER(); |
| 5423 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; |
| 5424 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5425 | } |
| 5426 | |
| 5427 | static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5428 | { |
| 5429 | RTC_CRITICAL_SECTION_ENTER(); |
| 5430 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); |
| 5431 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5432 | } |
| 5433 | |
| 5434 | static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, |
| 5435 | hri_rtcmode2_ctrlb_reg_t mask) |
| 5436 | { |
| 5437 | uint16_t tmp; |
| 5438 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5439 | tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; |
| 5440 | return tmp; |
| 5441 | } |
| 5442 | |
| 5443 | static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) |
| 5444 | { |
| 5445 | uint16_t tmp; |
| 5446 | RTC_CRITICAL_SECTION_ENTER(); |
| 5447 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5448 | tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; |
| 5449 | tmp |= RTC_MODE2_CTRLB_DEBF(data); |
| 5450 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5451 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5452 | } |
| 5453 | |
| 5454 | static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5455 | { |
| 5456 | RTC_CRITICAL_SECTION_ENTER(); |
| 5457 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); |
| 5458 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5459 | } |
| 5460 | |
| 5461 | static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5462 | { |
| 5463 | RTC_CRITICAL_SECTION_ENTER(); |
| 5464 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); |
| 5465 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5466 | } |
| 5467 | |
| 5468 | static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) |
| 5469 | { |
| 5470 | uint16_t tmp; |
| 5471 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5472 | tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; |
| 5473 | return tmp; |
| 5474 | } |
| 5475 | |
| 5476 | static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5477 | { |
| 5478 | RTC_CRITICAL_SECTION_ENTER(); |
| 5479 | ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); |
| 5480 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5481 | } |
| 5482 | |
| 5483 | static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, |
| 5484 | hri_rtcmode2_ctrlb_reg_t mask) |
| 5485 | { |
| 5486 | uint16_t tmp; |
| 5487 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5488 | tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; |
| 5489 | return tmp; |
| 5490 | } |
| 5491 | |
| 5492 | static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) |
| 5493 | { |
| 5494 | uint16_t tmp; |
| 5495 | RTC_CRITICAL_SECTION_ENTER(); |
| 5496 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5497 | tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; |
| 5498 | tmp |= RTC_MODE2_CTRLB_ACTF(data); |
| 5499 | ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; |
| 5500 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5501 | } |
| 5502 | |
| 5503 | static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5504 | { |
| 5505 | RTC_CRITICAL_SECTION_ENTER(); |
| 5506 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); |
| 5507 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5508 | } |
| 5509 | |
| 5510 | static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5511 | { |
| 5512 | RTC_CRITICAL_SECTION_ENTER(); |
| 5513 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); |
| 5514 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5515 | } |
| 5516 | |
| 5517 | static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) |
| 5518 | { |
| 5519 | uint16_t tmp; |
| 5520 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5521 | tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; |
| 5522 | return tmp; |
| 5523 | } |
| 5524 | |
| 5525 | static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5526 | { |
| 5527 | RTC_CRITICAL_SECTION_ENTER(); |
| 5528 | ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; |
| 5529 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5530 | } |
| 5531 | |
| 5532 | static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5533 | { |
| 5534 | uint16_t tmp; |
| 5535 | tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5536 | tmp &= mask; |
| 5537 | return tmp; |
| 5538 | } |
| 5539 | |
| 5540 | static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) |
| 5541 | { |
| 5542 | RTC_CRITICAL_SECTION_ENTER(); |
| 5543 | ((Rtc *)hw)->MODE2.CTRLB.reg = data; |
| 5544 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5545 | } |
| 5546 | |
| 5547 | static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5548 | { |
| 5549 | RTC_CRITICAL_SECTION_ENTER(); |
| 5550 | ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; |
| 5551 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5552 | } |
| 5553 | |
| 5554 | static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) |
| 5555 | { |
| 5556 | RTC_CRITICAL_SECTION_ENTER(); |
| 5557 | ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; |
| 5558 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5559 | } |
| 5560 | |
| 5561 | static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) |
| 5562 | { |
| 5563 | return ((Rtc *)hw)->MODE2.CTRLB.reg; |
| 5564 | } |
| 5565 | |
| 5566 | static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) |
| 5567 | { |
| 5568 | RTC_CRITICAL_SECTION_ENTER(); |
| 5569 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; |
| 5570 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5571 | } |
| 5572 | |
| 5573 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) |
| 5574 | { |
| 5575 | uint32_t tmp; |
| 5576 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5577 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; |
| 5578 | return (bool)tmp; |
| 5579 | } |
| 5580 | |
| 5581 | static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) |
| 5582 | { |
| 5583 | uint32_t tmp; |
| 5584 | RTC_CRITICAL_SECTION_ENTER(); |
| 5585 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5586 | tmp &= ~RTC_MODE0_EVCTRL_PEREO0; |
| 5587 | tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; |
| 5588 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5589 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5590 | } |
| 5591 | |
| 5592 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) |
| 5593 | { |
| 5594 | RTC_CRITICAL_SECTION_ENTER(); |
| 5595 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; |
| 5596 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5597 | } |
| 5598 | |
| 5599 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) |
| 5600 | { |
| 5601 | RTC_CRITICAL_SECTION_ENTER(); |
| 5602 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; |
| 5603 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5604 | } |
| 5605 | |
| 5606 | static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) |
| 5607 | { |
| 5608 | RTC_CRITICAL_SECTION_ENTER(); |
| 5609 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; |
| 5610 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5611 | } |
| 5612 | |
| 5613 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) |
| 5614 | { |
| 5615 | uint32_t tmp; |
| 5616 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5617 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; |
| 5618 | return (bool)tmp; |
| 5619 | } |
| 5620 | |
| 5621 | static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) |
| 5622 | { |
| 5623 | uint32_t tmp; |
| 5624 | RTC_CRITICAL_SECTION_ENTER(); |
| 5625 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5626 | tmp &= ~RTC_MODE0_EVCTRL_PEREO1; |
| 5627 | tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; |
| 5628 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5629 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5630 | } |
| 5631 | |
| 5632 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) |
| 5633 | { |
| 5634 | RTC_CRITICAL_SECTION_ENTER(); |
| 5635 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; |
| 5636 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5637 | } |
| 5638 | |
| 5639 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) |
| 5640 | { |
| 5641 | RTC_CRITICAL_SECTION_ENTER(); |
| 5642 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; |
| 5643 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5644 | } |
| 5645 | |
| 5646 | static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) |
| 5647 | { |
| 5648 | RTC_CRITICAL_SECTION_ENTER(); |
| 5649 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; |
| 5650 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5651 | } |
| 5652 | |
| 5653 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) |
| 5654 | { |
| 5655 | uint32_t tmp; |
| 5656 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5657 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; |
| 5658 | return (bool)tmp; |
| 5659 | } |
| 5660 | |
| 5661 | static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) |
| 5662 | { |
| 5663 | uint32_t tmp; |
| 5664 | RTC_CRITICAL_SECTION_ENTER(); |
| 5665 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5666 | tmp &= ~RTC_MODE0_EVCTRL_PEREO2; |
| 5667 | tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; |
| 5668 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5669 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5670 | } |
| 5671 | |
| 5672 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) |
| 5673 | { |
| 5674 | RTC_CRITICAL_SECTION_ENTER(); |
| 5675 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; |
| 5676 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5677 | } |
| 5678 | |
| 5679 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) |
| 5680 | { |
| 5681 | RTC_CRITICAL_SECTION_ENTER(); |
| 5682 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; |
| 5683 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5684 | } |
| 5685 | |
| 5686 | static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) |
| 5687 | { |
| 5688 | RTC_CRITICAL_SECTION_ENTER(); |
| 5689 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; |
| 5690 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5691 | } |
| 5692 | |
| 5693 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) |
| 5694 | { |
| 5695 | uint32_t tmp; |
| 5696 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5697 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; |
| 5698 | return (bool)tmp; |
| 5699 | } |
| 5700 | |
| 5701 | static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) |
| 5702 | { |
| 5703 | uint32_t tmp; |
| 5704 | RTC_CRITICAL_SECTION_ENTER(); |
| 5705 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5706 | tmp &= ~RTC_MODE0_EVCTRL_PEREO3; |
| 5707 | tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; |
| 5708 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5709 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5710 | } |
| 5711 | |
| 5712 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) |
| 5713 | { |
| 5714 | RTC_CRITICAL_SECTION_ENTER(); |
| 5715 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; |
| 5716 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5717 | } |
| 5718 | |
| 5719 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) |
| 5720 | { |
| 5721 | RTC_CRITICAL_SECTION_ENTER(); |
| 5722 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; |
| 5723 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5724 | } |
| 5725 | |
| 5726 | static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) |
| 5727 | { |
| 5728 | RTC_CRITICAL_SECTION_ENTER(); |
| 5729 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; |
| 5730 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5731 | } |
| 5732 | |
| 5733 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) |
| 5734 | { |
| 5735 | uint32_t tmp; |
| 5736 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5737 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; |
| 5738 | return (bool)tmp; |
| 5739 | } |
| 5740 | |
| 5741 | static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) |
| 5742 | { |
| 5743 | uint32_t tmp; |
| 5744 | RTC_CRITICAL_SECTION_ENTER(); |
| 5745 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5746 | tmp &= ~RTC_MODE0_EVCTRL_PEREO4; |
| 5747 | tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; |
| 5748 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5749 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5750 | } |
| 5751 | |
| 5752 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) |
| 5753 | { |
| 5754 | RTC_CRITICAL_SECTION_ENTER(); |
| 5755 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; |
| 5756 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5757 | } |
| 5758 | |
| 5759 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) |
| 5760 | { |
| 5761 | RTC_CRITICAL_SECTION_ENTER(); |
| 5762 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; |
| 5763 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5764 | } |
| 5765 | |
| 5766 | static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) |
| 5767 | { |
| 5768 | RTC_CRITICAL_SECTION_ENTER(); |
| 5769 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; |
| 5770 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5771 | } |
| 5772 | |
| 5773 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) |
| 5774 | { |
| 5775 | uint32_t tmp; |
| 5776 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5777 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; |
| 5778 | return (bool)tmp; |
| 5779 | } |
| 5780 | |
| 5781 | static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) |
| 5782 | { |
| 5783 | uint32_t tmp; |
| 5784 | RTC_CRITICAL_SECTION_ENTER(); |
| 5785 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5786 | tmp &= ~RTC_MODE0_EVCTRL_PEREO5; |
| 5787 | tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; |
| 5788 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5789 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5790 | } |
| 5791 | |
| 5792 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) |
| 5793 | { |
| 5794 | RTC_CRITICAL_SECTION_ENTER(); |
| 5795 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; |
| 5796 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5797 | } |
| 5798 | |
| 5799 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) |
| 5800 | { |
| 5801 | RTC_CRITICAL_SECTION_ENTER(); |
| 5802 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; |
| 5803 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5804 | } |
| 5805 | |
| 5806 | static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) |
| 5807 | { |
| 5808 | RTC_CRITICAL_SECTION_ENTER(); |
| 5809 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; |
| 5810 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5811 | } |
| 5812 | |
| 5813 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) |
| 5814 | { |
| 5815 | uint32_t tmp; |
| 5816 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5817 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; |
| 5818 | return (bool)tmp; |
| 5819 | } |
| 5820 | |
| 5821 | static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) |
| 5822 | { |
| 5823 | uint32_t tmp; |
| 5824 | RTC_CRITICAL_SECTION_ENTER(); |
| 5825 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5826 | tmp &= ~RTC_MODE0_EVCTRL_PEREO6; |
| 5827 | tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; |
| 5828 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5829 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5830 | } |
| 5831 | |
| 5832 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) |
| 5833 | { |
| 5834 | RTC_CRITICAL_SECTION_ENTER(); |
| 5835 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; |
| 5836 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5837 | } |
| 5838 | |
| 5839 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) |
| 5840 | { |
| 5841 | RTC_CRITICAL_SECTION_ENTER(); |
| 5842 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; |
| 5843 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5844 | } |
| 5845 | |
| 5846 | static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) |
| 5847 | { |
| 5848 | RTC_CRITICAL_SECTION_ENTER(); |
| 5849 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; |
| 5850 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5851 | } |
| 5852 | |
| 5853 | static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) |
| 5854 | { |
| 5855 | uint32_t tmp; |
| 5856 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5857 | tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; |
| 5858 | return (bool)tmp; |
| 5859 | } |
| 5860 | |
| 5861 | static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) |
| 5862 | { |
| 5863 | uint32_t tmp; |
| 5864 | RTC_CRITICAL_SECTION_ENTER(); |
| 5865 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5866 | tmp &= ~RTC_MODE0_EVCTRL_PEREO7; |
| 5867 | tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; |
| 5868 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5869 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5870 | } |
| 5871 | |
| 5872 | static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) |
| 5873 | { |
| 5874 | RTC_CRITICAL_SECTION_ENTER(); |
| 5875 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; |
| 5876 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5877 | } |
| 5878 | |
| 5879 | static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) |
| 5880 | { |
| 5881 | RTC_CRITICAL_SECTION_ENTER(); |
| 5882 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; |
| 5883 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5884 | } |
| 5885 | |
| 5886 | static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) |
| 5887 | { |
| 5888 | RTC_CRITICAL_SECTION_ENTER(); |
| 5889 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; |
| 5890 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5891 | } |
| 5892 | |
| 5893 | static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) |
| 5894 | { |
| 5895 | uint32_t tmp; |
| 5896 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5897 | tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; |
| 5898 | return (bool)tmp; |
| 5899 | } |
| 5900 | |
| 5901 | static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) |
| 5902 | { |
| 5903 | uint32_t tmp; |
| 5904 | RTC_CRITICAL_SECTION_ENTER(); |
| 5905 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5906 | tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; |
| 5907 | tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; |
| 5908 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5909 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5910 | } |
| 5911 | |
| 5912 | static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) |
| 5913 | { |
| 5914 | RTC_CRITICAL_SECTION_ENTER(); |
| 5915 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; |
| 5916 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5917 | } |
| 5918 | |
| 5919 | static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) |
| 5920 | { |
| 5921 | RTC_CRITICAL_SECTION_ENTER(); |
| 5922 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; |
| 5923 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5924 | } |
| 5925 | |
| 5926 | static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) |
| 5927 | { |
| 5928 | RTC_CRITICAL_SECTION_ENTER(); |
| 5929 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; |
| 5930 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5931 | } |
| 5932 | |
| 5933 | static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) |
| 5934 | { |
| 5935 | uint32_t tmp; |
| 5936 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5937 | tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; |
| 5938 | return (bool)tmp; |
| 5939 | } |
| 5940 | |
| 5941 | static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) |
| 5942 | { |
| 5943 | uint32_t tmp; |
| 5944 | RTC_CRITICAL_SECTION_ENTER(); |
| 5945 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5946 | tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; |
| 5947 | tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; |
| 5948 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5949 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5950 | } |
| 5951 | |
| 5952 | static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) |
| 5953 | { |
| 5954 | RTC_CRITICAL_SECTION_ENTER(); |
| 5955 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; |
| 5956 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5957 | } |
| 5958 | |
| 5959 | static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) |
| 5960 | { |
| 5961 | RTC_CRITICAL_SECTION_ENTER(); |
| 5962 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; |
| 5963 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5964 | } |
| 5965 | |
| 5966 | static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 5967 | { |
| 5968 | RTC_CRITICAL_SECTION_ENTER(); |
| 5969 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; |
| 5970 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5971 | } |
| 5972 | |
| 5973 | static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 5974 | { |
| 5975 | uint32_t tmp; |
| 5976 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5977 | tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; |
| 5978 | return (bool)tmp; |
| 5979 | } |
| 5980 | |
| 5981 | static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) |
| 5982 | { |
| 5983 | uint32_t tmp; |
| 5984 | RTC_CRITICAL_SECTION_ENTER(); |
| 5985 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 5986 | tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; |
| 5987 | tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; |
| 5988 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 5989 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5990 | } |
| 5991 | |
| 5992 | static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 5993 | { |
| 5994 | RTC_CRITICAL_SECTION_ENTER(); |
| 5995 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; |
| 5996 | RTC_CRITICAL_SECTION_LEAVE(); |
| 5997 | } |
| 5998 | |
| 5999 | static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 6000 | { |
| 6001 | RTC_CRITICAL_SECTION_ENTER(); |
| 6002 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; |
| 6003 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6004 | } |
| 6005 | |
| 6006 | static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) |
| 6007 | { |
| 6008 | RTC_CRITICAL_SECTION_ENTER(); |
| 6009 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; |
| 6010 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6011 | } |
| 6012 | |
| 6013 | static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) |
| 6014 | { |
| 6015 | uint32_t tmp; |
| 6016 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 6017 | tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; |
| 6018 | return (bool)tmp; |
| 6019 | } |
| 6020 | |
| 6021 | static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) |
| 6022 | { |
| 6023 | uint32_t tmp; |
| 6024 | RTC_CRITICAL_SECTION_ENTER(); |
| 6025 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 6026 | tmp &= ~RTC_MODE0_EVCTRL_OVFEO; |
| 6027 | tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; |
| 6028 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 6029 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6030 | } |
| 6031 | |
| 6032 | static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) |
| 6033 | { |
| 6034 | RTC_CRITICAL_SECTION_ENTER(); |
| 6035 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; |
| 6036 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6037 | } |
| 6038 | |
| 6039 | static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) |
| 6040 | { |
| 6041 | RTC_CRITICAL_SECTION_ENTER(); |
| 6042 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; |
| 6043 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6044 | } |
| 6045 | |
| 6046 | static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6047 | { |
| 6048 | RTC_CRITICAL_SECTION_ENTER(); |
| 6049 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; |
| 6050 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6051 | } |
| 6052 | |
| 6053 | static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6054 | { |
| 6055 | uint32_t tmp; |
| 6056 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 6057 | tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; |
| 6058 | return (bool)tmp; |
| 6059 | } |
| 6060 | |
| 6061 | static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) |
| 6062 | { |
| 6063 | uint32_t tmp; |
| 6064 | RTC_CRITICAL_SECTION_ENTER(); |
| 6065 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 6066 | tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; |
| 6067 | tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; |
| 6068 | ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; |
| 6069 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6070 | } |
| 6071 | |
| 6072 | static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6073 | { |
| 6074 | RTC_CRITICAL_SECTION_ENTER(); |
| 6075 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; |
| 6076 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6077 | } |
| 6078 | |
| 6079 | static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6080 | { |
| 6081 | RTC_CRITICAL_SECTION_ENTER(); |
| 6082 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; |
| 6083 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6084 | } |
| 6085 | |
| 6086 | static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) |
| 6087 | { |
| 6088 | RTC_CRITICAL_SECTION_ENTER(); |
| 6089 | ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; |
| 6090 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6091 | } |
| 6092 | |
| 6093 | static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, |
| 6094 | hri_rtcmode0_evctrl_reg_t mask) |
| 6095 | { |
| 6096 | uint32_t tmp; |
| 6097 | tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 6098 | tmp &= mask; |
| 6099 | return tmp; |
| 6100 | } |
| 6101 | |
| 6102 | static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) |
| 6103 | { |
| 6104 | RTC_CRITICAL_SECTION_ENTER(); |
| 6105 | ((Rtc *)hw)->MODE0.EVCTRL.reg = data; |
| 6106 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6107 | } |
| 6108 | |
| 6109 | static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) |
| 6110 | { |
| 6111 | RTC_CRITICAL_SECTION_ENTER(); |
| 6112 | ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; |
| 6113 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6114 | } |
| 6115 | |
| 6116 | static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) |
| 6117 | { |
| 6118 | RTC_CRITICAL_SECTION_ENTER(); |
| 6119 | ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; |
| 6120 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6121 | } |
| 6122 | |
| 6123 | static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) |
| 6124 | { |
| 6125 | return ((Rtc *)hw)->MODE0.EVCTRL.reg; |
| 6126 | } |
| 6127 | |
| 6128 | static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) |
| 6129 | { |
| 6130 | RTC_CRITICAL_SECTION_ENTER(); |
| 6131 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; |
| 6132 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6133 | } |
| 6134 | |
| 6135 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) |
| 6136 | { |
| 6137 | uint32_t tmp; |
| 6138 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6139 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; |
| 6140 | return (bool)tmp; |
| 6141 | } |
| 6142 | |
| 6143 | static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) |
| 6144 | { |
| 6145 | uint32_t tmp; |
| 6146 | RTC_CRITICAL_SECTION_ENTER(); |
| 6147 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6148 | tmp &= ~RTC_MODE1_EVCTRL_PEREO0; |
| 6149 | tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; |
| 6150 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6151 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6152 | } |
| 6153 | |
| 6154 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) |
| 6155 | { |
| 6156 | RTC_CRITICAL_SECTION_ENTER(); |
| 6157 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; |
| 6158 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6159 | } |
| 6160 | |
| 6161 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) |
| 6162 | { |
| 6163 | RTC_CRITICAL_SECTION_ENTER(); |
| 6164 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; |
| 6165 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6166 | } |
| 6167 | |
| 6168 | static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) |
| 6169 | { |
| 6170 | RTC_CRITICAL_SECTION_ENTER(); |
| 6171 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; |
| 6172 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6173 | } |
| 6174 | |
| 6175 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) |
| 6176 | { |
| 6177 | uint32_t tmp; |
| 6178 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6179 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; |
| 6180 | return (bool)tmp; |
| 6181 | } |
| 6182 | |
| 6183 | static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) |
| 6184 | { |
| 6185 | uint32_t tmp; |
| 6186 | RTC_CRITICAL_SECTION_ENTER(); |
| 6187 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6188 | tmp &= ~RTC_MODE1_EVCTRL_PEREO1; |
| 6189 | tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; |
| 6190 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6191 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6192 | } |
| 6193 | |
| 6194 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) |
| 6195 | { |
| 6196 | RTC_CRITICAL_SECTION_ENTER(); |
| 6197 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; |
| 6198 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6199 | } |
| 6200 | |
| 6201 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) |
| 6202 | { |
| 6203 | RTC_CRITICAL_SECTION_ENTER(); |
| 6204 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; |
| 6205 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6206 | } |
| 6207 | |
| 6208 | static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) |
| 6209 | { |
| 6210 | RTC_CRITICAL_SECTION_ENTER(); |
| 6211 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; |
| 6212 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6213 | } |
| 6214 | |
| 6215 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) |
| 6216 | { |
| 6217 | uint32_t tmp; |
| 6218 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6219 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; |
| 6220 | return (bool)tmp; |
| 6221 | } |
| 6222 | |
| 6223 | static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) |
| 6224 | { |
| 6225 | uint32_t tmp; |
| 6226 | RTC_CRITICAL_SECTION_ENTER(); |
| 6227 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6228 | tmp &= ~RTC_MODE1_EVCTRL_PEREO2; |
| 6229 | tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; |
| 6230 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6231 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6232 | } |
| 6233 | |
| 6234 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) |
| 6235 | { |
| 6236 | RTC_CRITICAL_SECTION_ENTER(); |
| 6237 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; |
| 6238 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6239 | } |
| 6240 | |
| 6241 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) |
| 6242 | { |
| 6243 | RTC_CRITICAL_SECTION_ENTER(); |
| 6244 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; |
| 6245 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6246 | } |
| 6247 | |
| 6248 | static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) |
| 6249 | { |
| 6250 | RTC_CRITICAL_SECTION_ENTER(); |
| 6251 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; |
| 6252 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6253 | } |
| 6254 | |
| 6255 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) |
| 6256 | { |
| 6257 | uint32_t tmp; |
| 6258 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6259 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; |
| 6260 | return (bool)tmp; |
| 6261 | } |
| 6262 | |
| 6263 | static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) |
| 6264 | { |
| 6265 | uint32_t tmp; |
| 6266 | RTC_CRITICAL_SECTION_ENTER(); |
| 6267 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6268 | tmp &= ~RTC_MODE1_EVCTRL_PEREO3; |
| 6269 | tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; |
| 6270 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6271 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6272 | } |
| 6273 | |
| 6274 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) |
| 6275 | { |
| 6276 | RTC_CRITICAL_SECTION_ENTER(); |
| 6277 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; |
| 6278 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6279 | } |
| 6280 | |
| 6281 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) |
| 6282 | { |
| 6283 | RTC_CRITICAL_SECTION_ENTER(); |
| 6284 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; |
| 6285 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6286 | } |
| 6287 | |
| 6288 | static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) |
| 6289 | { |
| 6290 | RTC_CRITICAL_SECTION_ENTER(); |
| 6291 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; |
| 6292 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6293 | } |
| 6294 | |
| 6295 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) |
| 6296 | { |
| 6297 | uint32_t tmp; |
| 6298 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6299 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; |
| 6300 | return (bool)tmp; |
| 6301 | } |
| 6302 | |
| 6303 | static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) |
| 6304 | { |
| 6305 | uint32_t tmp; |
| 6306 | RTC_CRITICAL_SECTION_ENTER(); |
| 6307 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6308 | tmp &= ~RTC_MODE1_EVCTRL_PEREO4; |
| 6309 | tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; |
| 6310 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6311 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6312 | } |
| 6313 | |
| 6314 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) |
| 6315 | { |
| 6316 | RTC_CRITICAL_SECTION_ENTER(); |
| 6317 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; |
| 6318 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6319 | } |
| 6320 | |
| 6321 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) |
| 6322 | { |
| 6323 | RTC_CRITICAL_SECTION_ENTER(); |
| 6324 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; |
| 6325 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6326 | } |
| 6327 | |
| 6328 | static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) |
| 6329 | { |
| 6330 | RTC_CRITICAL_SECTION_ENTER(); |
| 6331 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; |
| 6332 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6333 | } |
| 6334 | |
| 6335 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) |
| 6336 | { |
| 6337 | uint32_t tmp; |
| 6338 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6339 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; |
| 6340 | return (bool)tmp; |
| 6341 | } |
| 6342 | |
| 6343 | static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) |
| 6344 | { |
| 6345 | uint32_t tmp; |
| 6346 | RTC_CRITICAL_SECTION_ENTER(); |
| 6347 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6348 | tmp &= ~RTC_MODE1_EVCTRL_PEREO5; |
| 6349 | tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; |
| 6350 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6351 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6352 | } |
| 6353 | |
| 6354 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) |
| 6355 | { |
| 6356 | RTC_CRITICAL_SECTION_ENTER(); |
| 6357 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; |
| 6358 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6359 | } |
| 6360 | |
| 6361 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) |
| 6362 | { |
| 6363 | RTC_CRITICAL_SECTION_ENTER(); |
| 6364 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; |
| 6365 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6366 | } |
| 6367 | |
| 6368 | static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) |
| 6369 | { |
| 6370 | RTC_CRITICAL_SECTION_ENTER(); |
| 6371 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; |
| 6372 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6373 | } |
| 6374 | |
| 6375 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) |
| 6376 | { |
| 6377 | uint32_t tmp; |
| 6378 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6379 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; |
| 6380 | return (bool)tmp; |
| 6381 | } |
| 6382 | |
| 6383 | static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) |
| 6384 | { |
| 6385 | uint32_t tmp; |
| 6386 | RTC_CRITICAL_SECTION_ENTER(); |
| 6387 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6388 | tmp &= ~RTC_MODE1_EVCTRL_PEREO6; |
| 6389 | tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; |
| 6390 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6391 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6392 | } |
| 6393 | |
| 6394 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) |
| 6395 | { |
| 6396 | RTC_CRITICAL_SECTION_ENTER(); |
| 6397 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; |
| 6398 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6399 | } |
| 6400 | |
| 6401 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) |
| 6402 | { |
| 6403 | RTC_CRITICAL_SECTION_ENTER(); |
| 6404 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; |
| 6405 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6406 | } |
| 6407 | |
| 6408 | static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) |
| 6409 | { |
| 6410 | RTC_CRITICAL_SECTION_ENTER(); |
| 6411 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; |
| 6412 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6413 | } |
| 6414 | |
| 6415 | static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) |
| 6416 | { |
| 6417 | uint32_t tmp; |
| 6418 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6419 | tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; |
| 6420 | return (bool)tmp; |
| 6421 | } |
| 6422 | |
| 6423 | static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) |
| 6424 | { |
| 6425 | uint32_t tmp; |
| 6426 | RTC_CRITICAL_SECTION_ENTER(); |
| 6427 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6428 | tmp &= ~RTC_MODE1_EVCTRL_PEREO7; |
| 6429 | tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; |
| 6430 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6431 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6432 | } |
| 6433 | |
| 6434 | static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) |
| 6435 | { |
| 6436 | RTC_CRITICAL_SECTION_ENTER(); |
| 6437 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; |
| 6438 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6439 | } |
| 6440 | |
| 6441 | static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) |
| 6442 | { |
| 6443 | RTC_CRITICAL_SECTION_ENTER(); |
| 6444 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; |
| 6445 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6446 | } |
| 6447 | |
| 6448 | static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) |
| 6449 | { |
| 6450 | RTC_CRITICAL_SECTION_ENTER(); |
| 6451 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; |
| 6452 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6453 | } |
| 6454 | |
| 6455 | static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) |
| 6456 | { |
| 6457 | uint32_t tmp; |
| 6458 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6459 | tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; |
| 6460 | return (bool)tmp; |
| 6461 | } |
| 6462 | |
| 6463 | static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) |
| 6464 | { |
| 6465 | uint32_t tmp; |
| 6466 | RTC_CRITICAL_SECTION_ENTER(); |
| 6467 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6468 | tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; |
| 6469 | tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; |
| 6470 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6471 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6472 | } |
| 6473 | |
| 6474 | static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) |
| 6475 | { |
| 6476 | RTC_CRITICAL_SECTION_ENTER(); |
| 6477 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; |
| 6478 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6479 | } |
| 6480 | |
| 6481 | static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) |
| 6482 | { |
| 6483 | RTC_CRITICAL_SECTION_ENTER(); |
| 6484 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; |
| 6485 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6486 | } |
| 6487 | |
| 6488 | static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) |
| 6489 | { |
| 6490 | RTC_CRITICAL_SECTION_ENTER(); |
| 6491 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; |
| 6492 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6493 | } |
| 6494 | |
| 6495 | static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) |
| 6496 | { |
| 6497 | uint32_t tmp; |
| 6498 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6499 | tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; |
| 6500 | return (bool)tmp; |
| 6501 | } |
| 6502 | |
| 6503 | static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) |
| 6504 | { |
| 6505 | uint32_t tmp; |
| 6506 | RTC_CRITICAL_SECTION_ENTER(); |
| 6507 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6508 | tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; |
| 6509 | tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; |
| 6510 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6511 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6512 | } |
| 6513 | |
| 6514 | static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) |
| 6515 | { |
| 6516 | RTC_CRITICAL_SECTION_ENTER(); |
| 6517 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; |
| 6518 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6519 | } |
| 6520 | |
| 6521 | static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) |
| 6522 | { |
| 6523 | RTC_CRITICAL_SECTION_ENTER(); |
| 6524 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; |
| 6525 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6526 | } |
| 6527 | |
| 6528 | static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) |
| 6529 | { |
| 6530 | RTC_CRITICAL_SECTION_ENTER(); |
| 6531 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; |
| 6532 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6533 | } |
| 6534 | |
| 6535 | static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) |
| 6536 | { |
| 6537 | uint32_t tmp; |
| 6538 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6539 | tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; |
| 6540 | return (bool)tmp; |
| 6541 | } |
| 6542 | |
| 6543 | static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) |
| 6544 | { |
| 6545 | uint32_t tmp; |
| 6546 | RTC_CRITICAL_SECTION_ENTER(); |
| 6547 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6548 | tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; |
| 6549 | tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; |
| 6550 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6551 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6552 | } |
| 6553 | |
| 6554 | static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) |
| 6555 | { |
| 6556 | RTC_CRITICAL_SECTION_ENTER(); |
| 6557 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; |
| 6558 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6559 | } |
| 6560 | |
| 6561 | static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) |
| 6562 | { |
| 6563 | RTC_CRITICAL_SECTION_ENTER(); |
| 6564 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; |
| 6565 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6566 | } |
| 6567 | |
| 6568 | static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) |
| 6569 | { |
| 6570 | RTC_CRITICAL_SECTION_ENTER(); |
| 6571 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; |
| 6572 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6573 | } |
| 6574 | |
| 6575 | static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) |
| 6576 | { |
| 6577 | uint32_t tmp; |
| 6578 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6579 | tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; |
| 6580 | return (bool)tmp; |
| 6581 | } |
| 6582 | |
| 6583 | static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) |
| 6584 | { |
| 6585 | uint32_t tmp; |
| 6586 | RTC_CRITICAL_SECTION_ENTER(); |
| 6587 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6588 | tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; |
| 6589 | tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; |
| 6590 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6591 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6592 | } |
| 6593 | |
| 6594 | static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) |
| 6595 | { |
| 6596 | RTC_CRITICAL_SECTION_ENTER(); |
| 6597 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; |
| 6598 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6599 | } |
| 6600 | |
| 6601 | static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) |
| 6602 | { |
| 6603 | RTC_CRITICAL_SECTION_ENTER(); |
| 6604 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; |
| 6605 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6606 | } |
| 6607 | |
| 6608 | static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 6609 | { |
| 6610 | RTC_CRITICAL_SECTION_ENTER(); |
| 6611 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; |
| 6612 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6613 | } |
| 6614 | |
| 6615 | static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 6616 | { |
| 6617 | uint32_t tmp; |
| 6618 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6619 | tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; |
| 6620 | return (bool)tmp; |
| 6621 | } |
| 6622 | |
| 6623 | static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) |
| 6624 | { |
| 6625 | uint32_t tmp; |
| 6626 | RTC_CRITICAL_SECTION_ENTER(); |
| 6627 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6628 | tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; |
| 6629 | tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; |
| 6630 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6631 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6632 | } |
| 6633 | |
| 6634 | static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 6635 | { |
| 6636 | RTC_CRITICAL_SECTION_ENTER(); |
| 6637 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; |
| 6638 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6639 | } |
| 6640 | |
| 6641 | static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 6642 | { |
| 6643 | RTC_CRITICAL_SECTION_ENTER(); |
| 6644 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; |
| 6645 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6646 | } |
| 6647 | |
| 6648 | static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) |
| 6649 | { |
| 6650 | RTC_CRITICAL_SECTION_ENTER(); |
| 6651 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; |
| 6652 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6653 | } |
| 6654 | |
| 6655 | static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) |
| 6656 | { |
| 6657 | uint32_t tmp; |
| 6658 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6659 | tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; |
| 6660 | return (bool)tmp; |
| 6661 | } |
| 6662 | |
| 6663 | static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) |
| 6664 | { |
| 6665 | uint32_t tmp; |
| 6666 | RTC_CRITICAL_SECTION_ENTER(); |
| 6667 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6668 | tmp &= ~RTC_MODE1_EVCTRL_OVFEO; |
| 6669 | tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; |
| 6670 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6671 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6672 | } |
| 6673 | |
| 6674 | static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) |
| 6675 | { |
| 6676 | RTC_CRITICAL_SECTION_ENTER(); |
| 6677 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; |
| 6678 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6679 | } |
| 6680 | |
| 6681 | static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) |
| 6682 | { |
| 6683 | RTC_CRITICAL_SECTION_ENTER(); |
| 6684 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; |
| 6685 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6686 | } |
| 6687 | |
| 6688 | static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6689 | { |
| 6690 | RTC_CRITICAL_SECTION_ENTER(); |
| 6691 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; |
| 6692 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6693 | } |
| 6694 | |
| 6695 | static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6696 | { |
| 6697 | uint32_t tmp; |
| 6698 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6699 | tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; |
| 6700 | return (bool)tmp; |
| 6701 | } |
| 6702 | |
| 6703 | static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) |
| 6704 | { |
| 6705 | uint32_t tmp; |
| 6706 | RTC_CRITICAL_SECTION_ENTER(); |
| 6707 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6708 | tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; |
| 6709 | tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; |
| 6710 | ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; |
| 6711 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6712 | } |
| 6713 | |
| 6714 | static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6715 | { |
| 6716 | RTC_CRITICAL_SECTION_ENTER(); |
| 6717 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; |
| 6718 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6719 | } |
| 6720 | |
| 6721 | static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 6722 | { |
| 6723 | RTC_CRITICAL_SECTION_ENTER(); |
| 6724 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; |
| 6725 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6726 | } |
| 6727 | |
| 6728 | static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) |
| 6729 | { |
| 6730 | RTC_CRITICAL_SECTION_ENTER(); |
| 6731 | ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; |
| 6732 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6733 | } |
| 6734 | |
| 6735 | static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, |
| 6736 | hri_rtcmode1_evctrl_reg_t mask) |
| 6737 | { |
| 6738 | uint32_t tmp; |
| 6739 | tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6740 | tmp &= mask; |
| 6741 | return tmp; |
| 6742 | } |
| 6743 | |
| 6744 | static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) |
| 6745 | { |
| 6746 | RTC_CRITICAL_SECTION_ENTER(); |
| 6747 | ((Rtc *)hw)->MODE1.EVCTRL.reg = data; |
| 6748 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6749 | } |
| 6750 | |
| 6751 | static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) |
| 6752 | { |
| 6753 | RTC_CRITICAL_SECTION_ENTER(); |
| 6754 | ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; |
| 6755 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6756 | } |
| 6757 | |
| 6758 | static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) |
| 6759 | { |
| 6760 | RTC_CRITICAL_SECTION_ENTER(); |
| 6761 | ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; |
| 6762 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6763 | } |
| 6764 | |
| 6765 | static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) |
| 6766 | { |
| 6767 | return ((Rtc *)hw)->MODE1.EVCTRL.reg; |
| 6768 | } |
| 6769 | |
| 6770 | static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) |
| 6771 | { |
| 6772 | RTC_CRITICAL_SECTION_ENTER(); |
| 6773 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; |
| 6774 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6775 | } |
| 6776 | |
| 6777 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) |
| 6778 | { |
| 6779 | uint32_t tmp; |
| 6780 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6781 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; |
| 6782 | return (bool)tmp; |
| 6783 | } |
| 6784 | |
| 6785 | static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) |
| 6786 | { |
| 6787 | uint32_t tmp; |
| 6788 | RTC_CRITICAL_SECTION_ENTER(); |
| 6789 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6790 | tmp &= ~RTC_MODE2_EVCTRL_PEREO0; |
| 6791 | tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; |
| 6792 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 6793 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6794 | } |
| 6795 | |
| 6796 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) |
| 6797 | { |
| 6798 | RTC_CRITICAL_SECTION_ENTER(); |
| 6799 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; |
| 6800 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6801 | } |
| 6802 | |
| 6803 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) |
| 6804 | { |
| 6805 | RTC_CRITICAL_SECTION_ENTER(); |
| 6806 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; |
| 6807 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6808 | } |
| 6809 | |
| 6810 | static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) |
| 6811 | { |
| 6812 | RTC_CRITICAL_SECTION_ENTER(); |
| 6813 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; |
| 6814 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6815 | } |
| 6816 | |
| 6817 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) |
| 6818 | { |
| 6819 | uint32_t tmp; |
| 6820 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6821 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; |
| 6822 | return (bool)tmp; |
| 6823 | } |
| 6824 | |
| 6825 | static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) |
| 6826 | { |
| 6827 | uint32_t tmp; |
| 6828 | RTC_CRITICAL_SECTION_ENTER(); |
| 6829 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6830 | tmp &= ~RTC_MODE2_EVCTRL_PEREO1; |
| 6831 | tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; |
| 6832 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 6833 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6834 | } |
| 6835 | |
| 6836 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) |
| 6837 | { |
| 6838 | RTC_CRITICAL_SECTION_ENTER(); |
| 6839 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; |
| 6840 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6841 | } |
| 6842 | |
| 6843 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) |
| 6844 | { |
| 6845 | RTC_CRITICAL_SECTION_ENTER(); |
| 6846 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; |
| 6847 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6848 | } |
| 6849 | |
| 6850 | static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) |
| 6851 | { |
| 6852 | RTC_CRITICAL_SECTION_ENTER(); |
| 6853 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; |
| 6854 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6855 | } |
| 6856 | |
| 6857 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) |
| 6858 | { |
| 6859 | uint32_t tmp; |
| 6860 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6861 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; |
| 6862 | return (bool)tmp; |
| 6863 | } |
| 6864 | |
| 6865 | static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) |
| 6866 | { |
| 6867 | uint32_t tmp; |
| 6868 | RTC_CRITICAL_SECTION_ENTER(); |
| 6869 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6870 | tmp &= ~RTC_MODE2_EVCTRL_PEREO2; |
| 6871 | tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; |
| 6872 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 6873 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6874 | } |
| 6875 | |
| 6876 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) |
| 6877 | { |
| 6878 | RTC_CRITICAL_SECTION_ENTER(); |
| 6879 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; |
| 6880 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6881 | } |
| 6882 | |
| 6883 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) |
| 6884 | { |
| 6885 | RTC_CRITICAL_SECTION_ENTER(); |
| 6886 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; |
| 6887 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6888 | } |
| 6889 | |
| 6890 | static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) |
| 6891 | { |
| 6892 | RTC_CRITICAL_SECTION_ENTER(); |
| 6893 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; |
| 6894 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6895 | } |
| 6896 | |
| 6897 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) |
| 6898 | { |
| 6899 | uint32_t tmp; |
| 6900 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6901 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; |
| 6902 | return (bool)tmp; |
| 6903 | } |
| 6904 | |
| 6905 | static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) |
| 6906 | { |
| 6907 | uint32_t tmp; |
| 6908 | RTC_CRITICAL_SECTION_ENTER(); |
| 6909 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6910 | tmp &= ~RTC_MODE2_EVCTRL_PEREO3; |
| 6911 | tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; |
| 6912 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 6913 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6914 | } |
| 6915 | |
| 6916 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) |
| 6917 | { |
| 6918 | RTC_CRITICAL_SECTION_ENTER(); |
| 6919 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; |
| 6920 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6921 | } |
| 6922 | |
| 6923 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) |
| 6924 | { |
| 6925 | RTC_CRITICAL_SECTION_ENTER(); |
| 6926 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; |
| 6927 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6928 | } |
| 6929 | |
| 6930 | static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) |
| 6931 | { |
| 6932 | RTC_CRITICAL_SECTION_ENTER(); |
| 6933 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; |
| 6934 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6935 | } |
| 6936 | |
| 6937 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) |
| 6938 | { |
| 6939 | uint32_t tmp; |
| 6940 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6941 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; |
| 6942 | return (bool)tmp; |
| 6943 | } |
| 6944 | |
| 6945 | static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) |
| 6946 | { |
| 6947 | uint32_t tmp; |
| 6948 | RTC_CRITICAL_SECTION_ENTER(); |
| 6949 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6950 | tmp &= ~RTC_MODE2_EVCTRL_PEREO4; |
| 6951 | tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; |
| 6952 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 6953 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6954 | } |
| 6955 | |
| 6956 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) |
| 6957 | { |
| 6958 | RTC_CRITICAL_SECTION_ENTER(); |
| 6959 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; |
| 6960 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6961 | } |
| 6962 | |
| 6963 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) |
| 6964 | { |
| 6965 | RTC_CRITICAL_SECTION_ENTER(); |
| 6966 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; |
| 6967 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6968 | } |
| 6969 | |
| 6970 | static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) |
| 6971 | { |
| 6972 | RTC_CRITICAL_SECTION_ENTER(); |
| 6973 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; |
| 6974 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6975 | } |
| 6976 | |
| 6977 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) |
| 6978 | { |
| 6979 | uint32_t tmp; |
| 6980 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6981 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; |
| 6982 | return (bool)tmp; |
| 6983 | } |
| 6984 | |
| 6985 | static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) |
| 6986 | { |
| 6987 | uint32_t tmp; |
| 6988 | RTC_CRITICAL_SECTION_ENTER(); |
| 6989 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 6990 | tmp &= ~RTC_MODE2_EVCTRL_PEREO5; |
| 6991 | tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; |
| 6992 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 6993 | RTC_CRITICAL_SECTION_LEAVE(); |
| 6994 | } |
| 6995 | |
| 6996 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) |
| 6997 | { |
| 6998 | RTC_CRITICAL_SECTION_ENTER(); |
| 6999 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; |
| 7000 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7001 | } |
| 7002 | |
| 7003 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) |
| 7004 | { |
| 7005 | RTC_CRITICAL_SECTION_ENTER(); |
| 7006 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; |
| 7007 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7008 | } |
| 7009 | |
| 7010 | static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) |
| 7011 | { |
| 7012 | RTC_CRITICAL_SECTION_ENTER(); |
| 7013 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; |
| 7014 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7015 | } |
| 7016 | |
| 7017 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) |
| 7018 | { |
| 7019 | uint32_t tmp; |
| 7020 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7021 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; |
| 7022 | return (bool)tmp; |
| 7023 | } |
| 7024 | |
| 7025 | static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) |
| 7026 | { |
| 7027 | uint32_t tmp; |
| 7028 | RTC_CRITICAL_SECTION_ENTER(); |
| 7029 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7030 | tmp &= ~RTC_MODE2_EVCTRL_PEREO6; |
| 7031 | tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; |
| 7032 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 7033 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7034 | } |
| 7035 | |
| 7036 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) |
| 7037 | { |
| 7038 | RTC_CRITICAL_SECTION_ENTER(); |
| 7039 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; |
| 7040 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7041 | } |
| 7042 | |
| 7043 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) |
| 7044 | { |
| 7045 | RTC_CRITICAL_SECTION_ENTER(); |
| 7046 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; |
| 7047 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7048 | } |
| 7049 | |
| 7050 | static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) |
| 7051 | { |
| 7052 | RTC_CRITICAL_SECTION_ENTER(); |
| 7053 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; |
| 7054 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7055 | } |
| 7056 | |
| 7057 | static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) |
| 7058 | { |
| 7059 | uint32_t tmp; |
| 7060 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7061 | tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; |
| 7062 | return (bool)tmp; |
| 7063 | } |
| 7064 | |
| 7065 | static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) |
| 7066 | { |
| 7067 | uint32_t tmp; |
| 7068 | RTC_CRITICAL_SECTION_ENTER(); |
| 7069 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7070 | tmp &= ~RTC_MODE2_EVCTRL_PEREO7; |
| 7071 | tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; |
| 7072 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 7073 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7074 | } |
| 7075 | |
| 7076 | static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) |
| 7077 | { |
| 7078 | RTC_CRITICAL_SECTION_ENTER(); |
| 7079 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; |
| 7080 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7081 | } |
| 7082 | |
| 7083 | static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) |
| 7084 | { |
| 7085 | RTC_CRITICAL_SECTION_ENTER(); |
| 7086 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; |
| 7087 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7088 | } |
| 7089 | |
| 7090 | static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) |
| 7091 | { |
| 7092 | RTC_CRITICAL_SECTION_ENTER(); |
| 7093 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; |
| 7094 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7095 | } |
| 7096 | |
| 7097 | static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) |
| 7098 | { |
| 7099 | uint32_t tmp; |
| 7100 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7101 | tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; |
| 7102 | return (bool)tmp; |
| 7103 | } |
| 7104 | |
| 7105 | static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) |
| 7106 | { |
| 7107 | uint32_t tmp; |
| 7108 | RTC_CRITICAL_SECTION_ENTER(); |
| 7109 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7110 | tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; |
| 7111 | tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; |
| 7112 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 7113 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7114 | } |
| 7115 | |
| 7116 | static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) |
| 7117 | { |
| 7118 | RTC_CRITICAL_SECTION_ENTER(); |
| 7119 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; |
| 7120 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7121 | } |
| 7122 | |
| 7123 | static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) |
| 7124 | { |
| 7125 | RTC_CRITICAL_SECTION_ENTER(); |
| 7126 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; |
| 7127 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7128 | } |
| 7129 | |
| 7130 | static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) |
| 7131 | { |
| 7132 | RTC_CRITICAL_SECTION_ENTER(); |
| 7133 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; |
| 7134 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7135 | } |
| 7136 | |
| 7137 | static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) |
| 7138 | { |
| 7139 | uint32_t tmp; |
| 7140 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7141 | tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; |
| 7142 | return (bool)tmp; |
| 7143 | } |
| 7144 | |
| 7145 | static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) |
| 7146 | { |
| 7147 | uint32_t tmp; |
| 7148 | RTC_CRITICAL_SECTION_ENTER(); |
| 7149 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7150 | tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; |
| 7151 | tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; |
| 7152 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 7153 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7154 | } |
| 7155 | |
| 7156 | static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) |
| 7157 | { |
| 7158 | RTC_CRITICAL_SECTION_ENTER(); |
| 7159 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; |
| 7160 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7161 | } |
| 7162 | |
| 7163 | static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) |
| 7164 | { |
| 7165 | RTC_CRITICAL_SECTION_ENTER(); |
| 7166 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; |
| 7167 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7168 | } |
| 7169 | |
| 7170 | static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 7171 | { |
| 7172 | RTC_CRITICAL_SECTION_ENTER(); |
| 7173 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; |
| 7174 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7175 | } |
| 7176 | |
| 7177 | static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 7178 | { |
| 7179 | uint32_t tmp; |
| 7180 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7181 | tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; |
| 7182 | return (bool)tmp; |
| 7183 | } |
| 7184 | |
| 7185 | static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) |
| 7186 | { |
| 7187 | uint32_t tmp; |
| 7188 | RTC_CRITICAL_SECTION_ENTER(); |
| 7189 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7190 | tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; |
| 7191 | tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; |
| 7192 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 7193 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7194 | } |
| 7195 | |
| 7196 | static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 7197 | { |
| 7198 | RTC_CRITICAL_SECTION_ENTER(); |
| 7199 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; |
| 7200 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7201 | } |
| 7202 | |
| 7203 | static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) |
| 7204 | { |
| 7205 | RTC_CRITICAL_SECTION_ENTER(); |
| 7206 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; |
| 7207 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7208 | } |
| 7209 | |
| 7210 | static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) |
| 7211 | { |
| 7212 | RTC_CRITICAL_SECTION_ENTER(); |
| 7213 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; |
| 7214 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7215 | } |
| 7216 | |
| 7217 | static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) |
| 7218 | { |
| 7219 | uint32_t tmp; |
| 7220 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7221 | tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; |
| 7222 | return (bool)tmp; |
| 7223 | } |
| 7224 | |
| 7225 | static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) |
| 7226 | { |
| 7227 | uint32_t tmp; |
| 7228 | RTC_CRITICAL_SECTION_ENTER(); |
| 7229 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7230 | tmp &= ~RTC_MODE2_EVCTRL_OVFEO; |
| 7231 | tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; |
| 7232 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 7233 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7234 | } |
| 7235 | |
| 7236 | static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) |
| 7237 | { |
| 7238 | RTC_CRITICAL_SECTION_ENTER(); |
| 7239 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; |
| 7240 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7241 | } |
| 7242 | |
| 7243 | static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) |
| 7244 | { |
| 7245 | RTC_CRITICAL_SECTION_ENTER(); |
| 7246 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; |
| 7247 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7248 | } |
| 7249 | |
| 7250 | static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 7251 | { |
| 7252 | RTC_CRITICAL_SECTION_ENTER(); |
| 7253 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; |
| 7254 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7255 | } |
| 7256 | |
| 7257 | static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 7258 | { |
| 7259 | uint32_t tmp; |
| 7260 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7261 | tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; |
| 7262 | return (bool)tmp; |
| 7263 | } |
| 7264 | |
| 7265 | static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) |
| 7266 | { |
| 7267 | uint32_t tmp; |
| 7268 | RTC_CRITICAL_SECTION_ENTER(); |
| 7269 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7270 | tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; |
| 7271 | tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; |
| 7272 | ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; |
| 7273 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7274 | } |
| 7275 | |
| 7276 | static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 7277 | { |
| 7278 | RTC_CRITICAL_SECTION_ENTER(); |
| 7279 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; |
| 7280 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7281 | } |
| 7282 | |
| 7283 | static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) |
| 7284 | { |
| 7285 | RTC_CRITICAL_SECTION_ENTER(); |
| 7286 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; |
| 7287 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7288 | } |
| 7289 | |
| 7290 | static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) |
| 7291 | { |
| 7292 | RTC_CRITICAL_SECTION_ENTER(); |
| 7293 | ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; |
| 7294 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7295 | } |
| 7296 | |
| 7297 | static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, |
| 7298 | hri_rtcmode2_evctrl_reg_t mask) |
| 7299 | { |
| 7300 | uint32_t tmp; |
| 7301 | tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7302 | tmp &= mask; |
| 7303 | return tmp; |
| 7304 | } |
| 7305 | |
| 7306 | static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) |
| 7307 | { |
| 7308 | RTC_CRITICAL_SECTION_ENTER(); |
| 7309 | ((Rtc *)hw)->MODE2.EVCTRL.reg = data; |
| 7310 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7311 | } |
| 7312 | |
| 7313 | static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) |
| 7314 | { |
| 7315 | RTC_CRITICAL_SECTION_ENTER(); |
| 7316 | ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; |
| 7317 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7318 | } |
| 7319 | |
| 7320 | static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) |
| 7321 | { |
| 7322 | RTC_CRITICAL_SECTION_ENTER(); |
| 7323 | ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; |
| 7324 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7325 | } |
| 7326 | |
| 7327 | static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) |
| 7328 | { |
| 7329 | return ((Rtc *)hw)->MODE2.EVCTRL.reg; |
| 7330 | } |
| 7331 | |
| 7332 | static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 7333 | { |
| 7334 | RTC_CRITICAL_SECTION_ENTER(); |
| 7335 | ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; |
| 7336 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7337 | } |
| 7338 | |
| 7339 | static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 7340 | { |
| 7341 | uint8_t tmp; |
| 7342 | tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; |
| 7343 | tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; |
| 7344 | return (bool)tmp; |
| 7345 | } |
| 7346 | |
| 7347 | static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) |
| 7348 | { |
| 7349 | uint8_t tmp; |
| 7350 | RTC_CRITICAL_SECTION_ENTER(); |
| 7351 | tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; |
| 7352 | tmp &= ~RTC_DBGCTRL_DBGRUN; |
| 7353 | tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; |
| 7354 | ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; |
| 7355 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7356 | } |
| 7357 | |
| 7358 | static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 7359 | { |
| 7360 | RTC_CRITICAL_SECTION_ENTER(); |
| 7361 | ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; |
| 7362 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7363 | } |
| 7364 | |
| 7365 | static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 7366 | { |
| 7367 | RTC_CRITICAL_SECTION_ENTER(); |
| 7368 | ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; |
| 7369 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7370 | } |
| 7371 | |
| 7372 | static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) |
| 7373 | { |
| 7374 | RTC_CRITICAL_SECTION_ENTER(); |
| 7375 | ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; |
| 7376 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7377 | } |
| 7378 | |
| 7379 | static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) |
| 7380 | { |
| 7381 | uint8_t tmp; |
| 7382 | tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; |
| 7383 | tmp &= mask; |
| 7384 | return tmp; |
| 7385 | } |
| 7386 | |
| 7387 | static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) |
| 7388 | { |
| 7389 | RTC_CRITICAL_SECTION_ENTER(); |
| 7390 | ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; |
| 7391 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7392 | } |
| 7393 | |
| 7394 | static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) |
| 7395 | { |
| 7396 | RTC_CRITICAL_SECTION_ENTER(); |
| 7397 | ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; |
| 7398 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7399 | } |
| 7400 | |
| 7401 | static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) |
| 7402 | { |
| 7403 | RTC_CRITICAL_SECTION_ENTER(); |
| 7404 | ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; |
| 7405 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7406 | } |
| 7407 | |
| 7408 | static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) |
| 7409 | { |
| 7410 | return ((Rtc *)hw)->MODE0.DBGCTRL.reg; |
| 7411 | } |
| 7412 | |
| 7413 | static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) |
| 7414 | { |
| 7415 | RTC_CRITICAL_SECTION_ENTER(); |
| 7416 | ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; |
| 7417 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7418 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7419 | } |
| 7420 | |
| 7421 | static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) |
| 7422 | { |
| 7423 | uint8_t tmp; |
| 7424 | tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; |
| 7425 | tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; |
| 7426 | return (bool)tmp; |
| 7427 | } |
| 7428 | |
| 7429 | static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) |
| 7430 | { |
| 7431 | uint8_t tmp; |
| 7432 | RTC_CRITICAL_SECTION_ENTER(); |
| 7433 | tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; |
| 7434 | tmp &= ~RTC_FREQCORR_SIGN; |
| 7435 | tmp |= value << RTC_FREQCORR_SIGN_Pos; |
| 7436 | ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; |
| 7437 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7438 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7439 | } |
| 7440 | |
| 7441 | static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) |
| 7442 | { |
| 7443 | RTC_CRITICAL_SECTION_ENTER(); |
| 7444 | ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; |
| 7445 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7446 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7447 | } |
| 7448 | |
| 7449 | static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) |
| 7450 | { |
| 7451 | RTC_CRITICAL_SECTION_ENTER(); |
| 7452 | ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; |
| 7453 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7454 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7455 | } |
| 7456 | |
| 7457 | static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7458 | { |
| 7459 | RTC_CRITICAL_SECTION_ENTER(); |
| 7460 | ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); |
| 7461 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7462 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7463 | } |
| 7464 | |
| 7465 | static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7466 | { |
| 7467 | uint8_t tmp; |
| 7468 | tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; |
| 7469 | tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; |
| 7470 | return tmp; |
| 7471 | } |
| 7472 | |
| 7473 | static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) |
| 7474 | { |
| 7475 | uint8_t tmp; |
| 7476 | RTC_CRITICAL_SECTION_ENTER(); |
| 7477 | tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; |
| 7478 | tmp &= ~RTC_FREQCORR_VALUE_Msk; |
| 7479 | tmp |= RTC_FREQCORR_VALUE(data); |
| 7480 | ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; |
| 7481 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7482 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7483 | } |
| 7484 | |
| 7485 | static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7486 | { |
| 7487 | RTC_CRITICAL_SECTION_ENTER(); |
| 7488 | ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); |
| 7489 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7490 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7491 | } |
| 7492 | |
| 7493 | static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7494 | { |
| 7495 | RTC_CRITICAL_SECTION_ENTER(); |
| 7496 | ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); |
| 7497 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7498 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7499 | } |
| 7500 | |
| 7501 | static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) |
| 7502 | { |
| 7503 | uint8_t tmp; |
| 7504 | tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; |
| 7505 | tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; |
| 7506 | return tmp; |
| 7507 | } |
| 7508 | |
| 7509 | static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7510 | { |
| 7511 | RTC_CRITICAL_SECTION_ENTER(); |
| 7512 | ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; |
| 7513 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7514 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7515 | } |
| 7516 | |
| 7517 | static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7518 | { |
| 7519 | uint8_t tmp; |
| 7520 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7521 | tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; |
| 7522 | tmp &= mask; |
| 7523 | return tmp; |
| 7524 | } |
| 7525 | |
| 7526 | static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) |
| 7527 | { |
| 7528 | RTC_CRITICAL_SECTION_ENTER(); |
| 7529 | ((Rtc *)hw)->MODE0.FREQCORR.reg = data; |
| 7530 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7531 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7532 | } |
| 7533 | |
| 7534 | static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7535 | { |
| 7536 | RTC_CRITICAL_SECTION_ENTER(); |
| 7537 | ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; |
| 7538 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7539 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7540 | } |
| 7541 | |
| 7542 | static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) |
| 7543 | { |
| 7544 | RTC_CRITICAL_SECTION_ENTER(); |
| 7545 | ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; |
| 7546 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7547 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7548 | } |
| 7549 | |
| 7550 | static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) |
| 7551 | { |
| 7552 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); |
| 7553 | return ((Rtc *)hw)->MODE0.FREQCORR.reg; |
| 7554 | } |
| 7555 | |
| 7556 | static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) |
| 7557 | { |
| 7558 | RTC_CRITICAL_SECTION_ENTER(); |
| 7559 | ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); |
| 7560 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7561 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7562 | } |
| 7563 | |
| 7564 | static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, |
| 7565 | hri_rtcmode0_count_reg_t mask) |
| 7566 | { |
| 7567 | uint32_t tmp; |
| 7568 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7569 | tmp = ((Rtc *)hw)->MODE0.COUNT.reg; |
| 7570 | tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; |
| 7571 | return tmp; |
| 7572 | } |
| 7573 | |
| 7574 | static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) |
| 7575 | { |
| 7576 | uint32_t tmp; |
| 7577 | RTC_CRITICAL_SECTION_ENTER(); |
| 7578 | tmp = ((Rtc *)hw)->MODE0.COUNT.reg; |
| 7579 | tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; |
| 7580 | tmp |= RTC_MODE0_COUNT_COUNT(data); |
| 7581 | ((Rtc *)hw)->MODE0.COUNT.reg = tmp; |
| 7582 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7583 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7584 | } |
| 7585 | |
| 7586 | static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) |
| 7587 | { |
| 7588 | RTC_CRITICAL_SECTION_ENTER(); |
| 7589 | ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); |
| 7590 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7591 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7592 | } |
| 7593 | |
| 7594 | static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) |
| 7595 | { |
| 7596 | RTC_CRITICAL_SECTION_ENTER(); |
| 7597 | ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); |
| 7598 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7599 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7600 | } |
| 7601 | |
| 7602 | static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) |
| 7603 | { |
| 7604 | uint32_t tmp; |
| 7605 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7606 | tmp = ((Rtc *)hw)->MODE0.COUNT.reg; |
| 7607 | tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; |
| 7608 | return tmp; |
| 7609 | } |
| 7610 | |
| 7611 | static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) |
| 7612 | { |
| 7613 | RTC_CRITICAL_SECTION_ENTER(); |
| 7614 | ((Rtc *)hw)->MODE0.COUNT.reg |= mask; |
| 7615 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7616 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7617 | } |
| 7618 | |
| 7619 | static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) |
| 7620 | { |
| 7621 | uint32_t tmp; |
| 7622 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7623 | tmp = ((Rtc *)hw)->MODE0.COUNT.reg; |
| 7624 | tmp &= mask; |
| 7625 | return tmp; |
| 7626 | } |
| 7627 | |
| 7628 | static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) |
| 7629 | { |
| 7630 | RTC_CRITICAL_SECTION_ENTER(); |
| 7631 | ((Rtc *)hw)->MODE0.COUNT.reg = data; |
| 7632 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7633 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7634 | } |
| 7635 | |
| 7636 | static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) |
| 7637 | { |
| 7638 | RTC_CRITICAL_SECTION_ENTER(); |
| 7639 | ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; |
| 7640 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7641 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7642 | } |
| 7643 | |
| 7644 | static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) |
| 7645 | { |
| 7646 | RTC_CRITICAL_SECTION_ENTER(); |
| 7647 | ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; |
| 7648 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7649 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7650 | } |
| 7651 | |
| 7652 | static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) |
| 7653 | { |
| 7654 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); |
| 7655 | return ((Rtc *)hw)->MODE0.COUNT.reg; |
| 7656 | } |
| 7657 | |
| 7658 | static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) |
| 7659 | { |
| 7660 | RTC_CRITICAL_SECTION_ENTER(); |
| 7661 | ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); |
| 7662 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7663 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7664 | } |
| 7665 | |
| 7666 | static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, |
| 7667 | hri_rtcmode1_count_reg_t mask) |
| 7668 | { |
| 7669 | uint16_t tmp; |
| 7670 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7671 | tmp = ((Rtc *)hw)->MODE1.COUNT.reg; |
| 7672 | tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; |
| 7673 | return tmp; |
| 7674 | } |
| 7675 | |
| 7676 | static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) |
| 7677 | { |
| 7678 | uint16_t tmp; |
| 7679 | RTC_CRITICAL_SECTION_ENTER(); |
| 7680 | tmp = ((Rtc *)hw)->MODE1.COUNT.reg; |
| 7681 | tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; |
| 7682 | tmp |= RTC_MODE1_COUNT_COUNT(data); |
| 7683 | ((Rtc *)hw)->MODE1.COUNT.reg = tmp; |
| 7684 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7685 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7686 | } |
| 7687 | |
| 7688 | static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) |
| 7689 | { |
| 7690 | RTC_CRITICAL_SECTION_ENTER(); |
| 7691 | ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); |
| 7692 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7693 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7694 | } |
| 7695 | |
| 7696 | static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) |
| 7697 | { |
| 7698 | RTC_CRITICAL_SECTION_ENTER(); |
| 7699 | ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); |
| 7700 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7701 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7702 | } |
| 7703 | |
| 7704 | static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) |
| 7705 | { |
| 7706 | uint16_t tmp; |
| 7707 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7708 | tmp = ((Rtc *)hw)->MODE1.COUNT.reg; |
| 7709 | tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; |
| 7710 | return tmp; |
| 7711 | } |
| 7712 | |
| 7713 | static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) |
| 7714 | { |
| 7715 | RTC_CRITICAL_SECTION_ENTER(); |
| 7716 | ((Rtc *)hw)->MODE1.COUNT.reg |= mask; |
| 7717 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7718 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7719 | } |
| 7720 | |
| 7721 | static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) |
| 7722 | { |
| 7723 | uint16_t tmp; |
| 7724 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7725 | tmp = ((Rtc *)hw)->MODE1.COUNT.reg; |
| 7726 | tmp &= mask; |
| 7727 | return tmp; |
| 7728 | } |
| 7729 | |
| 7730 | static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) |
| 7731 | { |
| 7732 | RTC_CRITICAL_SECTION_ENTER(); |
| 7733 | ((Rtc *)hw)->MODE1.COUNT.reg = data; |
| 7734 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7735 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7736 | } |
| 7737 | |
| 7738 | static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) |
| 7739 | { |
| 7740 | RTC_CRITICAL_SECTION_ENTER(); |
| 7741 | ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; |
| 7742 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7743 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7744 | } |
| 7745 | |
| 7746 | static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) |
| 7747 | { |
| 7748 | RTC_CRITICAL_SECTION_ENTER(); |
| 7749 | ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; |
| 7750 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7751 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7752 | } |
| 7753 | |
| 7754 | static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) |
| 7755 | { |
| 7756 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); |
| 7757 | return ((Rtc *)hw)->MODE1.COUNT.reg; |
| 7758 | } |
| 7759 | |
| 7760 | static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7761 | { |
| 7762 | RTC_CRITICAL_SECTION_ENTER(); |
| 7763 | ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); |
| 7764 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7765 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7766 | } |
| 7767 | |
| 7768 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, |
| 7769 | hri_rtcmode2_clock_reg_t mask) |
| 7770 | { |
| 7771 | uint32_t tmp; |
| 7772 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7773 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7774 | tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; |
| 7775 | return tmp; |
| 7776 | } |
| 7777 | |
| 7778 | static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) |
| 7779 | { |
| 7780 | uint32_t tmp; |
| 7781 | RTC_CRITICAL_SECTION_ENTER(); |
| 7782 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7783 | tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; |
| 7784 | tmp |= RTC_MODE2_CLOCK_SECOND(data); |
| 7785 | ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; |
| 7786 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7787 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7788 | } |
| 7789 | |
| 7790 | static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7791 | { |
| 7792 | RTC_CRITICAL_SECTION_ENTER(); |
| 7793 | ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); |
| 7794 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7795 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7796 | } |
| 7797 | |
| 7798 | static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7799 | { |
| 7800 | RTC_CRITICAL_SECTION_ENTER(); |
| 7801 | ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); |
| 7802 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7803 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7804 | } |
| 7805 | |
| 7806 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) |
| 7807 | { |
| 7808 | uint32_t tmp; |
| 7809 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7810 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7811 | tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; |
| 7812 | return tmp; |
| 7813 | } |
| 7814 | |
| 7815 | static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7816 | { |
| 7817 | RTC_CRITICAL_SECTION_ENTER(); |
| 7818 | ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); |
| 7819 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7820 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7821 | } |
| 7822 | |
| 7823 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, |
| 7824 | hri_rtcmode2_clock_reg_t mask) |
| 7825 | { |
| 7826 | uint32_t tmp; |
| 7827 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7828 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7829 | tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; |
| 7830 | return tmp; |
| 7831 | } |
| 7832 | |
| 7833 | static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) |
| 7834 | { |
| 7835 | uint32_t tmp; |
| 7836 | RTC_CRITICAL_SECTION_ENTER(); |
| 7837 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7838 | tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; |
| 7839 | tmp |= RTC_MODE2_CLOCK_MINUTE(data); |
| 7840 | ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; |
| 7841 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7842 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7843 | } |
| 7844 | |
| 7845 | static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7846 | { |
| 7847 | RTC_CRITICAL_SECTION_ENTER(); |
| 7848 | ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); |
| 7849 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7850 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7851 | } |
| 7852 | |
| 7853 | static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7854 | { |
| 7855 | RTC_CRITICAL_SECTION_ENTER(); |
| 7856 | ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); |
| 7857 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7858 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7859 | } |
| 7860 | |
| 7861 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) |
| 7862 | { |
| 7863 | uint32_t tmp; |
| 7864 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7865 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7866 | tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; |
| 7867 | return tmp; |
| 7868 | } |
| 7869 | |
| 7870 | static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7871 | { |
| 7872 | RTC_CRITICAL_SECTION_ENTER(); |
| 7873 | ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); |
| 7874 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7875 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7876 | } |
| 7877 | |
| 7878 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, |
| 7879 | hri_rtcmode2_clock_reg_t mask) |
| 7880 | { |
| 7881 | uint32_t tmp; |
| 7882 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7883 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7884 | tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; |
| 7885 | return tmp; |
| 7886 | } |
| 7887 | |
| 7888 | static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) |
| 7889 | { |
| 7890 | uint32_t tmp; |
| 7891 | RTC_CRITICAL_SECTION_ENTER(); |
| 7892 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7893 | tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; |
| 7894 | tmp |= RTC_MODE2_CLOCK_HOUR(data); |
| 7895 | ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; |
| 7896 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7897 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7898 | } |
| 7899 | |
| 7900 | static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7901 | { |
| 7902 | RTC_CRITICAL_SECTION_ENTER(); |
| 7903 | ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); |
| 7904 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7905 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7906 | } |
| 7907 | |
| 7908 | static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7909 | { |
| 7910 | RTC_CRITICAL_SECTION_ENTER(); |
| 7911 | ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); |
| 7912 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7913 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7914 | } |
| 7915 | |
| 7916 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) |
| 7917 | { |
| 7918 | uint32_t tmp; |
| 7919 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7920 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7921 | tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; |
| 7922 | return tmp; |
| 7923 | } |
| 7924 | |
| 7925 | static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7926 | { |
| 7927 | RTC_CRITICAL_SECTION_ENTER(); |
| 7928 | ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); |
| 7929 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7930 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7931 | } |
| 7932 | |
| 7933 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, |
| 7934 | hri_rtcmode2_clock_reg_t mask) |
| 7935 | { |
| 7936 | uint32_t tmp; |
| 7937 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7938 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7939 | tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; |
| 7940 | return tmp; |
| 7941 | } |
| 7942 | |
| 7943 | static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) |
| 7944 | { |
| 7945 | uint32_t tmp; |
| 7946 | RTC_CRITICAL_SECTION_ENTER(); |
| 7947 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7948 | tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; |
| 7949 | tmp |= RTC_MODE2_CLOCK_DAY(data); |
| 7950 | ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; |
| 7951 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7952 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7953 | } |
| 7954 | |
| 7955 | static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7956 | { |
| 7957 | RTC_CRITICAL_SECTION_ENTER(); |
| 7958 | ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); |
| 7959 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7960 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7961 | } |
| 7962 | |
| 7963 | static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7964 | { |
| 7965 | RTC_CRITICAL_SECTION_ENTER(); |
| 7966 | ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); |
| 7967 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7968 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7969 | } |
| 7970 | |
| 7971 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) |
| 7972 | { |
| 7973 | uint32_t tmp; |
| 7974 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7975 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7976 | tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; |
| 7977 | return tmp; |
| 7978 | } |
| 7979 | |
| 7980 | static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 7981 | { |
| 7982 | RTC_CRITICAL_SECTION_ENTER(); |
| 7983 | ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); |
| 7984 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7985 | RTC_CRITICAL_SECTION_LEAVE(); |
| 7986 | } |
| 7987 | |
| 7988 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, |
| 7989 | hri_rtcmode2_clock_reg_t mask) |
| 7990 | { |
| 7991 | uint32_t tmp; |
| 7992 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 7993 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 7994 | tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; |
| 7995 | return tmp; |
| 7996 | } |
| 7997 | |
| 7998 | static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) |
| 7999 | { |
| 8000 | uint32_t tmp; |
| 8001 | RTC_CRITICAL_SECTION_ENTER(); |
| 8002 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 8003 | tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; |
| 8004 | tmp |= RTC_MODE2_CLOCK_MONTH(data); |
| 8005 | ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; |
| 8006 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8007 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8008 | } |
| 8009 | |
| 8010 | static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8011 | { |
| 8012 | RTC_CRITICAL_SECTION_ENTER(); |
| 8013 | ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); |
| 8014 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8015 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8016 | } |
| 8017 | |
| 8018 | static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8019 | { |
| 8020 | RTC_CRITICAL_SECTION_ENTER(); |
| 8021 | ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); |
| 8022 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8023 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8024 | } |
| 8025 | |
| 8026 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) |
| 8027 | { |
| 8028 | uint32_t tmp; |
| 8029 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8030 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 8031 | tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; |
| 8032 | return tmp; |
| 8033 | } |
| 8034 | |
| 8035 | static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8036 | { |
| 8037 | RTC_CRITICAL_SECTION_ENTER(); |
| 8038 | ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); |
| 8039 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8040 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8041 | } |
| 8042 | |
| 8043 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, |
| 8044 | hri_rtcmode2_clock_reg_t mask) |
| 8045 | { |
| 8046 | uint32_t tmp; |
| 8047 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8048 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 8049 | tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; |
| 8050 | return tmp; |
| 8051 | } |
| 8052 | |
| 8053 | static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) |
| 8054 | { |
| 8055 | uint32_t tmp; |
| 8056 | RTC_CRITICAL_SECTION_ENTER(); |
| 8057 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 8058 | tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; |
| 8059 | tmp |= RTC_MODE2_CLOCK_YEAR(data); |
| 8060 | ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; |
| 8061 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8062 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8063 | } |
| 8064 | |
| 8065 | static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8066 | { |
| 8067 | RTC_CRITICAL_SECTION_ENTER(); |
| 8068 | ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); |
| 8069 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8070 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8071 | } |
| 8072 | |
| 8073 | static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8074 | { |
| 8075 | RTC_CRITICAL_SECTION_ENTER(); |
| 8076 | ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); |
| 8077 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8078 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8079 | } |
| 8080 | |
| 8081 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) |
| 8082 | { |
| 8083 | uint32_t tmp; |
| 8084 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8085 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 8086 | tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; |
| 8087 | return tmp; |
| 8088 | } |
| 8089 | |
| 8090 | static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8091 | { |
| 8092 | RTC_CRITICAL_SECTION_ENTER(); |
| 8093 | ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; |
| 8094 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8095 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8096 | } |
| 8097 | |
| 8098 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8099 | { |
| 8100 | uint32_t tmp; |
| 8101 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8102 | tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 8103 | tmp &= mask; |
| 8104 | return tmp; |
| 8105 | } |
| 8106 | |
| 8107 | static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) |
| 8108 | { |
| 8109 | RTC_CRITICAL_SECTION_ENTER(); |
| 8110 | ((Rtc *)hw)->MODE2.CLOCK.reg = data; |
| 8111 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8112 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8113 | } |
| 8114 | |
| 8115 | static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8116 | { |
| 8117 | RTC_CRITICAL_SECTION_ENTER(); |
| 8118 | ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; |
| 8119 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8120 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8121 | } |
| 8122 | |
| 8123 | static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) |
| 8124 | { |
| 8125 | RTC_CRITICAL_SECTION_ENTER(); |
| 8126 | ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; |
| 8127 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8128 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8129 | } |
| 8130 | |
| 8131 | static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) |
| 8132 | { |
| 8133 | hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); |
| 8134 | return ((Rtc *)hw)->MODE2.CLOCK.reg; |
| 8135 | } |
| 8136 | |
| 8137 | static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8138 | { |
| 8139 | RTC_CRITICAL_SECTION_ENTER(); |
| 8140 | ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); |
| 8141 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8142 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8143 | } |
| 8144 | |
| 8145 | static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8146 | { |
| 8147 | uint16_t tmp; |
| 8148 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8149 | tmp = ((Rtc *)hw)->MODE1.PER.reg; |
| 8150 | tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; |
| 8151 | return tmp; |
| 8152 | } |
| 8153 | |
| 8154 | static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) |
| 8155 | { |
| 8156 | uint16_t tmp; |
| 8157 | RTC_CRITICAL_SECTION_ENTER(); |
| 8158 | tmp = ((Rtc *)hw)->MODE1.PER.reg; |
| 8159 | tmp &= ~RTC_MODE1_PER_PER_Msk; |
| 8160 | tmp |= RTC_MODE1_PER_PER(data); |
| 8161 | ((Rtc *)hw)->MODE1.PER.reg = tmp; |
| 8162 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8163 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8164 | } |
| 8165 | |
| 8166 | static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8167 | { |
| 8168 | RTC_CRITICAL_SECTION_ENTER(); |
| 8169 | ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); |
| 8170 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8171 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8172 | } |
| 8173 | |
| 8174 | static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8175 | { |
| 8176 | RTC_CRITICAL_SECTION_ENTER(); |
| 8177 | ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); |
| 8178 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8179 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8180 | } |
| 8181 | |
| 8182 | static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) |
| 8183 | { |
| 8184 | uint16_t tmp; |
| 8185 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8186 | tmp = ((Rtc *)hw)->MODE1.PER.reg; |
| 8187 | tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; |
| 8188 | return tmp; |
| 8189 | } |
| 8190 | |
| 8191 | static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8192 | { |
| 8193 | RTC_CRITICAL_SECTION_ENTER(); |
| 8194 | ((Rtc *)hw)->MODE1.PER.reg |= mask; |
| 8195 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8196 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8197 | } |
| 8198 | |
| 8199 | static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8200 | { |
| 8201 | uint16_t tmp; |
| 8202 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8203 | tmp = ((Rtc *)hw)->MODE1.PER.reg; |
| 8204 | tmp &= mask; |
| 8205 | return tmp; |
| 8206 | } |
| 8207 | |
| 8208 | static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) |
| 8209 | { |
| 8210 | RTC_CRITICAL_SECTION_ENTER(); |
| 8211 | ((Rtc *)hw)->MODE1.PER.reg = data; |
| 8212 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8213 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8214 | } |
| 8215 | |
| 8216 | static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8217 | { |
| 8218 | RTC_CRITICAL_SECTION_ENTER(); |
| 8219 | ((Rtc *)hw)->MODE1.PER.reg &= ~mask; |
| 8220 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8221 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8222 | } |
| 8223 | |
| 8224 | static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) |
| 8225 | { |
| 8226 | RTC_CRITICAL_SECTION_ENTER(); |
| 8227 | ((Rtc *)hw)->MODE1.PER.reg ^= mask; |
| 8228 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8229 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8230 | } |
| 8231 | |
| 8232 | static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) |
| 8233 | { |
| 8234 | hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); |
| 8235 | return ((Rtc *)hw)->MODE1.PER.reg; |
| 8236 | } |
| 8237 | |
| 8238 | static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) |
| 8239 | { |
| 8240 | RTC_CRITICAL_SECTION_ENTER(); |
| 8241 | ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); |
| 8242 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8243 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8244 | } |
| 8245 | |
| 8246 | static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, |
| 8247 | hri_rtcmode0_comp_reg_t mask) |
| 8248 | { |
| 8249 | uint32_t tmp; |
| 8250 | tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; |
| 8251 | tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; |
| 8252 | return tmp; |
| 8253 | } |
| 8254 | |
| 8255 | static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) |
| 8256 | { |
| 8257 | uint32_t tmp; |
| 8258 | RTC_CRITICAL_SECTION_ENTER(); |
| 8259 | tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; |
| 8260 | tmp &= ~RTC_MODE0_COMP_COMP_Msk; |
| 8261 | tmp |= RTC_MODE0_COMP_COMP(data); |
| 8262 | ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; |
| 8263 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8264 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8265 | } |
| 8266 | |
| 8267 | static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) |
| 8268 | { |
| 8269 | RTC_CRITICAL_SECTION_ENTER(); |
| 8270 | ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); |
| 8271 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8272 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8273 | } |
| 8274 | |
| 8275 | static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) |
| 8276 | { |
| 8277 | RTC_CRITICAL_SECTION_ENTER(); |
| 8278 | ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); |
| 8279 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8280 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8281 | } |
| 8282 | |
| 8283 | static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) |
| 8284 | { |
| 8285 | uint32_t tmp; |
| 8286 | tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; |
| 8287 | tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; |
| 8288 | return tmp; |
| 8289 | } |
| 8290 | |
| 8291 | static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) |
| 8292 | { |
| 8293 | RTC_CRITICAL_SECTION_ENTER(); |
| 8294 | ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; |
| 8295 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8296 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8297 | } |
| 8298 | |
| 8299 | static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, |
| 8300 | hri_rtcmode0_comp_reg_t mask) |
| 8301 | { |
| 8302 | uint32_t tmp; |
| 8303 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8304 | tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; |
| 8305 | tmp &= mask; |
| 8306 | return tmp; |
| 8307 | } |
| 8308 | |
| 8309 | static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) |
| 8310 | { |
| 8311 | RTC_CRITICAL_SECTION_ENTER(); |
| 8312 | ((Rtc *)hw)->MODE0.COMP[index].reg = data; |
| 8313 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8314 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8315 | } |
| 8316 | |
| 8317 | static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) |
| 8318 | { |
| 8319 | RTC_CRITICAL_SECTION_ENTER(); |
| 8320 | ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; |
| 8321 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8322 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8323 | } |
| 8324 | |
| 8325 | static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) |
| 8326 | { |
| 8327 | RTC_CRITICAL_SECTION_ENTER(); |
| 8328 | ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; |
| 8329 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8330 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8331 | } |
| 8332 | |
| 8333 | static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) |
| 8334 | { |
| 8335 | hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); |
| 8336 | return ((Rtc *)hw)->MODE0.COMP[index].reg; |
| 8337 | } |
| 8338 | |
| 8339 | static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) |
| 8340 | { |
| 8341 | RTC_CRITICAL_SECTION_ENTER(); |
| 8342 | ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); |
| 8343 | hri_rtcmode1_wait_for_sync( |
| 8344 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8345 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8346 | } |
| 8347 | |
| 8348 | static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, |
| 8349 | hri_rtcmode1_comp_reg_t mask) |
| 8350 | { |
| 8351 | uint16_t tmp; |
| 8352 | tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; |
| 8353 | tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; |
| 8354 | return tmp; |
| 8355 | } |
| 8356 | |
| 8357 | static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) |
| 8358 | { |
| 8359 | uint16_t tmp; |
| 8360 | RTC_CRITICAL_SECTION_ENTER(); |
| 8361 | tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; |
| 8362 | tmp &= ~RTC_MODE1_COMP_COMP_Msk; |
| 8363 | tmp |= RTC_MODE1_COMP_COMP(data); |
| 8364 | ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; |
| 8365 | hri_rtcmode1_wait_for_sync( |
| 8366 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8367 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8368 | } |
| 8369 | |
| 8370 | static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) |
| 8371 | { |
| 8372 | RTC_CRITICAL_SECTION_ENTER(); |
| 8373 | ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); |
| 8374 | hri_rtcmode1_wait_for_sync( |
| 8375 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8376 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8377 | } |
| 8378 | |
| 8379 | static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) |
| 8380 | { |
| 8381 | RTC_CRITICAL_SECTION_ENTER(); |
| 8382 | ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); |
| 8383 | hri_rtcmode1_wait_for_sync( |
| 8384 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8385 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8386 | } |
| 8387 | |
| 8388 | static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) |
| 8389 | { |
| 8390 | uint16_t tmp; |
| 8391 | tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; |
| 8392 | tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; |
| 8393 | return tmp; |
| 8394 | } |
| 8395 | |
| 8396 | static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) |
| 8397 | { |
| 8398 | RTC_CRITICAL_SECTION_ENTER(); |
| 8399 | ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; |
| 8400 | hri_rtcmode1_wait_for_sync( |
| 8401 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8402 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8403 | } |
| 8404 | |
| 8405 | static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, |
| 8406 | hri_rtcmode1_comp_reg_t mask) |
| 8407 | { |
| 8408 | uint16_t tmp; |
| 8409 | hri_rtcmode1_wait_for_sync( |
| 8410 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8411 | tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; |
| 8412 | tmp &= mask; |
| 8413 | return tmp; |
| 8414 | } |
| 8415 | |
| 8416 | static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) |
| 8417 | { |
| 8418 | RTC_CRITICAL_SECTION_ENTER(); |
| 8419 | ((Rtc *)hw)->MODE1.COMP[index].reg = data; |
| 8420 | hri_rtcmode1_wait_for_sync( |
| 8421 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8422 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8423 | } |
| 8424 | |
| 8425 | static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) |
| 8426 | { |
| 8427 | RTC_CRITICAL_SECTION_ENTER(); |
| 8428 | ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; |
| 8429 | hri_rtcmode1_wait_for_sync( |
| 8430 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8431 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8432 | } |
| 8433 | |
| 8434 | static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) |
| 8435 | { |
| 8436 | RTC_CRITICAL_SECTION_ENTER(); |
| 8437 | ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; |
| 8438 | hri_rtcmode1_wait_for_sync( |
| 8439 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8440 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8441 | } |
| 8442 | |
| 8443 | static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) |
| 8444 | { |
| 8445 | hri_rtcmode1_wait_for_sync( |
| 8446 | hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); |
| 8447 | return ((Rtc *)hw)->MODE1.COMP[index].reg; |
| 8448 | } |
| 8449 | |
| 8450 | static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8451 | { |
| 8452 | RTC_CRITICAL_SECTION_ENTER(); |
| 8453 | ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); |
| 8454 | hri_rtcmode0_wait_for_sync( |
| 8455 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8456 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8457 | } |
| 8458 | |
| 8459 | static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8460 | { |
| 8461 | uint32_t tmp; |
| 8462 | tmp = ((Rtc *)hw)->MODE0.GP[index].reg; |
| 8463 | tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; |
| 8464 | return tmp; |
| 8465 | } |
| 8466 | |
| 8467 | static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) |
| 8468 | { |
| 8469 | uint32_t tmp; |
| 8470 | RTC_CRITICAL_SECTION_ENTER(); |
| 8471 | tmp = ((Rtc *)hw)->MODE0.GP[index].reg; |
| 8472 | tmp &= ~RTC_GP_GP_Msk; |
| 8473 | tmp |= RTC_GP_GP(data); |
| 8474 | ((Rtc *)hw)->MODE0.GP[index].reg = tmp; |
| 8475 | hri_rtcmode0_wait_for_sync( |
| 8476 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8477 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8478 | } |
| 8479 | |
| 8480 | static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8481 | { |
| 8482 | RTC_CRITICAL_SECTION_ENTER(); |
| 8483 | ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); |
| 8484 | hri_rtcmode0_wait_for_sync( |
| 8485 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8486 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8487 | } |
| 8488 | |
| 8489 | static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8490 | { |
| 8491 | RTC_CRITICAL_SECTION_ENTER(); |
| 8492 | ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); |
| 8493 | hri_rtcmode0_wait_for_sync( |
| 8494 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8495 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8496 | } |
| 8497 | |
| 8498 | static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) |
| 8499 | { |
| 8500 | uint32_t tmp; |
| 8501 | tmp = ((Rtc *)hw)->MODE0.GP[index].reg; |
| 8502 | tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; |
| 8503 | return tmp; |
| 8504 | } |
| 8505 | |
| 8506 | static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8507 | { |
| 8508 | RTC_CRITICAL_SECTION_ENTER(); |
| 8509 | ((Rtc *)hw)->MODE0.GP[index].reg |= mask; |
| 8510 | hri_rtcmode0_wait_for_sync( |
| 8511 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8512 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8513 | } |
| 8514 | |
| 8515 | static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8516 | { |
| 8517 | uint32_t tmp; |
| 8518 | hri_rtcmode0_wait_for_sync( |
| 8519 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8520 | tmp = ((Rtc *)hw)->MODE0.GP[index].reg; |
| 8521 | tmp &= mask; |
| 8522 | return tmp; |
| 8523 | } |
| 8524 | |
| 8525 | static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) |
| 8526 | { |
| 8527 | RTC_CRITICAL_SECTION_ENTER(); |
| 8528 | ((Rtc *)hw)->MODE0.GP[index].reg = data; |
| 8529 | hri_rtcmode0_wait_for_sync( |
| 8530 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8531 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8532 | } |
| 8533 | |
| 8534 | static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8535 | { |
| 8536 | RTC_CRITICAL_SECTION_ENTER(); |
| 8537 | ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; |
| 8538 | hri_rtcmode0_wait_for_sync( |
| 8539 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8540 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8541 | } |
| 8542 | |
| 8543 | static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) |
| 8544 | { |
| 8545 | RTC_CRITICAL_SECTION_ENTER(); |
| 8546 | ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; |
| 8547 | hri_rtcmode0_wait_for_sync( |
| 8548 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8549 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8550 | } |
| 8551 | |
| 8552 | static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) |
| 8553 | { |
| 8554 | hri_rtcmode0_wait_for_sync( |
| 8555 | hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); |
| 8556 | return ((Rtc *)hw)->MODE0.GP[index].reg; |
| 8557 | } |
| 8558 | |
| 8559 | static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) |
| 8560 | { |
| 8561 | RTC_CRITICAL_SECTION_ENTER(); |
| 8562 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; |
| 8563 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8564 | } |
| 8565 | |
| 8566 | static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) |
| 8567 | { |
| 8568 | uint32_t tmp; |
| 8569 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8570 | tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; |
| 8571 | return (bool)tmp; |
| 8572 | } |
| 8573 | |
| 8574 | static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) |
| 8575 | { |
| 8576 | uint32_t tmp; |
| 8577 | RTC_CRITICAL_SECTION_ENTER(); |
| 8578 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8579 | tmp &= ~RTC_TAMPCTRL_TAMLVL0; |
| 8580 | tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; |
| 8581 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8582 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8583 | } |
| 8584 | |
| 8585 | static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) |
| 8586 | { |
| 8587 | RTC_CRITICAL_SECTION_ENTER(); |
| 8588 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; |
| 8589 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8590 | } |
| 8591 | |
| 8592 | static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) |
| 8593 | { |
| 8594 | RTC_CRITICAL_SECTION_ENTER(); |
| 8595 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; |
| 8596 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8597 | } |
| 8598 | |
| 8599 | static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) |
| 8600 | { |
| 8601 | RTC_CRITICAL_SECTION_ENTER(); |
| 8602 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; |
| 8603 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8604 | } |
| 8605 | |
| 8606 | static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) |
| 8607 | { |
| 8608 | uint32_t tmp; |
| 8609 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8610 | tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; |
| 8611 | return (bool)tmp; |
| 8612 | } |
| 8613 | |
| 8614 | static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) |
| 8615 | { |
| 8616 | uint32_t tmp; |
| 8617 | RTC_CRITICAL_SECTION_ENTER(); |
| 8618 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8619 | tmp &= ~RTC_TAMPCTRL_TAMLVL1; |
| 8620 | tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; |
| 8621 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8622 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8623 | } |
| 8624 | |
| 8625 | static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) |
| 8626 | { |
| 8627 | RTC_CRITICAL_SECTION_ENTER(); |
| 8628 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; |
| 8629 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8630 | } |
| 8631 | |
| 8632 | static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) |
| 8633 | { |
| 8634 | RTC_CRITICAL_SECTION_ENTER(); |
| 8635 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; |
| 8636 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8637 | } |
| 8638 | |
| 8639 | static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) |
| 8640 | { |
| 8641 | RTC_CRITICAL_SECTION_ENTER(); |
| 8642 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; |
| 8643 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8644 | } |
| 8645 | |
| 8646 | static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) |
| 8647 | { |
| 8648 | uint32_t tmp; |
| 8649 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8650 | tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; |
| 8651 | return (bool)tmp; |
| 8652 | } |
| 8653 | |
| 8654 | static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) |
| 8655 | { |
| 8656 | uint32_t tmp; |
| 8657 | RTC_CRITICAL_SECTION_ENTER(); |
| 8658 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8659 | tmp &= ~RTC_TAMPCTRL_TAMLVL2; |
| 8660 | tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; |
| 8661 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8662 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8663 | } |
| 8664 | |
| 8665 | static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) |
| 8666 | { |
| 8667 | RTC_CRITICAL_SECTION_ENTER(); |
| 8668 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; |
| 8669 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8670 | } |
| 8671 | |
| 8672 | static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) |
| 8673 | { |
| 8674 | RTC_CRITICAL_SECTION_ENTER(); |
| 8675 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; |
| 8676 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8677 | } |
| 8678 | |
| 8679 | static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) |
| 8680 | { |
| 8681 | RTC_CRITICAL_SECTION_ENTER(); |
| 8682 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; |
| 8683 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8684 | } |
| 8685 | |
| 8686 | static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) |
| 8687 | { |
| 8688 | uint32_t tmp; |
| 8689 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8690 | tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; |
| 8691 | return (bool)tmp; |
| 8692 | } |
| 8693 | |
| 8694 | static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) |
| 8695 | { |
| 8696 | uint32_t tmp; |
| 8697 | RTC_CRITICAL_SECTION_ENTER(); |
| 8698 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8699 | tmp &= ~RTC_TAMPCTRL_TAMLVL3; |
| 8700 | tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; |
| 8701 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8702 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8703 | } |
| 8704 | |
| 8705 | static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) |
| 8706 | { |
| 8707 | RTC_CRITICAL_SECTION_ENTER(); |
| 8708 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; |
| 8709 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8710 | } |
| 8711 | |
| 8712 | static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) |
| 8713 | { |
| 8714 | RTC_CRITICAL_SECTION_ENTER(); |
| 8715 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; |
| 8716 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8717 | } |
| 8718 | |
| 8719 | static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) |
| 8720 | { |
| 8721 | RTC_CRITICAL_SECTION_ENTER(); |
| 8722 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; |
| 8723 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8724 | } |
| 8725 | |
| 8726 | static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) |
| 8727 | { |
| 8728 | uint32_t tmp; |
| 8729 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8730 | tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; |
| 8731 | return (bool)tmp; |
| 8732 | } |
| 8733 | |
| 8734 | static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) |
| 8735 | { |
| 8736 | uint32_t tmp; |
| 8737 | RTC_CRITICAL_SECTION_ENTER(); |
| 8738 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8739 | tmp &= ~RTC_TAMPCTRL_TAMLVL4; |
| 8740 | tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; |
| 8741 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8742 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8743 | } |
| 8744 | |
| 8745 | static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) |
| 8746 | { |
| 8747 | RTC_CRITICAL_SECTION_ENTER(); |
| 8748 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; |
| 8749 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8750 | } |
| 8751 | |
| 8752 | static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) |
| 8753 | { |
| 8754 | RTC_CRITICAL_SECTION_ENTER(); |
| 8755 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; |
| 8756 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8757 | } |
| 8758 | |
| 8759 | static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) |
| 8760 | { |
| 8761 | RTC_CRITICAL_SECTION_ENTER(); |
| 8762 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; |
| 8763 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8764 | } |
| 8765 | |
| 8766 | static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) |
| 8767 | { |
| 8768 | uint32_t tmp; |
| 8769 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8770 | tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; |
| 8771 | return (bool)tmp; |
| 8772 | } |
| 8773 | |
| 8774 | static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) |
| 8775 | { |
| 8776 | uint32_t tmp; |
| 8777 | RTC_CRITICAL_SECTION_ENTER(); |
| 8778 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8779 | tmp &= ~RTC_TAMPCTRL_DEBNC0; |
| 8780 | tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; |
| 8781 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8782 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8783 | } |
| 8784 | |
| 8785 | static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) |
| 8786 | { |
| 8787 | RTC_CRITICAL_SECTION_ENTER(); |
| 8788 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; |
| 8789 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8790 | } |
| 8791 | |
| 8792 | static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) |
| 8793 | { |
| 8794 | RTC_CRITICAL_SECTION_ENTER(); |
| 8795 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; |
| 8796 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8797 | } |
| 8798 | |
| 8799 | static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) |
| 8800 | { |
| 8801 | RTC_CRITICAL_SECTION_ENTER(); |
| 8802 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; |
| 8803 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8804 | } |
| 8805 | |
| 8806 | static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) |
| 8807 | { |
| 8808 | uint32_t tmp; |
| 8809 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8810 | tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; |
| 8811 | return (bool)tmp; |
| 8812 | } |
| 8813 | |
| 8814 | static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) |
| 8815 | { |
| 8816 | uint32_t tmp; |
| 8817 | RTC_CRITICAL_SECTION_ENTER(); |
| 8818 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8819 | tmp &= ~RTC_TAMPCTRL_DEBNC1; |
| 8820 | tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; |
| 8821 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8822 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8823 | } |
| 8824 | |
| 8825 | static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) |
| 8826 | { |
| 8827 | RTC_CRITICAL_SECTION_ENTER(); |
| 8828 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; |
| 8829 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8830 | } |
| 8831 | |
| 8832 | static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) |
| 8833 | { |
| 8834 | RTC_CRITICAL_SECTION_ENTER(); |
| 8835 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; |
| 8836 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8837 | } |
| 8838 | |
| 8839 | static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) |
| 8840 | { |
| 8841 | RTC_CRITICAL_SECTION_ENTER(); |
| 8842 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; |
| 8843 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8844 | } |
| 8845 | |
| 8846 | static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) |
| 8847 | { |
| 8848 | uint32_t tmp; |
| 8849 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8850 | tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; |
| 8851 | return (bool)tmp; |
| 8852 | } |
| 8853 | |
| 8854 | static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) |
| 8855 | { |
| 8856 | uint32_t tmp; |
| 8857 | RTC_CRITICAL_SECTION_ENTER(); |
| 8858 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8859 | tmp &= ~RTC_TAMPCTRL_DEBNC2; |
| 8860 | tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; |
| 8861 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8862 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8863 | } |
| 8864 | |
| 8865 | static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) |
| 8866 | { |
| 8867 | RTC_CRITICAL_SECTION_ENTER(); |
| 8868 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; |
| 8869 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8870 | } |
| 8871 | |
| 8872 | static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) |
| 8873 | { |
| 8874 | RTC_CRITICAL_SECTION_ENTER(); |
| 8875 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; |
| 8876 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8877 | } |
| 8878 | |
| 8879 | static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) |
| 8880 | { |
| 8881 | RTC_CRITICAL_SECTION_ENTER(); |
| 8882 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; |
| 8883 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8884 | } |
| 8885 | |
| 8886 | static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) |
| 8887 | { |
| 8888 | uint32_t tmp; |
| 8889 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8890 | tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; |
| 8891 | return (bool)tmp; |
| 8892 | } |
| 8893 | |
| 8894 | static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) |
| 8895 | { |
| 8896 | uint32_t tmp; |
| 8897 | RTC_CRITICAL_SECTION_ENTER(); |
| 8898 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8899 | tmp &= ~RTC_TAMPCTRL_DEBNC3; |
| 8900 | tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; |
| 8901 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8902 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8903 | } |
| 8904 | |
| 8905 | static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) |
| 8906 | { |
| 8907 | RTC_CRITICAL_SECTION_ENTER(); |
| 8908 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; |
| 8909 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8910 | } |
| 8911 | |
| 8912 | static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) |
| 8913 | { |
| 8914 | RTC_CRITICAL_SECTION_ENTER(); |
| 8915 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; |
| 8916 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8917 | } |
| 8918 | |
| 8919 | static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) |
| 8920 | { |
| 8921 | RTC_CRITICAL_SECTION_ENTER(); |
| 8922 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; |
| 8923 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8924 | } |
| 8925 | |
| 8926 | static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) |
| 8927 | { |
| 8928 | uint32_t tmp; |
| 8929 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8930 | tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; |
| 8931 | return (bool)tmp; |
| 8932 | } |
| 8933 | |
| 8934 | static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) |
| 8935 | { |
| 8936 | uint32_t tmp; |
| 8937 | RTC_CRITICAL_SECTION_ENTER(); |
| 8938 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8939 | tmp &= ~RTC_TAMPCTRL_DEBNC4; |
| 8940 | tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; |
| 8941 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8942 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8943 | } |
| 8944 | |
| 8945 | static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) |
| 8946 | { |
| 8947 | RTC_CRITICAL_SECTION_ENTER(); |
| 8948 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; |
| 8949 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8950 | } |
| 8951 | |
| 8952 | static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) |
| 8953 | { |
| 8954 | RTC_CRITICAL_SECTION_ENTER(); |
| 8955 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; |
| 8956 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8957 | } |
| 8958 | |
| 8959 | static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 8960 | { |
| 8961 | RTC_CRITICAL_SECTION_ENTER(); |
| 8962 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); |
| 8963 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8964 | } |
| 8965 | |
| 8966 | static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 8967 | { |
| 8968 | uint32_t tmp; |
| 8969 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8970 | tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; |
| 8971 | return tmp; |
| 8972 | } |
| 8973 | |
| 8974 | static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) |
| 8975 | { |
| 8976 | uint32_t tmp; |
| 8977 | RTC_CRITICAL_SECTION_ENTER(); |
| 8978 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 8979 | tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; |
| 8980 | tmp |= RTC_TAMPCTRL_IN0ACT(data); |
| 8981 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 8982 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8983 | } |
| 8984 | |
| 8985 | static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 8986 | { |
| 8987 | RTC_CRITICAL_SECTION_ENTER(); |
| 8988 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); |
| 8989 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8990 | } |
| 8991 | |
| 8992 | static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 8993 | { |
| 8994 | RTC_CRITICAL_SECTION_ENTER(); |
| 8995 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); |
| 8996 | RTC_CRITICAL_SECTION_LEAVE(); |
| 8997 | } |
| 8998 | |
| 8999 | static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) |
| 9000 | { |
| 9001 | uint32_t tmp; |
| 9002 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9003 | tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; |
| 9004 | return tmp; |
| 9005 | } |
| 9006 | |
| 9007 | static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9008 | { |
| 9009 | RTC_CRITICAL_SECTION_ENTER(); |
| 9010 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); |
| 9011 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9012 | } |
| 9013 | |
| 9014 | static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9015 | { |
| 9016 | uint32_t tmp; |
| 9017 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9018 | tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; |
| 9019 | return tmp; |
| 9020 | } |
| 9021 | |
| 9022 | static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) |
| 9023 | { |
| 9024 | uint32_t tmp; |
| 9025 | RTC_CRITICAL_SECTION_ENTER(); |
| 9026 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9027 | tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; |
| 9028 | tmp |= RTC_TAMPCTRL_IN1ACT(data); |
| 9029 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 9030 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9031 | } |
| 9032 | |
| 9033 | static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9034 | { |
| 9035 | RTC_CRITICAL_SECTION_ENTER(); |
| 9036 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); |
| 9037 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9038 | } |
| 9039 | |
| 9040 | static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9041 | { |
| 9042 | RTC_CRITICAL_SECTION_ENTER(); |
| 9043 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); |
| 9044 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9045 | } |
| 9046 | |
| 9047 | static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) |
| 9048 | { |
| 9049 | uint32_t tmp; |
| 9050 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9051 | tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; |
| 9052 | return tmp; |
| 9053 | } |
| 9054 | |
| 9055 | static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9056 | { |
| 9057 | RTC_CRITICAL_SECTION_ENTER(); |
| 9058 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); |
| 9059 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9060 | } |
| 9061 | |
| 9062 | static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9063 | { |
| 9064 | uint32_t tmp; |
| 9065 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9066 | tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; |
| 9067 | return tmp; |
| 9068 | } |
| 9069 | |
| 9070 | static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) |
| 9071 | { |
| 9072 | uint32_t tmp; |
| 9073 | RTC_CRITICAL_SECTION_ENTER(); |
| 9074 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9075 | tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; |
| 9076 | tmp |= RTC_TAMPCTRL_IN2ACT(data); |
| 9077 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 9078 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9079 | } |
| 9080 | |
| 9081 | static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9082 | { |
| 9083 | RTC_CRITICAL_SECTION_ENTER(); |
| 9084 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); |
| 9085 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9086 | } |
| 9087 | |
| 9088 | static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9089 | { |
| 9090 | RTC_CRITICAL_SECTION_ENTER(); |
| 9091 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); |
| 9092 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9093 | } |
| 9094 | |
| 9095 | static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) |
| 9096 | { |
| 9097 | uint32_t tmp; |
| 9098 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9099 | tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; |
| 9100 | return tmp; |
| 9101 | } |
| 9102 | |
| 9103 | static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9104 | { |
| 9105 | RTC_CRITICAL_SECTION_ENTER(); |
| 9106 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); |
| 9107 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9108 | } |
| 9109 | |
| 9110 | static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9111 | { |
| 9112 | uint32_t tmp; |
| 9113 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9114 | tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; |
| 9115 | return tmp; |
| 9116 | } |
| 9117 | |
| 9118 | static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) |
| 9119 | { |
| 9120 | uint32_t tmp; |
| 9121 | RTC_CRITICAL_SECTION_ENTER(); |
| 9122 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9123 | tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; |
| 9124 | tmp |= RTC_TAMPCTRL_IN3ACT(data); |
| 9125 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 9126 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9127 | } |
| 9128 | |
| 9129 | static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9130 | { |
| 9131 | RTC_CRITICAL_SECTION_ENTER(); |
| 9132 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); |
| 9133 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9134 | } |
| 9135 | |
| 9136 | static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9137 | { |
| 9138 | RTC_CRITICAL_SECTION_ENTER(); |
| 9139 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); |
| 9140 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9141 | } |
| 9142 | |
| 9143 | static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) |
| 9144 | { |
| 9145 | uint32_t tmp; |
| 9146 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9147 | tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; |
| 9148 | return tmp; |
| 9149 | } |
| 9150 | |
| 9151 | static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9152 | { |
| 9153 | RTC_CRITICAL_SECTION_ENTER(); |
| 9154 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); |
| 9155 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9156 | } |
| 9157 | |
| 9158 | static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9159 | { |
| 9160 | uint32_t tmp; |
| 9161 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9162 | tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; |
| 9163 | return tmp; |
| 9164 | } |
| 9165 | |
| 9166 | static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) |
| 9167 | { |
| 9168 | uint32_t tmp; |
| 9169 | RTC_CRITICAL_SECTION_ENTER(); |
| 9170 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9171 | tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; |
| 9172 | tmp |= RTC_TAMPCTRL_IN4ACT(data); |
| 9173 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; |
| 9174 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9175 | } |
| 9176 | |
| 9177 | static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9178 | { |
| 9179 | RTC_CRITICAL_SECTION_ENTER(); |
| 9180 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); |
| 9181 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9182 | } |
| 9183 | |
| 9184 | static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9185 | { |
| 9186 | RTC_CRITICAL_SECTION_ENTER(); |
| 9187 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); |
| 9188 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9189 | } |
| 9190 | |
| 9191 | static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) |
| 9192 | { |
| 9193 | uint32_t tmp; |
| 9194 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9195 | tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; |
| 9196 | return tmp; |
| 9197 | } |
| 9198 | |
| 9199 | static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9200 | { |
| 9201 | RTC_CRITICAL_SECTION_ENTER(); |
| 9202 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; |
| 9203 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9204 | } |
| 9205 | |
| 9206 | static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9207 | { |
| 9208 | uint32_t tmp; |
| 9209 | tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9210 | tmp &= mask; |
| 9211 | return tmp; |
| 9212 | } |
| 9213 | |
| 9214 | static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) |
| 9215 | { |
| 9216 | RTC_CRITICAL_SECTION_ENTER(); |
| 9217 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; |
| 9218 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9219 | } |
| 9220 | |
| 9221 | static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9222 | { |
| 9223 | RTC_CRITICAL_SECTION_ENTER(); |
| 9224 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; |
| 9225 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9226 | } |
| 9227 | |
| 9228 | static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) |
| 9229 | { |
| 9230 | RTC_CRITICAL_SECTION_ENTER(); |
| 9231 | ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; |
| 9232 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9233 | } |
| 9234 | |
| 9235 | static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) |
| 9236 | { |
| 9237 | return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; |
| 9238 | } |
| 9239 | |
| 9240 | static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) |
| 9241 | { |
| 9242 | RTC_CRITICAL_SECTION_ENTER(); |
| 9243 | ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; |
| 9244 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9245 | } |
| 9246 | |
| 9247 | static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) |
| 9248 | { |
| 9249 | uint32_t tmp; |
| 9250 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9251 | tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; |
| 9252 | return (bool)tmp; |
| 9253 | } |
| 9254 | |
| 9255 | static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) |
| 9256 | { |
| 9257 | uint32_t tmp; |
| 9258 | RTC_CRITICAL_SECTION_ENTER(); |
| 9259 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9260 | tmp &= ~RTC_TAMPID_TAMPID0; |
| 9261 | tmp |= value << RTC_TAMPID_TAMPID0_Pos; |
| 9262 | ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; |
| 9263 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9264 | } |
| 9265 | |
| 9266 | static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) |
| 9267 | { |
| 9268 | RTC_CRITICAL_SECTION_ENTER(); |
| 9269 | ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; |
| 9270 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9271 | } |
| 9272 | |
| 9273 | static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) |
| 9274 | { |
| 9275 | RTC_CRITICAL_SECTION_ENTER(); |
| 9276 | ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; |
| 9277 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9278 | } |
| 9279 | |
| 9280 | static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) |
| 9281 | { |
| 9282 | RTC_CRITICAL_SECTION_ENTER(); |
| 9283 | ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; |
| 9284 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9285 | } |
| 9286 | |
| 9287 | static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) |
| 9288 | { |
| 9289 | uint32_t tmp; |
| 9290 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9291 | tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; |
| 9292 | return (bool)tmp; |
| 9293 | } |
| 9294 | |
| 9295 | static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) |
| 9296 | { |
| 9297 | uint32_t tmp; |
| 9298 | RTC_CRITICAL_SECTION_ENTER(); |
| 9299 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9300 | tmp &= ~RTC_TAMPID_TAMPID1; |
| 9301 | tmp |= value << RTC_TAMPID_TAMPID1_Pos; |
| 9302 | ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; |
| 9303 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9304 | } |
| 9305 | |
| 9306 | static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) |
| 9307 | { |
| 9308 | RTC_CRITICAL_SECTION_ENTER(); |
| 9309 | ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; |
| 9310 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9311 | } |
| 9312 | |
| 9313 | static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) |
| 9314 | { |
| 9315 | RTC_CRITICAL_SECTION_ENTER(); |
| 9316 | ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; |
| 9317 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9318 | } |
| 9319 | |
| 9320 | static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) |
| 9321 | { |
| 9322 | RTC_CRITICAL_SECTION_ENTER(); |
| 9323 | ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; |
| 9324 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9325 | } |
| 9326 | |
| 9327 | static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) |
| 9328 | { |
| 9329 | uint32_t tmp; |
| 9330 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9331 | tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; |
| 9332 | return (bool)tmp; |
| 9333 | } |
| 9334 | |
| 9335 | static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) |
| 9336 | { |
| 9337 | uint32_t tmp; |
| 9338 | RTC_CRITICAL_SECTION_ENTER(); |
| 9339 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9340 | tmp &= ~RTC_TAMPID_TAMPID2; |
| 9341 | tmp |= value << RTC_TAMPID_TAMPID2_Pos; |
| 9342 | ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; |
| 9343 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9344 | } |
| 9345 | |
| 9346 | static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) |
| 9347 | { |
| 9348 | RTC_CRITICAL_SECTION_ENTER(); |
| 9349 | ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; |
| 9350 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9351 | } |
| 9352 | |
| 9353 | static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) |
| 9354 | { |
| 9355 | RTC_CRITICAL_SECTION_ENTER(); |
| 9356 | ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; |
| 9357 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9358 | } |
| 9359 | |
| 9360 | static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) |
| 9361 | { |
| 9362 | RTC_CRITICAL_SECTION_ENTER(); |
| 9363 | ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; |
| 9364 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9365 | } |
| 9366 | |
| 9367 | static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) |
| 9368 | { |
| 9369 | uint32_t tmp; |
| 9370 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9371 | tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; |
| 9372 | return (bool)tmp; |
| 9373 | } |
| 9374 | |
| 9375 | static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) |
| 9376 | { |
| 9377 | uint32_t tmp; |
| 9378 | RTC_CRITICAL_SECTION_ENTER(); |
| 9379 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9380 | tmp &= ~RTC_TAMPID_TAMPID3; |
| 9381 | tmp |= value << RTC_TAMPID_TAMPID3_Pos; |
| 9382 | ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; |
| 9383 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9384 | } |
| 9385 | |
| 9386 | static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) |
| 9387 | { |
| 9388 | RTC_CRITICAL_SECTION_ENTER(); |
| 9389 | ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; |
| 9390 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9391 | } |
| 9392 | |
| 9393 | static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) |
| 9394 | { |
| 9395 | RTC_CRITICAL_SECTION_ENTER(); |
| 9396 | ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; |
| 9397 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9398 | } |
| 9399 | |
| 9400 | static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) |
| 9401 | { |
| 9402 | RTC_CRITICAL_SECTION_ENTER(); |
| 9403 | ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; |
| 9404 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9405 | } |
| 9406 | |
| 9407 | static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) |
| 9408 | { |
| 9409 | uint32_t tmp; |
| 9410 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9411 | tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; |
| 9412 | return (bool)tmp; |
| 9413 | } |
| 9414 | |
| 9415 | static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) |
| 9416 | { |
| 9417 | uint32_t tmp; |
| 9418 | RTC_CRITICAL_SECTION_ENTER(); |
| 9419 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9420 | tmp &= ~RTC_TAMPID_TAMPID4; |
| 9421 | tmp |= value << RTC_TAMPID_TAMPID4_Pos; |
| 9422 | ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; |
| 9423 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9424 | } |
| 9425 | |
| 9426 | static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) |
| 9427 | { |
| 9428 | RTC_CRITICAL_SECTION_ENTER(); |
| 9429 | ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; |
| 9430 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9431 | } |
| 9432 | |
| 9433 | static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) |
| 9434 | { |
| 9435 | RTC_CRITICAL_SECTION_ENTER(); |
| 9436 | ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; |
| 9437 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9438 | } |
| 9439 | |
| 9440 | static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) |
| 9441 | { |
| 9442 | RTC_CRITICAL_SECTION_ENTER(); |
| 9443 | ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; |
| 9444 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9445 | } |
| 9446 | |
| 9447 | static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) |
| 9448 | { |
| 9449 | uint32_t tmp; |
| 9450 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9451 | tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; |
| 9452 | return (bool)tmp; |
| 9453 | } |
| 9454 | |
| 9455 | static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) |
| 9456 | { |
| 9457 | uint32_t tmp; |
| 9458 | RTC_CRITICAL_SECTION_ENTER(); |
| 9459 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9460 | tmp &= ~RTC_TAMPID_TAMPEVT; |
| 9461 | tmp |= value << RTC_TAMPID_TAMPEVT_Pos; |
| 9462 | ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; |
| 9463 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9464 | } |
| 9465 | |
| 9466 | static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) |
| 9467 | { |
| 9468 | RTC_CRITICAL_SECTION_ENTER(); |
| 9469 | ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; |
| 9470 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9471 | } |
| 9472 | |
| 9473 | static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) |
| 9474 | { |
| 9475 | RTC_CRITICAL_SECTION_ENTER(); |
| 9476 | ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; |
| 9477 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9478 | } |
| 9479 | |
| 9480 | static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) |
| 9481 | { |
| 9482 | RTC_CRITICAL_SECTION_ENTER(); |
| 9483 | ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; |
| 9484 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9485 | } |
| 9486 | |
| 9487 | static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) |
| 9488 | { |
| 9489 | uint32_t tmp; |
| 9490 | tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9491 | tmp &= mask; |
| 9492 | return tmp; |
| 9493 | } |
| 9494 | |
| 9495 | static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) |
| 9496 | { |
| 9497 | RTC_CRITICAL_SECTION_ENTER(); |
| 9498 | ((Rtc *)hw)->MODE0.TAMPID.reg = data; |
| 9499 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9500 | } |
| 9501 | |
| 9502 | static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) |
| 9503 | { |
| 9504 | RTC_CRITICAL_SECTION_ENTER(); |
| 9505 | ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; |
| 9506 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9507 | } |
| 9508 | |
| 9509 | static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) |
| 9510 | { |
| 9511 | RTC_CRITICAL_SECTION_ENTER(); |
| 9512 | ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; |
| 9513 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9514 | } |
| 9515 | |
| 9516 | static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) |
| 9517 | { |
| 9518 | return ((Rtc *)hw)->MODE0.TAMPID.reg; |
| 9519 | } |
| 9520 | |
| 9521 | static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9522 | { |
| 9523 | RTC_CRITICAL_SECTION_ENTER(); |
| 9524 | ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); |
| 9525 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9526 | } |
| 9527 | |
| 9528 | static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9529 | { |
| 9530 | uint32_t tmp; |
| 9531 | tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; |
| 9532 | tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; |
| 9533 | return tmp; |
| 9534 | } |
| 9535 | |
| 9536 | static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) |
| 9537 | { |
| 9538 | uint32_t tmp; |
| 9539 | RTC_CRITICAL_SECTION_ENTER(); |
| 9540 | tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; |
| 9541 | tmp &= ~RTC_BKUP_BKUP_Msk; |
| 9542 | tmp |= RTC_BKUP_BKUP(data); |
| 9543 | ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; |
| 9544 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9545 | } |
| 9546 | |
| 9547 | static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9548 | { |
| 9549 | RTC_CRITICAL_SECTION_ENTER(); |
| 9550 | ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); |
| 9551 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9552 | } |
| 9553 | |
| 9554 | static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9555 | { |
| 9556 | RTC_CRITICAL_SECTION_ENTER(); |
| 9557 | ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); |
| 9558 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9559 | } |
| 9560 | |
| 9561 | static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) |
| 9562 | { |
| 9563 | uint32_t tmp; |
| 9564 | tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; |
| 9565 | tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; |
| 9566 | return tmp; |
| 9567 | } |
| 9568 | |
| 9569 | static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9570 | { |
| 9571 | RTC_CRITICAL_SECTION_ENTER(); |
| 9572 | ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; |
| 9573 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9574 | } |
| 9575 | |
| 9576 | static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9577 | { |
| 9578 | uint32_t tmp; |
| 9579 | tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; |
| 9580 | tmp &= mask; |
| 9581 | return tmp; |
| 9582 | } |
| 9583 | |
| 9584 | static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) |
| 9585 | { |
| 9586 | RTC_CRITICAL_SECTION_ENTER(); |
| 9587 | ((Rtc *)hw)->MODE0.BKUP[index].reg = data; |
| 9588 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9589 | } |
| 9590 | |
| 9591 | static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9592 | { |
| 9593 | RTC_CRITICAL_SECTION_ENTER(); |
| 9594 | ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; |
| 9595 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9596 | } |
| 9597 | |
| 9598 | static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) |
| 9599 | { |
| 9600 | RTC_CRITICAL_SECTION_ENTER(); |
| 9601 | ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; |
| 9602 | RTC_CRITICAL_SECTION_LEAVE(); |
| 9603 | } |
| 9604 | |
| 9605 | static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) |
| 9606 | { |
| 9607 | return ((Rtc *)hw)->MODE0.BKUP[index].reg; |
| 9608 | } |
| 9609 | |
| 9610 | /* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ |
| 9611 | #define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) |
| 9612 | #define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) |
| 9613 | #define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) |
| 9614 | #define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) |
| 9615 | #define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) |
| 9616 | #define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) |
| 9617 | #define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) |
| 9618 | #define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) |
| 9619 | #define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) |
| 9620 | #define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) |
| 9621 | #define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) |
| 9622 | #define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) |
| 9623 | #define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) |
| 9624 | #define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) |
| 9625 | #define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) |
| 9626 | #define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) |
| 9627 | #define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) |
| 9628 | #define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) |
| 9629 | #define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) |
| 9630 | #define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) |
| 9631 | #define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) |
| 9632 | #define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) |
| 9633 | #define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) |
| 9634 | #define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) |
| 9635 | #define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) |
| 9636 | #define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) |
| 9637 | #define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) |
| 9638 | #define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) |
| 9639 | #define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) |
| 9640 | #define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) |
| 9641 | #define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) |
| 9642 | #define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) |
| 9643 | #define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) |
| 9644 | #define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) |
| 9645 | #define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) |
| 9646 | #define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) |
| 9647 | #define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) |
| 9648 | #define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) |
| 9649 | #define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) |
| 9650 | #define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) |
| 9651 | #define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) |
| 9652 | #define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) |
| 9653 | #define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) |
| 9654 | #define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) |
| 9655 | #define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) |
| 9656 | #define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) |
| 9657 | #define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) |
| 9658 | #define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) |
| 9659 | #define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) |
| 9660 | #define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) |
| 9661 | #define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) |
| 9662 | #define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) |
| 9663 | #define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) |
| 9664 | #define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) |
| 9665 | #define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) |
| 9666 | #define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) |
| 9667 | #define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) |
| 9668 | #define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) |
| 9669 | #define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) |
| 9670 | #define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) |
| 9671 | #define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) |
| 9672 | #define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) |
| 9673 | #define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) |
| 9674 | #define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) |
| 9675 | #define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) |
| 9676 | #define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) |
| 9677 | #define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) |
| 9678 | #define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) |
| 9679 | #define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) |
| 9680 | #define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) |
| 9681 | #define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) |
| 9682 | #define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) |
| 9683 | #define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) |
| 9684 | #define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) |
| 9685 | #define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) |
| 9686 | #define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) |
| 9687 | #define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) |
| 9688 | #define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) |
| 9689 | #define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) |
| 9690 | #define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) |
| 9691 | #define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) |
| 9692 | #define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) |
| 9693 | #define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) |
| 9694 | #define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) |
| 9695 | #define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) |
| 9696 | #define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) |
| 9697 | #define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) |
| 9698 | #define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) |
| 9699 | #define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) |
| 9700 | #define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) |
| 9701 | #define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) |
| 9702 | #define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) |
| 9703 | #define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) |
| 9704 | #define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) |
| 9705 | #define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) |
| 9706 | #define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) |
| 9707 | #define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) |
| 9708 | #define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) |
| 9709 | #define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) |
| 9710 | #define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) |
| 9711 | #define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) |
| 9712 | #define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) |
| 9713 | #define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) |
| 9714 | #define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) |
| 9715 | #define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) |
| 9716 | #define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) |
| 9717 | #define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) |
| 9718 | #define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) |
| 9719 | #define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) |
| 9720 | #define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) |
| 9721 | #define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) |
| 9722 | #define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) |
| 9723 | #define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) |
| 9724 | #define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) |
| 9725 | #define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) |
| 9726 | #define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) |
| 9727 | #define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) |
| 9728 | #define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) |
| 9729 | #define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) |
| 9730 | #define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) |
| 9731 | #define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) |
| 9732 | #define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) |
| 9733 | #define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) |
| 9734 | #define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) |
| 9735 | #define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) |
| 9736 | #define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) |
| 9737 | #define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) |
| 9738 | #define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) |
| 9739 | #define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) |
| 9740 | #define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) |
| 9741 | #define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) |
| 9742 | #define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) |
| 9743 | #define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) |
| 9744 | #define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) |
| 9745 | #define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) |
| 9746 | #define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) |
| 9747 | #define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) |
| 9748 | #define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) |
| 9749 | #define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) |
| 9750 | #define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) |
| 9751 | #define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) |
| 9752 | #define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) |
| 9753 | #define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) |
| 9754 | #define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) |
| 9755 | #define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) |
| 9756 | #define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) |
| 9757 | #define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) |
| 9758 | #define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) |
| 9759 | #define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) |
| 9760 | #define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) |
| 9761 | #define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) |
| 9762 | #define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) |
| 9763 | #define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) |
| 9764 | #define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) |
| 9765 | #define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) |
| 9766 | #define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) |
| 9767 | #define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) |
| 9768 | #define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) |
| 9769 | #define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) |
| 9770 | #define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) |
| 9771 | #define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) |
| 9772 | #define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) |
| 9773 | #define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) |
| 9774 | #define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) |
| 9775 | #define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) |
| 9776 | #define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) |
| 9777 | #define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) |
| 9778 | #define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) |
| 9779 | #define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) |
| 9780 | #define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) |
| 9781 | #define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) |
| 9782 | #define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) |
| 9783 | #define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) |
| 9784 | #define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) |
| 9785 | #define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) |
| 9786 | #define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) |
| 9787 | #define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) |
| 9788 | #define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) |
| 9789 | #define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) |
| 9790 | #define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) |
| 9791 | #define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) |
| 9792 | #define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) |
| 9793 | #define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) |
| 9794 | #define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) |
| 9795 | #define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) |
| 9796 | #define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) |
| 9797 | #define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) |
| 9798 | #define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) |
| 9799 | #define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) |
| 9800 | #define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) |
| 9801 | #define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) |
| 9802 | #define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) |
| 9803 | #define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) |
| 9804 | #define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) |
| 9805 | #define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) |
| 9806 | #define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) |
| 9807 | #define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) |
| 9808 | #define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) |
| 9809 | #define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) |
| 9810 | #define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) |
| 9811 | #define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) |
| 9812 | #define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) |
| 9813 | #define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) |
| 9814 | #define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) |
| 9815 | #define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) |
| 9816 | #define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) |
| 9817 | #define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) |
| 9818 | #define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) |
| 9819 | #define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) |
| 9820 | #define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) |
| 9821 | #define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) |
| 9822 | #define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) |
| 9823 | #define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) |
| 9824 | #define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) |
| 9825 | #define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) |
| 9826 | #define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) |
| 9827 | #define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) |
| 9828 | #define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) |
| 9829 | #define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) |
| 9830 | #define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) |
| 9831 | #define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) |
| 9832 | #define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) |
| 9833 | #define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) |
| 9834 | #define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) |
| 9835 | #define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) |
| 9836 | #define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) |
| 9837 | #define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) |
| 9838 | #define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) |
| 9839 | #define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) |
| 9840 | #define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) |
| 9841 | #define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) |
| 9842 | #define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) |
| 9843 | #define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) |
| 9844 | #define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) |
| 9845 | #define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) |
| 9846 | #define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) |
| 9847 | #define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) |
| 9848 | #define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) |
| 9849 | #define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) |
| 9850 | #define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) |
| 9851 | #define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) |
| 9852 | #define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) |
| 9853 | #define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) |
| 9854 | #define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) |
| 9855 | #define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) |
| 9856 | #define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) |
| 9857 | #define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) |
| 9858 | #define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) |
| 9859 | #define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) |
| 9860 | #define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) |
| 9861 | #define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) |
| 9862 | #define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) |
| 9863 | #define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) |
| 9864 | #define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) |
| 9865 | #define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) |
| 9866 | #define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) |
| 9867 | #define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) |
| 9868 | #define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) |
| 9869 | #define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) |
| 9870 | #define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) |
| 9871 | #define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) |
| 9872 | #define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) |
| 9873 | #define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) |
| 9874 | #define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) |
| 9875 | #define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) |
| 9876 | #define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) |
| 9877 | #define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) |
| 9878 | #define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) |
| 9879 | #define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) |
| 9880 | #define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) |
| 9881 | #define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) |
| 9882 | #define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) |
| 9883 | #define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) |
| 9884 | #define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) |
| 9885 | #define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) |
| 9886 | #define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) |
| 9887 | #define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) |
| 9888 | #define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) |
| 9889 | #define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) |
| 9890 | #define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) |
| 9891 | #define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) |
| 9892 | #define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) |
| 9893 | #define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) |
| 9894 | #define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) |
| 9895 | #define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) |
| 9896 | #define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) |
| 9897 | #define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) |
| 9898 | #define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) |
| 9899 | #define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) |
| 9900 | #define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) |
| 9901 | #define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) |
| 9902 | #define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) |
| 9903 | #define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) |
| 9904 | #define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) |
| 9905 | #define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) |
| 9906 | #define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) |
| 9907 | #define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) |
| 9908 | #define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) |
| 9909 | #define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) |
| 9910 | #define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) |
| 9911 | #define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) |
| 9912 | #define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) |
| 9913 | #define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) |
| 9914 | #define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) |
| 9915 | #define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) |
| 9916 | #define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) |
| 9917 | #define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) |
| 9918 | #define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) |
| 9919 | #define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) |
| 9920 | #define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) |
| 9921 | #define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) |
| 9922 | #define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) |
| 9923 | #define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) |
| 9924 | #define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) |
| 9925 | #define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) |
| 9926 | #define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) |
| 9927 | #define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) |
| 9928 | #define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) |
| 9929 | #define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) |
| 9930 | #define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) |
| 9931 | #define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) |
| 9932 | #define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) |
| 9933 | #define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) |
| 9934 | #define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) |
| 9935 | #define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) |
| 9936 | #define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) |
| 9937 | #define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) |
| 9938 | #define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) |
| 9939 | #define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) |
| 9940 | #define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) |
| 9941 | #define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) |
| 9942 | #define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) |
| 9943 | #define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) |
| 9944 | #define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) |
| 9945 | #define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) |
| 9946 | #define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) |
| 9947 | #define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) |
| 9948 | #define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) |
| 9949 | #define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) |
| 9950 | #define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) |
| 9951 | #define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) |
| 9952 | #define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) |
| 9953 | #define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) |
| 9954 | #define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) |
| 9955 | #define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) |
| 9956 | #define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) |
| 9957 | #define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) |
| 9958 | #define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) |
| 9959 | #define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) |
| 9960 | #define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) |
| 9961 | #define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) |
| 9962 | #define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) |
| 9963 | #define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) |
| 9964 | #define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) |
| 9965 | #define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) |
| 9966 | #define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) |
| 9967 | #define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) |
| 9968 | #define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) |
| 9969 | #define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) |
| 9970 | #define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) |
| 9971 | #define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) |
| 9972 | #define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) |
| 9973 | #define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) |
| 9974 | #define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) |
| 9975 | #define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) |
| 9976 | #define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) |
| 9977 | #define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) |
| 9978 | #define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) |
| 9979 | #define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) |
| 9980 | #define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) |
| 9981 | #define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) |
| 9982 | #define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) |
| 9983 | #define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) |
| 9984 | #define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) |
| 9985 | #define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) |
| 9986 | #define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) |
| 9987 | #define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) |
| 9988 | #define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) |
| 9989 | #define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) |
| 9990 | #define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) |
| 9991 | #define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) |
| 9992 | #define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) |
| 9993 | #define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) |
| 9994 | #define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) |
| 9995 | #define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) |
| 9996 | #define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) |
| 9997 | #define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) |
| 9998 | #define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) |
| 9999 | #define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) |
| 10000 | #define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) |
| 10001 | #define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) |
| 10002 | #define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) |
| 10003 | #define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) |
| 10004 | #define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) |
| 10005 | #define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) |
| 10006 | #define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) |
| 10007 | #define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) |
| 10008 | #define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) |
| 10009 | #define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) |
| 10010 | #define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) |
| 10011 | #define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) |
| 10012 | #define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) |
| 10013 | #define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) |
| 10014 | #define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) |
| 10015 | #define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) |
| 10016 | #define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) |
| 10017 | #define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) |
| 10018 | #define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) |
| 10019 | #define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) |
| 10020 | #define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) |
| 10021 | #define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) |
| 10022 | #define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) |
| 10023 | #define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) |
| 10024 | #define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) |
| 10025 | #define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) |
| 10026 | #define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) |
| 10027 | #define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) |
| 10028 | #define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) |
| 10029 | #define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) |
| 10030 | #define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) |
| 10031 | #define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) |
| 10032 | #define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) |
| 10033 | #define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) |
| 10034 | #define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) |
| 10035 | #define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) |
| 10036 | #define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) |
| 10037 | #define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) |
| 10038 | #define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) |
| 10039 | #define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) |
| 10040 | #define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) |
| 10041 | #define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) |
| 10042 | #define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) |
| 10043 | #define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) |
| 10044 | #define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) |
| 10045 | #define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) |
| 10046 | #define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) |
| 10047 | #define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) |
| 10048 | #define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) |
| 10049 | #define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) |
| 10050 | #define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) |
| 10051 | #define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) |
| 10052 | #define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) |
| 10053 | #define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) |
| 10054 | #define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) |
| 10055 | #define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) |
| 10056 | #define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) |
| 10057 | #define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) |
| 10058 | #define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) |
| 10059 | #define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) |
| 10060 | #define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) |
| 10061 | #define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) |
| 10062 | #define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) |
| 10063 | #define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) |
| 10064 | #define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) |
| 10065 | #define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) |
| 10066 | #define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) |
| 10067 | #define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) |
| 10068 | #define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) |
| 10069 | #define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) |
| 10070 | #define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) |
| 10071 | #define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) |
| 10072 | #define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) |
| 10073 | #define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) |
| 10074 | #define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) |
| 10075 | #define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) |
| 10076 | #define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) |
| 10077 | #define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) |
| 10078 | #define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) |
| 10079 | #define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) |
| 10080 | #define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) |
| 10081 | #define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) |
| 10082 | #define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) |
| 10083 | #define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) |
| 10084 | #define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) |
| 10085 | #define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) |
| 10086 | #define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) |
| 10087 | #define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) |
| 10088 | #define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) |
| 10089 | #define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) |
| 10090 | #define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) |
| 10091 | #define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) |
| 10092 | #define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) |
| 10093 | #define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) |
| 10094 | #define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) |
| 10095 | #define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) |
| 10096 | #define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) |
| 10097 | #define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) |
| 10098 | #define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) |
| 10099 | #define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) |
| 10100 | #define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) |
| 10101 | #define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) |
| 10102 | #define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) |
| 10103 | #define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) |
| 10104 | #define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) |
| 10105 | #define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) |
| 10106 | #define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) |
| 10107 | #define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) |
| 10108 | #define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) |
| 10109 | #define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) |
| 10110 | #define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) |
| 10111 | #define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) |
| 10112 | #define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) |
| 10113 | #define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) |
| 10114 | #define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) |
| 10115 | #define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) |
| 10116 | #define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) |
| 10117 | #define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) |
| 10118 | #define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) |
| 10119 | #define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) |
| 10120 | #define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) |
| 10121 | #define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) |
| 10122 | #define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) |
| 10123 | #define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) |
| 10124 | #define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) |
| 10125 | #define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) |
| 10126 | #define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) |
| 10127 | #define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) |
| 10128 | #define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) |
| 10129 | #define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) |
| 10130 | #define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) |
| 10131 | #define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) |
| 10132 | #define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) |
| 10133 | |
| 10134 | #ifdef __cplusplus |
| 10135 | } |
| 10136 | #endif |
| 10137 | |
| 10138 | #endif /* _HRI_RTC_E54_H_INCLUDED */ |
| 10139 | #endif /* _SAME54_RTC_COMPONENT_ */ |