Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM OSC32KCTRL |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_OSC32KCTRL_COMPONENT_ |
| 35 | #ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_ |
| 36 | #define _HRI_OSC32KCTRL_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) |
| 46 | #define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define OSC32KCTRL_CRITICAL_SECTION_ENTER() |
| 50 | #define OSC32KCTRL_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; |
| 54 | typedef uint32_t hri_osc32kctrl_intenset_reg_t; |
| 55 | typedef uint32_t hri_osc32kctrl_intflag_reg_t; |
| 56 | typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; |
| 57 | typedef uint32_t hri_osc32kctrl_status_reg_t; |
| 58 | typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; |
| 59 | typedef uint8_t hri_osc32kctrl_evctrl_reg_t; |
| 60 | typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; |
| 61 | |
| 62 | static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) |
| 63 | { |
| 64 | return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; |
| 65 | } |
| 66 | |
| 67 | static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) |
| 68 | { |
| 69 | ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; |
| 70 | } |
| 71 | |
| 72 | static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) |
| 73 | { |
| 74 | return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; |
| 75 | } |
| 76 | |
| 77 | static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) |
| 78 | { |
| 79 | ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; |
| 80 | } |
| 81 | |
| 82 | static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) |
| 83 | { |
| 84 | return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; |
| 85 | } |
| 86 | |
| 87 | static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) |
| 88 | { |
| 89 | ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; |
| 90 | } |
| 91 | |
| 92 | static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) |
| 93 | { |
| 94 | return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; |
| 95 | } |
| 96 | |
| 97 | static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) |
| 98 | { |
| 99 | ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; |
| 100 | } |
| 101 | |
| 102 | static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, |
| 103 | hri_osc32kctrl_intflag_reg_t mask) |
| 104 | { |
| 105 | uint32_t tmp; |
| 106 | tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; |
| 107 | tmp &= mask; |
| 108 | return tmp; |
| 109 | } |
| 110 | |
| 111 | static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) |
| 112 | { |
| 113 | return ((Osc32kctrl *)hw)->INTFLAG.reg; |
| 114 | } |
| 115 | |
| 116 | static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) |
| 117 | { |
| 118 | ((Osc32kctrl *)hw)->INTFLAG.reg = mask; |
| 119 | } |
| 120 | |
| 121 | static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) |
| 122 | { |
| 123 | ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; |
| 124 | } |
| 125 | |
| 126 | static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) |
| 127 | { |
| 128 | return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; |
| 129 | } |
| 130 | |
| 131 | static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) |
| 132 | { |
| 133 | if (value == 0x0) { |
| 134 | ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; |
| 135 | } else { |
| 136 | ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) |
| 141 | { |
| 142 | ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; |
| 143 | } |
| 144 | |
| 145 | static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) |
| 146 | { |
| 147 | ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; |
| 148 | } |
| 149 | |
| 150 | static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) |
| 151 | { |
| 152 | return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; |
| 153 | } |
| 154 | |
| 155 | static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) |
| 156 | { |
| 157 | if (value == 0x0) { |
| 158 | ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; |
| 159 | } else { |
| 160 | ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) |
| 165 | { |
| 166 | ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; |
| 167 | } |
| 168 | |
| 169 | static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) |
| 170 | { |
| 171 | ((Osc32kctrl *)hw)->INTENSET.reg = mask; |
| 172 | } |
| 173 | |
| 174 | static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, |
| 175 | hri_osc32kctrl_intenset_reg_t mask) |
| 176 | { |
| 177 | uint32_t tmp; |
| 178 | tmp = ((Osc32kctrl *)hw)->INTENSET.reg; |
| 179 | tmp &= mask; |
| 180 | return tmp; |
| 181 | } |
| 182 | |
| 183 | static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) |
| 184 | { |
| 185 | return ((Osc32kctrl *)hw)->INTENSET.reg; |
| 186 | } |
| 187 | |
| 188 | static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) |
| 189 | { |
| 190 | ((Osc32kctrl *)hw)->INTENSET.reg = data; |
| 191 | ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; |
| 192 | } |
| 193 | |
| 194 | static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) |
| 195 | { |
| 196 | ((Osc32kctrl *)hw)->INTENCLR.reg = mask; |
| 197 | } |
| 198 | |
| 199 | static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) |
| 200 | { |
| 201 | return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; |
| 202 | } |
| 203 | |
| 204 | static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) |
| 205 | { |
| 206 | return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; |
| 207 | } |
| 208 | |
| 209 | static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) |
| 210 | { |
| 211 | return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; |
| 212 | } |
| 213 | |
| 214 | static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, |
| 215 | hri_osc32kctrl_status_reg_t mask) |
| 216 | { |
| 217 | uint32_t tmp; |
| 218 | tmp = ((Osc32kctrl *)hw)->STATUS.reg; |
| 219 | tmp &= mask; |
| 220 | return tmp; |
| 221 | } |
| 222 | |
| 223 | static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) |
| 224 | { |
| 225 | return ((Osc32kctrl *)hw)->STATUS.reg; |
| 226 | } |
| 227 | |
| 228 | static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) |
| 229 | { |
| 230 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 231 | ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); |
| 232 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 233 | } |
| 234 | |
| 235 | static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, |
| 236 | hri_osc32kctrl_rtcctrl_reg_t mask) |
| 237 | { |
| 238 | uint8_t tmp; |
| 239 | tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; |
| 240 | tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; |
| 241 | return tmp; |
| 242 | } |
| 243 | |
| 244 | static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) |
| 245 | { |
| 246 | uint8_t tmp; |
| 247 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 248 | tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; |
| 249 | tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; |
| 250 | tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); |
| 251 | ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; |
| 252 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 253 | } |
| 254 | |
| 255 | static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) |
| 256 | { |
| 257 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 258 | ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); |
| 259 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 260 | } |
| 261 | |
| 262 | static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) |
| 263 | { |
| 264 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 265 | ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); |
| 266 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 267 | } |
| 268 | |
| 269 | static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) |
| 270 | { |
| 271 | uint8_t tmp; |
| 272 | tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; |
| 273 | tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; |
| 274 | return tmp; |
| 275 | } |
| 276 | |
| 277 | static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) |
| 278 | { |
| 279 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 280 | ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; |
| 281 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 282 | } |
| 283 | |
| 284 | static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, |
| 285 | hri_osc32kctrl_rtcctrl_reg_t mask) |
| 286 | { |
| 287 | uint8_t tmp; |
| 288 | tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; |
| 289 | tmp &= mask; |
| 290 | return tmp; |
| 291 | } |
| 292 | |
| 293 | static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) |
| 294 | { |
| 295 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 296 | ((Osc32kctrl *)hw)->RTCCTRL.reg = data; |
| 297 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 298 | } |
| 299 | |
| 300 | static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) |
| 301 | { |
| 302 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 303 | ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; |
| 304 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 305 | } |
| 306 | |
| 307 | static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) |
| 308 | { |
| 309 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 310 | ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; |
| 311 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 312 | } |
| 313 | |
| 314 | static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) |
| 315 | { |
| 316 | return ((Osc32kctrl *)hw)->RTCCTRL.reg; |
| 317 | } |
| 318 | |
| 319 | static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) |
| 320 | { |
| 321 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 322 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; |
| 323 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 324 | } |
| 325 | |
| 326 | static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) |
| 327 | { |
| 328 | uint16_t tmp; |
| 329 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 330 | tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; |
| 331 | return (bool)tmp; |
| 332 | } |
| 333 | |
| 334 | static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) |
| 335 | { |
| 336 | uint16_t tmp; |
| 337 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 338 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 339 | tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; |
| 340 | tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; |
| 341 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 342 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 343 | } |
| 344 | |
| 345 | static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) |
| 346 | { |
| 347 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 348 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; |
| 349 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 350 | } |
| 351 | |
| 352 | static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) |
| 353 | { |
| 354 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 355 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; |
| 356 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 357 | } |
| 358 | |
| 359 | static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) |
| 360 | { |
| 361 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 362 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; |
| 363 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 364 | } |
| 365 | |
| 366 | static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) |
| 367 | { |
| 368 | uint16_t tmp; |
| 369 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 370 | tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; |
| 371 | return (bool)tmp; |
| 372 | } |
| 373 | |
| 374 | static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) |
| 375 | { |
| 376 | uint16_t tmp; |
| 377 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 378 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 379 | tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; |
| 380 | tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; |
| 381 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 382 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 383 | } |
| 384 | |
| 385 | static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) |
| 386 | { |
| 387 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 388 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; |
| 389 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 390 | } |
| 391 | |
| 392 | static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) |
| 393 | { |
| 394 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 395 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; |
| 396 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 397 | } |
| 398 | |
| 399 | static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) |
| 400 | { |
| 401 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 402 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; |
| 403 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 404 | } |
| 405 | |
| 406 | static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) |
| 407 | { |
| 408 | uint16_t tmp; |
| 409 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 410 | tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; |
| 411 | return (bool)tmp; |
| 412 | } |
| 413 | |
| 414 | static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) |
| 415 | { |
| 416 | uint16_t tmp; |
| 417 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 418 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 419 | tmp &= ~OSC32KCTRL_XOSC32K_EN32K; |
| 420 | tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; |
| 421 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 422 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 423 | } |
| 424 | |
| 425 | static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) |
| 426 | { |
| 427 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 428 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; |
| 429 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 430 | } |
| 431 | |
| 432 | static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) |
| 433 | { |
| 434 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 435 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; |
| 436 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 437 | } |
| 438 | |
| 439 | static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) |
| 440 | { |
| 441 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 442 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; |
| 443 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 444 | } |
| 445 | |
| 446 | static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) |
| 447 | { |
| 448 | uint16_t tmp; |
| 449 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 450 | tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; |
| 451 | return (bool)tmp; |
| 452 | } |
| 453 | |
| 454 | static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) |
| 455 | { |
| 456 | uint16_t tmp; |
| 457 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 458 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 459 | tmp &= ~OSC32KCTRL_XOSC32K_EN1K; |
| 460 | tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; |
| 461 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 462 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 463 | } |
| 464 | |
| 465 | static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) |
| 466 | { |
| 467 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 468 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; |
| 469 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 470 | } |
| 471 | |
| 472 | static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) |
| 473 | { |
| 474 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 475 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; |
| 476 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 477 | } |
| 478 | |
| 479 | static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) |
| 480 | { |
| 481 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 482 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; |
| 483 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 484 | } |
| 485 | |
| 486 | static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) |
| 487 | { |
| 488 | uint16_t tmp; |
| 489 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 490 | tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; |
| 491 | return (bool)tmp; |
| 492 | } |
| 493 | |
| 494 | static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) |
| 495 | { |
| 496 | uint16_t tmp; |
| 497 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 498 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 499 | tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; |
| 500 | tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; |
| 501 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 502 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 503 | } |
| 504 | |
| 505 | static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) |
| 506 | { |
| 507 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 508 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; |
| 509 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 510 | } |
| 511 | |
| 512 | static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) |
| 513 | { |
| 514 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 515 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; |
| 516 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 517 | } |
| 518 | |
| 519 | static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) |
| 520 | { |
| 521 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 522 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; |
| 523 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 524 | } |
| 525 | |
| 526 | static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) |
| 527 | { |
| 528 | uint16_t tmp; |
| 529 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 530 | tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; |
| 531 | return (bool)tmp; |
| 532 | } |
| 533 | |
| 534 | static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) |
| 535 | { |
| 536 | uint16_t tmp; |
| 537 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 538 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 539 | tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; |
| 540 | tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; |
| 541 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 542 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 543 | } |
| 544 | |
| 545 | static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) |
| 546 | { |
| 547 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 548 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; |
| 549 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 550 | } |
| 551 | |
| 552 | static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) |
| 553 | { |
| 554 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 555 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; |
| 556 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 557 | } |
| 558 | |
| 559 | static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) |
| 560 | { |
| 561 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 562 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; |
| 563 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 564 | } |
| 565 | |
| 566 | static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) |
| 567 | { |
| 568 | uint16_t tmp; |
| 569 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 570 | tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; |
| 571 | return (bool)tmp; |
| 572 | } |
| 573 | |
| 574 | static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) |
| 575 | { |
| 576 | uint16_t tmp; |
| 577 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 578 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 579 | tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; |
| 580 | tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; |
| 581 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 582 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 583 | } |
| 584 | |
| 585 | static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) |
| 586 | { |
| 587 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 588 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; |
| 589 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 590 | } |
| 591 | |
| 592 | static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) |
| 593 | { |
| 594 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 595 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; |
| 596 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 597 | } |
| 598 | |
| 599 | static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 600 | { |
| 601 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 602 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); |
| 603 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 604 | } |
| 605 | |
| 606 | static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, |
| 607 | hri_osc32kctrl_xosc32k_reg_t mask) |
| 608 | { |
| 609 | uint16_t tmp; |
| 610 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 611 | tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; |
| 612 | return tmp; |
| 613 | } |
| 614 | |
| 615 | static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) |
| 616 | { |
| 617 | uint16_t tmp; |
| 618 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 619 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 620 | tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; |
| 621 | tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); |
| 622 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 623 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 624 | } |
| 625 | |
| 626 | static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 627 | { |
| 628 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 629 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); |
| 630 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 631 | } |
| 632 | |
| 633 | static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 634 | { |
| 635 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 636 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); |
| 637 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 638 | } |
| 639 | |
| 640 | static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) |
| 641 | { |
| 642 | uint16_t tmp; |
| 643 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 644 | tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; |
| 645 | return tmp; |
| 646 | } |
| 647 | |
| 648 | static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 649 | { |
| 650 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 651 | ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); |
| 652 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 653 | } |
| 654 | |
| 655 | static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, |
| 656 | hri_osc32kctrl_xosc32k_reg_t mask) |
| 657 | { |
| 658 | uint16_t tmp; |
| 659 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 660 | tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; |
| 661 | return tmp; |
| 662 | } |
| 663 | |
| 664 | static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) |
| 665 | { |
| 666 | uint16_t tmp; |
| 667 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 668 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 669 | tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; |
| 670 | tmp |= OSC32KCTRL_XOSC32K_CGM(data); |
| 671 | ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; |
| 672 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 673 | } |
| 674 | |
| 675 | static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 676 | { |
| 677 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 678 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); |
| 679 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 680 | } |
| 681 | |
| 682 | static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 683 | { |
| 684 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 685 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); |
| 686 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 687 | } |
| 688 | |
| 689 | static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) |
| 690 | { |
| 691 | uint16_t tmp; |
| 692 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 693 | tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; |
| 694 | return tmp; |
| 695 | } |
| 696 | |
| 697 | static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 698 | { |
| 699 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 700 | ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; |
| 701 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 702 | } |
| 703 | |
| 704 | static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, |
| 705 | hri_osc32kctrl_xosc32k_reg_t mask) |
| 706 | { |
| 707 | uint16_t tmp; |
| 708 | tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 709 | tmp &= mask; |
| 710 | return tmp; |
| 711 | } |
| 712 | |
| 713 | static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) |
| 714 | { |
| 715 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 716 | ((Osc32kctrl *)hw)->XOSC32K.reg = data; |
| 717 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 718 | } |
| 719 | |
| 720 | static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 721 | { |
| 722 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 723 | ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; |
| 724 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 725 | } |
| 726 | |
| 727 | static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) |
| 728 | { |
| 729 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 730 | ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; |
| 731 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 732 | } |
| 733 | |
| 734 | static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) |
| 735 | { |
| 736 | return ((Osc32kctrl *)hw)->XOSC32K.reg; |
| 737 | } |
| 738 | |
| 739 | static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) |
| 740 | { |
| 741 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 742 | ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; |
| 743 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 744 | } |
| 745 | |
| 746 | static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) |
| 747 | { |
| 748 | uint8_t tmp; |
| 749 | tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 750 | tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; |
| 751 | return (bool)tmp; |
| 752 | } |
| 753 | |
| 754 | static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) |
| 755 | { |
| 756 | uint8_t tmp; |
| 757 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 758 | tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 759 | tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; |
| 760 | tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; |
| 761 | ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; |
| 762 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 763 | } |
| 764 | |
| 765 | static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) |
| 766 | { |
| 767 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 768 | ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; |
| 769 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 770 | } |
| 771 | |
| 772 | static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) |
| 773 | { |
| 774 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 775 | ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; |
| 776 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 777 | } |
| 778 | |
| 779 | static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) |
| 780 | { |
| 781 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 782 | ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; |
| 783 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 784 | } |
| 785 | |
| 786 | static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) |
| 787 | { |
| 788 | uint8_t tmp; |
| 789 | tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 790 | tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; |
| 791 | return (bool)tmp; |
| 792 | } |
| 793 | |
| 794 | static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) |
| 795 | { |
| 796 | uint8_t tmp; |
| 797 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 798 | tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 799 | tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; |
| 800 | tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; |
| 801 | ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; |
| 802 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 803 | } |
| 804 | |
| 805 | static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) |
| 806 | { |
| 807 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 808 | ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; |
| 809 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 810 | } |
| 811 | |
| 812 | static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) |
| 813 | { |
| 814 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 815 | ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; |
| 816 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 817 | } |
| 818 | |
| 819 | static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) |
| 820 | { |
| 821 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 822 | ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; |
| 823 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 824 | } |
| 825 | |
| 826 | static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) |
| 827 | { |
| 828 | uint8_t tmp; |
| 829 | tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 830 | tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; |
| 831 | return (bool)tmp; |
| 832 | } |
| 833 | |
| 834 | static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) |
| 835 | { |
| 836 | uint8_t tmp; |
| 837 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 838 | tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 839 | tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; |
| 840 | tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; |
| 841 | ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; |
| 842 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 843 | } |
| 844 | |
| 845 | static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) |
| 846 | { |
| 847 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 848 | ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; |
| 849 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 850 | } |
| 851 | |
| 852 | static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) |
| 853 | { |
| 854 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 855 | ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; |
| 856 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 857 | } |
| 858 | |
| 859 | static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) |
| 860 | { |
| 861 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 862 | ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; |
| 863 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 864 | } |
| 865 | |
| 866 | static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, |
| 867 | hri_osc32kctrl_cfdctrl_reg_t mask) |
| 868 | { |
| 869 | uint8_t tmp; |
| 870 | tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 871 | tmp &= mask; |
| 872 | return tmp; |
| 873 | } |
| 874 | |
| 875 | static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) |
| 876 | { |
| 877 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 878 | ((Osc32kctrl *)hw)->CFDCTRL.reg = data; |
| 879 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 880 | } |
| 881 | |
| 882 | static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) |
| 883 | { |
| 884 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 885 | ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; |
| 886 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 887 | } |
| 888 | |
| 889 | static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) |
| 890 | { |
| 891 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 892 | ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; |
| 893 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 894 | } |
| 895 | |
| 896 | static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) |
| 897 | { |
| 898 | return ((Osc32kctrl *)hw)->CFDCTRL.reg; |
| 899 | } |
| 900 | |
| 901 | static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) |
| 902 | { |
| 903 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 904 | ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; |
| 905 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 906 | } |
| 907 | |
| 908 | static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) |
| 909 | { |
| 910 | uint8_t tmp; |
| 911 | tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; |
| 912 | tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; |
| 913 | return (bool)tmp; |
| 914 | } |
| 915 | |
| 916 | static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) |
| 917 | { |
| 918 | uint8_t tmp; |
| 919 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 920 | tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; |
| 921 | tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; |
| 922 | tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; |
| 923 | ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; |
| 924 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 925 | } |
| 926 | |
| 927 | static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) |
| 928 | { |
| 929 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 930 | ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; |
| 931 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 932 | } |
| 933 | |
| 934 | static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) |
| 935 | { |
| 936 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 937 | ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; |
| 938 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 939 | } |
| 940 | |
| 941 | static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) |
| 942 | { |
| 943 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 944 | ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; |
| 945 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 946 | } |
| 947 | |
| 948 | static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, |
| 949 | hri_osc32kctrl_evctrl_reg_t mask) |
| 950 | { |
| 951 | uint8_t tmp; |
| 952 | tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; |
| 953 | tmp &= mask; |
| 954 | return tmp; |
| 955 | } |
| 956 | |
| 957 | static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) |
| 958 | { |
| 959 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 960 | ((Osc32kctrl *)hw)->EVCTRL.reg = data; |
| 961 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 962 | } |
| 963 | |
| 964 | static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) |
| 965 | { |
| 966 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 967 | ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; |
| 968 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 969 | } |
| 970 | |
| 971 | static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) |
| 972 | { |
| 973 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 974 | ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; |
| 975 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 976 | } |
| 977 | |
| 978 | static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) |
| 979 | { |
| 980 | return ((Osc32kctrl *)hw)->EVCTRL.reg; |
| 981 | } |
| 982 | |
| 983 | static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) |
| 984 | { |
| 985 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 986 | ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; |
| 987 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 988 | } |
| 989 | |
| 990 | static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) |
| 991 | { |
| 992 | uint32_t tmp; |
| 993 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 994 | tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; |
| 995 | return (bool)tmp; |
| 996 | } |
| 997 | |
| 998 | static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) |
| 999 | { |
| 1000 | uint32_t tmp; |
| 1001 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1002 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1003 | tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; |
| 1004 | tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; |
| 1005 | ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; |
| 1006 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1007 | } |
| 1008 | |
| 1009 | static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) |
| 1010 | { |
| 1011 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1012 | ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; |
| 1013 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1014 | } |
| 1015 | |
| 1016 | static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) |
| 1017 | { |
| 1018 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1019 | ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; |
| 1020 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1021 | } |
| 1022 | |
| 1023 | static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) |
| 1024 | { |
| 1025 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1026 | ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; |
| 1027 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1028 | } |
| 1029 | |
| 1030 | static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) |
| 1031 | { |
| 1032 | uint32_t tmp; |
| 1033 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1034 | tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; |
| 1035 | return (bool)tmp; |
| 1036 | } |
| 1037 | |
| 1038 | static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) |
| 1039 | { |
| 1040 | uint32_t tmp; |
| 1041 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1042 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1043 | tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; |
| 1044 | tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; |
| 1045 | ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; |
| 1046 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1047 | } |
| 1048 | |
| 1049 | static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) |
| 1050 | { |
| 1051 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1052 | ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; |
| 1053 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1054 | } |
| 1055 | |
| 1056 | static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) |
| 1057 | { |
| 1058 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1059 | ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; |
| 1060 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1061 | } |
| 1062 | |
| 1063 | static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) |
| 1064 | { |
| 1065 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1066 | ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; |
| 1067 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1068 | } |
| 1069 | |
| 1070 | static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) |
| 1071 | { |
| 1072 | uint32_t tmp; |
| 1073 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1074 | tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; |
| 1075 | return (bool)tmp; |
| 1076 | } |
| 1077 | |
| 1078 | static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) |
| 1079 | { |
| 1080 | uint32_t tmp; |
| 1081 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1082 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1083 | tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; |
| 1084 | tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; |
| 1085 | ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; |
| 1086 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1087 | } |
| 1088 | |
| 1089 | static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) |
| 1090 | { |
| 1091 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1092 | ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; |
| 1093 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1094 | } |
| 1095 | |
| 1096 | static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) |
| 1097 | { |
| 1098 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1099 | ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; |
| 1100 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1101 | } |
| 1102 | |
| 1103 | static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) |
| 1104 | { |
| 1105 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1106 | ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); |
| 1107 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1108 | } |
| 1109 | |
| 1110 | static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, |
| 1111 | hri_osc32kctrl_osculp32k_reg_t mask) |
| 1112 | { |
| 1113 | uint32_t tmp; |
| 1114 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1115 | tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; |
| 1116 | return tmp; |
| 1117 | } |
| 1118 | |
| 1119 | static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) |
| 1120 | { |
| 1121 | uint32_t tmp; |
| 1122 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1123 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1124 | tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; |
| 1125 | tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); |
| 1126 | ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; |
| 1127 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1128 | } |
| 1129 | |
| 1130 | static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) |
| 1131 | { |
| 1132 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1133 | ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); |
| 1134 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1135 | } |
| 1136 | |
| 1137 | static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) |
| 1138 | { |
| 1139 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1140 | ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); |
| 1141 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1142 | } |
| 1143 | |
| 1144 | static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) |
| 1145 | { |
| 1146 | uint32_t tmp; |
| 1147 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1148 | tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; |
| 1149 | return tmp; |
| 1150 | } |
| 1151 | |
| 1152 | static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) |
| 1153 | { |
| 1154 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1155 | ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; |
| 1156 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1157 | } |
| 1158 | |
| 1159 | static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, |
| 1160 | hri_osc32kctrl_osculp32k_reg_t mask) |
| 1161 | { |
| 1162 | uint32_t tmp; |
| 1163 | tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1164 | tmp &= mask; |
| 1165 | return tmp; |
| 1166 | } |
| 1167 | |
| 1168 | static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) |
| 1169 | { |
| 1170 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1171 | ((Osc32kctrl *)hw)->OSCULP32K.reg = data; |
| 1172 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1173 | } |
| 1174 | |
| 1175 | static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) |
| 1176 | { |
| 1177 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1178 | ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; |
| 1179 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1180 | } |
| 1181 | |
| 1182 | static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) |
| 1183 | { |
| 1184 | OSC32KCTRL_CRITICAL_SECTION_ENTER(); |
| 1185 | ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; |
| 1186 | OSC32KCTRL_CRITICAL_SECTION_LEAVE(); |
| 1187 | } |
| 1188 | |
| 1189 | static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) |
| 1190 | { |
| 1191 | return ((Osc32kctrl *)hw)->OSCULP32K.reg; |
| 1192 | } |
| 1193 | |
| 1194 | #ifdef __cplusplus |
| 1195 | } |
| 1196 | #endif |
| 1197 | |
| 1198 | #endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */ |
| 1199 | #endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ |