Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM FREQM |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_FREQM_COMPONENT_ |
| 35 | #ifndef _HRI_FREQM_E54_H_INCLUDED_ |
| 36 | #define _HRI_FREQM_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_FREQM_CRITICAL_SECTIONS) |
| 46 | #define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define FREQM_CRITICAL_SECTION_ENTER() |
| 50 | #define FREQM_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_freqm_cfga_reg_t; |
| 54 | typedef uint32_t hri_freqm_syncbusy_reg_t; |
| 55 | typedef uint32_t hri_freqm_value_reg_t; |
| 56 | typedef uint8_t hri_freqm_ctrla_reg_t; |
| 57 | typedef uint8_t hri_freqm_ctrlb_reg_t; |
| 58 | typedef uint8_t hri_freqm_intenset_reg_t; |
| 59 | typedef uint8_t hri_freqm_intflag_reg_t; |
| 60 | typedef uint8_t hri_freqm_status_reg_t; |
| 61 | |
| 62 | static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) |
| 63 | { |
| 64 | while (((Freqm *)hw)->SYNCBUSY.reg & reg) { |
| 65 | }; |
| 66 | } |
| 67 | |
| 68 | static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) |
| 69 | { |
| 70 | return ((Freqm *)hw)->SYNCBUSY.reg & reg; |
| 71 | } |
| 72 | |
| 73 | static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) |
| 74 | { |
| 75 | return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; |
| 76 | } |
| 77 | |
| 78 | static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) |
| 79 | { |
| 80 | ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; |
| 81 | } |
| 82 | |
| 83 | static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) |
| 84 | { |
| 85 | return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; |
| 86 | } |
| 87 | |
| 88 | static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) |
| 89 | { |
| 90 | ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; |
| 91 | } |
| 92 | |
| 93 | static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) |
| 94 | { |
| 95 | uint8_t tmp; |
| 96 | tmp = ((Freqm *)hw)->INTFLAG.reg; |
| 97 | tmp &= mask; |
| 98 | return tmp; |
| 99 | } |
| 100 | |
| 101 | static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) |
| 102 | { |
| 103 | return ((Freqm *)hw)->INTFLAG.reg; |
| 104 | } |
| 105 | |
| 106 | static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) |
| 107 | { |
| 108 | ((Freqm *)hw)->INTFLAG.reg = mask; |
| 109 | } |
| 110 | |
| 111 | static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) |
| 112 | { |
| 113 | ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; |
| 114 | } |
| 115 | |
| 116 | static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) |
| 117 | { |
| 118 | return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; |
| 119 | } |
| 120 | |
| 121 | static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) |
| 122 | { |
| 123 | if (value == 0x0) { |
| 124 | ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; |
| 125 | } else { |
| 126 | ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) |
| 131 | { |
| 132 | ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; |
| 133 | } |
| 134 | |
| 135 | static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) |
| 136 | { |
| 137 | ((Freqm *)hw)->INTENSET.reg = mask; |
| 138 | } |
| 139 | |
| 140 | static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) |
| 141 | { |
| 142 | uint8_t tmp; |
| 143 | tmp = ((Freqm *)hw)->INTENSET.reg; |
| 144 | tmp &= mask; |
| 145 | return tmp; |
| 146 | } |
| 147 | |
| 148 | static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) |
| 149 | { |
| 150 | return ((Freqm *)hw)->INTENSET.reg; |
| 151 | } |
| 152 | |
| 153 | static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) |
| 154 | { |
| 155 | ((Freqm *)hw)->INTENSET.reg = data; |
| 156 | ((Freqm *)hw)->INTENCLR.reg = ~data; |
| 157 | } |
| 158 | |
| 159 | static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) |
| 160 | { |
| 161 | ((Freqm *)hw)->INTENCLR.reg = mask; |
| 162 | } |
| 163 | |
| 164 | static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 165 | { |
| 166 | return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; |
| 167 | } |
| 168 | |
| 169 | static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 170 | { |
| 171 | return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; |
| 172 | } |
| 173 | |
| 174 | static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) |
| 175 | { |
| 176 | uint32_t tmp; |
| 177 | tmp = ((Freqm *)hw)->SYNCBUSY.reg; |
| 178 | tmp &= mask; |
| 179 | return tmp; |
| 180 | } |
| 181 | |
| 182 | static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) |
| 183 | { |
| 184 | return ((Freqm *)hw)->SYNCBUSY.reg; |
| 185 | } |
| 186 | |
| 187 | static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) |
| 188 | { |
| 189 | return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; |
| 190 | } |
| 191 | |
| 192 | static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) |
| 193 | { |
| 194 | return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; |
| 195 | } |
| 196 | |
| 197 | static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) |
| 198 | { |
| 199 | uint32_t tmp; |
| 200 | tmp = ((Freqm *)hw)->VALUE.reg; |
| 201 | tmp &= mask; |
| 202 | return tmp; |
| 203 | } |
| 204 | |
| 205 | static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) |
| 206 | { |
| 207 | return ((Freqm *)hw)->VALUE.reg; |
| 208 | } |
| 209 | |
| 210 | static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) |
| 211 | { |
| 212 | FREQM_CRITICAL_SECTION_ENTER(); |
| 213 | ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; |
| 214 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); |
| 215 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 216 | } |
| 217 | |
| 218 | static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) |
| 219 | { |
| 220 | uint8_t tmp; |
| 221 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); |
| 222 | tmp = ((Freqm *)hw)->CTRLA.reg; |
| 223 | tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; |
| 224 | return (bool)tmp; |
| 225 | } |
| 226 | |
| 227 | static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) |
| 228 | { |
| 229 | FREQM_CRITICAL_SECTION_ENTER(); |
| 230 | ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; |
| 231 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); |
| 232 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 233 | } |
| 234 | |
| 235 | static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) |
| 236 | { |
| 237 | uint8_t tmp; |
| 238 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); |
| 239 | tmp = ((Freqm *)hw)->CTRLA.reg; |
| 240 | tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; |
| 241 | return (bool)tmp; |
| 242 | } |
| 243 | |
| 244 | static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 245 | { |
| 246 | uint8_t tmp; |
| 247 | FREQM_CRITICAL_SECTION_ENTER(); |
| 248 | tmp = ((Freqm *)hw)->CTRLA.reg; |
| 249 | tmp &= ~FREQM_CTRLA_ENABLE; |
| 250 | tmp |= value << FREQM_CTRLA_ENABLE_Pos; |
| 251 | ((Freqm *)hw)->CTRLA.reg = tmp; |
| 252 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); |
| 253 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 254 | } |
| 255 | |
| 256 | static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 257 | { |
| 258 | FREQM_CRITICAL_SECTION_ENTER(); |
| 259 | ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; |
| 260 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); |
| 261 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 262 | } |
| 263 | |
| 264 | static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 265 | { |
| 266 | FREQM_CRITICAL_SECTION_ENTER(); |
| 267 | ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; |
| 268 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); |
| 269 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 270 | } |
| 271 | |
| 272 | static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) |
| 273 | { |
| 274 | FREQM_CRITICAL_SECTION_ENTER(); |
| 275 | ((Freqm *)hw)->CTRLA.reg |= mask; |
| 276 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); |
| 277 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 278 | } |
| 279 | |
| 280 | static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) |
| 281 | { |
| 282 | uint8_t tmp; |
| 283 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); |
| 284 | tmp = ((Freqm *)hw)->CTRLA.reg; |
| 285 | tmp &= mask; |
| 286 | return tmp; |
| 287 | } |
| 288 | |
| 289 | static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) |
| 290 | { |
| 291 | FREQM_CRITICAL_SECTION_ENTER(); |
| 292 | ((Freqm *)hw)->CTRLA.reg = data; |
| 293 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); |
| 294 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 295 | } |
| 296 | |
| 297 | static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) |
| 298 | { |
| 299 | FREQM_CRITICAL_SECTION_ENTER(); |
| 300 | ((Freqm *)hw)->CTRLA.reg &= ~mask; |
| 301 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); |
| 302 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 303 | } |
| 304 | |
| 305 | static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) |
| 306 | { |
| 307 | FREQM_CRITICAL_SECTION_ENTER(); |
| 308 | ((Freqm *)hw)->CTRLA.reg ^= mask; |
| 309 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); |
| 310 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 311 | } |
| 312 | |
| 313 | static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) |
| 314 | { |
| 315 | hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); |
| 316 | return ((Freqm *)hw)->CTRLA.reg; |
| 317 | } |
| 318 | |
| 319 | static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 320 | { |
| 321 | FREQM_CRITICAL_SECTION_ENTER(); |
| 322 | ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); |
| 323 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 324 | } |
| 325 | |
| 326 | static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 327 | { |
| 328 | uint16_t tmp; |
| 329 | tmp = ((Freqm *)hw)->CFGA.reg; |
| 330 | tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; |
| 331 | return tmp; |
| 332 | } |
| 333 | |
| 334 | static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) |
| 335 | { |
| 336 | uint16_t tmp; |
| 337 | FREQM_CRITICAL_SECTION_ENTER(); |
| 338 | tmp = ((Freqm *)hw)->CFGA.reg; |
| 339 | tmp &= ~FREQM_CFGA_REFNUM_Msk; |
| 340 | tmp |= FREQM_CFGA_REFNUM(data); |
| 341 | ((Freqm *)hw)->CFGA.reg = tmp; |
| 342 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 343 | } |
| 344 | |
| 345 | static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 346 | { |
| 347 | FREQM_CRITICAL_SECTION_ENTER(); |
| 348 | ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); |
| 349 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 350 | } |
| 351 | |
| 352 | static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 353 | { |
| 354 | FREQM_CRITICAL_SECTION_ENTER(); |
| 355 | ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); |
| 356 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 357 | } |
| 358 | |
| 359 | static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) |
| 360 | { |
| 361 | uint16_t tmp; |
| 362 | tmp = ((Freqm *)hw)->CFGA.reg; |
| 363 | tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; |
| 364 | return tmp; |
| 365 | } |
| 366 | |
| 367 | static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 368 | { |
| 369 | FREQM_CRITICAL_SECTION_ENTER(); |
| 370 | ((Freqm *)hw)->CFGA.reg |= mask; |
| 371 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 372 | } |
| 373 | |
| 374 | static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 375 | { |
| 376 | uint16_t tmp; |
| 377 | tmp = ((Freqm *)hw)->CFGA.reg; |
| 378 | tmp &= mask; |
| 379 | return tmp; |
| 380 | } |
| 381 | |
| 382 | static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) |
| 383 | { |
| 384 | FREQM_CRITICAL_SECTION_ENTER(); |
| 385 | ((Freqm *)hw)->CFGA.reg = data; |
| 386 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 387 | } |
| 388 | |
| 389 | static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 390 | { |
| 391 | FREQM_CRITICAL_SECTION_ENTER(); |
| 392 | ((Freqm *)hw)->CFGA.reg &= ~mask; |
| 393 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 394 | } |
| 395 | |
| 396 | static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) |
| 397 | { |
| 398 | FREQM_CRITICAL_SECTION_ENTER(); |
| 399 | ((Freqm *)hw)->CFGA.reg ^= mask; |
| 400 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 401 | } |
| 402 | |
| 403 | static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) |
| 404 | { |
| 405 | return ((Freqm *)hw)->CFGA.reg; |
| 406 | } |
| 407 | |
| 408 | static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) |
| 409 | { |
| 410 | return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; |
| 411 | } |
| 412 | |
| 413 | static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) |
| 414 | { |
| 415 | FREQM_CRITICAL_SECTION_ENTER(); |
| 416 | ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; |
| 417 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 418 | } |
| 419 | |
| 420 | static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) |
| 421 | { |
| 422 | return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; |
| 423 | } |
| 424 | |
| 425 | static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) |
| 426 | { |
| 427 | FREQM_CRITICAL_SECTION_ENTER(); |
| 428 | ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; |
| 429 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 430 | } |
| 431 | |
| 432 | static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) |
| 433 | { |
| 434 | uint8_t tmp; |
| 435 | tmp = ((Freqm *)hw)->STATUS.reg; |
| 436 | tmp &= mask; |
| 437 | return tmp; |
| 438 | } |
| 439 | |
| 440 | static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) |
| 441 | { |
| 442 | FREQM_CRITICAL_SECTION_ENTER(); |
| 443 | ((Freqm *)hw)->STATUS.reg = mask; |
| 444 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 445 | } |
| 446 | |
| 447 | static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) |
| 448 | { |
| 449 | return ((Freqm *)hw)->STATUS.reg; |
| 450 | } |
| 451 | |
| 452 | static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) |
| 453 | { |
| 454 | FREQM_CRITICAL_SECTION_ENTER(); |
| 455 | ((Freqm *)hw)->CTRLB.reg = data; |
| 456 | FREQM_CRITICAL_SECTION_LEAVE(); |
| 457 | } |
| 458 | |
| 459 | #ifdef __cplusplus |
| 460 | } |
| 461 | #endif |
| 462 | |
| 463 | #endif /* _HRI_FREQM_E54_H_INCLUDED */ |
| 464 | #endif /* _SAME54_FREQM_COMPONENT_ */ |