Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for TCC2 |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_TCC2_INSTANCE_ |
| 31 | #define _SAME54_TCC2_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for TCC2 peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_TCC2_CTRLA (0x42000C00) /**< \brief (TCC2) Control A */ |
| 36 | #define REG_TCC2_CTRLBCLR (0x42000C04) /**< \brief (TCC2) Control B Clear */ |
| 37 | #define REG_TCC2_CTRLBSET (0x42000C05) /**< \brief (TCC2) Control B Set */ |
| 38 | #define REG_TCC2_SYNCBUSY (0x42000C08) /**< \brief (TCC2) Synchronization Busy */ |
| 39 | #define REG_TCC2_FCTRLA (0x42000C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */ |
| 40 | #define REG_TCC2_FCTRLB (0x42000C10) /**< \brief (TCC2) Recoverable Fault B Configuration */ |
| 41 | #define REG_TCC2_WEXCTRL (0x42000C14) /**< \brief (TCC2) Waveform Extension Configuration */ |
| 42 | #define REG_TCC2_DRVCTRL (0x42000C18) /**< \brief (TCC2) Driver Control */ |
| 43 | #define REG_TCC2_DBGCTRL (0x42000C1E) /**< \brief (TCC2) Debug Control */ |
| 44 | #define REG_TCC2_EVCTRL (0x42000C20) /**< \brief (TCC2) Event Control */ |
| 45 | #define REG_TCC2_INTENCLR (0x42000C24) /**< \brief (TCC2) Interrupt Enable Clear */ |
| 46 | #define REG_TCC2_INTENSET (0x42000C28) /**< \brief (TCC2) Interrupt Enable Set */ |
| 47 | #define REG_TCC2_INTFLAG (0x42000C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */ |
| 48 | #define REG_TCC2_STATUS (0x42000C30) /**< \brief (TCC2) Status */ |
| 49 | #define REG_TCC2_COUNT (0x42000C34) /**< \brief (TCC2) Count */ |
| 50 | #define REG_TCC2_WAVE (0x42000C3C) /**< \brief (TCC2) Waveform Control */ |
| 51 | #define REG_TCC2_PER (0x42000C40) /**< \brief (TCC2) Period */ |
| 52 | #define REG_TCC2_CC0 (0x42000C44) /**< \brief (TCC2) Compare and Capture 0 */ |
| 53 | #define REG_TCC2_CC1 (0x42000C48) /**< \brief (TCC2) Compare and Capture 1 */ |
| 54 | #define REG_TCC2_CC2 (0x42000C4C) /**< \brief (TCC2) Compare and Capture 2 */ |
| 55 | #define REG_TCC2_PERBUF (0x42000C6C) /**< \brief (TCC2) Period Buffer */ |
| 56 | #define REG_TCC2_CCBUF0 (0x42000C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */ |
| 57 | #define REG_TCC2_CCBUF1 (0x42000C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */ |
| 58 | #define REG_TCC2_CCBUF2 (0x42000C78) /**< \brief (TCC2) Compare and Capture Buffer 2 */ |
| 59 | #else |
| 60 | #define REG_TCC2_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (TCC2) Control A */ |
| 61 | #define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42000C04UL) /**< \brief (TCC2) Control B Clear */ |
| 62 | #define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42000C05UL) /**< \brief (TCC2) Control B Set */ |
| 63 | #define REG_TCC2_SYNCBUSY (*(RoReg *)0x42000C08UL) /**< \brief (TCC2) Synchronization Busy */ |
| 64 | #define REG_TCC2_FCTRLA (*(RwReg *)0x42000C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */ |
| 65 | #define REG_TCC2_FCTRLB (*(RwReg *)0x42000C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */ |
| 66 | #define REG_TCC2_WEXCTRL (*(RwReg *)0x42000C14UL) /**< \brief (TCC2) Waveform Extension Configuration */ |
| 67 | #define REG_TCC2_DRVCTRL (*(RwReg *)0x42000C18UL) /**< \brief (TCC2) Driver Control */ |
| 68 | #define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42000C1EUL) /**< \brief (TCC2) Debug Control */ |
| 69 | #define REG_TCC2_EVCTRL (*(RwReg *)0x42000C20UL) /**< \brief (TCC2) Event Control */ |
| 70 | #define REG_TCC2_INTENCLR (*(RwReg *)0x42000C24UL) /**< \brief (TCC2) Interrupt Enable Clear */ |
| 71 | #define REG_TCC2_INTENSET (*(RwReg *)0x42000C28UL) /**< \brief (TCC2) Interrupt Enable Set */ |
| 72 | #define REG_TCC2_INTFLAG (*(RwReg *)0x42000C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */ |
| 73 | #define REG_TCC2_STATUS (*(RwReg *)0x42000C30UL) /**< \brief (TCC2) Status */ |
| 74 | #define REG_TCC2_COUNT (*(RwReg *)0x42000C34UL) /**< \brief (TCC2) Count */ |
| 75 | #define REG_TCC2_WAVE (*(RwReg *)0x42000C3CUL) /**< \brief (TCC2) Waveform Control */ |
| 76 | #define REG_TCC2_PER (*(RwReg *)0x42000C40UL) /**< \brief (TCC2) Period */ |
| 77 | #define REG_TCC2_CC0 (*(RwReg *)0x42000C44UL) /**< \brief (TCC2) Compare and Capture 0 */ |
| 78 | #define REG_TCC2_CC1 (*(RwReg *)0x42000C48UL) /**< \brief (TCC2) Compare and Capture 1 */ |
| 79 | #define REG_TCC2_CC2 (*(RwReg *)0x42000C4CUL) /**< \brief (TCC2) Compare and Capture 2 */ |
| 80 | #define REG_TCC2_PERBUF (*(RwReg *)0x42000C6CUL) /**< \brief (TCC2) Period Buffer */ |
| 81 | #define REG_TCC2_CCBUF0 (*(RwReg *)0x42000C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */ |
| 82 | #define REG_TCC2_CCBUF1 (*(RwReg *)0x42000C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */ |
| 83 | #define REG_TCC2_CCBUF2 (*(RwReg *)0x42000C78UL) /**< \brief (TCC2) Compare and Capture Buffer 2 */ |
| 84 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 85 | |
| 86 | /* ========== Instance parameters for TCC2 peripheral ========== */ |
| 87 | #define TCC2_CC_NUM 3 // Number of Compare/Capture units |
| 88 | #define TCC2_DITHERING 0 // Dithering feature implemented |
| 89 | #define TCC2_DMAC_ID_MC_0 35 |
| 90 | #define TCC2_DMAC_ID_MC_1 36 |
| 91 | #define TCC2_DMAC_ID_MC_2 37 |
| 92 | #define TCC2_DMAC_ID_MC_LSB 35 |
| 93 | #define TCC2_DMAC_ID_MC_MSB 37 |
| 94 | #define TCC2_DMAC_ID_MC_SIZE 3 |
| 95 | #define TCC2_DMAC_ID_OVF 34 // DMA overflow/underflow/retrigger trigger |
| 96 | #define TCC2_DTI 0 // Dead-Time-Insertion feature implemented |
| 97 | #define TCC2_EXT 1 // Coding of implemented extended features |
| 98 | #define TCC2_GCLK_ID 29 // Index of Generic Clock |
| 99 | #define TCC2_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave |
| 100 | #define TCC2_OTMX 1 // Output Matrix feature implemented |
| 101 | #define TCC2_OW_NUM 3 // Number of Output Waveforms |
| 102 | #define TCC2_PG 0 // Pattern Generation feature implemented |
| 103 | #define TCC2_SIZE 16 |
| 104 | #define TCC2_SWAP 0 // DTI outputs swap feature implemented |
| 105 | |
| 106 | #endif /* _SAME54_TCC2_INSTANCE_ */ |