| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for NVMCTRL |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_NVMCTRL_INSTANCE_ |
| 31 | #define _SAME54_NVMCTRL_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for NVMCTRL peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ |
| 36 | #define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ |
| 37 | #define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ |
| 38 | #define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ |
| 39 | #define REG_NVMCTRL_INTENSET (0x4100400E) /**< \brief (NVMCTRL) Interrupt Enable Set */ |
| 40 | #define REG_NVMCTRL_INTFLAG (0x41004010) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ |
| 41 | #define REG_NVMCTRL_STATUS (0x41004012) /**< \brief (NVMCTRL) Status */ |
| 42 | #define REG_NVMCTRL_ADDR (0x41004014) /**< \brief (NVMCTRL) Address */ |
| 43 | #define REG_NVMCTRL_RUNLOCK (0x41004018) /**< \brief (NVMCTRL) Lock Section */ |
| 44 | #define REG_NVMCTRL_PBLDATA0 (0x4100401C) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */ |
| 45 | #define REG_NVMCTRL_PBLDATA1 (0x41004020) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */ |
| 46 | #define REG_NVMCTRL_ECCERR (0x41004024) /**< \brief (NVMCTRL) ECC Error Status Register */ |
| 47 | #define REG_NVMCTRL_DBGCTRL (0x41004028) /**< \brief (NVMCTRL) Debug Control */ |
| 48 | #define REG_NVMCTRL_SEECFG (0x4100402A) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */ |
| 49 | #define REG_NVMCTRL_SEESTAT (0x4100402C) /**< \brief (NVMCTRL) SmartEEPROM Status Register */ |
| 50 | #else |
| 51 | #define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ |
| 52 | #define REG_NVMCTRL_CTRLB (*(WoReg16*)0x41004004UL) /**< \brief (NVMCTRL) Control B */ |
| 53 | #define REG_NVMCTRL_PARAM (*(RoReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ |
| 54 | #define REG_NVMCTRL_INTENCLR (*(RwReg16*)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ |
| 55 | #define REG_NVMCTRL_INTENSET (*(RwReg16*)0x4100400EUL) /**< \brief (NVMCTRL) Interrupt Enable Set */ |
| 56 | #define REG_NVMCTRL_INTFLAG (*(RwReg16*)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ |
| 57 | #define REG_NVMCTRL_STATUS (*(RoReg16*)0x41004012UL) /**< \brief (NVMCTRL) Status */ |
| 58 | #define REG_NVMCTRL_ADDR (*(RwReg *)0x41004014UL) /**< \brief (NVMCTRL) Address */ |
| 59 | #define REG_NVMCTRL_RUNLOCK (*(RoReg *)0x41004018UL) /**< \brief (NVMCTRL) Lock Section */ |
| 60 | #define REG_NVMCTRL_PBLDATA0 (*(RoReg *)0x4100401CUL) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */ |
| 61 | #define REG_NVMCTRL_PBLDATA1 (*(RoReg *)0x41004020UL) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */ |
| 62 | #define REG_NVMCTRL_ECCERR (*(RoReg *)0x41004024UL) /**< \brief (NVMCTRL) ECC Error Status Register */ |
| 63 | #define REG_NVMCTRL_DBGCTRL (*(RwReg8 *)0x41004028UL) /**< \brief (NVMCTRL) Debug Control */ |
| 64 | #define REG_NVMCTRL_SEECFG (*(RwReg8 *)0x4100402AUL) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */ |
| 65 | #define REG_NVMCTRL_SEESTAT (*(RoReg *)0x4100402CUL) /**< \brief (NVMCTRL) SmartEEPROM Status Register */ |
| 66 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 67 | |
| 68 | /* ========== Instance parameters for NVMCTRL peripheral ========== */ |
| 69 | #define NVMCTRL_BLOCK_SIZE 8192 // Size Of Block (Bytes, Smallest Granularity for Erase Operation) |
| 70 | #define NVMCTRL_CLK_AHB_ID 6 // Index of AHB Clock in PM.AHBMASK register |
| 71 | #define NVMCTRL_CLK_AHB_ID_CACHE 23 // Index of AHB Clock in PM.AHBMASK register for NVMCTRL CACHE lines |
| 72 | #define NVMCTRL_CLK_AHB_ID_SMEEPROM 22 // Index of AHB Clock in PM.AHBMASK register for SMEE submodule |
| 73 | #define NVMCTRL_PAGE_SIZE 512 // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array) |
| 74 | |
| 75 | #endif /* _SAME54_NVMCTRL_INSTANCE_ */ |