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gerrit.osmocom.org / osmo-ccid-firmware / 18c2dbbb15a1a66bbf009ea57d5b281e24468645 / . / sysmoOCTSIM / CMSIS / Include / core_sc000.h
blob: 8305271f48a4da3852ad0910cc4fff59c00ba0bd [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V5.0.1
5 * @date 25. November 2016
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_SC000_H_GENERIC
32#define __CORE_SC000_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup SC000
60 @{
61 */
62
63/* CMSIS SC000 definitions */
64#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
67 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69#define __CORTEX_SC (000U) /*!< Cortex secure core */
70
71/** __FPU_USED indicates whether an FPU is used or not.
72 This core does not support an FPU at all
73*/
74#define __FPU_USED 0U
75
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #endif
80
81#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
82 #if defined __ARM_PCS_VFP
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #endif
85
86#elif defined ( __GNUC__ )
87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89 #endif
90
91#elif defined ( __ICCARM__ )
92 #if defined __ARMVFP__
93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #endif
95
96#elif defined ( __TI_ARM__ )
97 #if defined __TI_VFP_SUPPORT__
98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99 #endif
100
101#elif defined ( __TASKING__ )
102 #if defined __FPU_VFP__
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #endif
105
106#elif defined ( __CSMC__ )
107 #if ( __CSMC__ & 0x400U)
108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109 #endif
110
111#endif
112
113#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
114
115
116#ifdef __cplusplus
117}
118#endif
119
120#endif /* __CORE_SC000_H_GENERIC */
121
122#ifndef __CMSIS_GENERIC
123
124#ifndef __CORE_SC000_H_DEPENDANT
125#define __CORE_SC000_H_DEPENDANT
126
127#ifdef __cplusplus
128 extern "C" {
129#endif
130
131/* check device defines and use defaults */
132#if defined __CHECK_DEVICE_DEFINES
133 #ifndef __SC000_REV
134 #define __SC000_REV 0x0000U
135 #warning "__SC000_REV not defined in device header file; using default!"
136 #endif
137
138 #ifndef __MPU_PRESENT
139 #define __MPU_PRESENT 0U
140 #warning "__MPU_PRESENT not defined in device header file; using default!"
141 #endif
142
143 #ifndef __NVIC_PRIO_BITS
144 #define __NVIC_PRIO_BITS 2U
145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
146 #endif
147
148 #ifndef __Vendor_SysTickConfig
149 #define __Vendor_SysTickConfig 0U
150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
151 #endif
152#endif
153
154/* IO definitions (access restrictions to peripheral registers) */
155/**
156 \defgroup CMSIS_glob_defs CMSIS Global Defines
157
158 <strong>IO Type Qualifiers</strong> are used
159 \li to specify the access to peripheral variables.
160 \li for automatic generation of peripheral register debug information.
161*/
162#ifdef __cplusplus
163 #define __I volatile /*!< Defines 'read only' permissions */
164#else
165 #define __I volatile const /*!< Defines 'read only' permissions */
166#endif
167#define __O volatile /*!< Defines 'write only' permissions */
168#define __IO volatile /*!< Defines 'read / write' permissions */
169
170/* following defines should be used for structure members */
171#define __IM volatile const /*! Defines 'read only' structure member permissions */
172#define __OM volatile /*! Defines 'write only' structure member permissions */
173#define __IOM volatile /*! Defines 'read / write' structure member permissions */
174
175/*@} end of group SC000 */
176
177
178
179/*******************************************************************************
180 * Register Abstraction
181 Core Register contain:
182 - Core Register
183 - Core NVIC Register
184 - Core SCB Register
185 - Core SysTick Register
186 - Core MPU Register
187 ******************************************************************************/
188/**
189 \defgroup CMSIS_core_register Defines and Type Definitions
190 \brief Type definitions and defines for Cortex-M processor based devices.
191*/
192
193/**
194 \ingroup CMSIS_core_register
195 \defgroup CMSIS_CORE Status and Control Registers
196 \brief Core Register type definitions.
197 @{
198 */
199
200/**
201 \brief Union type to access the Application Program Status Register (APSR).
202 */
203typedef union
204{
205 struct
206 {
207 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
212 } b; /*!< Structure used for bit access */
213 uint32_t w; /*!< Type used for word access */
214} APSR_Type;
215
216/* APSR Register Definitions */
217#define APSR_N_Pos 31U /*!< APSR: N Position */
218#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
219
220#define APSR_Z_Pos 30U /*!< APSR: Z Position */
221#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
222
223#define APSR_C_Pos 29U /*!< APSR: C Position */
224#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
225
226#define APSR_V_Pos 28U /*!< APSR: V Position */
227#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
228
229
230/**
231 \brief Union type to access the Interrupt Program Status Register (IPSR).
232 */
233typedef union
234{
235 struct
236 {
237 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
238 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
239 } b; /*!< Structure used for bit access */
240 uint32_t w; /*!< Type used for word access */
241} IPSR_Type;
242
243/* IPSR Register Definitions */
244#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
245#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
246
247
248/**
249 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
250 */
251typedef union
252{
253 struct
254 {
255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
256 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
257 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
258 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
259 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
260 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
261 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
262 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
263 } b; /*!< Structure used for bit access */
264 uint32_t w; /*!< Type used for word access */
265} xPSR_Type;
266
267/* xPSR Register Definitions */
268#define xPSR_N_Pos 31U /*!< xPSR: N Position */
269#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
270
271#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
272#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
273
274#define xPSR_C_Pos 29U /*!< xPSR: C Position */
275#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
276
277#define xPSR_V_Pos 28U /*!< xPSR: V Position */
278#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
279
280#define xPSR_T_Pos 24U /*!< xPSR: T Position */
281#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
282
283#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
284#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
285
286
287/**
288 \brief Union type to access the Control Registers (CONTROL).
289 */
290typedef union
291{
292 struct
293 {
294 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
296 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
297 } b; /*!< Structure used for bit access */
298 uint32_t w; /*!< Type used for word access */
299} CONTROL_Type;
300
301/* CONTROL Register Definitions */
302#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
303#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
304
305/*@} end of group CMSIS_CORE */
306
307
308/**
309 \ingroup CMSIS_core_register
310 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
311 \brief Type definitions for the NVIC Registers
312 @{
313 */
314
315/**
316 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
317 */
318typedef struct
319{
320 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
321 uint32_t RESERVED0[31U];
322 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
323 uint32_t RSERVED1[31U];
324 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
325 uint32_t RESERVED2[31U];
326 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
327 uint32_t RESERVED3[31U];
328 uint32_t RESERVED4[64U];
329 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
330} NVIC_Type;
331
332/*@} end of group CMSIS_NVIC */
333
334
335/**
336 \ingroup CMSIS_core_register
337 \defgroup CMSIS_SCB System Control Block (SCB)
338 \brief Type definitions for the System Control Block Registers
339 @{
340 */
341
342/**
343 \brief Structure type to access the System Control Block (SCB).
344 */
345typedef struct
346{
347 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
348 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
349 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
350 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
351 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
352 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
353 uint32_t RESERVED0[1U];
354 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
355 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
356 uint32_t RESERVED1[154U];
357 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
358} SCB_Type;
359
360/* SCB CPUID Register Definitions */
361#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
362#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
363
364#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
365#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
366
367#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
368#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
369
370#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
371#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
372
373#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
374#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
375
376/* SCB Interrupt Control State Register Definitions */
377#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
378#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
379
380#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
381#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
382
383#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
384#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
385
386#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
387#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
388
389#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
390#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
391
392#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
393#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
394
395#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
396#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
397
398#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
399#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
400
401#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
402#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
403
404/* SCB Interrupt Control State Register Definitions */
405#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
406#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
407
408/* SCB Application Interrupt and Reset Control Register Definitions */
409#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
410#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
411
412#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
413#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
414
415#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
416#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
417
418#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
419#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
420
421#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
422#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
423
424/* SCB System Control Register Definitions */
425#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
426#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
427
428#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
429#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
430
431#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
432#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
433
434/* SCB Configuration Control Register Definitions */
435#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
436#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
437
438#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
439#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
440
441/* SCB System Handler Control and State Register Definitions */
442#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
443#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
444
445/*@} end of group CMSIS_SCB */
446
447
448/**
449 \ingroup CMSIS_core_register
450 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
451 \brief Type definitions for the System Control and ID Register not in the SCB
452 @{
453 */
454
455/**
456 \brief Structure type to access the System Control and ID Register not in the SCB.
457 */
458typedef struct
459{
460 uint32_t RESERVED0[2U];
461 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
462} SCnSCB_Type;
463
464/* Auxiliary Control Register Definitions */
465#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
466#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
467
468/*@} end of group CMSIS_SCnotSCB */
469
470
471/**
472 \ingroup CMSIS_core_register
473 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
474 \brief Type definitions for the System Timer Registers.
475 @{
476 */
477
478/**
479 \brief Structure type to access the System Timer (SysTick).
480 */
481typedef struct
482{
483 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
484 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
485 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
486 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
487} SysTick_Type;
488
489/* SysTick Control / Status Register Definitions */
490#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
491#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
492
493#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
494#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
495
496#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
497#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
498
499#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
500#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
501
502/* SysTick Reload Register Definitions */
503#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
504#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
505
506/* SysTick Current Register Definitions */
507#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
508#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
509
510/* SysTick Calibration Register Definitions */
511#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
512#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
513
514#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
515#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
516
517#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
518#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
519
520/*@} end of group CMSIS_SysTick */
521
522#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
523/**
524 \ingroup CMSIS_core_register
525 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
526 \brief Type definitions for the Memory Protection Unit (MPU)
527 @{
528 */
529
530/**
531 \brief Structure type to access the Memory Protection Unit (MPU).
532 */
533typedef struct
534{
535 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
536 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
537 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
538 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
539 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
540} MPU_Type;
541
542/* MPU Type Register Definitions */
543#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
544#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
545
546#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
547#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
548
549#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
550#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
551
552/* MPU Control Register Definitions */
553#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
554#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
555
556#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
557#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
558
559#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
560#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
561
562/* MPU Region Number Register Definitions */
563#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
564#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
565
566/* MPU Region Base Address Register Definitions */
567#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
568#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
569
570#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
571#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
572
573#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
574#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
575
576/* MPU Region Attribute and Size Register Definitions */
577#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
578#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
579
580#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
581#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
582
583#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
584#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
585
586#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
587#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
588
589#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
590#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
591
592#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
593#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
594
595#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
596#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
597
598#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
599#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
600
601#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
602#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
603
604#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
605#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
606
607/*@} end of group CMSIS_MPU */
608#endif
609
610
611/**
612 \ingroup CMSIS_core_register
613 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
614 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
615 Therefore they are not covered by the SC000 header file.
616 @{
617 */
618/*@} end of group CMSIS_CoreDebug */
619
620
621/**
622 \ingroup CMSIS_core_register
623 \defgroup CMSIS_core_bitfield Core register bit field macros
624 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
625 @{
626 */
627
628/**
629 \brief Mask and shift a bit field value for use in a register bit range.
630 \param[in] field Name of the register bit field.
631 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
632 \return Masked and shifted value.
633*/
634#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
635
636/**
637 \brief Mask and shift a register value to extract a bit filed value.
638 \param[in] field Name of the register bit field.
639 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
640 \return Masked and shifted bit field value.
641*/
642#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
643
644/*@} end of group CMSIS_core_bitfield */
645
646
647/**
648 \ingroup CMSIS_core_register
649 \defgroup CMSIS_core_base Core Definitions
650 \brief Definitions for base addresses, unions, and structures.
651 @{
652 */
653
654/* Memory mapping of Core Hardware */
655#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
656#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
657#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
658#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
659
660#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
661#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
662#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
663#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
664
665#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
666 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
667 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
668#endif
669
670/*@} */
671
672
673
674/*******************************************************************************
675 * Hardware Abstraction Layer
676 Core Function Interface contains:
677 - Core NVIC Functions
678 - Core SysTick Functions
679 - Core Register Access Functions
680 ******************************************************************************/
681/**
682 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
683*/
684
685
686
687/* ########################## NVIC functions #################################### */
688/**
689 \ingroup CMSIS_Core_FunctionInterface
690 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
691 \brief Functions that manage interrupts and exceptions via the NVIC.
692 @{
693 */
694
695#ifndef CMSIS_NVIC_VIRTUAL
696/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
697/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
698 #define NVIC_EnableIRQ __NVIC_EnableIRQ
699 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
700 #define NVIC_DisableIRQ __NVIC_DisableIRQ
701 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
702 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
703 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
704/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
705 #define NVIC_SetPriority __NVIC_SetPriority
706 #define NVIC_GetPriority __NVIC_GetPriority
707#endif /* CMSIS_NVIC_VIRTUAL */
708
709#ifndef CMSIS_VECTAB_VIRTUAL
710 #define NVIC_SetVector __NVIC_SetVector
711 #define NVIC_GetVector __NVIC_GetVector
712#endif /* (CMSIS_VECTAB_VIRTUAL) */
713
714#define NVIC_USER_IRQ_OFFSET 16
715
716
717/* Interrupt Priorities are WORD accessible only under ARMv6M */
718/* The following MACROS handle generation of the register offset and byte masks */
719#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
720#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
721#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
722
723
724/**
725 \brief Enable Interrupt
726 \details Enables a device specific interrupt in the NVIC interrupt controller.
727 \param [in] IRQn Device specific interrupt number.
728 \note IRQn must not be negative.
729 */
730__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
731{
732 if ((int32_t)(IRQn) >= 0)
733 {
734 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
735 }
736}
737
738
739/**
740 \brief Get Interrupt Enable status
741 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
742 \param [in] IRQn Device specific interrupt number.
743 \return 0 Interrupt is not enabled.
744 \return 1 Interrupt is enabled.
745 \note IRQn must not be negative.
746 */
747__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
748{
749 if ((int32_t)(IRQn) >= 0)
750 {
751 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
752 }
753 else
754 {
755 return(0U);
756 }
757}
758
759
760/**
761 \brief Disable Interrupt
762 \details Disables a device specific interrupt in the NVIC interrupt controller.
763 \param [in] IRQn Device specific interrupt number.
764 \note IRQn must not be negative.
765 */
766__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
767{
768 if ((int32_t)(IRQn) >= 0)
769 {
770 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
771 __DSB();
772 __ISB();
773 }
774}
775
776
777/**
778 \brief Get Pending Interrupt
779 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
780 \param [in] IRQn Device specific interrupt number.
781 \return 0 Interrupt status is not pending.
782 \return 1 Interrupt status is pending.
783 \note IRQn must not be negative.
784 */
785__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
786{
787 if ((int32_t)(IRQn) >= 0)
788 {
789 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
790 }
791 else
792 {
793 return(0U);
794 }
795}
796
797
798/**
799 \brief Set Pending Interrupt
800 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
801 \param [in] IRQn Device specific interrupt number.
802 \note IRQn must not be negative.
803 */
804__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
805{
806 if ((int32_t)(IRQn) >= 0)
807 {
808 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
809 }
810}
811
812
813/**
814 \brief Clear Pending Interrupt
815 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
816 \param [in] IRQn Device specific interrupt number.
817 \note IRQn must not be negative.
818 */
819__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
820{
821 if ((int32_t)(IRQn) >= 0)
822 {
823 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
824 }
825}
826
827
828/**
829 \brief Set Interrupt Priority
830 \details Sets the priority of a device specific interrupt or a processor exception.
831 The interrupt number can be positive to specify a device specific interrupt,
832 or negative to specify a processor exception.
833 \param [in] IRQn Interrupt number.
834 \param [in] priority Priority to set.
835 \note The priority cannot be set for every processor exception.
836 */
837__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
838{
839 if ((int32_t)(IRQn) >= 0)
840 {
841 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
842 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
843 }
844 else
845 {
846 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
847 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
848 }
849}
850
851
852/**
853 \brief Get Interrupt Priority
854 \details Reads the priority of a device specific interrupt or a processor exception.
855 The interrupt number can be positive to specify a device specific interrupt,
856 or negative to specify a processor exception.
857 \param [in] IRQn Interrupt number.
858 \return Interrupt Priority.
859 Value is aligned automatically to the implemented priority bits of the microcontroller.
860 */
861__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
862{
863
864 if ((int32_t)(IRQn) >= 0)
865 {
866 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
867 }
868 else
869 {
870 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
871 }
872}
873
874
875/**
876 \brief Set Interrupt Vector
877 \details Sets an interrupt vector in SRAM based interrupt vector table.
878 The interrupt number can be positive to specify a device specific interrupt,
879 or negative to specify a processor exception.
880 VTOR must been relocated to SRAM before.
881 \param [in] IRQn Interrupt number
882 \param [in] vector Address of interrupt handler function
883 */
884__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
885{
886 uint32_t *vectors = (uint32_t *)SCB->VTOR;
887 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
888}
889
890
891/**
892 \brief Get Interrupt Vector
893 \details Reads an interrupt vector from interrupt vector table.
894 The interrupt number can be positive to specify a device specific interrupt,
895 or negative to specify a processor exception.
896 \param [in] IRQn Interrupt number.
897 \return Address of interrupt handler function
898 */
899__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
900{
901 uint32_t *vectors = (uint32_t *)SCB->VTOR;
902 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
903}
904
905
906/**
907 \brief System Reset
908 \details Initiates a system reset request to reset the MCU.
909 */
910__STATIC_INLINE void NVIC_SystemReset(void)
911{
912 __DSB(); /* Ensure all outstanding memory accesses included
913 buffered write are completed before reset */
914 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
915 SCB_AIRCR_SYSRESETREQ_Msk);
916 __DSB(); /* Ensure completion of memory access */
917
918 for(;;) /* wait until reset */
919 {
920 __NOP();
921 }
922}
923
924/*@} end of CMSIS_Core_NVICFunctions */
925
926
927/* ########################## FPU functions #################################### */
928/**
929 \ingroup CMSIS_Core_FunctionInterface
930 \defgroup CMSIS_Core_FpuFunctions FPU Functions
931 \brief Function that provides FPU type.
932 @{
933 */
934
935/**
936 \brief get FPU type
937 \details returns the FPU type
938 \returns
939 - \b 0: No FPU
940 - \b 1: Single precision FPU
941 - \b 2: Double + Single precision FPU
942 */
943__STATIC_INLINE uint32_t SCB_GetFPUType(void)
944{
945 return 0U; /* No FPU */
946}
947
948
949/*@} end of CMSIS_Core_FpuFunctions */
950
951
952
953/* ################################## SysTick function ############################################ */
954/**
955 \ingroup CMSIS_Core_FunctionInterface
956 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
957 \brief Functions that configure the System.
958 @{
959 */
960
961#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
962
963/**
964 \brief System Tick Configuration
965 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
966 Counter is in free running mode to generate periodic interrupts.
967 \param [in] ticks Number of ticks between two interrupts.
968 \return 0 Function succeeded.
969 \return 1 Function failed.
970 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
971 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
972 must contain a vendor-specific implementation of this function.
973 */
974__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
975{
976 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
977 {
978 return (1UL); /* Reload value impossible */
979 }
980
981 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
982 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
983 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
984 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
985 SysTick_CTRL_TICKINT_Msk |
986 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
987 return (0UL); /* Function successful */
988}
989
990#endif
991
992/*@} end of CMSIS_Core_SysTickFunctions */
993
994
995
996
997#ifdef __cplusplus
998}
999#endif
1000
1001#endif /* __CORE_SC000_H_DEPENDANT */
1002
1003#endif /* __CMSIS_GENERIC */