| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /**************************************************************************//** |
| 2 | * @file core_cm7.h |
| 3 | * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File |
| 4 | * @version V5.0.1 |
| 5 | * @date 25. November 2016 |
| 6 | ******************************************************************************/ |
| 7 | /* |
| 8 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. |
| 9 | * |
| 10 | * SPDX-License-Identifier: Apache-2.0 |
| 11 | * |
| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 13 | * not use this file except in compliance with the License. |
| 14 | * You may obtain a copy of the License at |
| 15 | * |
| 16 | * www.apache.org/licenses/LICENSE-2.0 |
| 17 | * |
| 18 | * Unless required by applicable law or agreed to in writing, software |
| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 21 | * See the License for the specific language governing permissions and |
| 22 | * limitations under the License. |
| 23 | */ |
| 24 | |
| 25 | #if defined ( __ICCARM__ ) |
| 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
| 27 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| 28 | #pragma clang system_header /* treat file as system include file */ |
| 29 | #endif |
| 30 | |
| 31 | #ifndef __CORE_CM7_H_GENERIC |
| 32 | #define __CORE_CM7_H_GENERIC |
| 33 | |
| 34 | #include <stdint.h> |
| 35 | |
| 36 | #ifdef __cplusplus |
| 37 | extern "C" { |
| 38 | #endif |
| 39 | |
| 40 | /** |
| 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| 42 | CMSIS violates the following MISRA-C:2004 rules: |
| 43 | |
| 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
| 45 | Function definitions in header files are used to allow 'inlining'. |
| 46 | |
| 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| 48 | Unions are used for effective representation of core registers. |
| 49 | |
| 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
| 51 | Function-like macros are used to allow more efficient code. |
| 52 | */ |
| 53 | |
| 54 | |
| 55 | /******************************************************************************* |
| 56 | * CMSIS definitions |
| 57 | ******************************************************************************/ |
| 58 | /** |
| 59 | \ingroup Cortex_M7 |
| 60 | @{ |
| 61 | */ |
| 62 | |
| 63 | /* CMSIS CM7 definitions */ |
| 64 | #define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ |
| 65 | #define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ |
| 66 | #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ |
| 67 | __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
| 68 | |
| 69 | #define __CORTEX_M (7U) /*!< Cortex-M Core */ |
| 70 | |
| 71 | /** __FPU_USED indicates whether an FPU is used or not. |
| 72 | For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. |
| 73 | */ |
| 74 | #if defined ( __CC_ARM ) |
| 75 | #if defined __TARGET_FPU_VFP |
| 76 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| 77 | #define __FPU_USED 1U |
| 78 | #else |
| 79 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 80 | #define __FPU_USED 0U |
| 81 | #endif |
| 82 | #else |
| 83 | #define __FPU_USED 0U |
| 84 | #endif |
| 85 | |
| 86 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| 87 | #if defined __ARM_PCS_VFP |
| 88 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| 89 | #define __FPU_USED 1U |
| 90 | #else |
| 91 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 92 | #define __FPU_USED 0U |
| 93 | #endif |
| 94 | #else |
| 95 | #define __FPU_USED 0U |
| 96 | #endif |
| 97 | |
| 98 | #elif defined ( __GNUC__ ) |
| 99 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| 100 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| 101 | #define __FPU_USED 1U |
| 102 | #else |
| 103 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 104 | #define __FPU_USED 0U |
| 105 | #endif |
| 106 | #else |
| 107 | #define __FPU_USED 0U |
| 108 | #endif |
| 109 | |
| 110 | #elif defined ( __ICCARM__ ) |
| 111 | #if defined __ARMVFP__ |
| 112 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| 113 | #define __FPU_USED 1U |
| 114 | #else |
| 115 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 116 | #define __FPU_USED 0U |
| 117 | #endif |
| 118 | #else |
| 119 | #define __FPU_USED 0U |
| 120 | #endif |
| 121 | |
| 122 | #elif defined ( __TI_ARM__ ) |
| 123 | #if defined __TI_VFP_SUPPORT__ |
| 124 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| 125 | #define __FPU_USED 1U |
| 126 | #else |
| 127 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 128 | #define __FPU_USED 0U |
| 129 | #endif |
| 130 | #else |
| 131 | #define __FPU_USED 0U |
| 132 | #endif |
| 133 | |
| 134 | #elif defined ( __TASKING__ ) |
| 135 | #if defined __FPU_VFP__ |
| 136 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| 137 | #define __FPU_USED 1U |
| 138 | #else |
| 139 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 140 | #define __FPU_USED 0U |
| 141 | #endif |
| 142 | #else |
| 143 | #define __FPU_USED 0U |
| 144 | #endif |
| 145 | |
| 146 | #elif defined ( __CSMC__ ) |
| 147 | #if ( __CSMC__ & 0x400U) |
| 148 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
| 149 | #define __FPU_USED 1U |
| 150 | #else |
| 151 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| 152 | #define __FPU_USED 0U |
| 153 | #endif |
| 154 | #else |
| 155 | #define __FPU_USED 0U |
| 156 | #endif |
| 157 | |
| 158 | #endif |
| 159 | |
| 160 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
| 161 | |
| 162 | |
| 163 | #ifdef __cplusplus |
| 164 | } |
| 165 | #endif |
| 166 | |
| 167 | #endif /* __CORE_CM7_H_GENERIC */ |
| 168 | |
| 169 | #ifndef __CMSIS_GENERIC |
| 170 | |
| 171 | #ifndef __CORE_CM7_H_DEPENDANT |
| 172 | #define __CORE_CM7_H_DEPENDANT |
| 173 | |
| 174 | #ifdef __cplusplus |
| 175 | extern "C" { |
| 176 | #endif |
| 177 | |
| 178 | /* check device defines and use defaults */ |
| 179 | #if defined __CHECK_DEVICE_DEFINES |
| 180 | #ifndef __CM7_REV |
| 181 | #define __CM7_REV 0x0000U |
| 182 | #warning "__CM7_REV not defined in device header file; using default!" |
| 183 | #endif |
| 184 | |
| 185 | #ifndef __FPU_PRESENT |
| 186 | #define __FPU_PRESENT 0U |
| 187 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
| 188 | #endif |
| 189 | |
| 190 | #ifndef __MPU_PRESENT |
| 191 | #define __MPU_PRESENT 0U |
| 192 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
| 193 | #endif |
| 194 | |
| 195 | #ifndef __ICACHE_PRESENT |
| 196 | #define __ICACHE_PRESENT 0U |
| 197 | #warning "__ICACHE_PRESENT not defined in device header file; using default!" |
| 198 | #endif |
| 199 | |
| 200 | #ifndef __DCACHE_PRESENT |
| 201 | #define __DCACHE_PRESENT 0U |
| 202 | #warning "__DCACHE_PRESENT not defined in device header file; using default!" |
| 203 | #endif |
| 204 | |
| 205 | #ifndef __DTCM_PRESENT |
| 206 | #define __DTCM_PRESENT 0U |
| 207 | #warning "__DTCM_PRESENT not defined in device header file; using default!" |
| 208 | #endif |
| 209 | |
| 210 | #ifndef __NVIC_PRIO_BITS |
| 211 | #define __NVIC_PRIO_BITS 3U |
| 212 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| 213 | #endif |
| 214 | |
| 215 | #ifndef __Vendor_SysTickConfig |
| 216 | #define __Vendor_SysTickConfig 0U |
| 217 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| 218 | #endif |
| 219 | #endif |
| 220 | |
| 221 | /* IO definitions (access restrictions to peripheral registers) */ |
| 222 | /** |
| 223 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| 224 | |
| 225 | <strong>IO Type Qualifiers</strong> are used |
| 226 | \li to specify the access to peripheral variables. |
| 227 | \li for automatic generation of peripheral register debug information. |
| 228 | */ |
| 229 | #ifdef __cplusplus |
| 230 | #define __I volatile /*!< Defines 'read only' permissions */ |
| 231 | #else |
| 232 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| 233 | #endif |
| 234 | #define __O volatile /*!< Defines 'write only' permissions */ |
| 235 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| 236 | |
| 237 | /* following defines should be used for structure members */ |
| 238 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
| 239 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
| 240 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
| 241 | |
| 242 | /*@} end of group Cortex_M7 */ |
| 243 | |
| 244 | |
| 245 | |
| 246 | /******************************************************************************* |
| 247 | * Register Abstraction |
| 248 | Core Register contain: |
| 249 | - Core Register |
| 250 | - Core NVIC Register |
| 251 | - Core SCB Register |
| 252 | - Core SysTick Register |
| 253 | - Core Debug Register |
| 254 | - Core MPU Register |
| 255 | - Core FPU Register |
| 256 | ******************************************************************************/ |
| 257 | /** |
| 258 | \defgroup CMSIS_core_register Defines and Type Definitions |
| 259 | \brief Type definitions and defines for Cortex-M processor based devices. |
| 260 | */ |
| 261 | |
| 262 | /** |
| 263 | \ingroup CMSIS_core_register |
| 264 | \defgroup CMSIS_CORE Status and Control Registers |
| 265 | \brief Core Register type definitions. |
| 266 | @{ |
| 267 | */ |
| 268 | |
| 269 | /** |
| 270 | \brief Union type to access the Application Program Status Register (APSR). |
| 271 | */ |
| 272 | typedef union |
| 273 | { |
| 274 | struct |
| 275 | { |
| 276 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
| 277 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| 278 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
| 279 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| 280 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| 281 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| 282 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| 283 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| 284 | } b; /*!< Structure used for bit access */ |
| 285 | uint32_t w; /*!< Type used for word access */ |
| 286 | } APSR_Type; |
| 287 | |
| 288 | /* APSR Register Definitions */ |
| 289 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
| 290 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
| 291 | |
| 292 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
| 293 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
| 294 | |
| 295 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
| 296 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
| 297 | |
| 298 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
| 299 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
| 300 | |
| 301 | #define APSR_Q_Pos 27U /*!< APSR: Q Position */ |
| 302 | #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ |
| 303 | |
| 304 | #define APSR_GE_Pos 16U /*!< APSR: GE Position */ |
| 305 | #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ |
| 306 | |
| 307 | |
| 308 | /** |
| 309 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
| 310 | */ |
| 311 | typedef union |
| 312 | { |
| 313 | struct |
| 314 | { |
| 315 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| 316 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| 317 | } b; /*!< Structure used for bit access */ |
| 318 | uint32_t w; /*!< Type used for word access */ |
| 319 | } IPSR_Type; |
| 320 | |
| 321 | /* IPSR Register Definitions */ |
| 322 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
| 323 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
| 324 | |
| 325 | |
| 326 | /** |
| 327 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| 328 | */ |
| 329 | typedef union |
| 330 | { |
| 331 | struct |
| 332 | { |
| 333 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| 334 | uint32_t _reserved0:1; /*!< bit: 9 Reserved */ |
| 335 | uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ |
| 336 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| 337 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
| 338 | uint32_t T:1; /*!< bit: 24 Thumb bit */ |
| 339 | uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ |
| 340 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| 341 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| 342 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| 343 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| 344 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| 345 | } b; /*!< Structure used for bit access */ |
| 346 | uint32_t w; /*!< Type used for word access */ |
| 347 | } xPSR_Type; |
| 348 | |
| 349 | /* xPSR Register Definitions */ |
| 350 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
| 351 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
| 352 | |
| 353 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
| 354 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
| 355 | |
| 356 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
| 357 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
| 358 | |
| 359 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
| 360 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
| 361 | |
| 362 | #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ |
| 363 | #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ |
| 364 | |
| 365 | #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ |
| 366 | #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ |
| 367 | |
| 368 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
| 369 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
| 370 | |
| 371 | #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ |
| 372 | #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ |
| 373 | |
| 374 | #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ |
| 375 | #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ |
| 376 | |
| 377 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
| 378 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
| 379 | |
| 380 | |
| 381 | /** |
| 382 | \brief Union type to access the Control Registers (CONTROL). |
| 383 | */ |
| 384 | typedef union |
| 385 | { |
| 386 | struct |
| 387 | { |
| 388 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
| 389 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| 390 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
| 391 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
| 392 | } b; /*!< Structure used for bit access */ |
| 393 | uint32_t w; /*!< Type used for word access */ |
| 394 | } CONTROL_Type; |
| 395 | |
| 396 | /* CONTROL Register Definitions */ |
| 397 | #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ |
| 398 | #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ |
| 399 | |
| 400 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
| 401 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
| 402 | |
| 403 | #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
| 404 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
| 405 | |
| 406 | /*@} end of group CMSIS_CORE */ |
| 407 | |
| 408 | |
| 409 | /** |
| 410 | \ingroup CMSIS_core_register |
| 411 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| 412 | \brief Type definitions for the NVIC Registers |
| 413 | @{ |
| 414 | */ |
| 415 | |
| 416 | /** |
| 417 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| 418 | */ |
| 419 | typedef struct |
| 420 | { |
| 421 | __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| 422 | uint32_t RESERVED0[24U]; |
| 423 | __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| 424 | uint32_t RSERVED1[24U]; |
| 425 | __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| 426 | uint32_t RESERVED2[24U]; |
| 427 | __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| 428 | uint32_t RESERVED3[24U]; |
| 429 | __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
| 430 | uint32_t RESERVED4[56U]; |
| 431 | __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
| 432 | uint32_t RESERVED5[644U]; |
| 433 | __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
| 434 | } NVIC_Type; |
| 435 | |
| 436 | /* Software Triggered Interrupt Register Definitions */ |
| 437 | #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ |
| 438 | #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ |
| 439 | |
| 440 | /*@} end of group CMSIS_NVIC */ |
| 441 | |
| 442 | |
| 443 | /** |
| 444 | \ingroup CMSIS_core_register |
| 445 | \defgroup CMSIS_SCB System Control Block (SCB) |
| 446 | \brief Type definitions for the System Control Block Registers |
| 447 | @{ |
| 448 | */ |
| 449 | |
| 450 | /** |
| 451 | \brief Structure type to access the System Control Block (SCB). |
| 452 | */ |
| 453 | typedef struct |
| 454 | { |
| 455 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| 456 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| 457 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
| 458 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| 459 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| 460 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| 461 | __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
| 462 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| 463 | __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
| 464 | __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
| 465 | __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
| 466 | __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
| 467 | __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
| 468 | __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
| 469 | __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
| 470 | __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
| 471 | __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
| 472 | __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
| 473 | __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
| 474 | uint32_t RESERVED0[1U]; |
| 475 | __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ |
| 476 | __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ |
| 477 | __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ |
| 478 | __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ |
| 479 | __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
| 480 | uint32_t RESERVED3[93U]; |
| 481 | __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ |
| 482 | uint32_t RESERVED4[15U]; |
| 483 | __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ |
| 484 | __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ |
| 485 | __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ |
| 486 | uint32_t RESERVED5[1U]; |
| 487 | __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ |
| 488 | uint32_t RESERVED6[1U]; |
| 489 | __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ |
| 490 | __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ |
| 491 | __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ |
| 492 | __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ |
| 493 | __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ |
| 494 | __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ |
| 495 | __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ |
| 496 | __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ |
| 497 | uint32_t RESERVED7[6U]; |
| 498 | __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ |
| 499 | __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ |
| 500 | __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ |
| 501 | __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ |
| 502 | __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ |
| 503 | uint32_t RESERVED8[1U]; |
| 504 | __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ |
| 505 | } SCB_Type; |
| 506 | |
| 507 | /* SCB CPUID Register Definitions */ |
| 508 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
| 509 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| 510 | |
| 511 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
| 512 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| 513 | |
| 514 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
| 515 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| 516 | |
| 517 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
| 518 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| 519 | |
| 520 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
| 521 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
| 522 | |
| 523 | /* SCB Interrupt Control State Register Definitions */ |
| 524 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
| 525 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| 526 | |
| 527 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
| 528 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| 529 | |
| 530 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
| 531 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| 532 | |
| 533 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
| 534 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| 535 | |
| 536 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
| 537 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| 538 | |
| 539 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
| 540 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| 541 | |
| 542 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
| 543 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| 544 | |
| 545 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
| 546 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| 547 | |
| 548 | #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ |
| 549 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
| 550 | |
| 551 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
| 552 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
| 553 | |
| 554 | /* SCB Vector Table Offset Register Definitions */ |
| 555 | #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
| 556 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
| 557 | |
| 558 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
| 559 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
| 560 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| 561 | |
| 562 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| 563 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| 564 | |
| 565 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
| 566 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| 567 | |
| 568 | #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ |
| 569 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
| 570 | |
| 571 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
| 572 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| 573 | |
| 574 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| 575 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| 576 | |
| 577 | #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ |
| 578 | #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ |
| 579 | |
| 580 | /* SCB System Control Register Definitions */ |
| 581 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
| 582 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| 583 | |
| 584 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
| 585 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| 586 | |
| 587 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
| 588 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| 589 | |
| 590 | /* SCB Configuration Control Register Definitions */ |
| 591 | #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ |
| 592 | #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ |
| 593 | |
| 594 | #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ |
| 595 | #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ |
| 596 | |
| 597 | #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ |
| 598 | #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ |
| 599 | |
| 600 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
| 601 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| 602 | |
| 603 | #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ |
| 604 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
| 605 | |
| 606 | #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ |
| 607 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
| 608 | |
| 609 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
| 610 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| 611 | |
| 612 | #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ |
| 613 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
| 614 | |
| 615 | #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ |
| 616 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ |
| 617 | |
| 618 | /* SCB System Handler Control and State Register Definitions */ |
| 619 | #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ |
| 620 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
| 621 | |
| 622 | #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ |
| 623 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
| 624 | |
| 625 | #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ |
| 626 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
| 627 | |
| 628 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
| 629 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| 630 | |
| 631 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
| 632 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
| 633 | |
| 634 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
| 635 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
| 636 | |
| 637 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ |
| 638 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
| 639 | |
| 640 | #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ |
| 641 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
| 642 | |
| 643 | #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ |
| 644 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
| 645 | |
| 646 | #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ |
| 647 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
| 648 | |
| 649 | #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ |
| 650 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
| 651 | |
| 652 | #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ |
| 653 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
| 654 | |
| 655 | #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ |
| 656 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
| 657 | |
| 658 | #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ |
| 659 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
| 660 | |
| 661 | /* SCB Configurable Fault Status Register Definitions */ |
| 662 | #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ |
| 663 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
| 664 | |
| 665 | #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ |
| 666 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
| 667 | |
| 668 | #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
| 669 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
| 670 | |
| 671 | /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ |
| 672 | #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ |
| 673 | #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ |
| 674 | |
| 675 | #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ |
| 676 | #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ |
| 677 | |
| 678 | #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ |
| 679 | #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ |
| 680 | |
| 681 | #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ |
| 682 | #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ |
| 683 | |
| 684 | #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ |
| 685 | #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ |
| 686 | |
| 687 | #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ |
| 688 | #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ |
| 689 | |
| 690 | /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ |
| 691 | #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ |
| 692 | #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ |
| 693 | |
| 694 | #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ |
| 695 | #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ |
| 696 | |
| 697 | #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ |
| 698 | #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ |
| 699 | |
| 700 | #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ |
| 701 | #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ |
| 702 | |
| 703 | #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ |
| 704 | #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ |
| 705 | |
| 706 | #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ |
| 707 | #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ |
| 708 | |
| 709 | #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ |
| 710 | #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ |
| 711 | |
| 712 | /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ |
| 713 | #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ |
| 714 | #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ |
| 715 | |
| 716 | #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ |
| 717 | #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ |
| 718 | |
| 719 | #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ |
| 720 | #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ |
| 721 | |
| 722 | #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ |
| 723 | #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ |
| 724 | |
| 725 | #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ |
| 726 | #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ |
| 727 | |
| 728 | #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ |
| 729 | #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ |
| 730 | |
| 731 | /* SCB Hard Fault Status Register Definitions */ |
| 732 | #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ |
| 733 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
| 734 | |
| 735 | #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ |
| 736 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
| 737 | |
| 738 | #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ |
| 739 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
| 740 | |
| 741 | /* SCB Debug Fault Status Register Definitions */ |
| 742 | #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ |
| 743 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
| 744 | |
| 745 | #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ |
| 746 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
| 747 | |
| 748 | #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ |
| 749 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
| 750 | |
| 751 | #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ |
| 752 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
| 753 | |
| 754 | #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ |
| 755 | #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ |
| 756 | |
| 757 | /* SCB Cache Level ID Register Definitions */ |
| 758 | #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ |
| 759 | #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ |
| 760 | |
| 761 | #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ |
| 762 | #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ |
| 763 | |
| 764 | /* SCB Cache Type Register Definitions */ |
| 765 | #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ |
| 766 | #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ |
| 767 | |
| 768 | #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ |
| 769 | #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ |
| 770 | |
| 771 | #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ |
| 772 | #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ |
| 773 | |
| 774 | #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ |
| 775 | #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ |
| 776 | |
| 777 | #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ |
| 778 | #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ |
| 779 | |
| 780 | /* SCB Cache Size ID Register Definitions */ |
| 781 | #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ |
| 782 | #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ |
| 783 | |
| 784 | #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ |
| 785 | #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ |
| 786 | |
| 787 | #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ |
| 788 | #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ |
| 789 | |
| 790 | #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ |
| 791 | #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ |
| 792 | |
| 793 | #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ |
| 794 | #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ |
| 795 | |
| 796 | #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ |
| 797 | #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ |
| 798 | |
| 799 | #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ |
| 800 | #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ |
| 801 | |
| 802 | /* SCB Cache Size Selection Register Definitions */ |
| 803 | #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ |
| 804 | #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ |
| 805 | |
| 806 | #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ |
| 807 | #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ |
| 808 | |
| 809 | /* SCB Software Triggered Interrupt Register Definitions */ |
| 810 | #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ |
| 811 | #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ |
| 812 | |
| 813 | /* SCB D-Cache Invalidate by Set-way Register Definitions */ |
| 814 | #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ |
| 815 | #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ |
| 816 | |
| 817 | #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ |
| 818 | #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ |
| 819 | |
| 820 | /* SCB D-Cache Clean by Set-way Register Definitions */ |
| 821 | #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ |
| 822 | #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ |
| 823 | |
| 824 | #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ |
| 825 | #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ |
| 826 | |
| 827 | /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ |
| 828 | #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ |
| 829 | #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ |
| 830 | |
| 831 | #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ |
| 832 | #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ |
| 833 | |
| 834 | /* Instruction Tightly-Coupled Memory Control Register Definitions */ |
| 835 | #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ |
| 836 | #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ |
| 837 | |
| 838 | #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ |
| 839 | #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ |
| 840 | |
| 841 | #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ |
| 842 | #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ |
| 843 | |
| 844 | #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ |
| 845 | #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ |
| 846 | |
| 847 | /* Data Tightly-Coupled Memory Control Register Definitions */ |
| 848 | #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ |
| 849 | #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ |
| 850 | |
| 851 | #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ |
| 852 | #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ |
| 853 | |
| 854 | #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ |
| 855 | #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ |
| 856 | |
| 857 | #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ |
| 858 | #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ |
| 859 | |
| 860 | /* AHBP Control Register Definitions */ |
| 861 | #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ |
| 862 | #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ |
| 863 | |
| 864 | #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ |
| 865 | #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ |
| 866 | |
| 867 | /* L1 Cache Control Register Definitions */ |
| 868 | #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ |
| 869 | #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ |
| 870 | |
| 871 | #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ |
| 872 | #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ |
| 873 | |
| 874 | #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ |
| 875 | #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ |
| 876 | |
| 877 | /* AHBS Control Register Definitions */ |
| 878 | #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ |
| 879 | #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ |
| 880 | |
| 881 | #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ |
| 882 | #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ |
| 883 | |
| 884 | #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ |
| 885 | #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ |
| 886 | |
| 887 | /* Auxiliary Bus Fault Status Register Definitions */ |
| 888 | #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ |
| 889 | #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ |
| 890 | |
| 891 | #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ |
| 892 | #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ |
| 893 | |
| 894 | #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ |
| 895 | #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ |
| 896 | |
| 897 | #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ |
| 898 | #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ |
| 899 | |
| 900 | #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ |
| 901 | #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ |
| 902 | |
| 903 | #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ |
| 904 | #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ |
| 905 | |
| 906 | /*@} end of group CMSIS_SCB */ |
| 907 | |
| 908 | |
| 909 | /** |
| 910 | \ingroup CMSIS_core_register |
| 911 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
| 912 | \brief Type definitions for the System Control and ID Register not in the SCB |
| 913 | @{ |
| 914 | */ |
| 915 | |
| 916 | /** |
| 917 | \brief Structure type to access the System Control and ID Register not in the SCB. |
| 918 | */ |
| 919 | typedef struct |
| 920 | { |
| 921 | uint32_t RESERVED0[1U]; |
| 922 | __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
| 923 | __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
| 924 | } SCnSCB_Type; |
| 925 | |
| 926 | /* Interrupt Controller Type Register Definitions */ |
| 927 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ |
| 928 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ |
| 929 | |
| 930 | /* Auxiliary Control Register Definitions */ |
| 931 | #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ |
| 932 | #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ |
| 933 | |
| 934 | #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ |
| 935 | #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ |
| 936 | |
| 937 | #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ |
| 938 | #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ |
| 939 | |
| 940 | #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ |
| 941 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ |
| 942 | |
| 943 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ |
| 944 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
| 945 | |
| 946 | /*@} end of group CMSIS_SCnotSCB */ |
| 947 | |
| 948 | |
| 949 | /** |
| 950 | \ingroup CMSIS_core_register |
| 951 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| 952 | \brief Type definitions for the System Timer Registers. |
| 953 | @{ |
| 954 | */ |
| 955 | |
| 956 | /** |
| 957 | \brief Structure type to access the System Timer (SysTick). |
| 958 | */ |
| 959 | typedef struct |
| 960 | { |
| 961 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| 962 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| 963 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| 964 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| 965 | } SysTick_Type; |
| 966 | |
| 967 | /* SysTick Control / Status Register Definitions */ |
| 968 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
| 969 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| 970 | |
| 971 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
| 972 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| 973 | |
| 974 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
| 975 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| 976 | |
| 977 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
| 978 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
| 979 | |
| 980 | /* SysTick Reload Register Definitions */ |
| 981 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
| 982 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
| 983 | |
| 984 | /* SysTick Current Register Definitions */ |
| 985 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
| 986 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
| 987 | |
| 988 | /* SysTick Calibration Register Definitions */ |
| 989 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
| 990 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| 991 | |
| 992 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
| 993 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| 994 | |
| 995 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
| 996 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
| 997 | |
| 998 | /*@} end of group CMSIS_SysTick */ |
| 999 | |
| 1000 | |
| 1001 | /** |
| 1002 | \ingroup CMSIS_core_register |
| 1003 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
| 1004 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
| 1005 | @{ |
| 1006 | */ |
| 1007 | |
| 1008 | /** |
| 1009 | \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
| 1010 | */ |
| 1011 | typedef struct |
| 1012 | { |
| 1013 | __OM union |
| 1014 | { |
| 1015 | __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
| 1016 | __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
| 1017 | __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
| 1018 | } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
| 1019 | uint32_t RESERVED0[864U]; |
| 1020 | __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
| 1021 | uint32_t RESERVED1[15U]; |
| 1022 | __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
| 1023 | uint32_t RESERVED2[15U]; |
| 1024 | __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
| 1025 | uint32_t RESERVED3[29U]; |
| 1026 | __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
| 1027 | __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
| 1028 | __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
| 1029 | uint32_t RESERVED4[43U]; |
| 1030 | __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
| 1031 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
| 1032 | uint32_t RESERVED5[6U]; |
| 1033 | __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
| 1034 | __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
| 1035 | __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
| 1036 | __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
| 1037 | __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
| 1038 | __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
| 1039 | __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
| 1040 | __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
| 1041 | __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
| 1042 | __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
| 1043 | __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
| 1044 | __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
| 1045 | } ITM_Type; |
| 1046 | |
| 1047 | /* ITM Trace Privilege Register Definitions */ |
| 1048 | #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ |
| 1049 | #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ |
| 1050 | |
| 1051 | /* ITM Trace Control Register Definitions */ |
| 1052 | #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ |
| 1053 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
| 1054 | |
| 1055 | #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ |
| 1056 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ |
| 1057 | |
| 1058 | #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ |
| 1059 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
| 1060 | |
| 1061 | #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ |
| 1062 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
| 1063 | |
| 1064 | #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ |
| 1065 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
| 1066 | |
| 1067 | #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ |
| 1068 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
| 1069 | |
| 1070 | #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ |
| 1071 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
| 1072 | |
| 1073 | #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ |
| 1074 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
| 1075 | |
| 1076 | #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ |
| 1077 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ |
| 1078 | |
| 1079 | /* ITM Integration Write Register Definitions */ |
| 1080 | #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ |
| 1081 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ |
| 1082 | |
| 1083 | /* ITM Integration Read Register Definitions */ |
| 1084 | #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ |
| 1085 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ |
| 1086 | |
| 1087 | /* ITM Integration Mode Control Register Definitions */ |
| 1088 | #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ |
| 1089 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ |
| 1090 | |
| 1091 | /* ITM Lock Status Register Definitions */ |
| 1092 | #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ |
| 1093 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
| 1094 | |
| 1095 | #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ |
| 1096 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
| 1097 | |
| 1098 | #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ |
| 1099 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ |
| 1100 | |
| 1101 | /*@}*/ /* end of group CMSIS_ITM */ |
| 1102 | |
| 1103 | |
| 1104 | /** |
| 1105 | \ingroup CMSIS_core_register |
| 1106 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
| 1107 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
| 1108 | @{ |
| 1109 | */ |
| 1110 | |
| 1111 | /** |
| 1112 | \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
| 1113 | */ |
| 1114 | typedef struct |
| 1115 | { |
| 1116 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
| 1117 | __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
| 1118 | __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
| 1119 | __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
| 1120 | __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
| 1121 | __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
| 1122 | __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
| 1123 | __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
| 1124 | __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
| 1125 | __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
| 1126 | __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
| 1127 | uint32_t RESERVED0[1U]; |
| 1128 | __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
| 1129 | __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
| 1130 | __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
| 1131 | uint32_t RESERVED1[1U]; |
| 1132 | __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
| 1133 | __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
| 1134 | __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
| 1135 | uint32_t RESERVED2[1U]; |
| 1136 | __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
| 1137 | __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
| 1138 | __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
| 1139 | uint32_t RESERVED3[981U]; |
| 1140 | __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ |
| 1141 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ |
| 1142 | } DWT_Type; |
| 1143 | |
| 1144 | /* DWT Control Register Definitions */ |
| 1145 | #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ |
| 1146 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
| 1147 | |
| 1148 | #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ |
| 1149 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
| 1150 | |
| 1151 | #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ |
| 1152 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
| 1153 | |
| 1154 | #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ |
| 1155 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
| 1156 | |
| 1157 | #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ |
| 1158 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
| 1159 | |
| 1160 | #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ |
| 1161 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
| 1162 | |
| 1163 | #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ |
| 1164 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
| 1165 | |
| 1166 | #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ |
| 1167 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
| 1168 | |
| 1169 | #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ |
| 1170 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
| 1171 | |
| 1172 | #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ |
| 1173 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
| 1174 | |
| 1175 | #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ |
| 1176 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
| 1177 | |
| 1178 | #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ |
| 1179 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
| 1180 | |
| 1181 | #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ |
| 1182 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
| 1183 | |
| 1184 | #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ |
| 1185 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
| 1186 | |
| 1187 | #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ |
| 1188 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
| 1189 | |
| 1190 | #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ |
| 1191 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
| 1192 | |
| 1193 | #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ |
| 1194 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
| 1195 | |
| 1196 | #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ |
| 1197 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ |
| 1198 | |
| 1199 | /* DWT CPI Count Register Definitions */ |
| 1200 | #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ |
| 1201 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ |
| 1202 | |
| 1203 | /* DWT Exception Overhead Count Register Definitions */ |
| 1204 | #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ |
| 1205 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ |
| 1206 | |
| 1207 | /* DWT Sleep Count Register Definitions */ |
| 1208 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
| 1209 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
| 1210 | |
| 1211 | /* DWT LSU Count Register Definitions */ |
| 1212 | #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ |
| 1213 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ |
| 1214 | |
| 1215 | /* DWT Folded-instruction Count Register Definitions */ |
| 1216 | #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ |
| 1217 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
| 1218 | |
| 1219 | /* DWT Comparator Mask Register Definitions */ |
| 1220 | #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ |
| 1221 | #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ |
| 1222 | |
| 1223 | /* DWT Comparator Function Register Definitions */ |
| 1224 | #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ |
| 1225 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
| 1226 | |
| 1227 | #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ |
| 1228 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ |
| 1229 | |
| 1230 | #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ |
| 1231 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ |
| 1232 | |
| 1233 | #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ |
| 1234 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
| 1235 | |
| 1236 | #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ |
| 1237 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ |
| 1238 | |
| 1239 | #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ |
| 1240 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ |
| 1241 | |
| 1242 | #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ |
| 1243 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ |
| 1244 | |
| 1245 | #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ |
| 1246 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ |
| 1247 | |
| 1248 | #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ |
| 1249 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ |
| 1250 | |
| 1251 | /*@}*/ /* end of group CMSIS_DWT */ |
| 1252 | |
| 1253 | |
| 1254 | /** |
| 1255 | \ingroup CMSIS_core_register |
| 1256 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
| 1257 | \brief Type definitions for the Trace Port Interface (TPI) |
| 1258 | @{ |
| 1259 | */ |
| 1260 | |
| 1261 | /** |
| 1262 | \brief Structure type to access the Trace Port Interface Register (TPI). |
| 1263 | */ |
| 1264 | typedef struct |
| 1265 | { |
| 1266 | __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
| 1267 | __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
| 1268 | uint32_t RESERVED0[2U]; |
| 1269 | __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
| 1270 | uint32_t RESERVED1[55U]; |
| 1271 | __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
| 1272 | uint32_t RESERVED2[131U]; |
| 1273 | __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
| 1274 | __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
| 1275 | __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
| 1276 | uint32_t RESERVED3[759U]; |
| 1277 | __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
| 1278 | __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
| 1279 | __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
| 1280 | uint32_t RESERVED4[1U]; |
| 1281 | __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
| 1282 | __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
| 1283 | __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
| 1284 | uint32_t RESERVED5[39U]; |
| 1285 | __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
| 1286 | __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
| 1287 | uint32_t RESERVED7[8U]; |
| 1288 | __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
| 1289 | __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
| 1290 | } TPI_Type; |
| 1291 | |
| 1292 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
| 1293 | #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ |
| 1294 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ |
| 1295 | |
| 1296 | /* TPI Selected Pin Protocol Register Definitions */ |
| 1297 | #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ |
| 1298 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ |
| 1299 | |
| 1300 | /* TPI Formatter and Flush Status Register Definitions */ |
| 1301 | #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ |
| 1302 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
| 1303 | |
| 1304 | #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ |
| 1305 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
| 1306 | |
| 1307 | #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ |
| 1308 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
| 1309 | |
| 1310 | #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ |
| 1311 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ |
| 1312 | |
| 1313 | /* TPI Formatter and Flush Control Register Definitions */ |
| 1314 | #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ |
| 1315 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
| 1316 | |
| 1317 | #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ |
| 1318 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
| 1319 | |
| 1320 | /* TPI TRIGGER Register Definitions */ |
| 1321 | #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ |
| 1322 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ |
| 1323 | |
| 1324 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
| 1325 | #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ |
| 1326 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
| 1327 | |
| 1328 | #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ |
| 1329 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
| 1330 | |
| 1331 | #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ |
| 1332 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
| 1333 | |
| 1334 | #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ |
| 1335 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
| 1336 | |
| 1337 | #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ |
| 1338 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
| 1339 | |
| 1340 | #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ |
| 1341 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
| 1342 | |
| 1343 | #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ |
| 1344 | #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ |
| 1345 | |
| 1346 | /* TPI ITATBCTR2 Register Definitions */ |
| 1347 | #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ |
| 1348 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ |
| 1349 | |
| 1350 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
| 1351 | #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ |
| 1352 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
| 1353 | |
| 1354 | #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ |
| 1355 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
| 1356 | |
| 1357 | #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ |
| 1358 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
| 1359 | |
| 1360 | #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ |
| 1361 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
| 1362 | |
| 1363 | #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ |
| 1364 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
| 1365 | |
| 1366 | #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ |
| 1367 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
| 1368 | |
| 1369 | #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ |
| 1370 | #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ |
| 1371 | |
| 1372 | /* TPI ITATBCTR0 Register Definitions */ |
| 1373 | #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ |
| 1374 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ |
| 1375 | |
| 1376 | /* TPI Integration Mode Control Register Definitions */ |
| 1377 | #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ |
| 1378 | #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ |
| 1379 | |
| 1380 | /* TPI DEVID Register Definitions */ |
| 1381 | #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ |
| 1382 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
| 1383 | |
| 1384 | #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ |
| 1385 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
| 1386 | |
| 1387 | #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ |
| 1388 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
| 1389 | |
| 1390 | #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ |
| 1391 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
| 1392 | |
| 1393 | #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ |
| 1394 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
| 1395 | |
| 1396 | #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ |
| 1397 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ |
| 1398 | |
| 1399 | /* TPI DEVTYPE Register Definitions */ |
| 1400 | #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ |
| 1401 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
| 1402 | |
| 1403 | #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ |
| 1404 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ |
| 1405 | |
| 1406 | /*@}*/ /* end of group CMSIS_TPI */ |
| 1407 | |
| 1408 | |
| 1409 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| 1410 | /** |
| 1411 | \ingroup CMSIS_core_register |
| 1412 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
| 1413 | \brief Type definitions for the Memory Protection Unit (MPU) |
| 1414 | @{ |
| 1415 | */ |
| 1416 | |
| 1417 | /** |
| 1418 | \brief Structure type to access the Memory Protection Unit (MPU). |
| 1419 | */ |
| 1420 | typedef struct |
| 1421 | { |
| 1422 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
| 1423 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
| 1424 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
| 1425 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
| 1426 | __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
| 1427 | __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ |
| 1428 | __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ |
| 1429 | __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ |
| 1430 | __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ |
| 1431 | __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ |
| 1432 | __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ |
| 1433 | } MPU_Type; |
| 1434 | |
| 1435 | /* MPU Type Register Definitions */ |
| 1436 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
| 1437 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
| 1438 | |
| 1439 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
| 1440 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
| 1441 | |
| 1442 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
| 1443 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
| 1444 | |
| 1445 | /* MPU Control Register Definitions */ |
| 1446 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
| 1447 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
| 1448 | |
| 1449 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
| 1450 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
| 1451 | |
| 1452 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
| 1453 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
| 1454 | |
| 1455 | /* MPU Region Number Register Definitions */ |
| 1456 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
| 1457 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
| 1458 | |
| 1459 | /* MPU Region Base Address Register Definitions */ |
| 1460 | #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ |
| 1461 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
| 1462 | |
| 1463 | #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
| 1464 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
| 1465 | |
| 1466 | #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
| 1467 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
| 1468 | |
| 1469 | /* MPU Region Attribute and Size Register Definitions */ |
| 1470 | #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
| 1471 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
| 1472 | |
| 1473 | #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
| 1474 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
| 1475 | |
| 1476 | #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
| 1477 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
| 1478 | |
| 1479 | #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
| 1480 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
| 1481 | |
| 1482 | #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
| 1483 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
| 1484 | |
| 1485 | #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
| 1486 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
| 1487 | |
| 1488 | #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
| 1489 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
| 1490 | |
| 1491 | #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
| 1492 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
| 1493 | |
| 1494 | #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
| 1495 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
| 1496 | |
| 1497 | #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
| 1498 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
| 1499 | |
| 1500 | /*@} end of group CMSIS_MPU */ |
| 1501 | #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ |
| 1502 | |
| 1503 | |
| 1504 | /** |
| 1505 | \ingroup CMSIS_core_register |
| 1506 | \defgroup CMSIS_FPU Floating Point Unit (FPU) |
| 1507 | \brief Type definitions for the Floating Point Unit (FPU) |
| 1508 | @{ |
| 1509 | */ |
| 1510 | |
| 1511 | /** |
| 1512 | \brief Structure type to access the Floating Point Unit (FPU). |
| 1513 | */ |
| 1514 | typedef struct |
| 1515 | { |
| 1516 | uint32_t RESERVED0[1U]; |
| 1517 | __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ |
| 1518 | __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ |
| 1519 | __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ |
| 1520 | __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ |
| 1521 | __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ |
| 1522 | __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ |
| 1523 | } FPU_Type; |
| 1524 | |
| 1525 | /* Floating-Point Context Control Register Definitions */ |
| 1526 | #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ |
| 1527 | #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ |
| 1528 | |
| 1529 | #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ |
| 1530 | #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ |
| 1531 | |
| 1532 | #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ |
| 1533 | #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ |
| 1534 | |
| 1535 | #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ |
| 1536 | #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ |
| 1537 | |
| 1538 | #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ |
| 1539 | #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ |
| 1540 | |
| 1541 | #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ |
| 1542 | #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ |
| 1543 | |
| 1544 | #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ |
| 1545 | #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ |
| 1546 | |
| 1547 | #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ |
| 1548 | #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ |
| 1549 | |
| 1550 | #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ |
| 1551 | #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ |
| 1552 | |
| 1553 | /* Floating-Point Context Address Register Definitions */ |
| 1554 | #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ |
| 1555 | #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ |
| 1556 | |
| 1557 | /* Floating-Point Default Status Control Register Definitions */ |
| 1558 | #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ |
| 1559 | #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ |
| 1560 | |
| 1561 | #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ |
| 1562 | #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ |
| 1563 | |
| 1564 | #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ |
| 1565 | #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ |
| 1566 | |
| 1567 | #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ |
| 1568 | #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ |
| 1569 | |
| 1570 | /* Media and FP Feature Register 0 Definitions */ |
| 1571 | #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ |
| 1572 | #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ |
| 1573 | |
| 1574 | #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ |
| 1575 | #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ |
| 1576 | |
| 1577 | #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ |
| 1578 | #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ |
| 1579 | |
| 1580 | #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ |
| 1581 | #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ |
| 1582 | |
| 1583 | #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ |
| 1584 | #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ |
| 1585 | |
| 1586 | #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ |
| 1587 | #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ |
| 1588 | |
| 1589 | #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ |
| 1590 | #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ |
| 1591 | |
| 1592 | #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ |
| 1593 | #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ |
| 1594 | |
| 1595 | /* Media and FP Feature Register 1 Definitions */ |
| 1596 | #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ |
| 1597 | #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ |
| 1598 | |
| 1599 | #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ |
| 1600 | #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ |
| 1601 | |
| 1602 | #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ |
| 1603 | #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ |
| 1604 | |
| 1605 | #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ |
| 1606 | #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ |
| 1607 | |
| 1608 | /* Media and FP Feature Register 2 Definitions */ |
| 1609 | |
| 1610 | /*@} end of group CMSIS_FPU */ |
| 1611 | |
| 1612 | |
| 1613 | /** |
| 1614 | \ingroup CMSIS_core_register |
| 1615 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| 1616 | \brief Type definitions for the Core Debug Registers |
| 1617 | @{ |
| 1618 | */ |
| 1619 | |
| 1620 | /** |
| 1621 | \brief Structure type to access the Core Debug Register (CoreDebug). |
| 1622 | */ |
| 1623 | typedef struct |
| 1624 | { |
| 1625 | __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
| 1626 | __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
| 1627 | __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
| 1628 | __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
| 1629 | } CoreDebug_Type; |
| 1630 | |
| 1631 | /* Debug Halting Control and Status Register Definitions */ |
| 1632 | #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ |
| 1633 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
| 1634 | |
| 1635 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
| 1636 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
| 1637 | |
| 1638 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
| 1639 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
| 1640 | |
| 1641 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
| 1642 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
| 1643 | |
| 1644 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ |
| 1645 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
| 1646 | |
| 1647 | #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ |
| 1648 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
| 1649 | |
| 1650 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ |
| 1651 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
| 1652 | |
| 1653 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
| 1654 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
| 1655 | |
| 1656 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
| 1657 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
| 1658 | |
| 1659 | #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ |
| 1660 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
| 1661 | |
| 1662 | #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ |
| 1663 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
| 1664 | |
| 1665 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
| 1666 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
| 1667 | |
| 1668 | /* Debug Core Register Selector Register Definitions */ |
| 1669 | #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ |
| 1670 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
| 1671 | |
| 1672 | #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ |
| 1673 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ |
| 1674 | |
| 1675 | /* Debug Exception and Monitor Control Register Definitions */ |
| 1676 | #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ |
| 1677 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
| 1678 | |
| 1679 | #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ |
| 1680 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
| 1681 | |
| 1682 | #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ |
| 1683 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
| 1684 | |
| 1685 | #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ |
| 1686 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
| 1687 | |
| 1688 | #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ |
| 1689 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
| 1690 | |
| 1691 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
| 1692 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
| 1693 | |
| 1694 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ |
| 1695 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
| 1696 | |
| 1697 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
| 1698 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
| 1699 | |
| 1700 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ |
| 1701 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
| 1702 | |
| 1703 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
| 1704 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
| 1705 | |
| 1706 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
| 1707 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
| 1708 | |
| 1709 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ |
| 1710 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
| 1711 | |
| 1712 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
| 1713 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
| 1714 | |
| 1715 | /*@} end of group CMSIS_CoreDebug */ |
| 1716 | |
| 1717 | |
| 1718 | /** |
| 1719 | \ingroup CMSIS_core_register |
| 1720 | \defgroup CMSIS_core_bitfield Core register bit field macros |
| 1721 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
| 1722 | @{ |
| 1723 | */ |
| 1724 | |
| 1725 | /** |
| 1726 | \brief Mask and shift a bit field value for use in a register bit range. |
| 1727 | \param[in] field Name of the register bit field. |
| 1728 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
| 1729 | \return Masked and shifted value. |
| 1730 | */ |
| 1731 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
| 1732 | |
| 1733 | /** |
| 1734 | \brief Mask and shift a register value to extract a bit filed value. |
| 1735 | \param[in] field Name of the register bit field. |
| 1736 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
| 1737 | \return Masked and shifted bit field value. |
| 1738 | */ |
| 1739 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
| 1740 | |
| 1741 | /*@} end of group CMSIS_core_bitfield */ |
| 1742 | |
| 1743 | |
| 1744 | /** |
| 1745 | \ingroup CMSIS_core_register |
| 1746 | \defgroup CMSIS_core_base Core Definitions |
| 1747 | \brief Definitions for base addresses, unions, and structures. |
| 1748 | @{ |
| 1749 | */ |
| 1750 | |
| 1751 | /* Memory mapping of Core Hardware */ |
| 1752 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| 1753 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
| 1754 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
| 1755 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
| 1756 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
| 1757 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| 1758 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| 1759 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| 1760 | |
| 1761 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
| 1762 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| 1763 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| 1764 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| 1765 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
| 1766 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
| 1767 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
| 1768 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
| 1769 | |
| 1770 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| 1771 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
| 1772 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
| 1773 | #endif |
| 1774 | |
| 1775 | #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ |
| 1776 | #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ |
| 1777 | |
| 1778 | /*@} */ |
| 1779 | |
| 1780 | |
| 1781 | |
| 1782 | /******************************************************************************* |
| 1783 | * Hardware Abstraction Layer |
| 1784 | Core Function Interface contains: |
| 1785 | - Core NVIC Functions |
| 1786 | - Core SysTick Functions |
| 1787 | - Core Debug Functions |
| 1788 | - Core Register Access Functions |
| 1789 | ******************************************************************************/ |
| 1790 | /** |
| 1791 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| 1792 | */ |
| 1793 | |
| 1794 | |
| 1795 | |
| 1796 | /* ########################## NVIC functions #################################### */ |
| 1797 | /** |
| 1798 | \ingroup CMSIS_Core_FunctionInterface |
| 1799 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| 1800 | \brief Functions that manage interrupts and exceptions via the NVIC. |
| 1801 | @{ |
| 1802 | */ |
| 1803 | |
| 1804 | #ifndef CMSIS_NVIC_VIRTUAL |
| 1805 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
| 1806 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
| 1807 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
| 1808 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
| 1809 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
| 1810 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
| 1811 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
| 1812 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
| 1813 | #define NVIC_GetActive __NVIC_GetActive |
| 1814 | #define NVIC_SetPriority __NVIC_SetPriority |
| 1815 | #define NVIC_GetPriority __NVIC_GetPriority |
| 1816 | #endif /* CMSIS_NVIC_VIRTUAL */ |
| 1817 | |
| 1818 | #ifndef CMSIS_VECTAB_VIRTUAL |
| 1819 | #define NVIC_SetVector __NVIC_SetVector |
| 1820 | #define NVIC_GetVector __NVIC_GetVector |
| 1821 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
| 1822 | |
| 1823 | #define NVIC_USER_IRQ_OFFSET 16 |
| 1824 | |
| 1825 | |
| 1826 | |
| 1827 | /** |
| 1828 | \brief Set Priority Grouping |
| 1829 | \details Sets the priority grouping field using the required unlock sequence. |
| 1830 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
| 1831 | Only values from 0..7 are used. |
| 1832 | In case of a conflict between priority grouping and available |
| 1833 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
| 1834 | \param [in] PriorityGroup Priority grouping field. |
| 1835 | */ |
| 1836 | __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
| 1837 | { |
| 1838 | uint32_t reg_value; |
| 1839 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| 1840 | |
| 1841 | reg_value = SCB->AIRCR; /* read old register configuration */ |
| 1842 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
| 1843 | reg_value = (reg_value | |
| 1844 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| 1845 | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ |
| 1846 | SCB->AIRCR = reg_value; |
| 1847 | } |
| 1848 | |
| 1849 | |
| 1850 | /** |
| 1851 | \brief Get Priority Grouping |
| 1852 | \details Reads the priority grouping field from the NVIC Interrupt Controller. |
| 1853 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
| 1854 | */ |
| 1855 | __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) |
| 1856 | { |
| 1857 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
| 1858 | } |
| 1859 | |
| 1860 | |
| 1861 | /** |
| 1862 | \brief Enable Interrupt |
| 1863 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
| 1864 | \param [in] IRQn Device specific interrupt number. |
| 1865 | \note IRQn must not be negative. |
| 1866 | */ |
| 1867 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
| 1868 | { |
| 1869 | if ((int32_t)(IRQn) >= 0) |
| 1870 | { |
| 1871 | NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 1872 | } |
| 1873 | } |
| 1874 | |
| 1875 | |
| 1876 | /** |
| 1877 | \brief Get Interrupt Enable status |
| 1878 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
| 1879 | \param [in] IRQn Device specific interrupt number. |
| 1880 | \return 0 Interrupt is not enabled. |
| 1881 | \return 1 Interrupt is enabled. |
| 1882 | \note IRQn must not be negative. |
| 1883 | */ |
| 1884 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
| 1885 | { |
| 1886 | if ((int32_t)(IRQn) >= 0) |
| 1887 | { |
| 1888 | return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| 1889 | } |
| 1890 | else |
| 1891 | { |
| 1892 | return(0U); |
| 1893 | } |
| 1894 | } |
| 1895 | |
| 1896 | |
| 1897 | /** |
| 1898 | \brief Disable Interrupt |
| 1899 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
| 1900 | \param [in] IRQn Device specific interrupt number. |
| 1901 | \note IRQn must not be negative. |
| 1902 | */ |
| 1903 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
| 1904 | { |
| 1905 | if ((int32_t)(IRQn) >= 0) |
| 1906 | { |
| 1907 | NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 1908 | __DSB(); |
| 1909 | __ISB(); |
| 1910 | } |
| 1911 | } |
| 1912 | |
| 1913 | |
| 1914 | /** |
| 1915 | \brief Get Pending Interrupt |
| 1916 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
| 1917 | \param [in] IRQn Device specific interrupt number. |
| 1918 | \return 0 Interrupt status is not pending. |
| 1919 | \return 1 Interrupt status is pending. |
| 1920 | \note IRQn must not be negative. |
| 1921 | */ |
| 1922 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| 1923 | { |
| 1924 | if ((int32_t)(IRQn) >= 0) |
| 1925 | { |
| 1926 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| 1927 | } |
| 1928 | else |
| 1929 | { |
| 1930 | return(0U); |
| 1931 | } |
| 1932 | } |
| 1933 | |
| 1934 | |
| 1935 | /** |
| 1936 | \brief Set Pending Interrupt |
| 1937 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
| 1938 | \param [in] IRQn Device specific interrupt number. |
| 1939 | \note IRQn must not be negative. |
| 1940 | */ |
| 1941 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| 1942 | { |
| 1943 | if ((int32_t)(IRQn) >= 0) |
| 1944 | { |
| 1945 | NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 1946 | } |
| 1947 | } |
| 1948 | |
| 1949 | |
| 1950 | /** |
| 1951 | \brief Clear Pending Interrupt |
| 1952 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
| 1953 | \param [in] IRQn Device specific interrupt number. |
| 1954 | \note IRQn must not be negative. |
| 1955 | */ |
| 1956 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| 1957 | { |
| 1958 | if ((int32_t)(IRQn) >= 0) |
| 1959 | { |
| 1960 | NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| 1961 | } |
| 1962 | } |
| 1963 | |
| 1964 | |
| 1965 | /** |
| 1966 | \brief Get Active Interrupt |
| 1967 | \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. |
| 1968 | \param [in] IRQn Device specific interrupt number. |
| 1969 | \return 0 Interrupt status is not active. |
| 1970 | \return 1 Interrupt status is active. |
| 1971 | \note IRQn must not be negative. |
| 1972 | */ |
| 1973 | __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) |
| 1974 | { |
| 1975 | if ((int32_t)(IRQn) >= 0) |
| 1976 | { |
| 1977 | return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| 1978 | } |
| 1979 | else |
| 1980 | { |
| 1981 | return(0U); |
| 1982 | } |
| 1983 | } |
| 1984 | |
| 1985 | |
| 1986 | /** |
| 1987 | \brief Set Interrupt Priority |
| 1988 | \details Sets the priority of a device specific interrupt or a processor exception. |
| 1989 | The interrupt number can be positive to specify a device specific interrupt, |
| 1990 | or negative to specify a processor exception. |
| 1991 | \param [in] IRQn Interrupt number. |
| 1992 | \param [in] priority Priority to set. |
| 1993 | \note The priority cannot be set for every processor exception. |
| 1994 | */ |
| 1995 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| 1996 | { |
| 1997 | if ((int32_t)(IRQn) >= 0) |
| 1998 | { |
| 1999 | NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
| 2000 | } |
| 2001 | else |
| 2002 | { |
| 2003 | SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
| 2004 | } |
| 2005 | } |
| 2006 | |
| 2007 | |
| 2008 | /** |
| 2009 | \brief Get Interrupt Priority |
| 2010 | \details Reads the priority of a device specific interrupt or a processor exception. |
| 2011 | The interrupt number can be positive to specify a device specific interrupt, |
| 2012 | or negative to specify a processor exception. |
| 2013 | \param [in] IRQn Interrupt number. |
| 2014 | \return Interrupt Priority. |
| 2015 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
| 2016 | */ |
| 2017 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
| 2018 | { |
| 2019 | |
| 2020 | if ((int32_t)(IRQn) >= 0) |
| 2021 | { |
| 2022 | return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); |
| 2023 | } |
| 2024 | else |
| 2025 | { |
| 2026 | return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); |
| 2027 | } |
| 2028 | } |
| 2029 | |
| 2030 | |
| 2031 | /** |
| 2032 | \brief Encode Priority |
| 2033 | \details Encodes the priority for an interrupt with the given priority group, |
| 2034 | preemptive priority value, and subpriority value. |
| 2035 | In case of a conflict between priority grouping and available |
| 2036 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
| 2037 | \param [in] PriorityGroup Used priority group. |
| 2038 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
| 2039 | \param [in] SubPriority Subpriority value (starting from 0). |
| 2040 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
| 2041 | */ |
| 2042 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
| 2043 | { |
| 2044 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| 2045 | uint32_t PreemptPriorityBits; |
| 2046 | uint32_t SubPriorityBits; |
| 2047 | |
| 2048 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
| 2049 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
| 2050 | |
| 2051 | return ( |
| 2052 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
| 2053 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
| 2054 | ); |
| 2055 | } |
| 2056 | |
| 2057 | |
| 2058 | /** |
| 2059 | \brief Decode Priority |
| 2060 | \details Decodes an interrupt priority value with a given priority group to |
| 2061 | preemptive priority value and subpriority value. |
| 2062 | In case of a conflict between priority grouping and available |
| 2063 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
| 2064 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
| 2065 | \param [in] PriorityGroup Used priority group. |
| 2066 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
| 2067 | \param [out] pSubPriority Subpriority value (starting from 0). |
| 2068 | */ |
| 2069 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
| 2070 | { |
| 2071 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| 2072 | uint32_t PreemptPriorityBits; |
| 2073 | uint32_t SubPriorityBits; |
| 2074 | |
| 2075 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
| 2076 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
| 2077 | |
| 2078 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
| 2079 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
| 2080 | } |
| 2081 | |
| 2082 | |
| 2083 | /** |
| 2084 | \brief Set Interrupt Vector |
| 2085 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
| 2086 | The interrupt number can be positive to specify a device specific interrupt, |
| 2087 | or negative to specify a processor exception. |
| 2088 | VTOR must been relocated to SRAM before. |
| 2089 | \param [in] IRQn Interrupt number |
| 2090 | \param [in] vector Address of interrupt handler function |
| 2091 | */ |
| 2092 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
| 2093 | { |
| 2094 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
| 2095 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
| 2096 | } |
| 2097 | |
| 2098 | |
| 2099 | /** |
| 2100 | \brief Get Interrupt Vector |
| 2101 | \details Reads an interrupt vector from interrupt vector table. |
| 2102 | The interrupt number can be positive to specify a device specific interrupt, |
| 2103 | or negative to specify a processor exception. |
| 2104 | \param [in] IRQn Interrupt number. |
| 2105 | \return Address of interrupt handler function |
| 2106 | */ |
| 2107 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
| 2108 | { |
| 2109 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
| 2110 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
| 2111 | } |
| 2112 | |
| 2113 | |
| 2114 | /** |
| 2115 | \brief System Reset |
| 2116 | \details Initiates a system reset request to reset the MCU. |
| 2117 | */ |
| 2118 | __STATIC_INLINE void NVIC_SystemReset(void) |
| 2119 | { |
| 2120 | __DSB(); /* Ensure all outstanding memory accesses included |
| 2121 | buffered write are completed before reset */ |
| 2122 | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| 2123 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
| 2124 | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ |
| 2125 | __DSB(); /* Ensure completion of memory access */ |
| 2126 | |
| 2127 | for(;;) /* wait until reset */ |
| 2128 | { |
| 2129 | __NOP(); |
| 2130 | } |
| 2131 | } |
| 2132 | |
| 2133 | /*@} end of CMSIS_Core_NVICFunctions */ |
| 2134 | |
| 2135 | |
| 2136 | /* ########################## FPU functions #################################### */ |
| 2137 | /** |
| 2138 | \ingroup CMSIS_Core_FunctionInterface |
| 2139 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
| 2140 | \brief Function that provides FPU type. |
| 2141 | @{ |
| 2142 | */ |
| 2143 | |
| 2144 | /** |
| 2145 | \brief get FPU type |
| 2146 | \details returns the FPU type |
| 2147 | \returns |
| 2148 | - \b 0: No FPU |
| 2149 | - \b 1: Single precision FPU |
| 2150 | - \b 2: Double + Single precision FPU |
| 2151 | */ |
| 2152 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
| 2153 | { |
| 2154 | uint32_t mvfr0; |
| 2155 | |
| 2156 | mvfr0 = SCB->MVFR0; |
| 2157 | if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) |
| 2158 | { |
| 2159 | return 2U; /* Double + Single precision FPU */ |
| 2160 | } |
| 2161 | else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) |
| 2162 | { |
| 2163 | return 1U; /* Single precision FPU */ |
| 2164 | } |
| 2165 | else |
| 2166 | { |
| 2167 | return 0U; /* No FPU */ |
| 2168 | } |
| 2169 | } |
| 2170 | |
| 2171 | |
| 2172 | /*@} end of CMSIS_Core_FpuFunctions */ |
| 2173 | |
| 2174 | |
| 2175 | |
| 2176 | /* ########################## Cache functions #################################### */ |
| 2177 | /** |
| 2178 | \ingroup CMSIS_Core_FunctionInterface |
| 2179 | \defgroup CMSIS_Core_CacheFunctions Cache Functions |
| 2180 | \brief Functions that configure Instruction and Data cache. |
| 2181 | @{ |
| 2182 | */ |
| 2183 | |
| 2184 | /* Cache Size ID Register Macros */ |
| 2185 | #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) |
| 2186 | #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) |
| 2187 | |
| 2188 | |
| 2189 | /** |
| 2190 | \brief Enable I-Cache |
| 2191 | \details Turns on I-Cache |
| 2192 | */ |
| 2193 | __STATIC_INLINE void SCB_EnableICache (void) |
| 2194 | { |
| 2195 | #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) |
| 2196 | __DSB(); |
| 2197 | __ISB(); |
| 2198 | SCB->ICIALLU = 0UL; /* invalidate I-Cache */ |
| 2199 | __DSB(); |
| 2200 | __ISB(); |
| 2201 | SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ |
| 2202 | __DSB(); |
| 2203 | __ISB(); |
| 2204 | #endif |
| 2205 | } |
| 2206 | |
| 2207 | |
| 2208 | /** |
| 2209 | \brief Disable I-Cache |
| 2210 | \details Turns off I-Cache |
| 2211 | */ |
| 2212 | __STATIC_INLINE void SCB_DisableICache (void) |
| 2213 | { |
| 2214 | #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) |
| 2215 | __DSB(); |
| 2216 | __ISB(); |
| 2217 | SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ |
| 2218 | SCB->ICIALLU = 0UL; /* invalidate I-Cache */ |
| 2219 | __DSB(); |
| 2220 | __ISB(); |
| 2221 | #endif |
| 2222 | } |
| 2223 | |
| 2224 | |
| 2225 | /** |
| 2226 | \brief Invalidate I-Cache |
| 2227 | \details Invalidates I-Cache |
| 2228 | */ |
| 2229 | __STATIC_INLINE void SCB_InvalidateICache (void) |
| 2230 | { |
| 2231 | #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) |
| 2232 | __DSB(); |
| 2233 | __ISB(); |
| 2234 | SCB->ICIALLU = 0UL; |
| 2235 | __DSB(); |
| 2236 | __ISB(); |
| 2237 | #endif |
| 2238 | } |
| 2239 | |
| 2240 | |
| 2241 | /** |
| 2242 | \brief Enable D-Cache |
| 2243 | \details Turns on D-Cache |
| 2244 | */ |
| 2245 | __STATIC_INLINE void SCB_EnableDCache (void) |
| 2246 | { |
| 2247 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2248 | uint32_t ccsidr; |
| 2249 | uint32_t sets; |
| 2250 | uint32_t ways; |
| 2251 | |
| 2252 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ |
| 2253 | __DSB(); |
| 2254 | |
| 2255 | ccsidr = SCB->CCSIDR; |
| 2256 | |
| 2257 | /* invalidate D-Cache */ |
| 2258 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
| 2259 | do { |
| 2260 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
| 2261 | do { |
| 2262 | SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | |
| 2263 | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); |
| 2264 | #if defined ( __CC_ARM ) |
| 2265 | __schedule_barrier(); |
| 2266 | #endif |
| 2267 | } while (ways-- != 0U); |
| 2268 | } while(sets-- != 0U); |
| 2269 | __DSB(); |
| 2270 | |
| 2271 | SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ |
| 2272 | |
| 2273 | __DSB(); |
| 2274 | __ISB(); |
| 2275 | #endif |
| 2276 | } |
| 2277 | |
| 2278 | |
| 2279 | /** |
| 2280 | \brief Disable D-Cache |
| 2281 | \details Turns off D-Cache |
| 2282 | */ |
| 2283 | __STATIC_INLINE void SCB_DisableDCache (void) |
| 2284 | { |
| 2285 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2286 | register uint32_t ccsidr; |
| 2287 | register uint32_t sets; |
| 2288 | register uint32_t ways; |
| 2289 | |
| 2290 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ |
| 2291 | __DSB(); |
| 2292 | |
| 2293 | SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ |
| 2294 | __DSB(); |
| 2295 | |
| 2296 | ccsidr = SCB->CCSIDR; |
| 2297 | |
| 2298 | /* clean & invalidate D-Cache */ |
| 2299 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
| 2300 | do { |
| 2301 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
| 2302 | do { |
| 2303 | SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | |
| 2304 | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); |
| 2305 | #if defined ( __CC_ARM ) |
| 2306 | __schedule_barrier(); |
| 2307 | #endif |
| 2308 | } while (ways-- != 0U); |
| 2309 | } while(sets-- != 0U); |
| 2310 | |
| 2311 | __DSB(); |
| 2312 | __ISB(); |
| 2313 | #endif |
| 2314 | } |
| 2315 | |
| 2316 | |
| 2317 | /** |
| 2318 | \brief Invalidate D-Cache |
| 2319 | \details Invalidates D-Cache |
| 2320 | */ |
| 2321 | __STATIC_INLINE void SCB_InvalidateDCache (void) |
| 2322 | { |
| 2323 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2324 | uint32_t ccsidr; |
| 2325 | uint32_t sets; |
| 2326 | uint32_t ways; |
| 2327 | |
| 2328 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ |
| 2329 | __DSB(); |
| 2330 | |
| 2331 | ccsidr = SCB->CCSIDR; |
| 2332 | |
| 2333 | /* invalidate D-Cache */ |
| 2334 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
| 2335 | do { |
| 2336 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
| 2337 | do { |
| 2338 | SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | |
| 2339 | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); |
| 2340 | #if defined ( __CC_ARM ) |
| 2341 | __schedule_barrier(); |
| 2342 | #endif |
| 2343 | } while (ways-- != 0U); |
| 2344 | } while(sets-- != 0U); |
| 2345 | |
| 2346 | __DSB(); |
| 2347 | __ISB(); |
| 2348 | #endif |
| 2349 | } |
| 2350 | |
| 2351 | |
| 2352 | /** |
| 2353 | \brief Clean D-Cache |
| 2354 | \details Cleans D-Cache |
| 2355 | */ |
| 2356 | __STATIC_INLINE void SCB_CleanDCache (void) |
| 2357 | { |
| 2358 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2359 | uint32_t ccsidr; |
| 2360 | uint32_t sets; |
| 2361 | uint32_t ways; |
| 2362 | |
| 2363 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ |
| 2364 | __DSB(); |
| 2365 | |
| 2366 | ccsidr = SCB->CCSIDR; |
| 2367 | |
| 2368 | /* clean D-Cache */ |
| 2369 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
| 2370 | do { |
| 2371 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
| 2372 | do { |
| 2373 | SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | |
| 2374 | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); |
| 2375 | #if defined ( __CC_ARM ) |
| 2376 | __schedule_barrier(); |
| 2377 | #endif |
| 2378 | } while (ways-- != 0U); |
| 2379 | } while(sets-- != 0U); |
| 2380 | |
| 2381 | __DSB(); |
| 2382 | __ISB(); |
| 2383 | #endif |
| 2384 | } |
| 2385 | |
| 2386 | |
| 2387 | /** |
| 2388 | \brief Clean & Invalidate D-Cache |
| 2389 | \details Cleans and Invalidates D-Cache |
| 2390 | */ |
| 2391 | __STATIC_INLINE void SCB_CleanInvalidateDCache (void) |
| 2392 | { |
| 2393 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2394 | uint32_t ccsidr; |
| 2395 | uint32_t sets; |
| 2396 | uint32_t ways; |
| 2397 | |
| 2398 | SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ |
| 2399 | __DSB(); |
| 2400 | |
| 2401 | ccsidr = SCB->CCSIDR; |
| 2402 | |
| 2403 | /* clean & invalidate D-Cache */ |
| 2404 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
| 2405 | do { |
| 2406 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
| 2407 | do { |
| 2408 | SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | |
| 2409 | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); |
| 2410 | #if defined ( __CC_ARM ) |
| 2411 | __schedule_barrier(); |
| 2412 | #endif |
| 2413 | } while (ways-- != 0U); |
| 2414 | } while(sets-- != 0U); |
| 2415 | |
| 2416 | __DSB(); |
| 2417 | __ISB(); |
| 2418 | #endif |
| 2419 | } |
| 2420 | |
| 2421 | |
| 2422 | /** |
| 2423 | \brief D-Cache Invalidate by address |
| 2424 | \details Invalidates D-Cache for the given address |
| 2425 | \param[in] addr address (aligned to 32-byte boundary) |
| 2426 | \param[in] dsize size of memory block (in number of bytes) |
| 2427 | */ |
| 2428 | __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) |
| 2429 | { |
| 2430 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2431 | int32_t op_size = dsize; |
| 2432 | uint32_t op_addr = (uint32_t)addr; |
| 2433 | int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ |
| 2434 | |
| 2435 | __DSB(); |
| 2436 | |
| 2437 | while (op_size > 0) { |
| 2438 | SCB->DCIMVAC = op_addr; |
| 2439 | op_addr += (uint32_t)linesize; |
| 2440 | op_size -= linesize; |
| 2441 | } |
| 2442 | |
| 2443 | __DSB(); |
| 2444 | __ISB(); |
| 2445 | #endif |
| 2446 | } |
| 2447 | |
| 2448 | |
| 2449 | /** |
| 2450 | \brief D-Cache Clean by address |
| 2451 | \details Cleans D-Cache for the given address |
| 2452 | \param[in] addr address (aligned to 32-byte boundary) |
| 2453 | \param[in] dsize size of memory block (in number of bytes) |
| 2454 | */ |
| 2455 | __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) |
| 2456 | { |
| 2457 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2458 | int32_t op_size = dsize; |
| 2459 | uint32_t op_addr = (uint32_t) addr; |
| 2460 | int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ |
| 2461 | |
| 2462 | __DSB(); |
| 2463 | |
| 2464 | while (op_size > 0) { |
| 2465 | SCB->DCCMVAC = op_addr; |
| 2466 | op_addr += (uint32_t)linesize; |
| 2467 | op_size -= linesize; |
| 2468 | } |
| 2469 | |
| 2470 | __DSB(); |
| 2471 | __ISB(); |
| 2472 | #endif |
| 2473 | } |
| 2474 | |
| 2475 | |
| 2476 | /** |
| 2477 | \brief D-Cache Clean and Invalidate by address |
| 2478 | \details Cleans and invalidates D_Cache for the given address |
| 2479 | \param[in] addr address (aligned to 32-byte boundary) |
| 2480 | \param[in] dsize size of memory block (in number of bytes) |
| 2481 | */ |
| 2482 | __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) |
| 2483 | { |
| 2484 | #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 2485 | int32_t op_size = dsize; |
| 2486 | uint32_t op_addr = (uint32_t) addr; |
| 2487 | int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ |
| 2488 | |
| 2489 | __DSB(); |
| 2490 | |
| 2491 | while (op_size > 0) { |
| 2492 | SCB->DCCIMVAC = op_addr; |
| 2493 | op_addr += (uint32_t)linesize; |
| 2494 | op_size -= linesize; |
| 2495 | } |
| 2496 | |
| 2497 | __DSB(); |
| 2498 | __ISB(); |
| 2499 | #endif |
| 2500 | } |
| 2501 | |
| 2502 | |
| 2503 | /*@} end of CMSIS_Core_CacheFunctions */ |
| 2504 | |
| 2505 | |
| 2506 | |
| 2507 | /* ################################## SysTick function ############################################ */ |
| 2508 | /** |
| 2509 | \ingroup CMSIS_Core_FunctionInterface |
| 2510 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| 2511 | \brief Functions that configure the System. |
| 2512 | @{ |
| 2513 | */ |
| 2514 | |
| 2515 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
| 2516 | |
| 2517 | /** |
| 2518 | \brief System Tick Configuration |
| 2519 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| 2520 | Counter is in free running mode to generate periodic interrupts. |
| 2521 | \param [in] ticks Number of ticks between two interrupts. |
| 2522 | \return 0 Function succeeded. |
| 2523 | \return 1 Function failed. |
| 2524 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| 2525 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| 2526 | must contain a vendor-specific implementation of this function. |
| 2527 | */ |
| 2528 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| 2529 | { |
| 2530 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
| 2531 | { |
| 2532 | return (1UL); /* Reload value impossible */ |
| 2533 | } |
| 2534 | |
| 2535 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
| 2536 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
| 2537 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
| 2538 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| 2539 | SysTick_CTRL_TICKINT_Msk | |
| 2540 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| 2541 | return (0UL); /* Function successful */ |
| 2542 | } |
| 2543 | |
| 2544 | #endif |
| 2545 | |
| 2546 | /*@} end of CMSIS_Core_SysTickFunctions */ |
| 2547 | |
| 2548 | |
| 2549 | |
| 2550 | /* ##################################### Debug In/Output function ########################################### */ |
| 2551 | /** |
| 2552 | \ingroup CMSIS_Core_FunctionInterface |
| 2553 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
| 2554 | \brief Functions that access the ITM debug interface. |
| 2555 | @{ |
| 2556 | */ |
| 2557 | |
| 2558 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
| 2559 | #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
| 2560 | |
| 2561 | |
| 2562 | /** |
| 2563 | \brief ITM Send Character |
| 2564 | \details Transmits a character via the ITM channel 0, and |
| 2565 | \li Just returns when no debugger is connected that has booked the output. |
| 2566 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
| 2567 | \param [in] ch Character to transmit. |
| 2568 | \returns Character to transmit. |
| 2569 | */ |
| 2570 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
| 2571 | { |
| 2572 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
| 2573 | ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ |
| 2574 | { |
| 2575 | while (ITM->PORT[0U].u32 == 0UL) |
| 2576 | { |
| 2577 | __NOP(); |
| 2578 | } |
| 2579 | ITM->PORT[0U].u8 = (uint8_t)ch; |
| 2580 | } |
| 2581 | return (ch); |
| 2582 | } |
| 2583 | |
| 2584 | |
| 2585 | /** |
| 2586 | \brief ITM Receive Character |
| 2587 | \details Inputs a character via the external variable \ref ITM_RxBuffer. |
| 2588 | \return Received character. |
| 2589 | \return -1 No character pending. |
| 2590 | */ |
| 2591 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) |
| 2592 | { |
| 2593 | int32_t ch = -1; /* no character available */ |
| 2594 | |
| 2595 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) |
| 2596 | { |
| 2597 | ch = ITM_RxBuffer; |
| 2598 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
| 2599 | } |
| 2600 | |
| 2601 | return (ch); |
| 2602 | } |
| 2603 | |
| 2604 | |
| 2605 | /** |
| 2606 | \brief ITM Check Character |
| 2607 | \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
| 2608 | \return 0 No character available. |
| 2609 | \return 1 Character available. |
| 2610 | */ |
| 2611 | __STATIC_INLINE int32_t ITM_CheckChar (void) |
| 2612 | { |
| 2613 | |
| 2614 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) |
| 2615 | { |
| 2616 | return (0); /* no character available */ |
| 2617 | } |
| 2618 | else |
| 2619 | { |
| 2620 | return (1); /* character available */ |
| 2621 | } |
| 2622 | } |
| 2623 | |
| 2624 | /*@} end of CMSIS_core_DebugFunctions */ |
| 2625 | |
| 2626 | |
| 2627 | |
| 2628 | |
| 2629 | #ifdef __cplusplus |
| 2630 | } |
| 2631 | #endif |
| 2632 | |
| 2633 | #endif /* __CORE_CM7_H_DEPENDANT */ |
| 2634 | |
| 2635 | #endif /* __CMSIS_GENERIC */ |