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gerrit.osmocom.org / osmo-ccid-firmware / 18c2dbbb15a1a66bbf009ea57d5b281e24468645 / . / sysmoOCTSIM / CMSIS / Include / core_cm33.h
blob: 65da8ef524f51b3578aa7d98d9511513bd38cb0e [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**************************************************************************//**
2 * @file core_cm33.h
3 * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
4 * @version V5.0.2
5 * @date 07. December 2016
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM33_H_GENERIC
32#define __CORE_CM33_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_M33
60 @{
61 */
62
63/* CMSIS CM33 definitions */
64#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
67 __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69#define __CORTEX_M (33U) /*!< Cortex-M Core */
70
71/** __FPU_USED indicates whether an FPU is used or not.
72 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
73*/
74#if defined ( __CC_ARM )
75 #if defined __TARGET_FPU_VFP
76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
77 #define __FPU_USED 1U
78 #else
79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
80 #define __FPU_USED 0U
81 #endif
82 #else
83 #define __FPU_USED 0U
84 #endif
85
86#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
87 #if defined __ARM_PCS_VFP
88 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
89 #define __FPU_USED 1U
90 #else
91 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
92 #define __FPU_USED 0U
93 #endif
94 #else
95 #define __FPU_USED 0U
96 #endif
97
98#elif defined ( __GNUC__ )
99 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
101 #define __FPU_USED 1U
102 #else
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #define __FPU_USED 0U
105 #endif
106 #else
107 #define __FPU_USED 0U
108 #endif
109
110#elif defined ( __ICCARM__ )
111 #if defined __ARMVFP__
112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
113 #define __FPU_USED 1U
114 #else
115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
116 #define __FPU_USED 0U
117 #endif
118 #else
119 #define __FPU_USED 0U
120 #endif
121
122#elif defined ( __TI_ARM__ )
123 #if defined __TI_VFP_SUPPORT__
124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125 #define __FPU_USED 1U
126 #else
127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #define __FPU_USED 0U
129 #endif
130 #else
131 #define __FPU_USED 0U
132 #endif
133
134#elif defined ( __TASKING__ )
135 #if defined __FPU_VFP__
136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
137 #define __FPU_USED 1U
138 #else
139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
140 #define __FPU_USED 0U
141 #endif
142 #else
143 #define __FPU_USED 0U
144 #endif
145
146#elif defined ( __CSMC__ )
147 #if ( __CSMC__ & 0x400U)
148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
149 #define __FPU_USED 1U
150 #else
151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
152 #define __FPU_USED 0U
153 #endif
154 #else
155 #define __FPU_USED 0U
156 #endif
157
158#endif
159
160#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
161
162
163#ifdef __cplusplus
164}
165#endif
166
167#endif /* __CORE_CM33_H_GENERIC */
168
169#ifndef __CMSIS_GENERIC
170
171#ifndef __CORE_CM33_H_DEPENDANT
172#define __CORE_CM33_H_DEPENDANT
173
174#ifdef __cplusplus
175 extern "C" {
176#endif
177
178/* check device defines and use defaults */
179#if defined __CHECK_DEVICE_DEFINES
180 #ifndef __CM33_REV
181 #define __CM33_REV 0x0000U
182 #warning "__CM33_REV not defined in device header file; using default!"
183 #endif
184
185 #ifndef __FPU_PRESENT
186 #define __FPU_PRESENT 0U
187 #warning "__FPU_PRESENT not defined in device header file; using default!"
188 #endif
189
190 #ifndef __MPU_PRESENT
191 #define __MPU_PRESENT 0U
192 #warning "__MPU_PRESENT not defined in device header file; using default!"
193 #endif
194
195 #ifndef __SAUREGION_PRESENT
196 #define __SAUREGION_PRESENT 0U
197 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
198 #endif
199
200 #ifndef __DSP_PRESENT
201 #define __DSP_PRESENT 0U
202 #warning "__DSP_PRESENT not defined in device header file; using default!"
203 #endif
204
205 #ifndef __NVIC_PRIO_BITS
206 #define __NVIC_PRIO_BITS 3U
207 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
208 #endif
209
210 #ifndef __Vendor_SysTickConfig
211 #define __Vendor_SysTickConfig 0U
212 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
213 #endif
214#endif
215
216/* IO definitions (access restrictions to peripheral registers) */
217/**
218 \defgroup CMSIS_glob_defs CMSIS Global Defines
219
220 <strong>IO Type Qualifiers</strong> are used
221 \li to specify the access to peripheral variables.
222 \li for automatic generation of peripheral register debug information.
223*/
224#ifdef __cplusplus
225 #define __I volatile /*!< Defines 'read only' permissions */
226#else
227 #define __I volatile const /*!< Defines 'read only' permissions */
228#endif
229#define __O volatile /*!< Defines 'write only' permissions */
230#define __IO volatile /*!< Defines 'read / write' permissions */
231
232/* following defines should be used for structure members */
233#define __IM volatile const /*! Defines 'read only' structure member permissions */
234#define __OM volatile /*! Defines 'write only' structure member permissions */
235#define __IOM volatile /*! Defines 'read / write' structure member permissions */
236
237/*@} end of group Cortex_M33 */
238
239
240
241/*******************************************************************************
242 * Register Abstraction
243 Core Register contain:
244 - Core Register
245 - Core NVIC Register
246 - Core SCB Register
247 - Core SysTick Register
248 - Core Debug Register
249 - Core MPU Register
250 - Core SAU Register
251 - Core FPU Register
252 ******************************************************************************/
253/**
254 \defgroup CMSIS_core_register Defines and Type Definitions
255 \brief Type definitions and defines for Cortex-M processor based devices.
256*/
257
258/**
259 \ingroup CMSIS_core_register
260 \defgroup CMSIS_CORE Status and Control Registers
261 \brief Core Register type definitions.
262 @{
263 */
264
265/**
266 \brief Union type to access the Application Program Status Register (APSR).
267 */
268typedef union
269{
270 struct
271 {
272 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
273 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
274 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
275 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
276 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
277 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
278 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
279 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
280 } b; /*!< Structure used for bit access */
281 uint32_t w; /*!< Type used for word access */
282} APSR_Type;
283
284/* APSR Register Definitions */
285#define APSR_N_Pos 31U /*!< APSR: N Position */
286#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
287
288#define APSR_Z_Pos 30U /*!< APSR: Z Position */
289#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
290
291#define APSR_C_Pos 29U /*!< APSR: C Position */
292#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
293
294#define APSR_V_Pos 28U /*!< APSR: V Position */
295#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
296
297#define APSR_Q_Pos 27U /*!< APSR: Q Position */
298#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
299
300#define APSR_GE_Pos 16U /*!< APSR: GE Position */
301#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
302
303
304/**
305 \brief Union type to access the Interrupt Program Status Register (IPSR).
306 */
307typedef union
308{
309 struct
310 {
311 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
312 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
313 } b; /*!< Structure used for bit access */
314 uint32_t w; /*!< Type used for word access */
315} IPSR_Type;
316
317/* IPSR Register Definitions */
318#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
319#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
320
321
322/**
323 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
324 */
325typedef union
326{
327 struct
328 {
329 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
330 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
331 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
332 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
333 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
334 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
335 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
336 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
337 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
338 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
339 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
340 } b; /*!< Structure used for bit access */
341 uint32_t w; /*!< Type used for word access */
342} xPSR_Type;
343
344/* xPSR Register Definitions */
345#define xPSR_N_Pos 31U /*!< xPSR: N Position */
346#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
347
348#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
349#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
350
351#define xPSR_C_Pos 29U /*!< xPSR: C Position */
352#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
353
354#define xPSR_V_Pos 28U /*!< xPSR: V Position */
355#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
356
357#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
358#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
359
360#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
361#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
362
363#define xPSR_T_Pos 24U /*!< xPSR: T Position */
364#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
365
366#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
367#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
368
369#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
370#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
371
372
373/**
374 \brief Union type to access the Control Registers (CONTROL).
375 */
376typedef union
377{
378 struct
379 {
380 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
381 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
382 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
383 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
384 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
385 } b; /*!< Structure used for bit access */
386 uint32_t w; /*!< Type used for word access */
387} CONTROL_Type;
388
389/* CONTROL Register Definitions */
390#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
391#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
392
393#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
394#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
395
396#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
397#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
398
399#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
400#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
401
402/*@} end of group CMSIS_CORE */
403
404
405/**
406 \ingroup CMSIS_core_register
407 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
408 \brief Type definitions for the NVIC Registers
409 @{
410 */
411
412/**
413 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
414 */
415typedef struct
416{
417 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
418 uint32_t RESERVED0[16U];
419 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
420 uint32_t RSERVED1[16U];
421 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
422 uint32_t RESERVED2[16U];
423 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
424 uint32_t RESERVED3[16U];
425 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
426 uint32_t RESERVED4[16U];
427 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
428 uint32_t RESERVED5[16U];
429 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
430 uint32_t RESERVED6[580U];
431 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
432} NVIC_Type;
433
434/* Software Triggered Interrupt Register Definitions */
435#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
436#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
437
438/*@} end of group CMSIS_NVIC */
439
440
441/**
442 \ingroup CMSIS_core_register
443 \defgroup CMSIS_SCB System Control Block (SCB)
444 \brief Type definitions for the System Control Block Registers
445 @{
446 */
447
448/**
449 \brief Structure type to access the System Control Block (SCB).
450 */
451typedef struct
452{
453 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
454 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
455 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
456 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
457 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
458 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
459 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
460 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
461 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
462 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
463 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
464 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
465 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
466 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
467 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
468 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
469 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
470 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
471 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
472 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
473 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
474 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
475 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
476 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
477 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
478 uint32_t RESERVED3[92U];
479 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
480 uint32_t RESERVED4[15U];
481 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
482 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
483 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
484 uint32_t RESERVED5[1U];
485 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
486 uint32_t RESERVED6[1U];
487 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
488 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
489 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
490 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
491 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
492 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
493 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
494 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
495 uint32_t RESERVED7[6U];
496 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
497 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
498 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
499 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
500 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
501 uint32_t RESERVED8[1U];
502 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
503} SCB_Type;
504
505/* SCB CPUID Register Definitions */
506#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
507#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
508
509#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
510#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
511
512#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
513#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
514
515#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
516#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
517
518#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
519#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
520
521/* SCB Interrupt Control State Register Definitions */
522#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
523#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
524
525#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
526#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
527
528#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
529#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
530
531#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
532#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
533
534#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
535#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
536
537#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
538#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
539
540#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
541#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
542
543#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
544#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
545
546#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
547#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
548
549#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
550#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
551
552#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
553#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
554
555#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
556#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
557
558/* SCB Vector Table Offset Register Definitions */
559#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
560#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
561
562/* SCB Application Interrupt and Reset Control Register Definitions */
563#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
564#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
565
566#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
567#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
568
569#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
570#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
571
572#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
573#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
574
575#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
576#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
577
578#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
579#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
580
581#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
582#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
583
584#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
585#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
586
587#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
588#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
589
590/* SCB System Control Register Definitions */
591#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
592#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
593
594#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
595#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
596
597#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
598#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
599
600#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
601#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
602
603/* SCB Configuration Control Register Definitions */
604#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
605#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
606
607#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
608#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
609
610#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
611#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
612
613#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
614#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
615
616#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
617#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
618
619#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
620#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
621
622#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
623#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
624
625#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
626#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
627
628/* SCB System Handler Control and State Register Definitions */
629#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
630#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
631
632#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
633#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
634
635#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
636#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
637
638#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
639#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
640
641#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
642#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
643
644#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
645#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
646
647#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
648#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
649
650#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
651#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
652
653#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
654#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
655
656#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
657#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
658
659#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
660#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
661
662#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
663#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
664
665#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
666#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
667
668#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
669#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
670
671#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
672#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
673
674#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
675#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
676
677#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
678#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
679
680#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
681#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
682
683#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
684#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
685
686#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
687#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
688
689/* SCB Configurable Fault Status Register Definitions */
690#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
691#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
692
693#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
694#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
695
696#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
697#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
698
699/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
700#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
701#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
702
703#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
704#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
705
706#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
707#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
708
709#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
710#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
711
712#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
713#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
714
715#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
716#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
717
718/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
719#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
720#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
721
722#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
723#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
724
725#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
726#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
727
728#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
729#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
730
731#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
732#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
733
734#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
735#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
736
737#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
738#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
739
740/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
741#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
742#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
743
744#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
745#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
746
747#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
748#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
749
750#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
751#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
752
753#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
754#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
755
756#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
757#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
758
759#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
760#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
761
762/* SCB Hard Fault Status Register Definitions */
763#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
764#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
765
766#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
767#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
768
769#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
770#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
771
772/* SCB Debug Fault Status Register Definitions */
773#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
774#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
775
776#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
777#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
778
779#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
780#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
781
782#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
783#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
784
785#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
786#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
787
788/* SCB Non-Secure Access Control Register Definitions */
789#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
790#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
791
792#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
793#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
794
795#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
796#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
797
798/* SCB Cache Level ID Register Definitions */
799#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
800#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
801
802#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
803#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
804
805/* SCB Cache Type Register Definitions */
806#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
807#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
808
809#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
810#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
811
812#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
813#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
814
815#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
816#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
817
818#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
819#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
820
821/* SCB Cache Size ID Register Definitions */
822#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
823#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
824
825#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
826#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
827
828#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
829#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
830
831#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
832#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
833
834#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
835#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
836
837#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
838#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
839
840#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
841#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
842
843/* SCB Cache Size Selection Register Definitions */
844#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
845#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
846
847#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
848#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
849
850/* SCB Software Triggered Interrupt Register Definitions */
851#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
852#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
853
854/* SCB D-Cache Invalidate by Set-way Register Definitions */
855#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
856#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
857
858#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
859#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
860
861/* SCB D-Cache Clean by Set-way Register Definitions */
862#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
863#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
864
865#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
866#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
867
868/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
869#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
870#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
871
872#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
873#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
874
875/* Instruction Tightly-Coupled Memory Control Register Definitions */
876#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
877#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
878
879#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
880#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
881
882#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
883#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
884
885#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
886#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
887
888/* Data Tightly-Coupled Memory Control Register Definitions */
889#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
890#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
891
892#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
893#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
894
895#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
896#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
897
898#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
899#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
900
901/* AHBP Control Register Definitions */
902#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
903#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
904
905#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
906#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
907
908/* L1 Cache Control Register Definitions */
909#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
910#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
911
912#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
913#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
914
915#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
916#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
917
918/* AHBS Control Register Definitions */
919#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
920#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
921
922#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
923#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
924
925#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
926#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
927
928/* Auxiliary Bus Fault Status Register Definitions */
929#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
930#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
931
932#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
933#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
934
935#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
936#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
937
938#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
939#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
940
941#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
942#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
943
944#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
945#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
946
947/*@} end of group CMSIS_SCB */
948
949
950/**
951 \ingroup CMSIS_core_register
952 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
953 \brief Type definitions for the System Control and ID Register not in the SCB
954 @{
955 */
956
957/**
958 \brief Structure type to access the System Control and ID Register not in the SCB.
959 */
960typedef struct
961{
962 uint32_t RESERVED0[1U];
963 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
964 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
965 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
966} SCnSCB_Type;
967
968/* Interrupt Controller Type Register Definitions */
969#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
970#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
971
972/*@} end of group CMSIS_SCnotSCB */
973
974
975/**
976 \ingroup CMSIS_core_register
977 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
978 \brief Type definitions for the System Timer Registers.
979 @{
980 */
981
982/**
983 \brief Structure type to access the System Timer (SysTick).
984 */
985typedef struct
986{
987 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
988 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
989 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
990 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
991} SysTick_Type;
992
993/* SysTick Control / Status Register Definitions */
994#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
995#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
996
997#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
998#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
999
1000#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1001#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1002
1003#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1004#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1005
1006/* SysTick Reload Register Definitions */
1007#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1008#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1009
1010/* SysTick Current Register Definitions */
1011#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1012#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1013
1014/* SysTick Calibration Register Definitions */
1015#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1016#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1017
1018#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1019#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1020
1021#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1022#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1023
1024/*@} end of group CMSIS_SysTick */
1025
1026
1027/**
1028 \ingroup CMSIS_core_register
1029 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1030 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1031 @{
1032 */
1033
1034/**
1035 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1036 */
1037typedef struct
1038{
1039 __OM union
1040 {
1041 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1042 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1043 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1044 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1045 uint32_t RESERVED0[864U];
1046 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1047 uint32_t RESERVED1[15U];
1048 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1049 uint32_t RESERVED2[15U];
1050 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1051 uint32_t RESERVED3[29U];
1052 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
1053 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
1054 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
1055 uint32_t RESERVED4[43U];
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1057 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1058 uint32_t RESERVED5[1U];
1059 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1060 uint32_t RESERVED6[4U];
1061 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1062 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1063 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1064 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1065 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1066 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1067 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1068 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1069 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1070 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1071 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1072 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1073} ITM_Type;
1074
1075/* ITM Stimulus Port Register Definitions */
1076#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1077#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1078
1079#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1080#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1081
1082/* ITM Trace Privilege Register Definitions */
1083#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1084#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1085
1086/* ITM Trace Control Register Definitions */
1087#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1088#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1089
1090#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1091#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1092
1093#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1094#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1095
1096#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1097#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1098
1099#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1100#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1101
1102#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1103#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1104
1105#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1106#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1107
1108#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1109#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1110
1111#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1112#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1113
1114#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1115#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1116
1117/* ITM Integration Write Register Definitions */
1118#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
1119#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
1120
1121/* ITM Integration Read Register Definitions */
1122#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
1123#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
1124
1125/* ITM Integration Mode Control Register Definitions */
1126#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
1127#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
1128
1129/* ITM Lock Status Register Definitions */
1130#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1131#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1132
1133#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1134#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1135
1136#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1137#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1138
1139/*@}*/ /* end of group CMSIS_ITM */
1140
1141
1142/**
1143 \ingroup CMSIS_core_register
1144 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1145 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1146 @{
1147 */
1148
1149/**
1150 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1151 */
1152typedef struct
1153{
1154 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1155 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1156 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1157 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1158 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1159 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1160 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1161 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1162 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1163 uint32_t RESERVED1[1U];
1164 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1165 uint32_t RESERVED2[1U];
1166 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1167 uint32_t RESERVED3[1U];
1168 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1169 uint32_t RESERVED4[1U];
1170 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1171 uint32_t RESERVED5[1U];
1172 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1173 uint32_t RESERVED6[1U];
1174 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1175 uint32_t RESERVED7[1U];
1176 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1177 uint32_t RESERVED8[1U];
1178 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1179 uint32_t RESERVED9[1U];
1180 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1181 uint32_t RESERVED10[1U];
1182 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1183 uint32_t RESERVED11[1U];
1184 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1185 uint32_t RESERVED12[1U];
1186 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1187 uint32_t RESERVED13[1U];
1188 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1189 uint32_t RESERVED14[1U];
1190 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1191 uint32_t RESERVED15[1U];
1192 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1193 uint32_t RESERVED16[1U];
1194 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1195 uint32_t RESERVED17[1U];
1196 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1197 uint32_t RESERVED18[1U];
1198 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1199 uint32_t RESERVED19[1U];
1200 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1201 uint32_t RESERVED20[1U];
1202 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1203 uint32_t RESERVED21[1U];
1204 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1205 uint32_t RESERVED22[1U];
1206 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1207 uint32_t RESERVED23[1U];
1208 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1209 uint32_t RESERVED24[1U];
1210 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1211 uint32_t RESERVED25[1U];
1212 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1213 uint32_t RESERVED26[1U];
1214 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1215 uint32_t RESERVED27[1U];
1216 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1217 uint32_t RESERVED28[1U];
1218 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1219 uint32_t RESERVED29[1U];
1220 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1221 uint32_t RESERVED30[1U];
1222 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1223 uint32_t RESERVED31[1U];
1224 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1225 uint32_t RESERVED32[934U];
1226 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1227 uint32_t RESERVED33[1U];
1228 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1229} DWT_Type;
1230
1231/* DWT Control Register Definitions */
1232#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1233#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1234
1235#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1236#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1237
1238#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1239#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1240
1241#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1242#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1243
1244#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1245#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1246
1247#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1248#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1249
1250#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1251#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1252
1253#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1254#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1255
1256#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1257#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1258
1259#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1260#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1261
1262#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1263#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1264
1265#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1266#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1267
1268#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1269#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1270
1271#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1272#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1273
1274#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1275#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1276
1277#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1278#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1279
1280#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1281#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1282
1283#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1284#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1285
1286#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1287#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1288
1289/* DWT CPI Count Register Definitions */
1290#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1291#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1292
1293/* DWT Exception Overhead Count Register Definitions */
1294#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1295#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1296
1297/* DWT Sleep Count Register Definitions */
1298#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1299#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1300
1301/* DWT LSU Count Register Definitions */
1302#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1303#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1304
1305/* DWT Folded-instruction Count Register Definitions */
1306#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1307#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1308
1309/* DWT Comparator Function Register Definitions */
1310#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1311#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1312
1313#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1314#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1315
1316#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1317#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1318
1319#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1320#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1321
1322#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1323#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1324
1325/*@}*/ /* end of group CMSIS_DWT */
1326
1327
1328/**
1329 \ingroup CMSIS_core_register
1330 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1331 \brief Type definitions for the Trace Port Interface (TPI)
1332 @{
1333 */
1334
1335/**
1336 \brief Structure type to access the Trace Port Interface Register (TPI).
1337 */
1338typedef struct
1339{
1340 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1341 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1342 uint32_t RESERVED0[2U];
1343 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1344 uint32_t RESERVED1[55U];
1345 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1346 uint32_t RESERVED2[131U];
1347 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1348 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1349 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1350 uint32_t RESERVED3[759U];
1351 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1352 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1353 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1354 uint32_t RESERVED4[1U];
1355 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1356 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1357 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1358 uint32_t RESERVED5[39U];
1359 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1360 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1361 uint32_t RESERVED7[8U];
1362 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1363 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1364} TPI_Type;
1365
1366/* TPI Asynchronous Clock Prescaler Register Definitions */
1367#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1368#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1369
1370/* TPI Selected Pin Protocol Register Definitions */
1371#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1372#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1373
1374/* TPI Formatter and Flush Status Register Definitions */
1375#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1376#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1377
1378#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1379#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1380
1381#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1382#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1383
1384#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1385#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1386
1387/* TPI Formatter and Flush Control Register Definitions */
1388#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1389#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1390
1391#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1392#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1393
1394/* TPI TRIGGER Register Definitions */
1395#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1396#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1397
1398/* TPI Integration ETM Data Register Definitions (FIFO0) */
1399#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1400#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1401
1402#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1403#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1404
1405#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1406#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1407
1408#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1409#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1410
1411#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1412#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1413
1414#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1415#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1416
1417#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1418#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1419
1420/* TPI ITATBCTR2 Register Definitions */
1421#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1422#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1423
1424/* TPI Integration ITM Data Register Definitions (FIFO1) */
1425#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1426#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1427
1428#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1429#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1430
1431#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1432#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1433
1434#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1435#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1436
1437#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1438#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1439
1440#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1441#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1442
1443#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1444#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1445
1446/* TPI ITATBCTR0 Register Definitions */
1447#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1448#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1449
1450/* TPI Integration Mode Control Register Definitions */
1451#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1452#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1453
1454/* TPI DEVID Register Definitions */
1455#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1456#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1457
1458#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1459#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1460
1461#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1462#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1463
1464#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1465#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1466
1467#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1468#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1469
1470#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1471#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1472
1473/* TPI DEVTYPE Register Definitions */
1474#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1475#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1476
1477#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1478#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1479
1480/*@}*/ /* end of group CMSIS_TPI */
1481
1482
1483#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1484/**
1485 \ingroup CMSIS_core_register
1486 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1487 \brief Type definitions for the Memory Protection Unit (MPU)
1488 @{
1489 */
1490
1491/**
1492 \brief Structure type to access the Memory Protection Unit (MPU).
1493 */
1494typedef struct
1495{
1496 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1497 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1498 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1499 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1500 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1501 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1502 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1503 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1504 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1505 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1506 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1507 uint32_t RESERVED0[1];
1508 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1509 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1510} MPU_Type;
1511
1512/* MPU Type Register Definitions */
1513#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1514#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1515
1516#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1517#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1518
1519#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1520#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1521
1522/* MPU Control Register Definitions */
1523#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1524#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1525
1526#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1527#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1528
1529#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1530#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1531
1532/* MPU Region Number Register Definitions */
1533#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1534#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1535
1536/* MPU Region Base Address Register Definitions */
1537#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1538#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1539
1540#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1541#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1542
1543#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1544#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1545
1546#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1547#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1548
1549/* MPU Region Limit Address Register Definitions */
1550#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1551#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1552
1553#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1554#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1555
1556#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1557#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1558
1559/* MPU Memory Attribute Indirection Register 0 Definitions */
1560#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1561#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1562
1563#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1564#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1565
1566#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1567#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1568
1569#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1570#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1571
1572/* MPU Memory Attribute Indirection Register 1 Definitions */
1573#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1574#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1575
1576#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1577#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1578
1579#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1580#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1581
1582#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1583#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1584
1585/*@} end of group CMSIS_MPU */
1586#endif
1587
1588
1589#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1590/**
1591 \ingroup CMSIS_core_register
1592 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1593 \brief Type definitions for the Security Attribution Unit (SAU)
1594 @{
1595 */
1596
1597/**
1598 \brief Structure type to access the Security Attribution Unit (SAU).
1599 */
1600typedef struct
1601{
1602 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1603 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1604#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1605 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1606 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1607 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1608#else
1609 uint32_t RESERVED0[3];
1610#endif
1611 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1612 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1613} SAU_Type;
1614
1615/* SAU Control Register Definitions */
1616#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1617#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1618
1619#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1620#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1621
1622/* SAU Type Register Definitions */
1623#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1624#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1625
1626#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1627/* SAU Region Number Register Definitions */
1628#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1629#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1630
1631/* SAU Region Base Address Register Definitions */
1632#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1633#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1634
1635/* SAU Region Limit Address Register Definitions */
1636#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1637#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1638
1639#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1640#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1641
1642#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1643#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1644
1645#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1646
1647/* Secure Fault Status Register Definitions */
1648#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1649#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1650
1651#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1652#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1653
1654#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1655#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1656
1657#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1658#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1659
1660#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1661#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1662
1663#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1664#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1665
1666#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1667#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1668
1669#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1670#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1671
1672/*@} end of group CMSIS_SAU */
1673#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1674
1675
1676/**
1677 \ingroup CMSIS_core_register
1678 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1679 \brief Type definitions for the Floating Point Unit (FPU)
1680 @{
1681 */
1682
1683/**
1684 \brief Structure type to access the Floating Point Unit (FPU).
1685 */
1686typedef struct
1687{
1688 uint32_t RESERVED0[1U];
1689 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1690 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1691 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1692 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1693 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1694} FPU_Type;
1695
1696/* Floating-Point Context Control Register Definitions */
1697#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1698#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1699
1700#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1701#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1702
1703#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1704#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1705
1706#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1707#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1708
1709#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1710#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1711
1712#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1713#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1714
1715#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1716#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1717
1718#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1719#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1720
1721#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1722#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1723
1724#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1725#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1726
1727#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1728#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1729
1730#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1731#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1732
1733#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1734#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1735
1736#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1737#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1738
1739#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1740#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1741
1742#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1743#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1744
1745#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1746#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1747
1748/* Floating-Point Context Address Register Definitions */
1749#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1750#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1751
1752/* Floating-Point Default Status Control Register Definitions */
1753#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1754#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1755
1756#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1757#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1758
1759#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1760#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1761
1762#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1763#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1764
1765/* Media and FP Feature Register 0 Definitions */
1766#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1767#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1768
1769#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1770#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1771
1772#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1773#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1774
1775#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1776#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1777
1778#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1779#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1780
1781#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1782#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1783
1784#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1785#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1786
1787#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1788#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1789
1790/* Media and FP Feature Register 1 Definitions */
1791#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1792#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1793
1794#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1795#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1796
1797#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1798#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1799
1800#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1801#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1802
1803/*@} end of group CMSIS_FPU */
1804
1805
1806/**
1807 \ingroup CMSIS_core_register
1808 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1809 \brief Type definitions for the Core Debug Registers
1810 @{
1811 */
1812
1813/**
1814 \brief Structure type to access the Core Debug Register (CoreDebug).
1815 */
1816typedef struct
1817{
1818 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1819 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1820 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1821 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1822 uint32_t RESERVED4[1U];
1823 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1824 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1825} CoreDebug_Type;
1826
1827/* Debug Halting Control and Status Register Definitions */
1828#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1829#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1830
1831#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1832#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1833
1834#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1835#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1836
1837#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1838#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1839
1840#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1841#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1842
1843#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1844#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1845
1846#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1847#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1848
1849#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1850#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1851
1852#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1853#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1854
1855#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1856#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1857
1858#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1859#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1860
1861#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1862#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1863
1864#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1865#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1866
1867/* Debug Core Register Selector Register Definitions */
1868#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1869#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1870
1871#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1872#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1873
1874/* Debug Exception and Monitor Control Register Definitions */
1875#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1876#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1877
1878#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1879#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1880
1881#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1882#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1883
1884#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1885#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1886
1887#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1888#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1889
1890#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1891#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1892
1893#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1894#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1895
1896#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1897#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1898
1899#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1900#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1901
1902#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1903#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1904
1905#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1906#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1907
1908#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1909#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1910
1911#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1912#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1913
1914/* Debug Authentication Control Register Definitions */
1915#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1916#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1917
1918#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1919#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1920
1921#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1922#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1923
1924#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1925#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1926
1927/* Debug Security Control and Status Register Definitions */
1928#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1929#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1930
1931#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1932#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1933
1934#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1935#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1936
1937/*@} end of group CMSIS_CoreDebug */
1938
1939
1940/**
1941 \ingroup CMSIS_core_register
1942 \defgroup CMSIS_core_bitfield Core register bit field macros
1943 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1944 @{
1945 */
1946
1947/**
1948 \brief Mask and shift a bit field value for use in a register bit range.
1949 \param[in] field Name of the register bit field.
1950 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1951 \return Masked and shifted value.
1952*/
1953#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1954
1955/**
1956 \brief Mask and shift a register value to extract a bit filed value.
1957 \param[in] field Name of the register bit field.
1958 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1959 \return Masked and shifted bit field value.
1960*/
1961#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1962
1963/*@} end of group CMSIS_core_bitfield */
1964
1965
1966/**
1967 \ingroup CMSIS_core_register
1968 \defgroup CMSIS_core_base Core Definitions
1969 \brief Definitions for base addresses, unions, and structures.
1970 @{
1971 */
1972
1973/* Memory mapping of Core Hardware */
1974 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1975 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1976 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1977 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1978 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1979 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1980 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1981 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1982
1983 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1984 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1985 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1986 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1987 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1988 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1989 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1990 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
1991
1992 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1993 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1994 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1995 #endif
1996
1997 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1998 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1999 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2000 #endif
2001
2002 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2003 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2004
2005#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2006 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2007 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
2008 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2009 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2010 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2011
2012 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2013 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2014 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2015 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2016 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
2017
2018 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2019 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2020 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2021 #endif
2022
2023 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2024 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2025
2026#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2027/*@} */
2028
2029
2030
2031/*******************************************************************************
2032 * Hardware Abstraction Layer
2033 Core Function Interface contains:
2034 - Core NVIC Functions
2035 - Core SysTick Functions
2036 - Core Debug Functions
2037 - Core Register Access Functions
2038 ******************************************************************************/
2039/**
2040 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2041*/
2042
2043
2044
2045/* ########################## NVIC functions #################################### */
2046/**
2047 \ingroup CMSIS_Core_FunctionInterface
2048 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2049 \brief Functions that manage interrupts and exceptions via the NVIC.
2050 @{
2051 */
2052
2053#ifndef CMSIS_NVIC_VIRTUAL
2054 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2055 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2056 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2057 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2058 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2059 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2060 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2061 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2062 #define NVIC_GetActive __NVIC_GetActive
2063 #define NVIC_SetPriority __NVIC_SetPriority
2064 #define NVIC_GetPriority __NVIC_GetPriority
2065#endif /* CMSIS_NVIC_VIRTUAL */
2066
2067#ifndef CMSIS_VECTAB_VIRTUAL
2068 #define NVIC_SetVector __NVIC_SetVector
2069 #define NVIC_GetVector __NVIC_GetVector
2070#endif /* (CMSIS_VECTAB_VIRTUAL) */
2071
2072#define NVIC_USER_IRQ_OFFSET 16
2073
2074
2075
2076/**
2077 \brief Set Priority Grouping
2078 \details Sets the priority grouping field using the required unlock sequence.
2079 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2080 Only values from 0..7 are used.
2081 In case of a conflict between priority grouping and available
2082 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2083 \param [in] PriorityGroup Priority grouping field.
2084 */
2085__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2086{
2087 uint32_t reg_value;
2088 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2089
2090 reg_value = SCB->AIRCR; /* read old register configuration */
2091 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2092 reg_value = (reg_value |
2093 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2094 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2095 SCB->AIRCR = reg_value;
2096}
2097
2098
2099/**
2100 \brief Get Priority Grouping
2101 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2102 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2103 */
2104__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2105{
2106 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2107}
2108
2109
2110/**
2111 \brief Enable Interrupt
2112 \details Enables a device specific interrupt in the NVIC interrupt controller.
2113 \param [in] IRQn Device specific interrupt number.
2114 \note IRQn must not be negative.
2115 */
2116__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2117{
2118 if ((int32_t)(IRQn) >= 0)
2119 {
2120 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2121 }
2122}
2123
2124
2125/**
2126 \brief Get Interrupt Enable status
2127 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2128 \param [in] IRQn Device specific interrupt number.
2129 \return 0 Interrupt is not enabled.
2130 \return 1 Interrupt is enabled.
2131 \note IRQn must not be negative.
2132 */
2133__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2134{
2135 if ((int32_t)(IRQn) >= 0)
2136 {
2137 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2138 }
2139 else
2140 {
2141 return(0U);
2142 }
2143}
2144
2145
2146/**
2147 \brief Disable Interrupt
2148 \details Disables a device specific interrupt in the NVIC interrupt controller.
2149 \param [in] IRQn Device specific interrupt number.
2150 \note IRQn must not be negative.
2151 */
2152__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2153{
2154 if ((int32_t)(IRQn) >= 0)
2155 {
2156 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2157 __DSB();
2158 __ISB();
2159 }
2160}
2161
2162
2163/**
2164 \brief Get Pending Interrupt
2165 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2166 \param [in] IRQn Device specific interrupt number.
2167 \return 0 Interrupt status is not pending.
2168 \return 1 Interrupt status is pending.
2169 \note IRQn must not be negative.
2170 */
2171__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2172{
2173 if ((int32_t)(IRQn) >= 0)
2174 {
2175 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2176 }
2177 else
2178 {
2179 return(0U);
2180 }
2181}
2182
2183
2184/**
2185 \brief Set Pending Interrupt
2186 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2187 \param [in] IRQn Device specific interrupt number.
2188 \note IRQn must not be negative.
2189 */
2190__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2191{
2192 if ((int32_t)(IRQn) >= 0)
2193 {
2194 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2195 }
2196}
2197
2198
2199/**
2200 \brief Clear Pending Interrupt
2201 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2202 \param [in] IRQn Device specific interrupt number.
2203 \note IRQn must not be negative.
2204 */
2205__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2206{
2207 if ((int32_t)(IRQn) >= 0)
2208 {
2209 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2210 }
2211}
2212
2213
2214/**
2215 \brief Get Active Interrupt
2216 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2217 \param [in] IRQn Device specific interrupt number.
2218 \return 0 Interrupt status is not active.
2219 \return 1 Interrupt status is active.
2220 \note IRQn must not be negative.
2221 */
2222__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2223{
2224 if ((int32_t)(IRQn) >= 0)
2225 {
2226 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2227 }
2228 else
2229 {
2230 return(0U);
2231 }
2232}
2233
2234
2235#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2236/**
2237 \brief Get Interrupt Target State
2238 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2239 \param [in] IRQn Device specific interrupt number.
2240 \return 0 if interrupt is assigned to Secure
2241 \return 1 if interrupt is assigned to Non Secure
2242 \note IRQn must not be negative.
2243 */
2244__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2245{
2246 if ((int32_t)(IRQn) >= 0)
2247 {
2248 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2249 }
2250 else
2251 {
2252 return(0U);
2253 }
2254}
2255
2256
2257/**
2258 \brief Set Interrupt Target State
2259 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2260 \param [in] IRQn Device specific interrupt number.
2261 \return 0 if interrupt is assigned to Secure
2262 1 if interrupt is assigned to Non Secure
2263 \note IRQn must not be negative.
2264 */
2265__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2266{
2267 if ((int32_t)(IRQn) >= 0)
2268 {
2269 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
2270 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2271 }
2272 else
2273 {
2274 return(0U);
2275 }
2276}
2277
2278
2279/**
2280 \brief Clear Interrupt Target State
2281 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2282 \param [in] IRQn Device specific interrupt number.
2283 \return 0 if interrupt is assigned to Secure
2284 1 if interrupt is assigned to Non Secure
2285 \note IRQn must not be negative.
2286 */
2287__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2288{
2289 if ((int32_t)(IRQn) >= 0)
2290 {
2291 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
2292 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2293 }
2294 else
2295 {
2296 return(0U);
2297 }
2298}
2299#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2300
2301
2302/**
2303 \brief Set Interrupt Priority
2304 \details Sets the priority of a device specific interrupt or a processor exception.
2305 The interrupt number can be positive to specify a device specific interrupt,
2306 or negative to specify a processor exception.
2307 \param [in] IRQn Interrupt number.
2308 \param [in] priority Priority to set.
2309 \note The priority cannot be set for every processor exception.
2310 */
2311__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2312{
2313 if ((int32_t)(IRQn) >= 0)
2314 {
2315 NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2316 }
2317 else
2318 {
2319 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2320 }
2321}
2322
2323
2324/**
2325 \brief Get Interrupt Priority
2326 \details Reads the priority of a device specific interrupt or a processor exception.
2327 The interrupt number can be positive to specify a device specific interrupt,
2328 or negative to specify a processor exception.
2329 \param [in] IRQn Interrupt number.
2330 \return Interrupt Priority.
2331 Value is aligned automatically to the implemented priority bits of the microcontroller.
2332 */
2333__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2334{
2335
2336 if ((int32_t)(IRQn) >= 0)
2337 {
2338 return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2339 }
2340 else
2341 {
2342 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2343 }
2344}
2345
2346
2347/**
2348 \brief Encode Priority
2349 \details Encodes the priority for an interrupt with the given priority group,
2350 preemptive priority value, and subpriority value.
2351 In case of a conflict between priority grouping and available
2352 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2353 \param [in] PriorityGroup Used priority group.
2354 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2355 \param [in] SubPriority Subpriority value (starting from 0).
2356 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2357 */
2358__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2359{
2360 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2361 uint32_t PreemptPriorityBits;
2362 uint32_t SubPriorityBits;
2363
2364 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2365 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2366
2367 return (
2368 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2369 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2370 );
2371}
2372
2373
2374/**
2375 \brief Decode Priority
2376 \details Decodes an interrupt priority value with a given priority group to
2377 preemptive priority value and subpriority value.
2378 In case of a conflict between priority grouping and available
2379 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2380 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2381 \param [in] PriorityGroup Used priority group.
2382 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2383 \param [out] pSubPriority Subpriority value (starting from 0).
2384 */
2385__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2386{
2387 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2388 uint32_t PreemptPriorityBits;
2389 uint32_t SubPriorityBits;
2390
2391 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2392 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2393
2394 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2395 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2396}
2397
2398
2399/**
2400 \brief Set Interrupt Vector
2401 \details Sets an interrupt vector in SRAM based interrupt vector table.
2402 The interrupt number can be positive to specify a device specific interrupt,
2403 or negative to specify a processor exception.
2404 VTOR must been relocated to SRAM before.
2405 \param [in] IRQn Interrupt number
2406 \param [in] vector Address of interrupt handler function
2407 */
2408__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2409{
2410 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2411 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2412}
2413
2414
2415/**
2416 \brief Get Interrupt Vector
2417 \details Reads an interrupt vector from interrupt vector table.
2418 The interrupt number can be positive to specify a device specific interrupt,
2419 or negative to specify a processor exception.
2420 \param [in] IRQn Interrupt number.
2421 \return Address of interrupt handler function
2422 */
2423__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2424{
2425 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2426 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2427}
2428
2429
2430/**
2431 \brief System Reset
2432 \details Initiates a system reset request to reset the MCU.
2433 */
2434__STATIC_INLINE void NVIC_SystemReset(void)
2435{
2436 __DSB(); /* Ensure all outstanding memory accesses included
2437 buffered write are completed before reset */
2438 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2439 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2440 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2441 __DSB(); /* Ensure completion of memory access */
2442
2443 for(;;) /* wait until reset */
2444 {
2445 __NOP();
2446 }
2447}
2448
2449#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2450/**
2451 \brief Set Priority Grouping (non-secure)
2452 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2453 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2454 Only values from 0..7 are used.
2455 In case of a conflict between priority grouping and available
2456 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2457 \param [in] PriorityGroup Priority grouping field.
2458 */
2459__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2460{
2461 uint32_t reg_value;
2462 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2463
2464 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2465 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2466 reg_value = (reg_value |
2467 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2468 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2469 SCB_NS->AIRCR = reg_value;
2470}
2471
2472
2473/**
2474 \brief Get Priority Grouping (non-secure)
2475 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2476 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2477 */
2478__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2479{
2480 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2481}
2482
2483
2484/**
2485 \brief Enable Interrupt (non-secure)
2486 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2487 \param [in] IRQn Device specific interrupt number.
2488 \note IRQn must not be negative.
2489 */
2490__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2491{
2492 if ((int32_t)(IRQn) >= 0)
2493 {
2494 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2495 }
2496}
2497
2498
2499/**
2500 \brief Get Interrupt Enable status (non-secure)
2501 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2502 \param [in] IRQn Device specific interrupt number.
2503 \return 0 Interrupt is not enabled.
2504 \return 1 Interrupt is enabled.
2505 \note IRQn must not be negative.
2506 */
2507__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2508{
2509 if ((int32_t)(IRQn) >= 0)
2510 {
2511 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2512 }
2513 else
2514 {
2515 return(0U);
2516 }
2517}
2518
2519
2520/**
2521 \brief Disable Interrupt (non-secure)
2522 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2523 \param [in] IRQn Device specific interrupt number.
2524 \note IRQn must not be negative.
2525 */
2526__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2527{
2528 if ((int32_t)(IRQn) >= 0)
2529 {
2530 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2531 }
2532}
2533
2534
2535/**
2536 \brief Get Pending Interrupt (non-secure)
2537 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2538 \param [in] IRQn Device specific interrupt number.
2539 \return 0 Interrupt status is not pending.
2540 \return 1 Interrupt status is pending.
2541 \note IRQn must not be negative.
2542 */
2543__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2544{
2545 if ((int32_t)(IRQn) >= 0)
2546 {
2547 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2548 }
2549}
2550
2551
2552/**
2553 \brief Set Pending Interrupt (non-secure)
2554 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2555 \param [in] IRQn Device specific interrupt number.
2556 \note IRQn must not be negative.
2557 */
2558__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2559{
2560 if ((int32_t)(IRQn) >= 0)
2561 {
2562 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2563 }
2564}
2565
2566
2567/**
2568 \brief Clear Pending Interrupt (non-secure)
2569 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2570 \param [in] IRQn Device specific interrupt number.
2571 \note IRQn must not be negative.
2572 */
2573__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2574{
2575 if ((int32_t)(IRQn) >= 0)
2576 {
2577 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2578 }
2579}
2580
2581
2582/**
2583 \brief Get Active Interrupt (non-secure)
2584 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2585 \param [in] IRQn Device specific interrupt number.
2586 \return 0 Interrupt status is not active.
2587 \return 1 Interrupt status is active.
2588 \note IRQn must not be negative.
2589 */
2590__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2591{
2592 if ((int32_t)(IRQn) >= 0)
2593 {
2594 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2595 }
2596 else
2597 {
2598 return(0U);
2599 }
2600}
2601
2602
2603/**
2604 \brief Set Interrupt Priority (non-secure)
2605 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2606 The interrupt number can be positive to specify a device specific interrupt,
2607 or negative to specify a processor exception.
2608 \param [in] IRQn Interrupt number.
2609 \param [in] priority Priority to set.
2610 \note The priority cannot be set for every non-secure processor exception.
2611 */
2612__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2613{
2614 if ((int32_t)(IRQn) >= 0)
2615 {
2616 NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2617 }
2618 else
2619 {
2620 SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2621 }
2622}
2623
2624
2625/**
2626 \brief Get Interrupt Priority (non-secure)
2627 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2628 The interrupt number can be positive to specify a device specific interrupt,
2629 or negative to specify a processor exception.
2630 \param [in] IRQn Interrupt number.
2631 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2632 */
2633__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2634{
2635
2636 if ((int32_t)(IRQn) >= 0)
2637 {
2638 return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2639 }
2640 else
2641 {
2642 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2643 }
2644}
2645#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2646
2647/*@} end of CMSIS_Core_NVICFunctions */
2648
2649
2650/* ########################## FPU functions #################################### */
2651/**
2652 \ingroup CMSIS_Core_FunctionInterface
2653 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2654 \brief Function that provides FPU type.
2655 @{
2656 */
2657
2658/**
2659 \brief get FPU type
2660 \details returns the FPU type
2661 \returns
2662 - \b 0: No FPU
2663 - \b 1: Single precision FPU
2664 - \b 2: Double + Single precision FPU
2665 */
2666__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2667{
2668 uint32_t mvfr0;
2669
2670 mvfr0 = FPU->MVFR0;
2671 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2672 {
2673 return 2U; /* Double + Single precision FPU */
2674 }
2675 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2676 {
2677 return 1U; /* Single precision FPU */
2678 }
2679 else
2680 {
2681 return 0U; /* No FPU */
2682 }
2683}
2684
2685
2686/*@} end of CMSIS_Core_FpuFunctions */
2687
2688
2689
2690/* ########################## SAU functions #################################### */
2691/**
2692 \ingroup CMSIS_Core_FunctionInterface
2693 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2694 \brief Functions that configure the SAU.
2695 @{
2696 */
2697
2698#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2699
2700/**
2701 \brief Enable SAU
2702 \details Enables the Security Attribution Unit (SAU).
2703 */
2704__STATIC_INLINE void TZ_SAU_Enable(void)
2705{
2706 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2707}
2708
2709
2710
2711/**
2712 \brief Disable SAU
2713 \details Disables the Security Attribution Unit (SAU).
2714 */
2715__STATIC_INLINE void TZ_SAU_Disable(void)
2716{
2717 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2718}
2719
2720#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2721
2722/*@} end of CMSIS_Core_SAUFunctions */
2723
2724
2725
2726
2727/* ################################## SysTick function ############################################ */
2728/**
2729 \ingroup CMSIS_Core_FunctionInterface
2730 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2731 \brief Functions that configure the System.
2732 @{
2733 */
2734
2735#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2736
2737/**
2738 \brief System Tick Configuration
2739 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2740 Counter is in free running mode to generate periodic interrupts.
2741 \param [in] ticks Number of ticks between two interrupts.
2742 \return 0 Function succeeded.
2743 \return 1 Function failed.
2744 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2745 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2746 must contain a vendor-specific implementation of this function.
2747 */
2748__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2749{
2750 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2751 {
2752 return (1UL); /* Reload value impossible */
2753 }
2754
2755 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2756 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2757 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2758 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2759 SysTick_CTRL_TICKINT_Msk |
2760 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2761 return (0UL); /* Function successful */
2762}
2763
2764#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2765/**
2766 \brief System Tick Configuration (non-secure)
2767 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2768 Counter is in free running mode to generate periodic interrupts.
2769 \param [in] ticks Number of ticks between two interrupts.
2770 \return 0 Function succeeded.
2771 \return 1 Function failed.
2772 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2773 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2774 must contain a vendor-specific implementation of this function.
2775
2776 */
2777__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2778{
2779 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2780 {
2781 return (1UL); /* Reload value impossible */
2782 }
2783
2784 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2785 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2786 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2787 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2788 SysTick_CTRL_TICKINT_Msk |
2789 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2790 return (0UL); /* Function successful */
2791}
2792#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2793
2794#endif
2795
2796/*@} end of CMSIS_Core_SysTickFunctions */
2797
2798
2799
2800/* ##################################### Debug In/Output function ########################################### */
2801/**
2802 \ingroup CMSIS_Core_FunctionInterface
2803 \defgroup CMSIS_core_DebugFunctions ITM Functions
2804 \brief Functions that access the ITM debug interface.
2805 @{
2806 */
2807
2808extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2809#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2810
2811
2812/**
2813 \brief ITM Send Character
2814 \details Transmits a character via the ITM channel 0, and
2815 \li Just returns when no debugger is connected that has booked the output.
2816 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2817 \param [in] ch Character to transmit.
2818 \returns Character to transmit.
2819 */
2820__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2821{
2822 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2823 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2824 {
2825 while (ITM->PORT[0U].u32 == 0UL)
2826 {
2827 __NOP();
2828 }
2829 ITM->PORT[0U].u8 = (uint8_t)ch;
2830 }
2831 return (ch);
2832}
2833
2834
2835/**
2836 \brief ITM Receive Character
2837 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2838 \return Received character.
2839 \return -1 No character pending.
2840 */
2841__STATIC_INLINE int32_t ITM_ReceiveChar (void)
2842{
2843 int32_t ch = -1; /* no character available */
2844
2845 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2846 {
2847 ch = ITM_RxBuffer;
2848 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2849 }
2850
2851 return (ch);
2852}
2853
2854
2855/**
2856 \brief ITM Check Character
2857 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2858 \return 0 No character available.
2859 \return 1 Character available.
2860 */
2861__STATIC_INLINE int32_t ITM_CheckChar (void)
2862{
2863
2864 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2865 {
2866 return (0); /* no character available */
2867 }
2868 else
2869 {
2870 return (1); /* character available */
2871 }
2872}
2873
2874/*@} end of CMSIS_core_DebugFunctions */
2875
2876
2877
2878
2879#ifdef __cplusplus
2880}
2881#endif
2882
2883#endif /* __CORE_CM33_H_DEPENDANT */
2884
2885#endif /* __CMSIS_GENERIC */