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gerrit.osmocom.org / osmo-ccid-firmware / 18c2dbbb15a1a66bbf009ea57d5b281e24468645 / . / sysmoOCTSIM / CMSIS / Include / core_armv8mbl.h
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Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**************************************************************************//**
2 * @file core_armv8mbl.h
3 * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
4 * @version V5.0.1
5 * @date 25. November 2016
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_ARMV8MBL_H_GENERIC
32#define __CORE_ARMV8MBL_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_ARMv8MBL
60 @{
61 */
62
63/* CMSIS cmGrebe definitions */
64#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
67 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
70
71/** __FPU_USED indicates whether an FPU is used or not.
72 This core does not support an FPU at all
73*/
74#define __FPU_USED 0U
75
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #endif
80
81#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
82 #if defined __ARM_PCS_VFP
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #endif
85
86#elif defined ( __GNUC__ )
87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89 #endif
90
91#elif defined ( __ICCARM__ )
92 #if defined __ARMVFP__
93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #endif
95
96#elif defined ( __TI_ARM__ )
97 #if defined __TI_VFP_SUPPORT__
98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99 #endif
100
101#elif defined ( __TASKING__ )
102 #if defined __FPU_VFP__
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #endif
105
106#elif defined ( __CSMC__ )
107 #if ( __CSMC__ & 0x400U)
108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109 #endif
110
111#endif
112
113#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
114
115
116#ifdef __cplusplus
117}
118#endif
119
120#endif /* __CORE_ARMV8MBL_H_GENERIC */
121
122#ifndef __CMSIS_GENERIC
123
124#ifndef __CORE_ARMV8MBL_H_DEPENDANT
125#define __CORE_ARMV8MBL_H_DEPENDANT
126
127#ifdef __cplusplus
128 extern "C" {
129#endif
130
131/* check device defines and use defaults */
132#if defined __CHECK_DEVICE_DEFINES
133 #ifndef __ARMv8MBL_REV
134 #define __ARMv8MBL_REV 0x0000U
135 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
136 #endif
137
138 #ifndef __FPU_PRESENT
139 #define __FPU_PRESENT 0U
140 #warning "__FPU_PRESENT not defined in device header file; using default!"
141 #endif
142
143 #ifndef __MPU_PRESENT
144 #define __MPU_PRESENT 0U
145 #warning "__MPU_PRESENT not defined in device header file; using default!"
146 #endif
147
148 #ifndef __SAUREGION_PRESENT
149 #define __SAUREGION_PRESENT 0U
150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
151 #endif
152
153 #ifndef __VTOR_PRESENT
154 #define __VTOR_PRESENT 0U
155 #warning "__VTOR_PRESENT not defined in device header file; using default!"
156 #endif
157
158 #ifndef __NVIC_PRIO_BITS
159 #define __NVIC_PRIO_BITS 2U
160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
161 #endif
162
163 #ifndef __Vendor_SysTickConfig
164 #define __Vendor_SysTickConfig 0U
165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
166 #endif
167
168 #ifndef __ETM_PRESENT
169 #define __ETM_PRESENT 0U
170 #warning "__ETM_PRESENT not defined in device header file; using default!"
171 #endif
172
173 #ifndef __MTB_PRESENT
174 #define __MTB_PRESENT 0U
175 #warning "__MTB_PRESENT not defined in device header file; using default!"
176 #endif
177
178#endif
179
180/* IO definitions (access restrictions to peripheral registers) */
181/**
182 \defgroup CMSIS_glob_defs CMSIS Global Defines
183
184 <strong>IO Type Qualifiers</strong> are used
185 \li to specify the access to peripheral variables.
186 \li for automatic generation of peripheral register debug information.
187*/
188#ifdef __cplusplus
189 #define __I volatile /*!< Defines 'read only' permissions */
190#else
191 #define __I volatile const /*!< Defines 'read only' permissions */
192#endif
193#define __O volatile /*!< Defines 'write only' permissions */
194#define __IO volatile /*!< Defines 'read / write' permissions */
195
196/* following defines should be used for structure members */
197#define __IM volatile const /*! Defines 'read only' structure member permissions */
198#define __OM volatile /*! Defines 'write only' structure member permissions */
199#define __IOM volatile /*! Defines 'read / write' structure member permissions */
200
201/*@} end of group ARMv8MBL */
202
203
204
205/*******************************************************************************
206 * Register Abstraction
207 Core Register contain:
208 - Core Register
209 - Core NVIC Register
210 - Core SCB Register
211 - Core SysTick Register
212 - Core Debug Register
213 - Core MPU Register
214 - Core SAU Register
215 ******************************************************************************/
216/**
217 \defgroup CMSIS_core_register Defines and Type Definitions
218 \brief Type definitions and defines for Cortex-M processor based devices.
219*/
220
221/**
222 \ingroup CMSIS_core_register
223 \defgroup CMSIS_CORE Status and Control Registers
224 \brief Core Register type definitions.
225 @{
226 */
227
228/**
229 \brief Union type to access the Application Program Status Register (APSR).
230 */
231typedef union
232{
233 struct
234 {
235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
240 } b; /*!< Structure used for bit access */
241 uint32_t w; /*!< Type used for word access */
242} APSR_Type;
243
244/* APSR Register Definitions */
245#define APSR_N_Pos 31U /*!< APSR: N Position */
246#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
247
248#define APSR_Z_Pos 30U /*!< APSR: Z Position */
249#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
250
251#define APSR_C_Pos 29U /*!< APSR: C Position */
252#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
253
254#define APSR_V_Pos 28U /*!< APSR: V Position */
255#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
256
257
258/**
259 \brief Union type to access the Interrupt Program Status Register (IPSR).
260 */
261typedef union
262{
263 struct
264 {
265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
267 } b; /*!< Structure used for bit access */
268 uint32_t w; /*!< Type used for word access */
269} IPSR_Type;
270
271/* IPSR Register Definitions */
272#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
273#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
274
275
276/**
277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
278 */
279typedef union
280{
281 struct
282 {
283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
291 } b; /*!< Structure used for bit access */
292 uint32_t w; /*!< Type used for word access */
293} xPSR_Type;
294
295/* xPSR Register Definitions */
296#define xPSR_N_Pos 31U /*!< xPSR: N Position */
297#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
298
299#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
300#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
301
302#define xPSR_C_Pos 29U /*!< xPSR: C Position */
303#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
304
305#define xPSR_V_Pos 28U /*!< xPSR: V Position */
306#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
307
308#define xPSR_T_Pos 24U /*!< xPSR: T Position */
309#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
310
311#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
312#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
313
314
315/**
316 \brief Union type to access the Control Registers (CONTROL).
317 */
318typedef union
319{
320 struct
321 {
322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
325 } b; /*!< Structure used for bit access */
326 uint32_t w; /*!< Type used for word access */
327} CONTROL_Type;
328
329/* CONTROL Register Definitions */
330#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
331#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
332
333#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
334#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
335
336/*@} end of group CMSIS_CORE */
337
338
339/**
340 \ingroup CMSIS_core_register
341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
342 \brief Type definitions for the NVIC Registers
343 @{
344 */
345
346/**
347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
348 */
349typedef struct
350{
351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
352 uint32_t RESERVED0[16U];
353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
354 uint32_t RSERVED1[16U];
355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
356 uint32_t RESERVED2[16U];
357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
358 uint32_t RESERVED3[16U];
359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
360 uint32_t RESERVED4[16U];
361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
362 uint32_t RESERVED5[16U];
363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
364} NVIC_Type;
365
366/*@} end of group CMSIS_NVIC */
367
368
369/**
370 \ingroup CMSIS_core_register
371 \defgroup CMSIS_SCB System Control Block (SCB)
372 \brief Type definitions for the System Control Block Registers
373 @{
374 */
375
376/**
377 \brief Structure type to access the System Control Block (SCB).
378 */
379typedef struct
380{
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
383#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
385#else
386 uint32_t RESERVED0;
387#endif
388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
391 uint32_t RESERVED1;
392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
394} SCB_Type;
395
396/* SCB CPUID Register Definitions */
397#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
398#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
399
400#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
401#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
402
403#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
404#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
405
406#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
407#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
408
409#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
410#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
411
412/* SCB Interrupt Control State Register Definitions */
413#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
414#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
415
416#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
417#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
418
419#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
420#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
421
422#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
423#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
424
425#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
426#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
427
428#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
429#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
430
431#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
432#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
433
434#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
435#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
436
437#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
438#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
439
440#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
441#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
442
443#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
444#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
445
446#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
447#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
448
449#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
450/* SCB Vector Table Offset Register Definitions */
451#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
452#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
453#endif
454
455/* SCB Application Interrupt and Reset Control Register Definitions */
456#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
457#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
458
459#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
460#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
461
462#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
463#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
464
465#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
466#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
467
468#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
469#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
470
471#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
472#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
473
474#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
475#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
476
477#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
478#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
479
480/* SCB System Control Register Definitions */
481#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
482#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
483
484#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
485#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
486
487#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
488#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
489
490#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
491#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
492
493/* SCB Configuration Control Register Definitions */
494#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
495#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
496
497#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
498#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
499
500#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
501#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
502
503#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
504#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
505
506#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
507#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
508
509#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
510#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
511
512#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
513#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
514
515#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
516#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
517
518/* SCB System Handler Control and State Register Definitions */
519#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
520#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
521
522#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
523#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
524
525#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
526#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
527
528#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
529#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
530
531#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
532#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
533
534#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
535#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
536
537#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
538#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
539
540/*@} end of group CMSIS_SCB */
541
542
543/**
544 \ingroup CMSIS_core_register
545 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
546 \brief Type definitions for the System Timer Registers.
547 @{
548 */
549
550/**
551 \brief Structure type to access the System Timer (SysTick).
552 */
553typedef struct
554{
555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
559} SysTick_Type;
560
561/* SysTick Control / Status Register Definitions */
562#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
563#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
564
565#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
566#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
567
568#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
569#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
570
571#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
572#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
573
574/* SysTick Reload Register Definitions */
575#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
576#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
577
578/* SysTick Current Register Definitions */
579#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
580#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
581
582/* SysTick Calibration Register Definitions */
583#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
584#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
585
586#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
587#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
588
589#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
590#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
591
592/*@} end of group CMSIS_SysTick */
593
594
595/**
596 \ingroup CMSIS_core_register
597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
598 \brief Type definitions for the Data Watchpoint and Trace (DWT)
599 @{
600 */
601
602/**
603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
604 */
605typedef struct
606{
607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
608 uint32_t RESERVED0[6U];
609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
611 uint32_t RESERVED1[1U];
612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
613 uint32_t RESERVED2[1U];
614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
615 uint32_t RESERVED3[1U];
616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
617 uint32_t RESERVED4[1U];
618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
619 uint32_t RESERVED5[1U];
620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
621 uint32_t RESERVED6[1U];
622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
623 uint32_t RESERVED7[1U];
624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
625 uint32_t RESERVED8[1U];
626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
627 uint32_t RESERVED9[1U];
628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
629 uint32_t RESERVED10[1U];
630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
631 uint32_t RESERVED11[1U];
632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
633 uint32_t RESERVED12[1U];
634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
635 uint32_t RESERVED13[1U];
636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
637 uint32_t RESERVED14[1U];
638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
639 uint32_t RESERVED15[1U];
640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
641 uint32_t RESERVED16[1U];
642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
643 uint32_t RESERVED17[1U];
644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
645 uint32_t RESERVED18[1U];
646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
647 uint32_t RESERVED19[1U];
648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
649 uint32_t RESERVED20[1U];
650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
651 uint32_t RESERVED21[1U];
652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
653 uint32_t RESERVED22[1U];
654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
655 uint32_t RESERVED23[1U];
656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
657 uint32_t RESERVED24[1U];
658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
659 uint32_t RESERVED25[1U];
660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
661 uint32_t RESERVED26[1U];
662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
663 uint32_t RESERVED27[1U];
664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
665 uint32_t RESERVED28[1U];
666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
667 uint32_t RESERVED29[1U];
668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
669 uint32_t RESERVED30[1U];
670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
671 uint32_t RESERVED31[1U];
672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
673} DWT_Type;
674
675/* DWT Control Register Definitions */
676#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
677#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
678
679#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
680#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
681
682#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
683#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
684
685#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
686#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
687
688#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
689#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
690
691/* DWT Comparator Function Register Definitions */
692#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
693#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
694
695#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
696#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
697
698#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
699#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
700
701#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
702#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
703
704#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
705#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
706
707/*@}*/ /* end of group CMSIS_DWT */
708
709
710/**
711 \ingroup CMSIS_core_register
712 \defgroup CMSIS_TPI Trace Port Interface (TPI)
713 \brief Type definitions for the Trace Port Interface (TPI)
714 @{
715 */
716
717/**
718 \brief Structure type to access the Trace Port Interface Register (TPI).
719 */
720typedef struct
721{
722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
724 uint32_t RESERVED0[2U];
725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
726 uint32_t RESERVED1[55U];
727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
728 uint32_t RESERVED2[131U];
729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
732 uint32_t RESERVED3[759U];
733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
736 uint32_t RESERVED4[1U];
737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
740 uint32_t RESERVED5[39U];
741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
743 uint32_t RESERVED7[8U];
744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
746} TPI_Type;
747
748/* TPI Asynchronous Clock Prescaler Register Definitions */
749#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
750#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
751
752/* TPI Selected Pin Protocol Register Definitions */
753#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
754#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
755
756/* TPI Formatter and Flush Status Register Definitions */
757#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
758#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
759
760#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
761#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
762
763#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
764#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
765
766#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
767#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
768
769/* TPI Formatter and Flush Control Register Definitions */
770#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
771#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
772
773#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
774#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
775
776/* TPI TRIGGER Register Definitions */
777#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
778#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
779
780/* TPI Integration ETM Data Register Definitions (FIFO0) */
781#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
782#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
783
784#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
785#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
786
787#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
788#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
789
790#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
791#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
792
793#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
794#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
795
796#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
797#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
798
799#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
800#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
801
802/* TPI ITATBCTR2 Register Definitions */
803#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
804#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
805
806/* TPI Integration ITM Data Register Definitions (FIFO1) */
807#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
808#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
809
810#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
811#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
812
813#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
814#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
815
816#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
817#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
818
819#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
820#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
821
822#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
823#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
824
825#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
826#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
827
828/* TPI ITATBCTR0 Register Definitions */
829#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
830#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
831
832/* TPI Integration Mode Control Register Definitions */
833#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
834#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
835
836/* TPI DEVID Register Definitions */
837#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
838#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
839
840#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
841#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
842
843#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
844#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
845
846#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
847#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
848
849#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
850#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
851
852#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
853#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
854
855/* TPI DEVTYPE Register Definitions */
856#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
857#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
858
859#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
860#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
861
862/*@}*/ /* end of group CMSIS_TPI */
863
864
865#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
866/**
867 \ingroup CMSIS_core_register
868 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
869 \brief Type definitions for the Memory Protection Unit (MPU)
870 @{
871 */
872
873/**
874 \brief Structure type to access the Memory Protection Unit (MPU).
875 */
876typedef struct
877{
878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
883 uint32_t RESERVED0[7U];
884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
886} MPU_Type;
887
888/* MPU Type Register Definitions */
889#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
890#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
891
892#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
893#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
894
895#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
896#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
897
898/* MPU Control Register Definitions */
899#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
900#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
901
902#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
903#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
904
905#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
906#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
907
908/* MPU Region Number Register Definitions */
909#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
910#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
911
912/* MPU Region Base Address Register Definitions */
913#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
914#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
915
916#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
917#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
918
919#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
920#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
921
922#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
923#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
924
925/* MPU Region Limit Address Register Definitions */
926#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
927#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
928
929#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
930#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
931
932#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
933#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
934
935/* MPU Memory Attribute Indirection Register 0 Definitions */
936#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
937#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
938
939#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
940#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
941
942#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
943#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
944
945#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
946#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
947
948/* MPU Memory Attribute Indirection Register 1 Definitions */
949#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
950#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
951
952#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
953#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
954
955#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
956#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
957
958#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
959#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
960
961/*@} end of group CMSIS_MPU */
962#endif
963
964
965#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
966/**
967 \ingroup CMSIS_core_register
968 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
969 \brief Type definitions for the Security Attribution Unit (SAU)
970 @{
971 */
972
973/**
974 \brief Structure type to access the Security Attribution Unit (SAU).
975 */
976typedef struct
977{
978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
980#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
984#endif
985} SAU_Type;
986
987/* SAU Control Register Definitions */
988#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
989#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
990
991#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
992#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
993
994/* SAU Type Register Definitions */
995#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
996#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
997
998#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
999/* SAU Region Number Register Definitions */
1000#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1001#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1002
1003/* SAU Region Base Address Register Definitions */
1004#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1005#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1006
1007/* SAU Region Limit Address Register Definitions */
1008#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1009#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1010
1011#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1012#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1013
1014#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1015#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1016
1017#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1018
1019/*@} end of group CMSIS_SAU */
1020#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1021
1022
1023/**
1024 \ingroup CMSIS_core_register
1025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1026 \brief Type definitions for the Core Debug Registers
1027 @{
1028 */
1029
1030/**
1031 \brief Structure type to access the Core Debug Register (CoreDebug).
1032 */
1033typedef struct
1034{
1035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1039 uint32_t RESERVED4[1U];
1040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1042} CoreDebug_Type;
1043
1044/* Debug Halting Control and Status Register Definitions */
1045#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1046#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1047
1048#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1049#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1050
1051#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1052#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1053
1054#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1055#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1056
1057#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1058#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1059
1060#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1061#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1062
1063#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1064#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1065
1066#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1067#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1068
1069#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1070#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1071
1072#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1073#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1074
1075#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1076#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1077
1078#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1079#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1080
1081/* Debug Core Register Selector Register Definitions */
1082#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1083#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1084
1085#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1086#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1087
1088/* Debug Exception and Monitor Control Register */
1089#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
1090#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
1091
1092#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1093#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1094
1095#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1096#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1097
1098/* Debug Authentication Control Register Definitions */
1099#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1100#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1101
1102#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1103#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1104
1105#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1106#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1107
1108#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1109#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1110
1111/* Debug Security Control and Status Register Definitions */
1112#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1113#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1114
1115#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1116#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1117
1118#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1119#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1120
1121/*@} end of group CMSIS_CoreDebug */
1122
1123
1124/**
1125 \ingroup CMSIS_core_register
1126 \defgroup CMSIS_core_bitfield Core register bit field macros
1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1128 @{
1129 */
1130
1131/**
1132 \brief Mask and shift a bit field value for use in a register bit range.
1133 \param[in] field Name of the register bit field.
1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1135 \return Masked and shifted value.
1136*/
1137#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1138
1139/**
1140 \brief Mask and shift a register value to extract a bit filed value.
1141 \param[in] field Name of the register bit field.
1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1143 \return Masked and shifted bit field value.
1144*/
1145#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1146
1147/*@} end of group CMSIS_core_bitfield */
1148
1149
1150/**
1151 \ingroup CMSIS_core_register
1152 \defgroup CMSIS_core_base Core Definitions
1153 \brief Definitions for base addresses, unions, and structures.
1154 @{
1155 */
1156
1157/* Memory mapping of Core Hardware */
1158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1165
1166
1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
1173
1174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1177 #endif
1178
1179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
1182 #endif
1183
1184#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
1186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
1187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
1188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
1189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
1190
1191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
1192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
1193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
1194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
1195
1196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
1198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
1199 #endif
1200
1201#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1202/*@} */
1203
1204
1205
1206/*******************************************************************************
1207 * Hardware Abstraction Layer
1208 Core Function Interface contains:
1209 - Core NVIC Functions
1210 - Core SysTick Functions
1211 - Core Register Access Functions
1212 ******************************************************************************/
1213/**
1214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1215*/
1216
1217
1218
1219/* ########################## NVIC functions #################################### */
1220/**
1221 \ingroup CMSIS_Core_FunctionInterface
1222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1223 \brief Functions that manage interrupts and exceptions via the NVIC.
1224 @{
1225 */
1226
1227#ifndef CMSIS_NVIC_VIRTUAL
1228/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */
1229/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */
1230 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1231 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1232 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1233 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1234 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1235 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1236 #define NVIC_GetActive __NVIC_GetActive
1237 #define NVIC_SetPriority __NVIC_SetPriority
1238 #define NVIC_GetPriority __NVIC_GetPriority
1239#endif /* CMSIS_NVIC_VIRTUAL */
1240
1241#ifndef CMSIS_VECTAB_VIRTUAL
1242 #define NVIC_SetVector __NVIC_SetVector
1243 #define NVIC_GetVector __NVIC_GetVector
1244#endif /* (CMSIS_VECTAB_VIRTUAL) */
1245
1246#define NVIC_USER_IRQ_OFFSET 16
1247
1248
1249/* Interrupt Priorities are WORD accessible only under ARMv6M */
1250/* The following MACROS handle generation of the register offset and byte masks */
1251#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1252#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1253#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1254
1255
1256/**
1257 \brief Enable Interrupt
1258 \details Enables a device specific interrupt in the NVIC interrupt controller.
1259 \param [in] IRQn Device specific interrupt number.
1260 \note IRQn must not be negative.
1261 */
1262__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1263{
1264 if ((int32_t)(IRQn) >= 0)
1265 {
1266 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1267 }
1268}
1269
1270
1271/**
1272 \brief Get Interrupt Enable status
1273 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1274 \param [in] IRQn Device specific interrupt number.
1275 \return 0 Interrupt is not enabled.
1276 \return 1 Interrupt is enabled.
1277 \note IRQn must not be negative.
1278 */
1279__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1280{
1281 if ((int32_t)(IRQn) >= 0)
1282 {
1283 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1284 }
1285 else
1286 {
1287 return(0U);
1288 }
1289}
1290
1291
1292/**
1293 \brief Disable Interrupt
1294 \details Disables a device specific interrupt in the NVIC interrupt controller.
1295 \param [in] IRQn Device specific interrupt number.
1296 \note IRQn must not be negative.
1297 */
1298__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1299{
1300 if ((int32_t)(IRQn) >= 0)
1301 {
1302 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1303 __DSB();
1304 __ISB();
1305 }
1306}
1307
1308
1309/**
1310 \brief Get Pending Interrupt
1311 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1312 \param [in] IRQn Device specific interrupt number.
1313 \return 0 Interrupt status is not pending.
1314 \return 1 Interrupt status is pending.
1315 \note IRQn must not be negative.
1316 */
1317__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1318{
1319 if ((int32_t)(IRQn) >= 0)
1320 {
1321 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1322 }
1323 else
1324 {
1325 return(0U);
1326 }
1327}
1328
1329
1330/**
1331 \brief Set Pending Interrupt
1332 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1333 \param [in] IRQn Device specific interrupt number.
1334 \note IRQn must not be negative.
1335 */
1336__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1337{
1338 if ((int32_t)(IRQn) >= 0)
1339 {
1340 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1341 }
1342}
1343
1344
1345/**
1346 \brief Clear Pending Interrupt
1347 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1348 \param [in] IRQn Device specific interrupt number.
1349 \note IRQn must not be negative.
1350 */
1351__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1352{
1353 if ((int32_t)(IRQn) >= 0)
1354 {
1355 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1356 }
1357}
1358
1359
1360/**
1361 \brief Get Active Interrupt
1362 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1363 \param [in] IRQn Device specific interrupt number.
1364 \return 0 Interrupt status is not active.
1365 \return 1 Interrupt status is active.
1366 \note IRQn must not be negative.
1367 */
1368__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1369{
1370 if ((int32_t)(IRQn) >= 0)
1371 {
1372 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1373 }
1374 else
1375 {
1376 return(0U);
1377 }
1378}
1379
1380
1381#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1382/**
1383 \brief Get Interrupt Target State
1384 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1385 \param [in] IRQn Device specific interrupt number.
1386 \return 0 if interrupt is assigned to Secure
1387 \return 1 if interrupt is assigned to Non Secure
1388 \note IRQn must not be negative.
1389 */
1390__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1391{
1392 if ((int32_t)(IRQn) >= 0)
1393 {
1394 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1395 }
1396 else
1397 {
1398 return(0U);
1399 }
1400}
1401
1402
1403/**
1404 \brief Set Interrupt Target State
1405 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1406 \param [in] IRQn Device specific interrupt number.
1407 \return 0 if interrupt is assigned to Secure
1408 1 if interrupt is assigned to Non Secure
1409 \note IRQn must not be negative.
1410 */
1411__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1412{
1413 if ((int32_t)(IRQn) >= 0)
1414 {
1415 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
1416 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1417 }
1418 else
1419 {
1420 return(0U);
1421 }
1422}
1423
1424
1425/**
1426 \brief Clear Interrupt Target State
1427 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1428 \param [in] IRQn Device specific interrupt number.
1429 \return 0 if interrupt is assigned to Secure
1430 1 if interrupt is assigned to Non Secure
1431 \note IRQn must not be negative.
1432 */
1433__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1434{
1435 if ((int32_t)(IRQn) >= 0)
1436 {
1437 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
1438 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1439 }
1440 else
1441 {
1442 return(0U);
1443 }
1444}
1445#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1446
1447
1448/**
1449 \brief Set Interrupt Priority
1450 \details Sets the priority of a device specific interrupt or a processor exception.
1451 The interrupt number can be positive to specify a device specific interrupt,
1452 or negative to specify a processor exception.
1453 \param [in] IRQn Interrupt number.
1454 \param [in] priority Priority to set.
1455 \note The priority cannot be set for every processor exception.
1456 */
1457__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1458{
1459 if ((int32_t)(IRQn) >= 0)
1460 {
1461 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1462 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1463 }
1464 else
1465 {
1466 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1467 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1468 }
1469}
1470
1471
1472/**
1473 \brief Get Interrupt Priority
1474 \details Reads the priority of a device specific interrupt or a processor exception.
1475 The interrupt number can be positive to specify a device specific interrupt,
1476 or negative to specify a processor exception.
1477 \param [in] IRQn Interrupt number.
1478 \return Interrupt Priority.
1479 Value is aligned automatically to the implemented priority bits of the microcontroller.
1480 */
1481__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1482{
1483
1484 if ((int32_t)(IRQn) >= 0)
1485 {
1486 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1487 }
1488 else
1489 {
1490 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1491 }
1492}
1493
1494
1495/**
1496 \brief Set Interrupt Vector
1497 \details Sets an interrupt vector in SRAM based interrupt vector table.
1498 The interrupt number can be positive to specify a device specific interrupt,
1499 or negative to specify a processor exception.
1500 VTOR must been relocated to SRAM before.
1501 If VTOR is not present address 0 must be mapped to SRAM.
1502 \param [in] IRQn Interrupt number
1503 \param [in] vector Address of interrupt handler function
1504 */
1505__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1506{
1507#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1508 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1509#else
1510 uint32_t *vectors = (uint32_t *)0x0U;
1511#endif
1512 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1513}
1514
1515
1516/**
1517 \brief Get Interrupt Vector
1518 \details Reads an interrupt vector from interrupt vector table.
1519 The interrupt number can be positive to specify a device specific interrupt,
1520 or negative to specify a processor exception.
1521 \param [in] IRQn Interrupt number.
1522 \return Address of interrupt handler function
1523 */
1524__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1525{
1526#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1527 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1528#else
1529 uint32_t *vectors = (uint32_t *)0x0U;
1530#endif
1531 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1532}
1533
1534
1535/**
1536 \brief System Reset
1537 \details Initiates a system reset request to reset the MCU.
1538 */
1539__STATIC_INLINE void NVIC_SystemReset(void)
1540{
1541 __DSB(); /* Ensure all outstanding memory accesses included
1542 buffered write are completed before reset */
1543 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1544 SCB_AIRCR_SYSRESETREQ_Msk);
1545 __DSB(); /* Ensure completion of memory access */
1546
1547 for(;;) /* wait until reset */
1548 {
1549 __NOP();
1550 }
1551}
1552
1553#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1554/**
1555 \brief Enable Interrupt (non-secure)
1556 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1557 \param [in] IRQn Device specific interrupt number.
1558 \note IRQn must not be negative.
1559 */
1560__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1561{
1562 if ((int32_t)(IRQn) >= 0)
1563 {
1564 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1565 }
1566}
1567
1568
1569/**
1570 \brief Get Interrupt Enable status (non-secure)
1571 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
1572 \param [in] IRQn Device specific interrupt number.
1573 \return 0 Interrupt is not enabled.
1574 \return 1 Interrupt is enabled.
1575 \note IRQn must not be negative.
1576 */
1577__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1578{
1579 if ((int32_t)(IRQn) >= 0)
1580 {
1581 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1582 }
1583 else
1584 {
1585 return(0U);
1586 }
1587}
1588
1589
1590/**
1591 \brief Disable Interrupt (non-secure)
1592 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1593 \param [in] IRQn Device specific interrupt number.
1594 \note IRQn must not be negative.
1595 */
1596__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1597{
1598 if ((int32_t)(IRQn) >= 0)
1599 {
1600 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1601 }
1602}
1603
1604
1605/**
1606 \brief Get Pending Interrupt (non-secure)
1607 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
1608 \param [in] IRQn Device specific interrupt number.
1609 \return 0 Interrupt status is not pending.
1610 \return 1 Interrupt status is pending.
1611 \note IRQn must not be negative.
1612 */
1613__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1614{
1615 if ((int32_t)(IRQn) >= 0)
1616 {
1617 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1618 }
1619}
1620
1621
1622/**
1623 \brief Set Pending Interrupt (non-secure)
1624 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1625 \param [in] IRQn Device specific interrupt number.
1626 \note IRQn must not be negative.
1627 */
1628__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1629{
1630 if ((int32_t)(IRQn) >= 0)
1631 {
1632 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1633 }
1634}
1635
1636
1637/**
1638 \brief Clear Pending Interrupt (non-secure)
1639 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1640 \param [in] IRQn Device specific interrupt number.
1641 \note IRQn must not be negative.
1642 */
1643__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1644{
1645 if ((int32_t)(IRQn) >= 0)
1646 {
1647 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1648 }
1649}
1650
1651
1652/**
1653 \brief Get Active Interrupt (non-secure)
1654 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
1655 \param [in] IRQn Device specific interrupt number.
1656 \return 0 Interrupt status is not active.
1657 \return 1 Interrupt status is active.
1658 \note IRQn must not be negative.
1659 */
1660__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1661{
1662 if ((int32_t)(IRQn) >= 0)
1663 {
1664 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1665 }
1666 else
1667 {
1668 return(0U);
1669 }
1670}
1671
1672
1673/**
1674 \brief Set Interrupt Priority (non-secure)
1675 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1676 The interrupt number can be positive to specify a device specific interrupt,
1677 or negative to specify a processor exception.
1678 \param [in] IRQn Interrupt number.
1679 \param [in] priority Priority to set.
1680 \note The priority cannot be set for every non-secure processor exception.
1681 */
1682__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1683{
1684 if ((int32_t)(IRQn) >= 0)
1685 {
1686 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1687 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1688 }
1689 else
1690 {
1691 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1692 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1693 }
1694}
1695
1696
1697/**
1698 \brief Get Interrupt Priority (non-secure)
1699 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1700 The interrupt number can be positive to specify a device specific interrupt,
1701 or negative to specify a processor exception.
1702 \param [in] IRQn Interrupt number.
1703 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
1704 */
1705__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1706{
1707
1708 if ((int32_t)(IRQn) >= 0)
1709 {
1710 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1711 }
1712 else
1713 {
1714 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1715 }
1716}
1717#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1718
1719/*@} end of CMSIS_Core_NVICFunctions */
1720
1721
1722/* ########################## FPU functions #################################### */
1723/**
1724 \ingroup CMSIS_Core_FunctionInterface
1725 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1726 \brief Function that provides FPU type.
1727 @{
1728 */
1729
1730/**
1731 \brief get FPU type
1732 \details returns the FPU type
1733 \returns
1734 - \b 0: No FPU
1735 - \b 1: Single precision FPU
1736 - \b 2: Double + Single precision FPU
1737 */
1738__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1739{
1740 return 0U; /* No FPU */
1741}
1742
1743
1744/*@} end of CMSIS_Core_FpuFunctions */
1745
1746
1747
1748/* ########################## SAU functions #################################### */
1749/**
1750 \ingroup CMSIS_Core_FunctionInterface
1751 \defgroup CMSIS_Core_SAUFunctions SAU Functions
1752 \brief Functions that configure the SAU.
1753 @{
1754 */
1755
1756#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1757
1758/**
1759 \brief Enable SAU
1760 \details Enables the Security Attribution Unit (SAU).
1761 */
1762__STATIC_INLINE void TZ_SAU_Enable(void)
1763{
1764 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
1765}
1766
1767
1768
1769/**
1770 \brief Disable SAU
1771 \details Disables the Security Attribution Unit (SAU).
1772 */
1773__STATIC_INLINE void TZ_SAU_Disable(void)
1774{
1775 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
1776}
1777
1778#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1779
1780/*@} end of CMSIS_Core_SAUFunctions */
1781
1782
1783
1784
1785/* ################################## SysTick function ############################################ */
1786/**
1787 \ingroup CMSIS_Core_FunctionInterface
1788 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1789 \brief Functions that configure the System.
1790 @{
1791 */
1792
1793#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1794
1795/**
1796 \brief System Tick Configuration
1797 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1798 Counter is in free running mode to generate periodic interrupts.
1799 \param [in] ticks Number of ticks between two interrupts.
1800 \return 0 Function succeeded.
1801 \return 1 Function failed.
1802 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1803 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1804 must contain a vendor-specific implementation of this function.
1805 */
1806__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1807{
1808 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1809 {
1810 return (1UL); /* Reload value impossible */
1811 }
1812
1813 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1814 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1815 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1816 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1817 SysTick_CTRL_TICKINT_Msk |
1818 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1819 return (0UL); /* Function successful */
1820}
1821
1822#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1823/**
1824 \brief System Tick Configuration (non-secure)
1825 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
1826 Counter is in free running mode to generate periodic interrupts.
1827 \param [in] ticks Number of ticks between two interrupts.
1828 \return 0 Function succeeded.
1829 \return 1 Function failed.
1830 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1831 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
1832 must contain a vendor-specific implementation of this function.
1833
1834 */
1835__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
1836{
1837 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1838 {
1839 return (1UL); /* Reload value impossible */
1840 }
1841
1842 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1843 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1844 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
1845 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1846 SysTick_CTRL_TICKINT_Msk |
1847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1848 return (0UL); /* Function successful */
1849}
1850#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1851
1852#endif
1853
1854/*@} end of CMSIS_Core_SysTickFunctions */
1855
1856
1857
1858
1859#ifdef __cplusplus
1860}
1861#endif
1862
1863#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
1864
1865#endif /* __CMSIS_GENERIC */