Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM SUPC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_SUPC_COMPONENT_ |
| 35 | #ifndef _HRI_SUPC_E54_H_INCLUDED_ |
| 36 | #define _HRI_SUPC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_SUPC_CRITICAL_SECTIONS) |
| 46 | #define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define SUPC_CRITICAL_SECTION_ENTER() |
| 50 | #define SUPC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_supc_bbps_reg_t; |
| 54 | typedef uint32_t hri_supc_bkin_reg_t; |
| 55 | typedef uint32_t hri_supc_bkout_reg_t; |
| 56 | typedef uint32_t hri_supc_bod12_reg_t; |
| 57 | typedef uint32_t hri_supc_bod33_reg_t; |
| 58 | typedef uint32_t hri_supc_intenset_reg_t; |
| 59 | typedef uint32_t hri_supc_intflag_reg_t; |
| 60 | typedef uint32_t hri_supc_status_reg_t; |
| 61 | typedef uint32_t hri_supc_vref_reg_t; |
| 62 | typedef uint32_t hri_supc_vreg_reg_t; |
| 63 | |
| 64 | static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) |
| 65 | { |
| 66 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; |
| 67 | } |
| 68 | |
| 69 | static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) |
| 70 | { |
| 71 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; |
| 72 | } |
| 73 | |
| 74 | static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) |
| 75 | { |
| 76 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; |
| 77 | } |
| 78 | |
| 79 | static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) |
| 80 | { |
| 81 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; |
| 82 | } |
| 83 | |
| 84 | static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) |
| 85 | { |
| 86 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; |
| 87 | } |
| 88 | |
| 89 | static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) |
| 90 | { |
| 91 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; |
| 92 | } |
| 93 | |
| 94 | static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) |
| 95 | { |
| 96 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; |
| 97 | } |
| 98 | |
| 99 | static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) |
| 100 | { |
| 101 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; |
| 102 | } |
| 103 | |
| 104 | static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) |
| 105 | { |
| 106 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; |
| 107 | } |
| 108 | |
| 109 | static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) |
| 110 | { |
| 111 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; |
| 112 | } |
| 113 | |
| 114 | static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) |
| 115 | { |
| 116 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; |
| 117 | } |
| 118 | |
| 119 | static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) |
| 120 | { |
| 121 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; |
| 122 | } |
| 123 | |
| 124 | static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) |
| 125 | { |
| 126 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; |
| 127 | } |
| 128 | |
| 129 | static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) |
| 130 | { |
| 131 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; |
| 132 | } |
| 133 | |
| 134 | static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) |
| 135 | { |
| 136 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; |
| 137 | } |
| 138 | |
| 139 | static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) |
| 140 | { |
| 141 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; |
| 142 | } |
| 143 | |
| 144 | static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) |
| 145 | { |
| 146 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; |
| 147 | } |
| 148 | |
| 149 | static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) |
| 150 | { |
| 151 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; |
| 152 | } |
| 153 | |
| 154 | static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) |
| 155 | { |
| 156 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; |
| 157 | } |
| 158 | |
| 159 | static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) |
| 160 | { |
| 161 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; |
| 162 | } |
| 163 | |
| 164 | static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) |
| 165 | { |
| 166 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; |
| 167 | } |
| 168 | |
| 169 | static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) |
| 170 | { |
| 171 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; |
| 172 | } |
| 173 | |
| 174 | static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) |
| 175 | { |
| 176 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; |
| 177 | } |
| 178 | |
| 179 | static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) |
| 180 | { |
| 181 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; |
| 182 | } |
| 183 | |
| 184 | static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) |
| 185 | { |
| 186 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; |
| 187 | } |
| 188 | |
| 189 | static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) |
| 190 | { |
| 191 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; |
| 192 | } |
| 193 | |
| 194 | static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) |
| 195 | { |
| 196 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; |
| 197 | } |
| 198 | |
| 199 | static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) |
| 200 | { |
| 201 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; |
| 202 | } |
| 203 | |
| 204 | static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) |
| 205 | { |
| 206 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; |
| 207 | } |
| 208 | |
| 209 | static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) |
| 210 | { |
| 211 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; |
| 212 | } |
| 213 | |
| 214 | static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) |
| 215 | { |
| 216 | return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; |
| 217 | } |
| 218 | |
| 219 | static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) |
| 220 | { |
| 221 | ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; |
| 222 | } |
| 223 | |
| 224 | static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) |
| 225 | { |
| 226 | uint32_t tmp; |
| 227 | tmp = ((Supc *)hw)->INTFLAG.reg; |
| 228 | tmp &= mask; |
| 229 | return tmp; |
| 230 | } |
| 231 | |
| 232 | static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) |
| 233 | { |
| 234 | return ((Supc *)hw)->INTFLAG.reg; |
| 235 | } |
| 236 | |
| 237 | static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) |
| 238 | { |
| 239 | ((Supc *)hw)->INTFLAG.reg = mask; |
| 240 | } |
| 241 | |
| 242 | static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) |
| 243 | { |
| 244 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; |
| 245 | } |
| 246 | |
| 247 | static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) |
| 248 | { |
| 249 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; |
| 250 | } |
| 251 | |
| 252 | static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) |
| 253 | { |
| 254 | if (value == 0x0) { |
| 255 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; |
| 256 | } else { |
| 257 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) |
| 262 | { |
| 263 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; |
| 264 | } |
| 265 | |
| 266 | static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) |
| 267 | { |
| 268 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; |
| 269 | } |
| 270 | |
| 271 | static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) |
| 272 | { |
| 273 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; |
| 274 | } |
| 275 | |
| 276 | static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) |
| 277 | { |
| 278 | if (value == 0x0) { |
| 279 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; |
| 280 | } else { |
| 281 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; |
| 282 | } |
| 283 | } |
| 284 | |
| 285 | static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) |
| 286 | { |
| 287 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; |
| 288 | } |
| 289 | |
| 290 | static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) |
| 291 | { |
| 292 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; |
| 293 | } |
| 294 | |
| 295 | static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) |
| 296 | { |
| 297 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; |
| 298 | } |
| 299 | |
| 300 | static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) |
| 301 | { |
| 302 | if (value == 0x0) { |
| 303 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; |
| 304 | } else { |
| 305 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) |
| 310 | { |
| 311 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; |
| 312 | } |
| 313 | |
| 314 | static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) |
| 315 | { |
| 316 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; |
| 317 | } |
| 318 | |
| 319 | static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) |
| 320 | { |
| 321 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; |
| 322 | } |
| 323 | |
| 324 | static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) |
| 325 | { |
| 326 | if (value == 0x0) { |
| 327 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; |
| 328 | } else { |
| 329 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) |
| 334 | { |
| 335 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; |
| 336 | } |
| 337 | |
| 338 | static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) |
| 339 | { |
| 340 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; |
| 341 | } |
| 342 | |
| 343 | static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) |
| 344 | { |
| 345 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; |
| 346 | } |
| 347 | |
| 348 | static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) |
| 349 | { |
| 350 | if (value == 0x0) { |
| 351 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; |
| 352 | } else { |
| 353 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; |
| 354 | } |
| 355 | } |
| 356 | |
| 357 | static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) |
| 358 | { |
| 359 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; |
| 360 | } |
| 361 | |
| 362 | static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) |
| 363 | { |
| 364 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; |
| 365 | } |
| 366 | |
| 367 | static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) |
| 368 | { |
| 369 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; |
| 370 | } |
| 371 | |
| 372 | static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) |
| 373 | { |
| 374 | if (value == 0x0) { |
| 375 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; |
| 376 | } else { |
| 377 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) |
| 382 | { |
| 383 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; |
| 384 | } |
| 385 | |
| 386 | static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) |
| 387 | { |
| 388 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; |
| 389 | } |
| 390 | |
| 391 | static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) |
| 392 | { |
| 393 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; |
| 394 | } |
| 395 | |
| 396 | static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) |
| 397 | { |
| 398 | if (value == 0x0) { |
| 399 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; |
| 400 | } else { |
| 401 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) |
| 406 | { |
| 407 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; |
| 408 | } |
| 409 | |
| 410 | static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) |
| 411 | { |
| 412 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; |
| 413 | } |
| 414 | |
| 415 | static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) |
| 416 | { |
| 417 | return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; |
| 418 | } |
| 419 | |
| 420 | static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) |
| 421 | { |
| 422 | if (value == 0x0) { |
| 423 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; |
| 424 | } else { |
| 425 | ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; |
| 426 | } |
| 427 | } |
| 428 | |
| 429 | static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) |
| 430 | { |
| 431 | ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; |
| 432 | } |
| 433 | |
| 434 | static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) |
| 435 | { |
| 436 | ((Supc *)hw)->INTENSET.reg = mask; |
| 437 | } |
| 438 | |
| 439 | static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) |
| 440 | { |
| 441 | uint32_t tmp; |
| 442 | tmp = ((Supc *)hw)->INTENSET.reg; |
| 443 | tmp &= mask; |
| 444 | return tmp; |
| 445 | } |
| 446 | |
| 447 | static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) |
| 448 | { |
| 449 | return ((Supc *)hw)->INTENSET.reg; |
| 450 | } |
| 451 | |
| 452 | static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) |
| 453 | { |
| 454 | ((Supc *)hw)->INTENSET.reg = data; |
| 455 | ((Supc *)hw)->INTENCLR.reg = ~data; |
| 456 | } |
| 457 | |
| 458 | static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) |
| 459 | { |
| 460 | ((Supc *)hw)->INTENCLR.reg = mask; |
| 461 | } |
| 462 | |
| 463 | static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) |
| 464 | { |
| 465 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; |
| 466 | } |
| 467 | |
| 468 | static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) |
| 469 | { |
| 470 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; |
| 471 | } |
| 472 | |
| 473 | static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) |
| 474 | { |
| 475 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; |
| 476 | } |
| 477 | |
| 478 | static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) |
| 479 | { |
| 480 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; |
| 481 | } |
| 482 | |
| 483 | static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) |
| 484 | { |
| 485 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; |
| 486 | } |
| 487 | |
| 488 | static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) |
| 489 | { |
| 490 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; |
| 491 | } |
| 492 | |
| 493 | static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) |
| 494 | { |
| 495 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; |
| 496 | } |
| 497 | |
| 498 | static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) |
| 499 | { |
| 500 | return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; |
| 501 | } |
| 502 | |
| 503 | static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) |
| 504 | { |
| 505 | uint32_t tmp; |
| 506 | tmp = ((Supc *)hw)->STATUS.reg; |
| 507 | tmp &= mask; |
| 508 | return tmp; |
| 509 | } |
| 510 | |
| 511 | static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) |
| 512 | { |
| 513 | return ((Supc *)hw)->STATUS.reg; |
| 514 | } |
| 515 | |
| 516 | static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) |
| 517 | { |
| 518 | return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; |
| 519 | } |
| 520 | |
| 521 | static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) |
| 522 | { |
| 523 | return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; |
| 524 | } |
| 525 | |
| 526 | static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) |
| 527 | { |
| 528 | uint32_t tmp; |
| 529 | tmp = ((Supc *)hw)->BKIN.reg; |
| 530 | tmp &= mask; |
| 531 | return tmp; |
| 532 | } |
| 533 | |
| 534 | static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) |
| 535 | { |
| 536 | return ((Supc *)hw)->BKIN.reg; |
| 537 | } |
| 538 | |
| 539 | static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) |
| 540 | { |
| 541 | SUPC_CRITICAL_SECTION_ENTER(); |
| 542 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; |
| 543 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 544 | } |
| 545 | |
| 546 | static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) |
| 547 | { |
| 548 | uint32_t tmp; |
| 549 | tmp = ((Supc *)hw)->BOD33.reg; |
| 550 | tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; |
| 551 | return (bool)tmp; |
| 552 | } |
| 553 | |
| 554 | static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) |
| 555 | { |
| 556 | uint32_t tmp; |
| 557 | SUPC_CRITICAL_SECTION_ENTER(); |
| 558 | tmp = ((Supc *)hw)->BOD33.reg; |
| 559 | tmp &= ~SUPC_BOD33_ENABLE; |
| 560 | tmp |= value << SUPC_BOD33_ENABLE_Pos; |
| 561 | ((Supc *)hw)->BOD33.reg = tmp; |
| 562 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 563 | } |
| 564 | |
| 565 | static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) |
| 566 | { |
| 567 | SUPC_CRITICAL_SECTION_ENTER(); |
| 568 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; |
| 569 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 570 | } |
| 571 | |
| 572 | static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) |
| 573 | { |
| 574 | SUPC_CRITICAL_SECTION_ENTER(); |
| 575 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; |
| 576 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 577 | } |
| 578 | |
| 579 | static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) |
| 580 | { |
| 581 | SUPC_CRITICAL_SECTION_ENTER(); |
| 582 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; |
| 583 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 584 | } |
| 585 | |
| 586 | static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) |
| 587 | { |
| 588 | uint32_t tmp; |
| 589 | tmp = ((Supc *)hw)->BOD33.reg; |
| 590 | tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; |
| 591 | return (bool)tmp; |
| 592 | } |
| 593 | |
| 594 | static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) |
| 595 | { |
| 596 | uint32_t tmp; |
| 597 | SUPC_CRITICAL_SECTION_ENTER(); |
| 598 | tmp = ((Supc *)hw)->BOD33.reg; |
| 599 | tmp &= ~SUPC_BOD33_STDBYCFG; |
| 600 | tmp |= value << SUPC_BOD33_STDBYCFG_Pos; |
| 601 | ((Supc *)hw)->BOD33.reg = tmp; |
| 602 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 603 | } |
| 604 | |
| 605 | static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) |
| 606 | { |
| 607 | SUPC_CRITICAL_SECTION_ENTER(); |
| 608 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; |
| 609 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 610 | } |
| 611 | |
| 612 | static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) |
| 613 | { |
| 614 | SUPC_CRITICAL_SECTION_ENTER(); |
| 615 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; |
| 616 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 617 | } |
| 618 | |
| 619 | static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) |
| 620 | { |
| 621 | SUPC_CRITICAL_SECTION_ENTER(); |
| 622 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; |
| 623 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 624 | } |
| 625 | |
| 626 | static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) |
| 627 | { |
| 628 | uint32_t tmp; |
| 629 | tmp = ((Supc *)hw)->BOD33.reg; |
| 630 | tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; |
| 631 | return (bool)tmp; |
| 632 | } |
| 633 | |
| 634 | static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) |
| 635 | { |
| 636 | uint32_t tmp; |
| 637 | SUPC_CRITICAL_SECTION_ENTER(); |
| 638 | tmp = ((Supc *)hw)->BOD33.reg; |
| 639 | tmp &= ~SUPC_BOD33_RUNSTDBY; |
| 640 | tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; |
| 641 | ((Supc *)hw)->BOD33.reg = tmp; |
| 642 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 643 | } |
| 644 | |
| 645 | static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) |
| 646 | { |
| 647 | SUPC_CRITICAL_SECTION_ENTER(); |
| 648 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; |
| 649 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 650 | } |
| 651 | |
| 652 | static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) |
| 653 | { |
| 654 | SUPC_CRITICAL_SECTION_ENTER(); |
| 655 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; |
| 656 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 657 | } |
| 658 | |
| 659 | static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) |
| 660 | { |
| 661 | SUPC_CRITICAL_SECTION_ENTER(); |
| 662 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; |
| 663 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 664 | } |
| 665 | |
| 666 | static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) |
| 667 | { |
| 668 | uint32_t tmp; |
| 669 | tmp = ((Supc *)hw)->BOD33.reg; |
| 670 | tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; |
| 671 | return (bool)tmp; |
| 672 | } |
| 673 | |
| 674 | static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) |
| 675 | { |
| 676 | uint32_t tmp; |
| 677 | SUPC_CRITICAL_SECTION_ENTER(); |
| 678 | tmp = ((Supc *)hw)->BOD33.reg; |
| 679 | tmp &= ~SUPC_BOD33_RUNHIB; |
| 680 | tmp |= value << SUPC_BOD33_RUNHIB_Pos; |
| 681 | ((Supc *)hw)->BOD33.reg = tmp; |
| 682 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 683 | } |
| 684 | |
| 685 | static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) |
| 686 | { |
| 687 | SUPC_CRITICAL_SECTION_ENTER(); |
| 688 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; |
| 689 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 690 | } |
| 691 | |
| 692 | static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) |
| 693 | { |
| 694 | SUPC_CRITICAL_SECTION_ENTER(); |
| 695 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; |
| 696 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 697 | } |
| 698 | |
| 699 | static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) |
| 700 | { |
| 701 | SUPC_CRITICAL_SECTION_ENTER(); |
| 702 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; |
| 703 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 704 | } |
| 705 | |
| 706 | static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) |
| 707 | { |
| 708 | uint32_t tmp; |
| 709 | tmp = ((Supc *)hw)->BOD33.reg; |
| 710 | tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; |
| 711 | return (bool)tmp; |
| 712 | } |
| 713 | |
| 714 | static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) |
| 715 | { |
| 716 | uint32_t tmp; |
| 717 | SUPC_CRITICAL_SECTION_ENTER(); |
| 718 | tmp = ((Supc *)hw)->BOD33.reg; |
| 719 | tmp &= ~SUPC_BOD33_RUNBKUP; |
| 720 | tmp |= value << SUPC_BOD33_RUNBKUP_Pos; |
| 721 | ((Supc *)hw)->BOD33.reg = tmp; |
| 722 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 723 | } |
| 724 | |
| 725 | static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) |
| 726 | { |
| 727 | SUPC_CRITICAL_SECTION_ENTER(); |
| 728 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; |
| 729 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 730 | } |
| 731 | |
| 732 | static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) |
| 733 | { |
| 734 | SUPC_CRITICAL_SECTION_ENTER(); |
| 735 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; |
| 736 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 737 | } |
| 738 | |
| 739 | static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 740 | { |
| 741 | SUPC_CRITICAL_SECTION_ENTER(); |
| 742 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); |
| 743 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 744 | } |
| 745 | |
| 746 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 747 | { |
| 748 | uint32_t tmp; |
| 749 | tmp = ((Supc *)hw)->BOD33.reg; |
| 750 | tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; |
| 751 | return tmp; |
| 752 | } |
| 753 | |
| 754 | static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 755 | { |
| 756 | uint32_t tmp; |
| 757 | SUPC_CRITICAL_SECTION_ENTER(); |
| 758 | tmp = ((Supc *)hw)->BOD33.reg; |
| 759 | tmp &= ~SUPC_BOD33_ACTION_Msk; |
| 760 | tmp |= SUPC_BOD33_ACTION(data); |
| 761 | ((Supc *)hw)->BOD33.reg = tmp; |
| 762 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 763 | } |
| 764 | |
| 765 | static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 766 | { |
| 767 | SUPC_CRITICAL_SECTION_ENTER(); |
| 768 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); |
| 769 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 770 | } |
| 771 | |
| 772 | static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 773 | { |
| 774 | SUPC_CRITICAL_SECTION_ENTER(); |
| 775 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); |
| 776 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 777 | } |
| 778 | |
| 779 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) |
| 780 | { |
| 781 | uint32_t tmp; |
| 782 | tmp = ((Supc *)hw)->BOD33.reg; |
| 783 | tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; |
| 784 | return tmp; |
| 785 | } |
| 786 | |
| 787 | static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 788 | { |
| 789 | SUPC_CRITICAL_SECTION_ENTER(); |
| 790 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); |
| 791 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 792 | } |
| 793 | |
| 794 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 795 | { |
| 796 | uint32_t tmp; |
| 797 | tmp = ((Supc *)hw)->BOD33.reg; |
| 798 | tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; |
| 799 | return tmp; |
| 800 | } |
| 801 | |
| 802 | static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 803 | { |
| 804 | uint32_t tmp; |
| 805 | SUPC_CRITICAL_SECTION_ENTER(); |
| 806 | tmp = ((Supc *)hw)->BOD33.reg; |
| 807 | tmp &= ~SUPC_BOD33_HYST_Msk; |
| 808 | tmp |= SUPC_BOD33_HYST(data); |
| 809 | ((Supc *)hw)->BOD33.reg = tmp; |
| 810 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 811 | } |
| 812 | |
| 813 | static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 814 | { |
| 815 | SUPC_CRITICAL_SECTION_ENTER(); |
| 816 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); |
| 817 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 818 | } |
| 819 | |
| 820 | static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 821 | { |
| 822 | SUPC_CRITICAL_SECTION_ENTER(); |
| 823 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); |
| 824 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 825 | } |
| 826 | |
| 827 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) |
| 828 | { |
| 829 | uint32_t tmp; |
| 830 | tmp = ((Supc *)hw)->BOD33.reg; |
| 831 | tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; |
| 832 | return tmp; |
| 833 | } |
| 834 | |
| 835 | static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 836 | { |
| 837 | SUPC_CRITICAL_SECTION_ENTER(); |
| 838 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); |
| 839 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 840 | } |
| 841 | |
| 842 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 843 | { |
| 844 | uint32_t tmp; |
| 845 | tmp = ((Supc *)hw)->BOD33.reg; |
| 846 | tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; |
| 847 | return tmp; |
| 848 | } |
| 849 | |
| 850 | static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 851 | { |
| 852 | uint32_t tmp; |
| 853 | SUPC_CRITICAL_SECTION_ENTER(); |
| 854 | tmp = ((Supc *)hw)->BOD33.reg; |
| 855 | tmp &= ~SUPC_BOD33_PSEL_Msk; |
| 856 | tmp |= SUPC_BOD33_PSEL(data); |
| 857 | ((Supc *)hw)->BOD33.reg = tmp; |
| 858 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 859 | } |
| 860 | |
| 861 | static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 862 | { |
| 863 | SUPC_CRITICAL_SECTION_ENTER(); |
| 864 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); |
| 865 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 866 | } |
| 867 | |
| 868 | static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 869 | { |
| 870 | SUPC_CRITICAL_SECTION_ENTER(); |
| 871 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); |
| 872 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 873 | } |
| 874 | |
| 875 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) |
| 876 | { |
| 877 | uint32_t tmp; |
| 878 | tmp = ((Supc *)hw)->BOD33.reg; |
| 879 | tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; |
| 880 | return tmp; |
| 881 | } |
| 882 | |
| 883 | static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 884 | { |
| 885 | SUPC_CRITICAL_SECTION_ENTER(); |
| 886 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); |
| 887 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 888 | } |
| 889 | |
| 890 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 891 | { |
| 892 | uint32_t tmp; |
| 893 | tmp = ((Supc *)hw)->BOD33.reg; |
| 894 | tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; |
| 895 | return tmp; |
| 896 | } |
| 897 | |
| 898 | static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 899 | { |
| 900 | uint32_t tmp; |
| 901 | SUPC_CRITICAL_SECTION_ENTER(); |
| 902 | tmp = ((Supc *)hw)->BOD33.reg; |
| 903 | tmp &= ~SUPC_BOD33_LEVEL_Msk; |
| 904 | tmp |= SUPC_BOD33_LEVEL(data); |
| 905 | ((Supc *)hw)->BOD33.reg = tmp; |
| 906 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 907 | } |
| 908 | |
| 909 | static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 910 | { |
| 911 | SUPC_CRITICAL_SECTION_ENTER(); |
| 912 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); |
| 913 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 914 | } |
| 915 | |
| 916 | static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 917 | { |
| 918 | SUPC_CRITICAL_SECTION_ENTER(); |
| 919 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); |
| 920 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 921 | } |
| 922 | |
| 923 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) |
| 924 | { |
| 925 | uint32_t tmp; |
| 926 | tmp = ((Supc *)hw)->BOD33.reg; |
| 927 | tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; |
| 928 | return tmp; |
| 929 | } |
| 930 | |
| 931 | static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 932 | { |
| 933 | SUPC_CRITICAL_SECTION_ENTER(); |
| 934 | ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); |
| 935 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 936 | } |
| 937 | |
| 938 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 939 | { |
| 940 | uint32_t tmp; |
| 941 | tmp = ((Supc *)hw)->BOD33.reg; |
| 942 | tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; |
| 943 | return tmp; |
| 944 | } |
| 945 | |
| 946 | static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) |
| 947 | { |
| 948 | uint32_t tmp; |
| 949 | SUPC_CRITICAL_SECTION_ENTER(); |
| 950 | tmp = ((Supc *)hw)->BOD33.reg; |
| 951 | tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; |
| 952 | tmp |= SUPC_BOD33_VBATLEVEL(data); |
| 953 | ((Supc *)hw)->BOD33.reg = tmp; |
| 954 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 955 | } |
| 956 | |
| 957 | static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 958 | { |
| 959 | SUPC_CRITICAL_SECTION_ENTER(); |
| 960 | ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); |
| 961 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 962 | } |
| 963 | |
| 964 | static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) |
| 965 | { |
| 966 | SUPC_CRITICAL_SECTION_ENTER(); |
| 967 | ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); |
| 968 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 969 | } |
| 970 | |
| 971 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) |
| 972 | { |
| 973 | uint32_t tmp; |
| 974 | tmp = ((Supc *)hw)->BOD33.reg; |
| 975 | tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; |
| 976 | return tmp; |
| 977 | } |
| 978 | |
| 979 | static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 980 | { |
| 981 | SUPC_CRITICAL_SECTION_ENTER(); |
| 982 | ((Supc *)hw)->BOD33.reg |= mask; |
| 983 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 984 | } |
| 985 | |
| 986 | static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 987 | { |
| 988 | uint32_t tmp; |
| 989 | tmp = ((Supc *)hw)->BOD33.reg; |
| 990 | tmp &= mask; |
| 991 | return tmp; |
| 992 | } |
| 993 | |
| 994 | static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) |
| 995 | { |
| 996 | SUPC_CRITICAL_SECTION_ENTER(); |
| 997 | ((Supc *)hw)->BOD33.reg = data; |
| 998 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 999 | } |
| 1000 | |
| 1001 | static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 1002 | { |
| 1003 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1004 | ((Supc *)hw)->BOD33.reg &= ~mask; |
| 1005 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1006 | } |
| 1007 | |
| 1008 | static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) |
| 1009 | { |
| 1010 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1011 | ((Supc *)hw)->BOD33.reg ^= mask; |
| 1012 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1013 | } |
| 1014 | |
| 1015 | static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) |
| 1016 | { |
| 1017 | return ((Supc *)hw)->BOD33.reg; |
| 1018 | } |
| 1019 | |
| 1020 | static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) |
| 1021 | { |
| 1022 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1023 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; |
| 1024 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1025 | } |
| 1026 | |
| 1027 | static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) |
| 1028 | { |
| 1029 | uint32_t tmp; |
| 1030 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1031 | tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; |
| 1032 | return (bool)tmp; |
| 1033 | } |
| 1034 | |
| 1035 | static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) |
| 1036 | { |
| 1037 | uint32_t tmp; |
| 1038 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1039 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1040 | tmp &= ~SUPC_BOD12_ENABLE; |
| 1041 | tmp |= value << SUPC_BOD12_ENABLE_Pos; |
| 1042 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1043 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1044 | } |
| 1045 | |
| 1046 | static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) |
| 1047 | { |
| 1048 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1049 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; |
| 1050 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1051 | } |
| 1052 | |
| 1053 | static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) |
| 1054 | { |
| 1055 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1056 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; |
| 1057 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1058 | } |
| 1059 | |
| 1060 | static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) |
| 1061 | { |
| 1062 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1063 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; |
| 1064 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1065 | } |
| 1066 | |
| 1067 | static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) |
| 1068 | { |
| 1069 | uint32_t tmp; |
| 1070 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1071 | tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; |
| 1072 | return (bool)tmp; |
| 1073 | } |
| 1074 | |
| 1075 | static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) |
| 1076 | { |
| 1077 | uint32_t tmp; |
| 1078 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1079 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1080 | tmp &= ~SUPC_BOD12_HYST; |
| 1081 | tmp |= value << SUPC_BOD12_HYST_Pos; |
| 1082 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1083 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1084 | } |
| 1085 | |
| 1086 | static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) |
| 1087 | { |
| 1088 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1089 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; |
| 1090 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1091 | } |
| 1092 | |
| 1093 | static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) |
| 1094 | { |
| 1095 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1096 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; |
| 1097 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1098 | } |
| 1099 | |
| 1100 | static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) |
| 1101 | { |
| 1102 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1103 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; |
| 1104 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1105 | } |
| 1106 | |
| 1107 | static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) |
| 1108 | { |
| 1109 | uint32_t tmp; |
| 1110 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1111 | tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; |
| 1112 | return (bool)tmp; |
| 1113 | } |
| 1114 | |
| 1115 | static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) |
| 1116 | { |
| 1117 | uint32_t tmp; |
| 1118 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1119 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1120 | tmp &= ~SUPC_BOD12_STDBYCFG; |
| 1121 | tmp |= value << SUPC_BOD12_STDBYCFG_Pos; |
| 1122 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1123 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1124 | } |
| 1125 | |
| 1126 | static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) |
| 1127 | { |
| 1128 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1129 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; |
| 1130 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1131 | } |
| 1132 | |
| 1133 | static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) |
| 1134 | { |
| 1135 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1136 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; |
| 1137 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1138 | } |
| 1139 | |
| 1140 | static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) |
| 1141 | { |
| 1142 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1143 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; |
| 1144 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1145 | } |
| 1146 | |
| 1147 | static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) |
| 1148 | { |
| 1149 | uint32_t tmp; |
| 1150 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1151 | tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; |
| 1152 | return (bool)tmp; |
| 1153 | } |
| 1154 | |
| 1155 | static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) |
| 1156 | { |
| 1157 | uint32_t tmp; |
| 1158 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1159 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1160 | tmp &= ~SUPC_BOD12_RUNSTDBY; |
| 1161 | tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; |
| 1162 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1163 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1164 | } |
| 1165 | |
| 1166 | static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) |
| 1167 | { |
| 1168 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1169 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; |
| 1170 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1171 | } |
| 1172 | |
| 1173 | static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) |
| 1174 | { |
| 1175 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1176 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; |
| 1177 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1178 | } |
| 1179 | |
| 1180 | static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) |
| 1181 | { |
| 1182 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1183 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; |
| 1184 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1185 | } |
| 1186 | |
| 1187 | static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) |
| 1188 | { |
| 1189 | uint32_t tmp; |
| 1190 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1191 | tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; |
| 1192 | return (bool)tmp; |
| 1193 | } |
| 1194 | |
| 1195 | static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) |
| 1196 | { |
| 1197 | uint32_t tmp; |
| 1198 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1199 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1200 | tmp &= ~SUPC_BOD12_ACTCFG; |
| 1201 | tmp |= value << SUPC_BOD12_ACTCFG_Pos; |
| 1202 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1203 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1204 | } |
| 1205 | |
| 1206 | static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) |
| 1207 | { |
| 1208 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1209 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; |
| 1210 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1211 | } |
| 1212 | |
| 1213 | static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) |
| 1214 | { |
| 1215 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1216 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; |
| 1217 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1218 | } |
| 1219 | |
| 1220 | static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1221 | { |
| 1222 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1223 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); |
| 1224 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1225 | } |
| 1226 | |
| 1227 | static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1228 | { |
| 1229 | uint32_t tmp; |
| 1230 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1231 | tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; |
| 1232 | return tmp; |
| 1233 | } |
| 1234 | |
| 1235 | static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) |
| 1236 | { |
| 1237 | uint32_t tmp; |
| 1238 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1239 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1240 | tmp &= ~SUPC_BOD12_ACTION_Msk; |
| 1241 | tmp |= SUPC_BOD12_ACTION(data); |
| 1242 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1243 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1244 | } |
| 1245 | |
| 1246 | static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1247 | { |
| 1248 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1249 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); |
| 1250 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1251 | } |
| 1252 | |
| 1253 | static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1254 | { |
| 1255 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1256 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); |
| 1257 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1258 | } |
| 1259 | |
| 1260 | static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) |
| 1261 | { |
| 1262 | uint32_t tmp; |
| 1263 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1264 | tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; |
| 1265 | return tmp; |
| 1266 | } |
| 1267 | |
| 1268 | static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1269 | { |
| 1270 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1271 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); |
| 1272 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1273 | } |
| 1274 | |
| 1275 | static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1276 | { |
| 1277 | uint32_t tmp; |
| 1278 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1279 | tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; |
| 1280 | return tmp; |
| 1281 | } |
| 1282 | |
| 1283 | static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) |
| 1284 | { |
| 1285 | uint32_t tmp; |
| 1286 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1287 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1288 | tmp &= ~SUPC_BOD12_PSEL_Msk; |
| 1289 | tmp |= SUPC_BOD12_PSEL(data); |
| 1290 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1291 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1292 | } |
| 1293 | |
| 1294 | static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1295 | { |
| 1296 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1297 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); |
| 1298 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1299 | } |
| 1300 | |
| 1301 | static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1302 | { |
| 1303 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1304 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); |
| 1305 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1306 | } |
| 1307 | |
| 1308 | static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) |
| 1309 | { |
| 1310 | uint32_t tmp; |
| 1311 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1312 | tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; |
| 1313 | return tmp; |
| 1314 | } |
| 1315 | |
| 1316 | static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1317 | { |
| 1318 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1319 | ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); |
| 1320 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1321 | } |
| 1322 | |
| 1323 | static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1324 | { |
| 1325 | uint32_t tmp; |
| 1326 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1327 | tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; |
| 1328 | return tmp; |
| 1329 | } |
| 1330 | |
| 1331 | static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) |
| 1332 | { |
| 1333 | uint32_t tmp; |
| 1334 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1335 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1336 | tmp &= ~SUPC_BOD12_LEVEL_Msk; |
| 1337 | tmp |= SUPC_BOD12_LEVEL(data); |
| 1338 | ((Supc *)hw)->BOD12.reg = tmp; |
| 1339 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1340 | } |
| 1341 | |
| 1342 | static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1343 | { |
| 1344 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1345 | ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); |
| 1346 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1347 | } |
| 1348 | |
| 1349 | static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1350 | { |
| 1351 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1352 | ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); |
| 1353 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1354 | } |
| 1355 | |
| 1356 | static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) |
| 1357 | { |
| 1358 | uint32_t tmp; |
| 1359 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1360 | tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; |
| 1361 | return tmp; |
| 1362 | } |
| 1363 | |
| 1364 | static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1365 | { |
| 1366 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1367 | ((Supc *)hw)->BOD12.reg |= mask; |
| 1368 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1369 | } |
| 1370 | |
| 1371 | static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1372 | { |
| 1373 | uint32_t tmp; |
| 1374 | tmp = ((Supc *)hw)->BOD12.reg; |
| 1375 | tmp &= mask; |
| 1376 | return tmp; |
| 1377 | } |
| 1378 | |
| 1379 | static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) |
| 1380 | { |
| 1381 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1382 | ((Supc *)hw)->BOD12.reg = data; |
| 1383 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1384 | } |
| 1385 | |
| 1386 | static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1387 | { |
| 1388 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1389 | ((Supc *)hw)->BOD12.reg &= ~mask; |
| 1390 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1391 | } |
| 1392 | |
| 1393 | static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) |
| 1394 | { |
| 1395 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1396 | ((Supc *)hw)->BOD12.reg ^= mask; |
| 1397 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1398 | } |
| 1399 | |
| 1400 | static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) |
| 1401 | { |
| 1402 | return ((Supc *)hw)->BOD12.reg; |
| 1403 | } |
| 1404 | |
| 1405 | static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) |
| 1406 | { |
| 1407 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1408 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; |
| 1409 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1410 | } |
| 1411 | |
| 1412 | static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) |
| 1413 | { |
| 1414 | uint32_t tmp; |
| 1415 | tmp = ((Supc *)hw)->VREG.reg; |
| 1416 | tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; |
| 1417 | return (bool)tmp; |
| 1418 | } |
| 1419 | |
| 1420 | static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) |
| 1421 | { |
| 1422 | uint32_t tmp; |
| 1423 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1424 | tmp = ((Supc *)hw)->VREG.reg; |
| 1425 | tmp &= ~SUPC_VREG_ENABLE; |
| 1426 | tmp |= value << SUPC_VREG_ENABLE_Pos; |
| 1427 | ((Supc *)hw)->VREG.reg = tmp; |
| 1428 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1429 | } |
| 1430 | |
| 1431 | static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) |
| 1432 | { |
| 1433 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1434 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; |
| 1435 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1436 | } |
| 1437 | |
| 1438 | static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) |
| 1439 | { |
| 1440 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1441 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; |
| 1442 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1443 | } |
| 1444 | |
| 1445 | static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) |
| 1446 | { |
| 1447 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1448 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; |
| 1449 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1450 | } |
| 1451 | |
| 1452 | static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) |
| 1453 | { |
| 1454 | uint32_t tmp; |
| 1455 | tmp = ((Supc *)hw)->VREG.reg; |
| 1456 | tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; |
| 1457 | return (bool)tmp; |
| 1458 | } |
| 1459 | |
| 1460 | static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) |
| 1461 | { |
| 1462 | uint32_t tmp; |
| 1463 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1464 | tmp = ((Supc *)hw)->VREG.reg; |
| 1465 | tmp &= ~SUPC_VREG_SEL; |
| 1466 | tmp |= value << SUPC_VREG_SEL_Pos; |
| 1467 | ((Supc *)hw)->VREG.reg = tmp; |
| 1468 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1469 | } |
| 1470 | |
| 1471 | static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) |
| 1472 | { |
| 1473 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1474 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; |
| 1475 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1476 | } |
| 1477 | |
| 1478 | static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) |
| 1479 | { |
| 1480 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1481 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; |
| 1482 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1483 | } |
| 1484 | |
| 1485 | static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) |
| 1486 | { |
| 1487 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1488 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; |
| 1489 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1490 | } |
| 1491 | |
| 1492 | static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) |
| 1493 | { |
| 1494 | uint32_t tmp; |
| 1495 | tmp = ((Supc *)hw)->VREG.reg; |
| 1496 | tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; |
| 1497 | return (bool)tmp; |
| 1498 | } |
| 1499 | |
| 1500 | static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) |
| 1501 | { |
| 1502 | uint32_t tmp; |
| 1503 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1504 | tmp = ((Supc *)hw)->VREG.reg; |
| 1505 | tmp &= ~SUPC_VREG_RUNBKUP; |
| 1506 | tmp |= value << SUPC_VREG_RUNBKUP_Pos; |
| 1507 | ((Supc *)hw)->VREG.reg = tmp; |
| 1508 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1509 | } |
| 1510 | |
| 1511 | static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) |
| 1512 | { |
| 1513 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1514 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; |
| 1515 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1516 | } |
| 1517 | |
| 1518 | static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) |
| 1519 | { |
| 1520 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1521 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; |
| 1522 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1523 | } |
| 1524 | |
| 1525 | static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) |
| 1526 | { |
| 1527 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1528 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; |
| 1529 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1530 | } |
| 1531 | |
| 1532 | static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) |
| 1533 | { |
| 1534 | uint32_t tmp; |
| 1535 | tmp = ((Supc *)hw)->VREG.reg; |
| 1536 | tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; |
| 1537 | return (bool)tmp; |
| 1538 | } |
| 1539 | |
| 1540 | static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) |
| 1541 | { |
| 1542 | uint32_t tmp; |
| 1543 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1544 | tmp = ((Supc *)hw)->VREG.reg; |
| 1545 | tmp &= ~SUPC_VREG_VSEN; |
| 1546 | tmp |= value << SUPC_VREG_VSEN_Pos; |
| 1547 | ((Supc *)hw)->VREG.reg = tmp; |
| 1548 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1549 | } |
| 1550 | |
| 1551 | static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) |
| 1552 | { |
| 1553 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1554 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; |
| 1555 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1556 | } |
| 1557 | |
| 1558 | static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) |
| 1559 | { |
| 1560 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1561 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; |
| 1562 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1563 | } |
| 1564 | |
| 1565 | static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1566 | { |
| 1567 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1568 | ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); |
| 1569 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1570 | } |
| 1571 | |
| 1572 | static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1573 | { |
| 1574 | uint32_t tmp; |
| 1575 | tmp = ((Supc *)hw)->VREG.reg; |
| 1576 | tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; |
| 1577 | return tmp; |
| 1578 | } |
| 1579 | |
| 1580 | static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) |
| 1581 | { |
| 1582 | uint32_t tmp; |
| 1583 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1584 | tmp = ((Supc *)hw)->VREG.reg; |
| 1585 | tmp &= ~SUPC_VREG_VSPER_Msk; |
| 1586 | tmp |= SUPC_VREG_VSPER(data); |
| 1587 | ((Supc *)hw)->VREG.reg = tmp; |
| 1588 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1589 | } |
| 1590 | |
| 1591 | static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1592 | { |
| 1593 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1594 | ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); |
| 1595 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1596 | } |
| 1597 | |
| 1598 | static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1599 | { |
| 1600 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1601 | ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); |
| 1602 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1603 | } |
| 1604 | |
| 1605 | static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) |
| 1606 | { |
| 1607 | uint32_t tmp; |
| 1608 | tmp = ((Supc *)hw)->VREG.reg; |
| 1609 | tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; |
| 1610 | return tmp; |
| 1611 | } |
| 1612 | |
| 1613 | static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1614 | { |
| 1615 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1616 | ((Supc *)hw)->VREG.reg |= mask; |
| 1617 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1618 | } |
| 1619 | |
| 1620 | static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1621 | { |
| 1622 | uint32_t tmp; |
| 1623 | tmp = ((Supc *)hw)->VREG.reg; |
| 1624 | tmp &= mask; |
| 1625 | return tmp; |
| 1626 | } |
| 1627 | |
| 1628 | static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) |
| 1629 | { |
| 1630 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1631 | ((Supc *)hw)->VREG.reg = data; |
| 1632 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1633 | } |
| 1634 | |
| 1635 | static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1636 | { |
| 1637 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1638 | ((Supc *)hw)->VREG.reg &= ~mask; |
| 1639 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1640 | } |
| 1641 | |
| 1642 | static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) |
| 1643 | { |
| 1644 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1645 | ((Supc *)hw)->VREG.reg ^= mask; |
| 1646 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1647 | } |
| 1648 | |
| 1649 | static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) |
| 1650 | { |
| 1651 | return ((Supc *)hw)->VREG.reg; |
| 1652 | } |
| 1653 | |
| 1654 | static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) |
| 1655 | { |
| 1656 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1657 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; |
| 1658 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1659 | } |
| 1660 | |
| 1661 | static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) |
| 1662 | { |
| 1663 | uint32_t tmp; |
| 1664 | tmp = ((Supc *)hw)->VREF.reg; |
| 1665 | tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; |
| 1666 | return (bool)tmp; |
| 1667 | } |
| 1668 | |
| 1669 | static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) |
| 1670 | { |
| 1671 | uint32_t tmp; |
| 1672 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1673 | tmp = ((Supc *)hw)->VREF.reg; |
| 1674 | tmp &= ~SUPC_VREF_TSEN; |
| 1675 | tmp |= value << SUPC_VREF_TSEN_Pos; |
| 1676 | ((Supc *)hw)->VREF.reg = tmp; |
| 1677 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1678 | } |
| 1679 | |
| 1680 | static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) |
| 1681 | { |
| 1682 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1683 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; |
| 1684 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1685 | } |
| 1686 | |
| 1687 | static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) |
| 1688 | { |
| 1689 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1690 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; |
| 1691 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1692 | } |
| 1693 | |
| 1694 | static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) |
| 1695 | { |
| 1696 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1697 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; |
| 1698 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1699 | } |
| 1700 | |
| 1701 | static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) |
| 1702 | { |
| 1703 | uint32_t tmp; |
| 1704 | tmp = ((Supc *)hw)->VREF.reg; |
| 1705 | tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; |
| 1706 | return (bool)tmp; |
| 1707 | } |
| 1708 | |
| 1709 | static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) |
| 1710 | { |
| 1711 | uint32_t tmp; |
| 1712 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1713 | tmp = ((Supc *)hw)->VREF.reg; |
| 1714 | tmp &= ~SUPC_VREF_VREFOE; |
| 1715 | tmp |= value << SUPC_VREF_VREFOE_Pos; |
| 1716 | ((Supc *)hw)->VREF.reg = tmp; |
| 1717 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1718 | } |
| 1719 | |
| 1720 | static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) |
| 1721 | { |
| 1722 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1723 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; |
| 1724 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1725 | } |
| 1726 | |
| 1727 | static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) |
| 1728 | { |
| 1729 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1730 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; |
| 1731 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1732 | } |
| 1733 | |
| 1734 | static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) |
| 1735 | { |
| 1736 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1737 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; |
| 1738 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1739 | } |
| 1740 | |
| 1741 | static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) |
| 1742 | { |
| 1743 | uint32_t tmp; |
| 1744 | tmp = ((Supc *)hw)->VREF.reg; |
| 1745 | tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; |
| 1746 | return (bool)tmp; |
| 1747 | } |
| 1748 | |
| 1749 | static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) |
| 1750 | { |
| 1751 | uint32_t tmp; |
| 1752 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1753 | tmp = ((Supc *)hw)->VREF.reg; |
| 1754 | tmp &= ~SUPC_VREF_TSSEL; |
| 1755 | tmp |= value << SUPC_VREF_TSSEL_Pos; |
| 1756 | ((Supc *)hw)->VREF.reg = tmp; |
| 1757 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1758 | } |
| 1759 | |
| 1760 | static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) |
| 1761 | { |
| 1762 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1763 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; |
| 1764 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1765 | } |
| 1766 | |
| 1767 | static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) |
| 1768 | { |
| 1769 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1770 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; |
| 1771 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1772 | } |
| 1773 | |
| 1774 | static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) |
| 1775 | { |
| 1776 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1777 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; |
| 1778 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1779 | } |
| 1780 | |
| 1781 | static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) |
| 1782 | { |
| 1783 | uint32_t tmp; |
| 1784 | tmp = ((Supc *)hw)->VREF.reg; |
| 1785 | tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; |
| 1786 | return (bool)tmp; |
| 1787 | } |
| 1788 | |
| 1789 | static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) |
| 1790 | { |
| 1791 | uint32_t tmp; |
| 1792 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1793 | tmp = ((Supc *)hw)->VREF.reg; |
| 1794 | tmp &= ~SUPC_VREF_RUNSTDBY; |
| 1795 | tmp |= value << SUPC_VREF_RUNSTDBY_Pos; |
| 1796 | ((Supc *)hw)->VREF.reg = tmp; |
| 1797 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1798 | } |
| 1799 | |
| 1800 | static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) |
| 1801 | { |
| 1802 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1803 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; |
| 1804 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1805 | } |
| 1806 | |
| 1807 | static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) |
| 1808 | { |
| 1809 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1810 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; |
| 1811 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1812 | } |
| 1813 | |
| 1814 | static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) |
| 1815 | { |
| 1816 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1817 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; |
| 1818 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1819 | } |
| 1820 | |
| 1821 | static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) |
| 1822 | { |
| 1823 | uint32_t tmp; |
| 1824 | tmp = ((Supc *)hw)->VREF.reg; |
| 1825 | tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; |
| 1826 | return (bool)tmp; |
| 1827 | } |
| 1828 | |
| 1829 | static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) |
| 1830 | { |
| 1831 | uint32_t tmp; |
| 1832 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1833 | tmp = ((Supc *)hw)->VREF.reg; |
| 1834 | tmp &= ~SUPC_VREF_ONDEMAND; |
| 1835 | tmp |= value << SUPC_VREF_ONDEMAND_Pos; |
| 1836 | ((Supc *)hw)->VREF.reg = tmp; |
| 1837 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1838 | } |
| 1839 | |
| 1840 | static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) |
| 1841 | { |
| 1842 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1843 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; |
| 1844 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1845 | } |
| 1846 | |
| 1847 | static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) |
| 1848 | { |
| 1849 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1850 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; |
| 1851 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1852 | } |
| 1853 | |
| 1854 | static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1855 | { |
| 1856 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1857 | ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); |
| 1858 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1859 | } |
| 1860 | |
| 1861 | static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1862 | { |
| 1863 | uint32_t tmp; |
| 1864 | tmp = ((Supc *)hw)->VREF.reg; |
| 1865 | tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; |
| 1866 | return tmp; |
| 1867 | } |
| 1868 | |
| 1869 | static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) |
| 1870 | { |
| 1871 | uint32_t tmp; |
| 1872 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1873 | tmp = ((Supc *)hw)->VREF.reg; |
| 1874 | tmp &= ~SUPC_VREF_SEL_Msk; |
| 1875 | tmp |= SUPC_VREF_SEL(data); |
| 1876 | ((Supc *)hw)->VREF.reg = tmp; |
| 1877 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1878 | } |
| 1879 | |
| 1880 | static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1881 | { |
| 1882 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1883 | ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); |
| 1884 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1885 | } |
| 1886 | |
| 1887 | static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) |
| 1888 | { |
| 1889 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1890 | ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); |
| 1891 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1892 | } |
| 1893 | |
| 1894 | static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) |
| 1895 | { |
| 1896 | uint32_t tmp; |
| 1897 | tmp = ((Supc *)hw)->VREF.reg; |
| 1898 | tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; |
| 1899 | return tmp; |
| 1900 | } |
| 1901 | |
| 1902 | static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1903 | { |
| 1904 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1905 | ((Supc *)hw)->VREF.reg |= mask; |
| 1906 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1907 | } |
| 1908 | |
| 1909 | static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1910 | { |
| 1911 | uint32_t tmp; |
| 1912 | tmp = ((Supc *)hw)->VREF.reg; |
| 1913 | tmp &= mask; |
| 1914 | return tmp; |
| 1915 | } |
| 1916 | |
| 1917 | static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) |
| 1918 | { |
| 1919 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1920 | ((Supc *)hw)->VREF.reg = data; |
| 1921 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1922 | } |
| 1923 | |
| 1924 | static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1925 | { |
| 1926 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1927 | ((Supc *)hw)->VREF.reg &= ~mask; |
| 1928 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1929 | } |
| 1930 | |
| 1931 | static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) |
| 1932 | { |
| 1933 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1934 | ((Supc *)hw)->VREF.reg ^= mask; |
| 1935 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1936 | } |
| 1937 | |
| 1938 | static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) |
| 1939 | { |
| 1940 | return ((Supc *)hw)->VREF.reg; |
| 1941 | } |
| 1942 | |
| 1943 | static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) |
| 1944 | { |
| 1945 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1946 | ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; |
| 1947 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1948 | } |
| 1949 | |
| 1950 | static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) |
| 1951 | { |
| 1952 | uint32_t tmp; |
| 1953 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1954 | tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; |
| 1955 | return (bool)tmp; |
| 1956 | } |
| 1957 | |
| 1958 | static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) |
| 1959 | { |
| 1960 | uint32_t tmp; |
| 1961 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1962 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1963 | tmp &= ~SUPC_BBPS_CONF; |
| 1964 | tmp |= value << SUPC_BBPS_CONF_Pos; |
| 1965 | ((Supc *)hw)->BBPS.reg = tmp; |
| 1966 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1967 | } |
| 1968 | |
| 1969 | static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) |
| 1970 | { |
| 1971 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1972 | ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; |
| 1973 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1974 | } |
| 1975 | |
| 1976 | static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) |
| 1977 | { |
| 1978 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1979 | ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; |
| 1980 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1981 | } |
| 1982 | |
| 1983 | static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) |
| 1984 | { |
| 1985 | SUPC_CRITICAL_SECTION_ENTER(); |
| 1986 | ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; |
| 1987 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 1988 | } |
| 1989 | |
| 1990 | static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) |
| 1991 | { |
| 1992 | uint32_t tmp; |
| 1993 | tmp = ((Supc *)hw)->BBPS.reg; |
| 1994 | tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; |
| 1995 | return (bool)tmp; |
| 1996 | } |
| 1997 | |
| 1998 | static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) |
| 1999 | { |
| 2000 | uint32_t tmp; |
| 2001 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2002 | tmp = ((Supc *)hw)->BBPS.reg; |
| 2003 | tmp &= ~SUPC_BBPS_WAKEEN; |
| 2004 | tmp |= value << SUPC_BBPS_WAKEEN_Pos; |
| 2005 | ((Supc *)hw)->BBPS.reg = tmp; |
| 2006 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2007 | } |
| 2008 | |
| 2009 | static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) |
| 2010 | { |
| 2011 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2012 | ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; |
| 2013 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2014 | } |
| 2015 | |
| 2016 | static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) |
| 2017 | { |
| 2018 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2019 | ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; |
| 2020 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2021 | } |
| 2022 | |
| 2023 | static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 2024 | { |
| 2025 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2026 | ((Supc *)hw)->BBPS.reg |= mask; |
| 2027 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2028 | } |
| 2029 | |
| 2030 | static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 2031 | { |
| 2032 | uint32_t tmp; |
| 2033 | tmp = ((Supc *)hw)->BBPS.reg; |
| 2034 | tmp &= mask; |
| 2035 | return tmp; |
| 2036 | } |
| 2037 | |
| 2038 | static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) |
| 2039 | { |
| 2040 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2041 | ((Supc *)hw)->BBPS.reg = data; |
| 2042 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2043 | } |
| 2044 | |
| 2045 | static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 2046 | { |
| 2047 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2048 | ((Supc *)hw)->BBPS.reg &= ~mask; |
| 2049 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2050 | } |
| 2051 | |
| 2052 | static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) |
| 2053 | { |
| 2054 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2055 | ((Supc *)hw)->BBPS.reg ^= mask; |
| 2056 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2057 | } |
| 2058 | |
| 2059 | static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) |
| 2060 | { |
| 2061 | return ((Supc *)hw)->BBPS.reg; |
| 2062 | } |
| 2063 | |
| 2064 | static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2065 | { |
| 2066 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2067 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); |
| 2068 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2069 | } |
| 2070 | |
| 2071 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2072 | { |
| 2073 | uint32_t tmp; |
| 2074 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2075 | tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; |
| 2076 | return tmp; |
| 2077 | } |
| 2078 | |
| 2079 | static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 2080 | { |
| 2081 | uint32_t tmp; |
| 2082 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2083 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2084 | tmp &= ~SUPC_BKOUT_EN_Msk; |
| 2085 | tmp |= SUPC_BKOUT_EN(data); |
| 2086 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 2087 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2088 | } |
| 2089 | |
| 2090 | static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2091 | { |
| 2092 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2093 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); |
| 2094 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2095 | } |
| 2096 | |
| 2097 | static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2098 | { |
| 2099 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2100 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); |
| 2101 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2102 | } |
| 2103 | |
| 2104 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) |
| 2105 | { |
| 2106 | uint32_t tmp; |
| 2107 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2108 | tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; |
| 2109 | return tmp; |
| 2110 | } |
| 2111 | |
| 2112 | static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2113 | { |
| 2114 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2115 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); |
| 2116 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2117 | } |
| 2118 | |
| 2119 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2120 | { |
| 2121 | uint32_t tmp; |
| 2122 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2123 | tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; |
| 2124 | return tmp; |
| 2125 | } |
| 2126 | |
| 2127 | static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 2128 | { |
| 2129 | uint32_t tmp; |
| 2130 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2131 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2132 | tmp &= ~SUPC_BKOUT_CLR_Msk; |
| 2133 | tmp |= SUPC_BKOUT_CLR(data); |
| 2134 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 2135 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2136 | } |
| 2137 | |
| 2138 | static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2139 | { |
| 2140 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2141 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); |
| 2142 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2143 | } |
| 2144 | |
| 2145 | static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2146 | { |
| 2147 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2148 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); |
| 2149 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2150 | } |
| 2151 | |
| 2152 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) |
| 2153 | { |
| 2154 | uint32_t tmp; |
| 2155 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2156 | tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; |
| 2157 | return tmp; |
| 2158 | } |
| 2159 | |
| 2160 | static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2161 | { |
| 2162 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2163 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); |
| 2164 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2165 | } |
| 2166 | |
| 2167 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2168 | { |
| 2169 | uint32_t tmp; |
| 2170 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2171 | tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; |
| 2172 | return tmp; |
| 2173 | } |
| 2174 | |
| 2175 | static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 2176 | { |
| 2177 | uint32_t tmp; |
| 2178 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2179 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2180 | tmp &= ~SUPC_BKOUT_SET_Msk; |
| 2181 | tmp |= SUPC_BKOUT_SET(data); |
| 2182 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 2183 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2184 | } |
| 2185 | |
| 2186 | static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2187 | { |
| 2188 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2189 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); |
| 2190 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2191 | } |
| 2192 | |
| 2193 | static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2194 | { |
| 2195 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2196 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); |
| 2197 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2198 | } |
| 2199 | |
| 2200 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) |
| 2201 | { |
| 2202 | uint32_t tmp; |
| 2203 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2204 | tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; |
| 2205 | return tmp; |
| 2206 | } |
| 2207 | |
| 2208 | static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2209 | { |
| 2210 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2211 | ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); |
| 2212 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2213 | } |
| 2214 | |
| 2215 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2216 | { |
| 2217 | uint32_t tmp; |
| 2218 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2219 | tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; |
| 2220 | return tmp; |
| 2221 | } |
| 2222 | |
| 2223 | static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) |
| 2224 | { |
| 2225 | uint32_t tmp; |
| 2226 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2227 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2228 | tmp &= ~SUPC_BKOUT_RTCTGL_Msk; |
| 2229 | tmp |= SUPC_BKOUT_RTCTGL(data); |
| 2230 | ((Supc *)hw)->BKOUT.reg = tmp; |
| 2231 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2232 | } |
| 2233 | |
| 2234 | static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2235 | { |
| 2236 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2237 | ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); |
| 2238 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2239 | } |
| 2240 | |
| 2241 | static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2242 | { |
| 2243 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2244 | ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); |
| 2245 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2246 | } |
| 2247 | |
| 2248 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) |
| 2249 | { |
| 2250 | uint32_t tmp; |
| 2251 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2252 | tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; |
| 2253 | return tmp; |
| 2254 | } |
| 2255 | |
| 2256 | static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2257 | { |
| 2258 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2259 | ((Supc *)hw)->BKOUT.reg |= mask; |
| 2260 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2261 | } |
| 2262 | |
| 2263 | static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2264 | { |
| 2265 | uint32_t tmp; |
| 2266 | tmp = ((Supc *)hw)->BKOUT.reg; |
| 2267 | tmp &= mask; |
| 2268 | return tmp; |
| 2269 | } |
| 2270 | |
| 2271 | static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) |
| 2272 | { |
| 2273 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2274 | ((Supc *)hw)->BKOUT.reg = data; |
| 2275 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2276 | } |
| 2277 | |
| 2278 | static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2279 | { |
| 2280 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2281 | ((Supc *)hw)->BKOUT.reg &= ~mask; |
| 2282 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2283 | } |
| 2284 | |
| 2285 | static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) |
| 2286 | { |
| 2287 | SUPC_CRITICAL_SECTION_ENTER(); |
| 2288 | ((Supc *)hw)->BKOUT.reg ^= mask; |
| 2289 | SUPC_CRITICAL_SECTION_LEAVE(); |
| 2290 | } |
| 2291 | |
| 2292 | static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) |
| 2293 | { |
| 2294 | return ((Supc *)hw)->BKOUT.reg; |
| 2295 | } |
| 2296 | |
| 2297 | #ifdef __cplusplus |
| 2298 | } |
| 2299 | #endif |
| 2300 | |
| 2301 | #endif /* _HRI_SUPC_E54_H_INCLUDED */ |
| 2302 | #endif /* _SAME54_SUPC_COMPONENT_ */ |