Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM PDEC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_PDEC_COMPONENT_ |
| 35 | #ifndef _HRI_PDEC_E54_H_INCLUDED_ |
| 36 | #define _HRI_PDEC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_PDEC_CRITICAL_SECTIONS) |
| 46 | #define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define PDEC_CRITICAL_SECTION_ENTER() |
| 50 | #define PDEC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_pdec_evctrl_reg_t; |
| 54 | typedef uint16_t hri_pdec_status_reg_t; |
| 55 | typedef uint32_t hri_pdec_cc_reg_t; |
| 56 | typedef uint32_t hri_pdec_ccbuf_reg_t; |
| 57 | typedef uint32_t hri_pdec_count_reg_t; |
| 58 | typedef uint32_t hri_pdec_ctrla_reg_t; |
| 59 | typedef uint32_t hri_pdec_syncbusy_reg_t; |
| 60 | typedef uint8_t hri_pdec_ctrlbset_reg_t; |
| 61 | typedef uint8_t hri_pdec_dbgctrl_reg_t; |
| 62 | typedef uint8_t hri_pdec_filter_reg_t; |
| 63 | typedef uint8_t hri_pdec_filterbuf_reg_t; |
| 64 | typedef uint8_t hri_pdec_intenset_reg_t; |
| 65 | typedef uint8_t hri_pdec_intflag_reg_t; |
| 66 | typedef uint8_t hri_pdec_presc_reg_t; |
| 67 | typedef uint8_t hri_pdec_prescbuf_reg_t; |
| 68 | |
| 69 | static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) |
| 70 | { |
| 71 | while (((Pdec *)hw)->SYNCBUSY.reg & reg) { |
| 72 | }; |
| 73 | } |
| 74 | |
| 75 | static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) |
| 76 | { |
| 77 | return ((Pdec *)hw)->SYNCBUSY.reg & reg; |
| 78 | } |
| 79 | |
| 80 | static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) |
| 81 | { |
| 82 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; |
| 83 | } |
| 84 | |
| 85 | static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) |
| 86 | { |
| 87 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; |
| 88 | } |
| 89 | |
| 90 | static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) |
| 91 | { |
| 92 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; |
| 93 | } |
| 94 | |
| 95 | static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) |
| 96 | { |
| 97 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; |
| 98 | } |
| 99 | |
| 100 | static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) |
| 101 | { |
| 102 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; |
| 103 | } |
| 104 | |
| 105 | static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) |
| 106 | { |
| 107 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; |
| 108 | } |
| 109 | |
| 110 | static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) |
| 111 | { |
| 112 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; |
| 113 | } |
| 114 | |
| 115 | static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) |
| 116 | { |
| 117 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; |
| 118 | } |
| 119 | |
| 120 | static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) |
| 121 | { |
| 122 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; |
| 123 | } |
| 124 | |
| 125 | static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) |
| 126 | { |
| 127 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; |
| 128 | } |
| 129 | |
| 130 | static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) |
| 131 | { |
| 132 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; |
| 133 | } |
| 134 | |
| 135 | static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) |
| 136 | { |
| 137 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; |
| 138 | } |
| 139 | |
| 140 | static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) |
| 141 | { |
| 142 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; |
| 143 | } |
| 144 | |
| 145 | static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) |
| 146 | { |
| 147 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; |
| 148 | } |
| 149 | |
| 150 | static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) |
| 151 | { |
| 152 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; |
| 153 | } |
| 154 | |
| 155 | static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) |
| 156 | { |
| 157 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; |
| 158 | } |
| 159 | |
| 160 | static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) |
| 161 | { |
| 162 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; |
| 163 | } |
| 164 | |
| 165 | static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) |
| 166 | { |
| 167 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; |
| 168 | } |
| 169 | |
| 170 | static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) |
| 171 | { |
| 172 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; |
| 173 | } |
| 174 | |
| 175 | static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) |
| 176 | { |
| 177 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; |
| 178 | } |
| 179 | |
| 180 | static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) |
| 181 | { |
| 182 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; |
| 183 | } |
| 184 | |
| 185 | static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) |
| 186 | { |
| 187 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; |
| 188 | } |
| 189 | |
| 190 | static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) |
| 191 | { |
| 192 | return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; |
| 193 | } |
| 194 | |
| 195 | static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) |
| 196 | { |
| 197 | ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; |
| 198 | } |
| 199 | |
| 200 | static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) |
| 201 | { |
| 202 | uint8_t tmp; |
| 203 | tmp = ((Pdec *)hw)->INTFLAG.reg; |
| 204 | tmp &= mask; |
| 205 | return tmp; |
| 206 | } |
| 207 | |
| 208 | static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) |
| 209 | { |
| 210 | return ((Pdec *)hw)->INTFLAG.reg; |
| 211 | } |
| 212 | |
| 213 | static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) |
| 214 | { |
| 215 | ((Pdec *)hw)->INTFLAG.reg = mask; |
| 216 | } |
| 217 | |
| 218 | static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) |
| 219 | { |
| 220 | ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; |
| 221 | } |
| 222 | |
| 223 | static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) |
| 224 | { |
| 225 | return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; |
| 226 | } |
| 227 | |
| 228 | static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) |
| 229 | { |
| 230 | if (value == 0x0) { |
| 231 | ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; |
| 232 | } else { |
| 233 | ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) |
| 238 | { |
| 239 | ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; |
| 240 | } |
| 241 | |
| 242 | static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) |
| 243 | { |
| 244 | ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); |
| 245 | } |
| 246 | |
| 247 | static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) |
| 248 | { |
| 249 | uint8_t tmp; |
| 250 | tmp = ((Pdec *)hw)->CTRLBSET.reg; |
| 251 | tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; |
| 252 | return tmp; |
| 253 | } |
| 254 | |
| 255 | static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) |
| 256 | { |
| 257 | uint8_t tmp; |
| 258 | tmp = ((Pdec *)hw)->CTRLBSET.reg; |
| 259 | tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; |
| 260 | return tmp; |
| 261 | } |
| 262 | |
| 263 | static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) |
| 264 | { |
| 265 | ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); |
| 266 | ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); |
| 267 | } |
| 268 | |
| 269 | static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) |
| 270 | { |
| 271 | ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); |
| 272 | } |
| 273 | |
| 274 | static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) |
| 275 | { |
| 276 | ((Pdec *)hw)->CTRLBSET.reg = mask; |
| 277 | } |
| 278 | |
| 279 | static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) |
| 280 | { |
| 281 | uint8_t tmp; |
| 282 | tmp = ((Pdec *)hw)->CTRLBSET.reg; |
| 283 | tmp &= mask; |
| 284 | return tmp; |
| 285 | } |
| 286 | |
| 287 | static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) |
| 288 | { |
| 289 | return ((Pdec *)hw)->CTRLBSET.reg; |
| 290 | } |
| 291 | |
| 292 | static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) |
| 293 | { |
| 294 | ((Pdec *)hw)->CTRLBSET.reg = data; |
| 295 | ((Pdec *)hw)->CTRLBCLR.reg = ~data; |
| 296 | } |
| 297 | |
| 298 | static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) |
| 299 | { |
| 300 | ((Pdec *)hw)->CTRLBCLR.reg = mask; |
| 301 | } |
| 302 | |
| 303 | static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) |
| 304 | { |
| 305 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; |
| 306 | } |
| 307 | |
| 308 | static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) |
| 309 | { |
| 310 | return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; |
| 311 | } |
| 312 | |
| 313 | static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) |
| 314 | { |
| 315 | if (value == 0x0) { |
| 316 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; |
| 317 | } else { |
| 318 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) |
| 323 | { |
| 324 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; |
| 325 | } |
| 326 | |
| 327 | static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) |
| 328 | { |
| 329 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; |
| 330 | } |
| 331 | |
| 332 | static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) |
| 333 | { |
| 334 | return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; |
| 335 | } |
| 336 | |
| 337 | static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) |
| 338 | { |
| 339 | if (value == 0x0) { |
| 340 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; |
| 341 | } else { |
| 342 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; |
| 343 | } |
| 344 | } |
| 345 | |
| 346 | static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) |
| 347 | { |
| 348 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; |
| 349 | } |
| 350 | |
| 351 | static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) |
| 352 | { |
| 353 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; |
| 354 | } |
| 355 | |
| 356 | static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) |
| 357 | { |
| 358 | return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; |
| 359 | } |
| 360 | |
| 361 | static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) |
| 362 | { |
| 363 | if (value == 0x0) { |
| 364 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; |
| 365 | } else { |
| 366 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) |
| 371 | { |
| 372 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; |
| 373 | } |
| 374 | |
| 375 | static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) |
| 376 | { |
| 377 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; |
| 378 | } |
| 379 | |
| 380 | static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) |
| 381 | { |
| 382 | return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; |
| 383 | } |
| 384 | |
| 385 | static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) |
| 386 | { |
| 387 | if (value == 0x0) { |
| 388 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; |
| 389 | } else { |
| 390 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) |
| 395 | { |
| 396 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; |
| 397 | } |
| 398 | |
| 399 | static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) |
| 400 | { |
| 401 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; |
| 402 | } |
| 403 | |
| 404 | static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) |
| 405 | { |
| 406 | return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; |
| 407 | } |
| 408 | |
| 409 | static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) |
| 410 | { |
| 411 | if (value == 0x0) { |
| 412 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; |
| 413 | } else { |
| 414 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) |
| 419 | { |
| 420 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; |
| 421 | } |
| 422 | |
| 423 | static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) |
| 424 | { |
| 425 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; |
| 426 | } |
| 427 | |
| 428 | static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) |
| 429 | { |
| 430 | return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; |
| 431 | } |
| 432 | |
| 433 | static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) |
| 434 | { |
| 435 | if (value == 0x0) { |
| 436 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; |
| 437 | } else { |
| 438 | ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; |
| 439 | } |
| 440 | } |
| 441 | |
| 442 | static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) |
| 443 | { |
| 444 | ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; |
| 445 | } |
| 446 | |
| 447 | static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) |
| 448 | { |
| 449 | ((Pdec *)hw)->INTENSET.reg = mask; |
| 450 | } |
| 451 | |
| 452 | static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) |
| 453 | { |
| 454 | uint8_t tmp; |
| 455 | tmp = ((Pdec *)hw)->INTENSET.reg; |
| 456 | tmp &= mask; |
| 457 | return tmp; |
| 458 | } |
| 459 | |
| 460 | static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) |
| 461 | { |
| 462 | return ((Pdec *)hw)->INTENSET.reg; |
| 463 | } |
| 464 | |
| 465 | static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) |
| 466 | { |
| 467 | ((Pdec *)hw)->INTENSET.reg = data; |
| 468 | ((Pdec *)hw)->INTENCLR.reg = ~data; |
| 469 | } |
| 470 | |
| 471 | static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) |
| 472 | { |
| 473 | ((Pdec *)hw)->INTENCLR.reg = mask; |
| 474 | } |
| 475 | |
| 476 | static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 477 | { |
| 478 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; |
| 479 | } |
| 480 | |
| 481 | static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 482 | { |
| 483 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; |
| 484 | } |
| 485 | |
| 486 | static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) |
| 487 | { |
| 488 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; |
| 489 | } |
| 490 | |
| 491 | static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) |
| 492 | { |
| 493 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; |
| 494 | } |
| 495 | |
| 496 | static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) |
| 497 | { |
| 498 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; |
| 499 | } |
| 500 | |
| 501 | static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) |
| 502 | { |
| 503 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; |
| 504 | } |
| 505 | |
| 506 | static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) |
| 507 | { |
| 508 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; |
| 509 | } |
| 510 | |
| 511 | static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) |
| 512 | { |
| 513 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; |
| 514 | } |
| 515 | |
| 516 | static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) |
| 517 | { |
| 518 | return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; |
| 519 | } |
| 520 | |
| 521 | static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) |
| 522 | { |
| 523 | uint32_t tmp; |
| 524 | tmp = ((Pdec *)hw)->SYNCBUSY.reg; |
| 525 | tmp &= mask; |
| 526 | return tmp; |
| 527 | } |
| 528 | |
| 529 | static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) |
| 530 | { |
| 531 | return ((Pdec *)hw)->SYNCBUSY.reg; |
| 532 | } |
| 533 | |
| 534 | static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) |
| 535 | { |
| 536 | PDEC_CRITICAL_SECTION_ENTER(); |
| 537 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; |
| 538 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); |
| 539 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 540 | } |
| 541 | |
| 542 | static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) |
| 543 | { |
| 544 | uint32_t tmp; |
| 545 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); |
| 546 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 547 | tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; |
| 548 | return (bool)tmp; |
| 549 | } |
| 550 | |
| 551 | static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) |
| 552 | { |
| 553 | PDEC_CRITICAL_SECTION_ENTER(); |
| 554 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; |
| 555 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 556 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 557 | } |
| 558 | |
| 559 | static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) |
| 560 | { |
| 561 | uint32_t tmp; |
| 562 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 563 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 564 | tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; |
| 565 | return (bool)tmp; |
| 566 | } |
| 567 | |
| 568 | static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 569 | { |
| 570 | uint32_t tmp; |
| 571 | PDEC_CRITICAL_SECTION_ENTER(); |
| 572 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 573 | tmp &= ~PDEC_CTRLA_ENABLE; |
| 574 | tmp |= value << PDEC_CTRLA_ENABLE_Pos; |
| 575 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 576 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 577 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 578 | } |
| 579 | |
| 580 | static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 581 | { |
| 582 | PDEC_CRITICAL_SECTION_ENTER(); |
| 583 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; |
| 584 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 585 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 586 | } |
| 587 | |
| 588 | static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 589 | { |
| 590 | PDEC_CRITICAL_SECTION_ENTER(); |
| 591 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; |
| 592 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 593 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 594 | } |
| 595 | |
| 596 | static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 597 | { |
| 598 | PDEC_CRITICAL_SECTION_ENTER(); |
| 599 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; |
| 600 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 601 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 602 | } |
| 603 | |
| 604 | static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 605 | { |
| 606 | uint32_t tmp; |
| 607 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 608 | tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; |
| 609 | return (bool)tmp; |
| 610 | } |
| 611 | |
| 612 | static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 613 | { |
| 614 | uint32_t tmp; |
| 615 | PDEC_CRITICAL_SECTION_ENTER(); |
| 616 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 617 | tmp &= ~PDEC_CTRLA_RUNSTDBY; |
| 618 | tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; |
| 619 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 620 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 621 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 622 | } |
| 623 | |
| 624 | static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 625 | { |
| 626 | PDEC_CRITICAL_SECTION_ENTER(); |
| 627 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; |
| 628 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 629 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 630 | } |
| 631 | |
| 632 | static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 633 | { |
| 634 | PDEC_CRITICAL_SECTION_ENTER(); |
| 635 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; |
| 636 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 637 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 638 | } |
| 639 | |
| 640 | static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) |
| 641 | { |
| 642 | PDEC_CRITICAL_SECTION_ENTER(); |
| 643 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; |
| 644 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 645 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 646 | } |
| 647 | |
| 648 | static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) |
| 649 | { |
| 650 | uint32_t tmp; |
| 651 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 652 | tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; |
| 653 | return (bool)tmp; |
| 654 | } |
| 655 | |
| 656 | static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) |
| 657 | { |
| 658 | uint32_t tmp; |
| 659 | PDEC_CRITICAL_SECTION_ENTER(); |
| 660 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 661 | tmp &= ~PDEC_CTRLA_ALOCK; |
| 662 | tmp |= value << PDEC_CTRLA_ALOCK_Pos; |
| 663 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 664 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 665 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 666 | } |
| 667 | |
| 668 | static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) |
| 669 | { |
| 670 | PDEC_CRITICAL_SECTION_ENTER(); |
| 671 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; |
| 672 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 673 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 674 | } |
| 675 | |
| 676 | static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) |
| 677 | { |
| 678 | PDEC_CRITICAL_SECTION_ENTER(); |
| 679 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; |
| 680 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 681 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 682 | } |
| 683 | |
| 684 | static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) |
| 685 | { |
| 686 | PDEC_CRITICAL_SECTION_ENTER(); |
| 687 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; |
| 688 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 689 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 690 | } |
| 691 | |
| 692 | static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) |
| 693 | { |
| 694 | uint32_t tmp; |
| 695 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 696 | tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; |
| 697 | return (bool)tmp; |
| 698 | } |
| 699 | |
| 700 | static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) |
| 701 | { |
| 702 | uint32_t tmp; |
| 703 | PDEC_CRITICAL_SECTION_ENTER(); |
| 704 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 705 | tmp &= ~PDEC_CTRLA_SWAP; |
| 706 | tmp |= value << PDEC_CTRLA_SWAP_Pos; |
| 707 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 708 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 709 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 710 | } |
| 711 | |
| 712 | static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) |
| 713 | { |
| 714 | PDEC_CRITICAL_SECTION_ENTER(); |
| 715 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; |
| 716 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 717 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 718 | } |
| 719 | |
| 720 | static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) |
| 721 | { |
| 722 | PDEC_CRITICAL_SECTION_ENTER(); |
| 723 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; |
| 724 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 725 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 726 | } |
| 727 | |
| 728 | static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) |
| 729 | { |
| 730 | PDEC_CRITICAL_SECTION_ENTER(); |
| 731 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; |
| 732 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 733 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 734 | } |
| 735 | |
| 736 | static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) |
| 737 | { |
| 738 | uint32_t tmp; |
| 739 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 740 | tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; |
| 741 | return (bool)tmp; |
| 742 | } |
| 743 | |
| 744 | static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) |
| 745 | { |
| 746 | uint32_t tmp; |
| 747 | PDEC_CRITICAL_SECTION_ENTER(); |
| 748 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 749 | tmp &= ~PDEC_CTRLA_PEREN; |
| 750 | tmp |= value << PDEC_CTRLA_PEREN_Pos; |
| 751 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 752 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 753 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 754 | } |
| 755 | |
| 756 | static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) |
| 757 | { |
| 758 | PDEC_CRITICAL_SECTION_ENTER(); |
| 759 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; |
| 760 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 761 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 762 | } |
| 763 | |
| 764 | static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) |
| 765 | { |
| 766 | PDEC_CRITICAL_SECTION_ENTER(); |
| 767 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; |
| 768 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 769 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 770 | } |
| 771 | |
| 772 | static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) |
| 773 | { |
| 774 | PDEC_CRITICAL_SECTION_ENTER(); |
| 775 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; |
| 776 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 777 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 778 | } |
| 779 | |
| 780 | static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) |
| 781 | { |
| 782 | uint32_t tmp; |
| 783 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 784 | tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; |
| 785 | return (bool)tmp; |
| 786 | } |
| 787 | |
| 788 | static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) |
| 789 | { |
| 790 | uint32_t tmp; |
| 791 | PDEC_CRITICAL_SECTION_ENTER(); |
| 792 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 793 | tmp &= ~PDEC_CTRLA_PINEN0; |
| 794 | tmp |= value << PDEC_CTRLA_PINEN0_Pos; |
| 795 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 796 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 797 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 798 | } |
| 799 | |
| 800 | static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) |
| 801 | { |
| 802 | PDEC_CRITICAL_SECTION_ENTER(); |
| 803 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; |
| 804 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 805 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 806 | } |
| 807 | |
| 808 | static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) |
| 809 | { |
| 810 | PDEC_CRITICAL_SECTION_ENTER(); |
| 811 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; |
| 812 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 813 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 814 | } |
| 815 | |
| 816 | static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) |
| 817 | { |
| 818 | PDEC_CRITICAL_SECTION_ENTER(); |
| 819 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; |
| 820 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 821 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 822 | } |
| 823 | |
| 824 | static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) |
| 825 | { |
| 826 | uint32_t tmp; |
| 827 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 828 | tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; |
| 829 | return (bool)tmp; |
| 830 | } |
| 831 | |
| 832 | static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) |
| 833 | { |
| 834 | uint32_t tmp; |
| 835 | PDEC_CRITICAL_SECTION_ENTER(); |
| 836 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 837 | tmp &= ~PDEC_CTRLA_PINEN1; |
| 838 | tmp |= value << PDEC_CTRLA_PINEN1_Pos; |
| 839 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 840 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 841 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 842 | } |
| 843 | |
| 844 | static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) |
| 845 | { |
| 846 | PDEC_CRITICAL_SECTION_ENTER(); |
| 847 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; |
| 848 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 849 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 850 | } |
| 851 | |
| 852 | static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) |
| 853 | { |
| 854 | PDEC_CRITICAL_SECTION_ENTER(); |
| 855 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; |
| 856 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 857 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 858 | } |
| 859 | |
| 860 | static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) |
| 861 | { |
| 862 | PDEC_CRITICAL_SECTION_ENTER(); |
| 863 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; |
| 864 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 865 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 866 | } |
| 867 | |
| 868 | static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) |
| 869 | { |
| 870 | uint32_t tmp; |
| 871 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 872 | tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; |
| 873 | return (bool)tmp; |
| 874 | } |
| 875 | |
| 876 | static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) |
| 877 | { |
| 878 | uint32_t tmp; |
| 879 | PDEC_CRITICAL_SECTION_ENTER(); |
| 880 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 881 | tmp &= ~PDEC_CTRLA_PINEN2; |
| 882 | tmp |= value << PDEC_CTRLA_PINEN2_Pos; |
| 883 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 884 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 885 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 886 | } |
| 887 | |
| 888 | static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) |
| 889 | { |
| 890 | PDEC_CRITICAL_SECTION_ENTER(); |
| 891 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; |
| 892 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 893 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 894 | } |
| 895 | |
| 896 | static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) |
| 897 | { |
| 898 | PDEC_CRITICAL_SECTION_ENTER(); |
| 899 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; |
| 900 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 901 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 902 | } |
| 903 | |
| 904 | static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) |
| 905 | { |
| 906 | PDEC_CRITICAL_SECTION_ENTER(); |
| 907 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; |
| 908 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 909 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 910 | } |
| 911 | |
| 912 | static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) |
| 913 | { |
| 914 | uint32_t tmp; |
| 915 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 916 | tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; |
| 917 | return (bool)tmp; |
| 918 | } |
| 919 | |
| 920 | static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) |
| 921 | { |
| 922 | uint32_t tmp; |
| 923 | PDEC_CRITICAL_SECTION_ENTER(); |
| 924 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 925 | tmp &= ~PDEC_CTRLA_PINVEN0; |
| 926 | tmp |= value << PDEC_CTRLA_PINVEN0_Pos; |
| 927 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 928 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 929 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 930 | } |
| 931 | |
| 932 | static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) |
| 933 | { |
| 934 | PDEC_CRITICAL_SECTION_ENTER(); |
| 935 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; |
| 936 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 937 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 938 | } |
| 939 | |
| 940 | static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) |
| 941 | { |
| 942 | PDEC_CRITICAL_SECTION_ENTER(); |
| 943 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; |
| 944 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 945 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 946 | } |
| 947 | |
| 948 | static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) |
| 949 | { |
| 950 | PDEC_CRITICAL_SECTION_ENTER(); |
| 951 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; |
| 952 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 953 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 954 | } |
| 955 | |
| 956 | static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) |
| 957 | { |
| 958 | uint32_t tmp; |
| 959 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 960 | tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; |
| 961 | return (bool)tmp; |
| 962 | } |
| 963 | |
| 964 | static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) |
| 965 | { |
| 966 | uint32_t tmp; |
| 967 | PDEC_CRITICAL_SECTION_ENTER(); |
| 968 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 969 | tmp &= ~PDEC_CTRLA_PINVEN1; |
| 970 | tmp |= value << PDEC_CTRLA_PINVEN1_Pos; |
| 971 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 972 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 973 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 974 | } |
| 975 | |
| 976 | static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) |
| 977 | { |
| 978 | PDEC_CRITICAL_SECTION_ENTER(); |
| 979 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; |
| 980 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 981 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 982 | } |
| 983 | |
| 984 | static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) |
| 985 | { |
| 986 | PDEC_CRITICAL_SECTION_ENTER(); |
| 987 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; |
| 988 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 989 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 990 | } |
| 991 | |
| 992 | static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) |
| 993 | { |
| 994 | PDEC_CRITICAL_SECTION_ENTER(); |
| 995 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; |
| 996 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 997 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 998 | } |
| 999 | |
| 1000 | static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) |
| 1001 | { |
| 1002 | uint32_t tmp; |
| 1003 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1004 | tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; |
| 1005 | return (bool)tmp; |
| 1006 | } |
| 1007 | |
| 1008 | static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) |
| 1009 | { |
| 1010 | uint32_t tmp; |
| 1011 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1012 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1013 | tmp &= ~PDEC_CTRLA_PINVEN2; |
| 1014 | tmp |= value << PDEC_CTRLA_PINVEN2_Pos; |
| 1015 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 1016 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1017 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1018 | } |
| 1019 | |
| 1020 | static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) |
| 1021 | { |
| 1022 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1023 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; |
| 1024 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1025 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1026 | } |
| 1027 | |
| 1028 | static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) |
| 1029 | { |
| 1030 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1031 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; |
| 1032 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1033 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1034 | } |
| 1035 | |
| 1036 | static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1037 | { |
| 1038 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1039 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); |
| 1040 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1041 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1042 | } |
| 1043 | |
| 1044 | static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1045 | { |
| 1046 | uint32_t tmp; |
| 1047 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1048 | tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; |
| 1049 | return tmp; |
| 1050 | } |
| 1051 | |
| 1052 | static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) |
| 1053 | { |
| 1054 | uint32_t tmp; |
| 1055 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1056 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1057 | tmp &= ~PDEC_CTRLA_MODE_Msk; |
| 1058 | tmp |= PDEC_CTRLA_MODE(data); |
| 1059 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 1060 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1061 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1062 | } |
| 1063 | |
| 1064 | static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1065 | { |
| 1066 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1067 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); |
| 1068 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1069 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1070 | } |
| 1071 | |
| 1072 | static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1073 | { |
| 1074 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1075 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); |
| 1076 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1077 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1078 | } |
| 1079 | |
| 1080 | static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) |
| 1081 | { |
| 1082 | uint32_t tmp; |
| 1083 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1084 | tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; |
| 1085 | return tmp; |
| 1086 | } |
| 1087 | |
| 1088 | static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1089 | { |
| 1090 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1091 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); |
| 1092 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1093 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1094 | } |
| 1095 | |
| 1096 | static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1097 | { |
| 1098 | uint32_t tmp; |
| 1099 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1100 | tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; |
| 1101 | return tmp; |
| 1102 | } |
| 1103 | |
| 1104 | static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) |
| 1105 | { |
| 1106 | uint32_t tmp; |
| 1107 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1108 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1109 | tmp &= ~PDEC_CTRLA_CONF_Msk; |
| 1110 | tmp |= PDEC_CTRLA_CONF(data); |
| 1111 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 1112 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1113 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1114 | } |
| 1115 | |
| 1116 | static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1117 | { |
| 1118 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1119 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); |
| 1120 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1121 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1122 | } |
| 1123 | |
| 1124 | static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1125 | { |
| 1126 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1127 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); |
| 1128 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1129 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1130 | } |
| 1131 | |
| 1132 | static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) |
| 1133 | { |
| 1134 | uint32_t tmp; |
| 1135 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1136 | tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; |
| 1137 | return tmp; |
| 1138 | } |
| 1139 | |
| 1140 | static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1141 | { |
| 1142 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1143 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); |
| 1144 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1145 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1146 | } |
| 1147 | |
| 1148 | static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1149 | { |
| 1150 | uint32_t tmp; |
| 1151 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1152 | tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; |
| 1153 | return tmp; |
| 1154 | } |
| 1155 | |
| 1156 | static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) |
| 1157 | { |
| 1158 | uint32_t tmp; |
| 1159 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1160 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1161 | tmp &= ~PDEC_CTRLA_ANGULAR_Msk; |
| 1162 | tmp |= PDEC_CTRLA_ANGULAR(data); |
| 1163 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 1164 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1165 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1166 | } |
| 1167 | |
| 1168 | static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1169 | { |
| 1170 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1171 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); |
| 1172 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1173 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1174 | } |
| 1175 | |
| 1176 | static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1177 | { |
| 1178 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1179 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); |
| 1180 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1181 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1182 | } |
| 1183 | |
| 1184 | static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) |
| 1185 | { |
| 1186 | uint32_t tmp; |
| 1187 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1188 | tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; |
| 1189 | return tmp; |
| 1190 | } |
| 1191 | |
| 1192 | static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1193 | { |
| 1194 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1195 | ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); |
| 1196 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1197 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1198 | } |
| 1199 | |
| 1200 | static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1201 | { |
| 1202 | uint32_t tmp; |
| 1203 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1204 | tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; |
| 1205 | return tmp; |
| 1206 | } |
| 1207 | |
| 1208 | static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) |
| 1209 | { |
| 1210 | uint32_t tmp; |
| 1211 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1212 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1213 | tmp &= ~PDEC_CTRLA_MAXCMP_Msk; |
| 1214 | tmp |= PDEC_CTRLA_MAXCMP(data); |
| 1215 | ((Pdec *)hw)->CTRLA.reg = tmp; |
| 1216 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1217 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1218 | } |
| 1219 | |
| 1220 | static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1221 | { |
| 1222 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1223 | ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); |
| 1224 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1225 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1226 | } |
| 1227 | |
| 1228 | static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1229 | { |
| 1230 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1231 | ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); |
| 1232 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 1233 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1234 | } |
| 1235 | |
| 1236 | static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) |
| 1237 | { |
| 1238 | uint32_t tmp; |
| 1239 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1240 | tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; |
| 1241 | return tmp; |
| 1242 | } |
| 1243 | |
| 1244 | static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1245 | { |
| 1246 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1247 | ((Pdec *)hw)->CTRLA.reg |= mask; |
| 1248 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 1249 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1250 | } |
| 1251 | |
| 1252 | static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1253 | { |
| 1254 | uint32_t tmp; |
| 1255 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 1256 | tmp = ((Pdec *)hw)->CTRLA.reg; |
| 1257 | tmp &= mask; |
| 1258 | return tmp; |
| 1259 | } |
| 1260 | |
| 1261 | static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) |
| 1262 | { |
| 1263 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1264 | ((Pdec *)hw)->CTRLA.reg = data; |
| 1265 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 1266 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1267 | } |
| 1268 | |
| 1269 | static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1270 | { |
| 1271 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1272 | ((Pdec *)hw)->CTRLA.reg &= ~mask; |
| 1273 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 1274 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1275 | } |
| 1276 | |
| 1277 | static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) |
| 1278 | { |
| 1279 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1280 | ((Pdec *)hw)->CTRLA.reg ^= mask; |
| 1281 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 1282 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1283 | } |
| 1284 | |
| 1285 | static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) |
| 1286 | { |
| 1287 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); |
| 1288 | return ((Pdec *)hw)->CTRLA.reg; |
| 1289 | } |
| 1290 | |
| 1291 | static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) |
| 1292 | { |
| 1293 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1294 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; |
| 1295 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1296 | } |
| 1297 | |
| 1298 | static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) |
| 1299 | { |
| 1300 | uint16_t tmp; |
| 1301 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1302 | tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; |
| 1303 | return (bool)tmp; |
| 1304 | } |
| 1305 | |
| 1306 | static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) |
| 1307 | { |
| 1308 | uint16_t tmp; |
| 1309 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1310 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1311 | tmp &= ~PDEC_EVCTRL_OVFEO; |
| 1312 | tmp |= value << PDEC_EVCTRL_OVFEO_Pos; |
| 1313 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1314 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1315 | } |
| 1316 | |
| 1317 | static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) |
| 1318 | { |
| 1319 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1320 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; |
| 1321 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1322 | } |
| 1323 | |
| 1324 | static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) |
| 1325 | { |
| 1326 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1327 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; |
| 1328 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1329 | } |
| 1330 | |
| 1331 | static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) |
| 1332 | { |
| 1333 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1334 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; |
| 1335 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1336 | } |
| 1337 | |
| 1338 | static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) |
| 1339 | { |
| 1340 | uint16_t tmp; |
| 1341 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1342 | tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; |
| 1343 | return (bool)tmp; |
| 1344 | } |
| 1345 | |
| 1346 | static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) |
| 1347 | { |
| 1348 | uint16_t tmp; |
| 1349 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1350 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1351 | tmp &= ~PDEC_EVCTRL_ERREO; |
| 1352 | tmp |= value << PDEC_EVCTRL_ERREO_Pos; |
| 1353 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1354 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1355 | } |
| 1356 | |
| 1357 | static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) |
| 1358 | { |
| 1359 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1360 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; |
| 1361 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1362 | } |
| 1363 | |
| 1364 | static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) |
| 1365 | { |
| 1366 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1367 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; |
| 1368 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1369 | } |
| 1370 | |
| 1371 | static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) |
| 1372 | { |
| 1373 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1374 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; |
| 1375 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1376 | } |
| 1377 | |
| 1378 | static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) |
| 1379 | { |
| 1380 | uint16_t tmp; |
| 1381 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1382 | tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; |
| 1383 | return (bool)tmp; |
| 1384 | } |
| 1385 | |
| 1386 | static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) |
| 1387 | { |
| 1388 | uint16_t tmp; |
| 1389 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1390 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1391 | tmp &= ~PDEC_EVCTRL_DIREO; |
| 1392 | tmp |= value << PDEC_EVCTRL_DIREO_Pos; |
| 1393 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1394 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1395 | } |
| 1396 | |
| 1397 | static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) |
| 1398 | { |
| 1399 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1400 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; |
| 1401 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1402 | } |
| 1403 | |
| 1404 | static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) |
| 1405 | { |
| 1406 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1407 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; |
| 1408 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1409 | } |
| 1410 | |
| 1411 | static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) |
| 1412 | { |
| 1413 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1414 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; |
| 1415 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1416 | } |
| 1417 | |
| 1418 | static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) |
| 1419 | { |
| 1420 | uint16_t tmp; |
| 1421 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1422 | tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; |
| 1423 | return (bool)tmp; |
| 1424 | } |
| 1425 | |
| 1426 | static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) |
| 1427 | { |
| 1428 | uint16_t tmp; |
| 1429 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1430 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1431 | tmp &= ~PDEC_EVCTRL_VLCEO; |
| 1432 | tmp |= value << PDEC_EVCTRL_VLCEO_Pos; |
| 1433 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1434 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1435 | } |
| 1436 | |
| 1437 | static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) |
| 1438 | { |
| 1439 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1440 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; |
| 1441 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1442 | } |
| 1443 | |
| 1444 | static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) |
| 1445 | { |
| 1446 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1447 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; |
| 1448 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1449 | } |
| 1450 | |
| 1451 | static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) |
| 1452 | { |
| 1453 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1454 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; |
| 1455 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1456 | } |
| 1457 | |
| 1458 | static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) |
| 1459 | { |
| 1460 | uint16_t tmp; |
| 1461 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1462 | tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; |
| 1463 | return (bool)tmp; |
| 1464 | } |
| 1465 | |
| 1466 | static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) |
| 1467 | { |
| 1468 | uint16_t tmp; |
| 1469 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1470 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1471 | tmp &= ~PDEC_EVCTRL_MCEO0; |
| 1472 | tmp |= value << PDEC_EVCTRL_MCEO0_Pos; |
| 1473 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1474 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1475 | } |
| 1476 | |
| 1477 | static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) |
| 1478 | { |
| 1479 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1480 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; |
| 1481 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1482 | } |
| 1483 | |
| 1484 | static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) |
| 1485 | { |
| 1486 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1487 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; |
| 1488 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1489 | } |
| 1490 | |
| 1491 | static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) |
| 1492 | { |
| 1493 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1494 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; |
| 1495 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1496 | } |
| 1497 | |
| 1498 | static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) |
| 1499 | { |
| 1500 | uint16_t tmp; |
| 1501 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1502 | tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; |
| 1503 | return (bool)tmp; |
| 1504 | } |
| 1505 | |
| 1506 | static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) |
| 1507 | { |
| 1508 | uint16_t tmp; |
| 1509 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1510 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1511 | tmp &= ~PDEC_EVCTRL_MCEO1; |
| 1512 | tmp |= value << PDEC_EVCTRL_MCEO1_Pos; |
| 1513 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1514 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1515 | } |
| 1516 | |
| 1517 | static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) |
| 1518 | { |
| 1519 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1520 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; |
| 1521 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1522 | } |
| 1523 | |
| 1524 | static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) |
| 1525 | { |
| 1526 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1527 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; |
| 1528 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1529 | } |
| 1530 | |
| 1531 | static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1532 | { |
| 1533 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1534 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); |
| 1535 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1536 | } |
| 1537 | |
| 1538 | static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1539 | { |
| 1540 | uint16_t tmp; |
| 1541 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1542 | tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; |
| 1543 | return tmp; |
| 1544 | } |
| 1545 | |
| 1546 | static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) |
| 1547 | { |
| 1548 | uint16_t tmp; |
| 1549 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1550 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1551 | tmp &= ~PDEC_EVCTRL_EVACT_Msk; |
| 1552 | tmp |= PDEC_EVCTRL_EVACT(data); |
| 1553 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1554 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1555 | } |
| 1556 | |
| 1557 | static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1558 | { |
| 1559 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1560 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); |
| 1561 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1562 | } |
| 1563 | |
| 1564 | static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1565 | { |
| 1566 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1567 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); |
| 1568 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1569 | } |
| 1570 | |
| 1571 | static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) |
| 1572 | { |
| 1573 | uint16_t tmp; |
| 1574 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1575 | tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; |
| 1576 | return tmp; |
| 1577 | } |
| 1578 | |
| 1579 | static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1580 | { |
| 1581 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1582 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); |
| 1583 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1584 | } |
| 1585 | |
| 1586 | static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1587 | { |
| 1588 | uint16_t tmp; |
| 1589 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1590 | tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; |
| 1591 | return tmp; |
| 1592 | } |
| 1593 | |
| 1594 | static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) |
| 1595 | { |
| 1596 | uint16_t tmp; |
| 1597 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1598 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1599 | tmp &= ~PDEC_EVCTRL_EVINV_Msk; |
| 1600 | tmp |= PDEC_EVCTRL_EVINV(data); |
| 1601 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1602 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1603 | } |
| 1604 | |
| 1605 | static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1606 | { |
| 1607 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1608 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); |
| 1609 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1610 | } |
| 1611 | |
| 1612 | static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1613 | { |
| 1614 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1615 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); |
| 1616 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1617 | } |
| 1618 | |
| 1619 | static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) |
| 1620 | { |
| 1621 | uint16_t tmp; |
| 1622 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1623 | tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; |
| 1624 | return tmp; |
| 1625 | } |
| 1626 | |
| 1627 | static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1628 | { |
| 1629 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1630 | ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); |
| 1631 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1632 | } |
| 1633 | |
| 1634 | static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1635 | { |
| 1636 | uint16_t tmp; |
| 1637 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1638 | tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; |
| 1639 | return tmp; |
| 1640 | } |
| 1641 | |
| 1642 | static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) |
| 1643 | { |
| 1644 | uint16_t tmp; |
| 1645 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1646 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1647 | tmp &= ~PDEC_EVCTRL_EVEI_Msk; |
| 1648 | tmp |= PDEC_EVCTRL_EVEI(data); |
| 1649 | ((Pdec *)hw)->EVCTRL.reg = tmp; |
| 1650 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1651 | } |
| 1652 | |
| 1653 | static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1654 | { |
| 1655 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1656 | ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); |
| 1657 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1658 | } |
| 1659 | |
| 1660 | static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1661 | { |
| 1662 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1663 | ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); |
| 1664 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1665 | } |
| 1666 | |
| 1667 | static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) |
| 1668 | { |
| 1669 | uint16_t tmp; |
| 1670 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1671 | tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; |
| 1672 | return tmp; |
| 1673 | } |
| 1674 | |
| 1675 | static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1676 | { |
| 1677 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1678 | ((Pdec *)hw)->EVCTRL.reg |= mask; |
| 1679 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1680 | } |
| 1681 | |
| 1682 | static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1683 | { |
| 1684 | uint16_t tmp; |
| 1685 | tmp = ((Pdec *)hw)->EVCTRL.reg; |
| 1686 | tmp &= mask; |
| 1687 | return tmp; |
| 1688 | } |
| 1689 | |
| 1690 | static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) |
| 1691 | { |
| 1692 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1693 | ((Pdec *)hw)->EVCTRL.reg = data; |
| 1694 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1695 | } |
| 1696 | |
| 1697 | static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1698 | { |
| 1699 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1700 | ((Pdec *)hw)->EVCTRL.reg &= ~mask; |
| 1701 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1702 | } |
| 1703 | |
| 1704 | static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) |
| 1705 | { |
| 1706 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1707 | ((Pdec *)hw)->EVCTRL.reg ^= mask; |
| 1708 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1709 | } |
| 1710 | |
| 1711 | static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) |
| 1712 | { |
| 1713 | return ((Pdec *)hw)->EVCTRL.reg; |
| 1714 | } |
| 1715 | |
| 1716 | static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1717 | { |
| 1718 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1719 | ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; |
| 1720 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1721 | } |
| 1722 | |
| 1723 | static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1724 | { |
| 1725 | uint8_t tmp; |
| 1726 | tmp = ((Pdec *)hw)->DBGCTRL.reg; |
| 1727 | tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; |
| 1728 | return (bool)tmp; |
| 1729 | } |
| 1730 | |
| 1731 | static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) |
| 1732 | { |
| 1733 | uint8_t tmp; |
| 1734 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1735 | tmp = ((Pdec *)hw)->DBGCTRL.reg; |
| 1736 | tmp &= ~PDEC_DBGCTRL_DBGRUN; |
| 1737 | tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; |
| 1738 | ((Pdec *)hw)->DBGCTRL.reg = tmp; |
| 1739 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1740 | } |
| 1741 | |
| 1742 | static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1743 | { |
| 1744 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1745 | ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; |
| 1746 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1747 | } |
| 1748 | |
| 1749 | static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1750 | { |
| 1751 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1752 | ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; |
| 1753 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1754 | } |
| 1755 | |
| 1756 | static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) |
| 1757 | { |
| 1758 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1759 | ((Pdec *)hw)->DBGCTRL.reg |= mask; |
| 1760 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1761 | } |
| 1762 | |
| 1763 | static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) |
| 1764 | { |
| 1765 | uint8_t tmp; |
| 1766 | tmp = ((Pdec *)hw)->DBGCTRL.reg; |
| 1767 | tmp &= mask; |
| 1768 | return tmp; |
| 1769 | } |
| 1770 | |
| 1771 | static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) |
| 1772 | { |
| 1773 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1774 | ((Pdec *)hw)->DBGCTRL.reg = data; |
| 1775 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1776 | } |
| 1777 | |
| 1778 | static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) |
| 1779 | { |
| 1780 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1781 | ((Pdec *)hw)->DBGCTRL.reg &= ~mask; |
| 1782 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1783 | } |
| 1784 | |
| 1785 | static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) |
| 1786 | { |
| 1787 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1788 | ((Pdec *)hw)->DBGCTRL.reg ^= mask; |
| 1789 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1790 | } |
| 1791 | |
| 1792 | static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) |
| 1793 | { |
| 1794 | return ((Pdec *)hw)->DBGCTRL.reg; |
| 1795 | } |
| 1796 | |
| 1797 | static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1798 | { |
| 1799 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1800 | ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); |
| 1801 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1802 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1803 | } |
| 1804 | |
| 1805 | static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1806 | { |
| 1807 | uint8_t tmp; |
| 1808 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1809 | tmp = ((Pdec *)hw)->PRESC.reg; |
| 1810 | tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; |
| 1811 | return tmp; |
| 1812 | } |
| 1813 | |
| 1814 | static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) |
| 1815 | { |
| 1816 | uint8_t tmp; |
| 1817 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1818 | tmp = ((Pdec *)hw)->PRESC.reg; |
| 1819 | tmp &= ~PDEC_PRESC_PRESC_Msk; |
| 1820 | tmp |= PDEC_PRESC_PRESC(data); |
| 1821 | ((Pdec *)hw)->PRESC.reg = tmp; |
| 1822 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1823 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1824 | } |
| 1825 | |
| 1826 | static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1827 | { |
| 1828 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1829 | ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); |
| 1830 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1831 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1832 | } |
| 1833 | |
| 1834 | static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1835 | { |
| 1836 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1837 | ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); |
| 1838 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1839 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1840 | } |
| 1841 | |
| 1842 | static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) |
| 1843 | { |
| 1844 | uint8_t tmp; |
| 1845 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1846 | tmp = ((Pdec *)hw)->PRESC.reg; |
| 1847 | tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; |
| 1848 | return tmp; |
| 1849 | } |
| 1850 | |
| 1851 | static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1852 | { |
| 1853 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1854 | ((Pdec *)hw)->PRESC.reg |= mask; |
| 1855 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1856 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1857 | } |
| 1858 | |
| 1859 | static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1860 | { |
| 1861 | uint8_t tmp; |
| 1862 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1863 | tmp = ((Pdec *)hw)->PRESC.reg; |
| 1864 | tmp &= mask; |
| 1865 | return tmp; |
| 1866 | } |
| 1867 | |
| 1868 | static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) |
| 1869 | { |
| 1870 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1871 | ((Pdec *)hw)->PRESC.reg = data; |
| 1872 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1873 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1874 | } |
| 1875 | |
| 1876 | static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1877 | { |
| 1878 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1879 | ((Pdec *)hw)->PRESC.reg &= ~mask; |
| 1880 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1881 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1882 | } |
| 1883 | |
| 1884 | static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) |
| 1885 | { |
| 1886 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1887 | ((Pdec *)hw)->PRESC.reg ^= mask; |
| 1888 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1889 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1890 | } |
| 1891 | |
| 1892 | static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) |
| 1893 | { |
| 1894 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); |
| 1895 | return ((Pdec *)hw)->PRESC.reg; |
| 1896 | } |
| 1897 | |
| 1898 | static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1899 | { |
| 1900 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1901 | ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); |
| 1902 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1903 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1904 | } |
| 1905 | |
| 1906 | static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1907 | { |
| 1908 | uint8_t tmp; |
| 1909 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1910 | tmp = ((Pdec *)hw)->FILTER.reg; |
| 1911 | tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; |
| 1912 | return tmp; |
| 1913 | } |
| 1914 | |
| 1915 | static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) |
| 1916 | { |
| 1917 | uint8_t tmp; |
| 1918 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1919 | tmp = ((Pdec *)hw)->FILTER.reg; |
| 1920 | tmp &= ~PDEC_FILTER_FILTER_Msk; |
| 1921 | tmp |= PDEC_FILTER_FILTER(data); |
| 1922 | ((Pdec *)hw)->FILTER.reg = tmp; |
| 1923 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1924 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1925 | } |
| 1926 | |
| 1927 | static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1928 | { |
| 1929 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1930 | ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); |
| 1931 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1932 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1933 | } |
| 1934 | |
| 1935 | static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1936 | { |
| 1937 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1938 | ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); |
| 1939 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1940 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1941 | } |
| 1942 | |
| 1943 | static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) |
| 1944 | { |
| 1945 | uint8_t tmp; |
| 1946 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1947 | tmp = ((Pdec *)hw)->FILTER.reg; |
| 1948 | tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; |
| 1949 | return tmp; |
| 1950 | } |
| 1951 | |
| 1952 | static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1953 | { |
| 1954 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1955 | ((Pdec *)hw)->FILTER.reg |= mask; |
| 1956 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1957 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1958 | } |
| 1959 | |
| 1960 | static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1961 | { |
| 1962 | uint8_t tmp; |
| 1963 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1964 | tmp = ((Pdec *)hw)->FILTER.reg; |
| 1965 | tmp &= mask; |
| 1966 | return tmp; |
| 1967 | } |
| 1968 | |
| 1969 | static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) |
| 1970 | { |
| 1971 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1972 | ((Pdec *)hw)->FILTER.reg = data; |
| 1973 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1974 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1975 | } |
| 1976 | |
| 1977 | static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1978 | { |
| 1979 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1980 | ((Pdec *)hw)->FILTER.reg &= ~mask; |
| 1981 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1982 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1983 | } |
| 1984 | |
| 1985 | static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) |
| 1986 | { |
| 1987 | PDEC_CRITICAL_SECTION_ENTER(); |
| 1988 | ((Pdec *)hw)->FILTER.reg ^= mask; |
| 1989 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1990 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 1991 | } |
| 1992 | |
| 1993 | static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) |
| 1994 | { |
| 1995 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); |
| 1996 | return ((Pdec *)hw)->FILTER.reg; |
| 1997 | } |
| 1998 | |
| 1999 | static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) |
| 2000 | { |
| 2001 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2002 | ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); |
| 2003 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2004 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2005 | } |
| 2006 | |
| 2007 | static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, |
| 2008 | hri_pdec_prescbuf_reg_t mask) |
| 2009 | { |
| 2010 | uint8_t tmp; |
| 2011 | tmp = ((Pdec *)hw)->PRESCBUF.reg; |
| 2012 | tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; |
| 2013 | return tmp; |
| 2014 | } |
| 2015 | |
| 2016 | static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) |
| 2017 | { |
| 2018 | uint8_t tmp; |
| 2019 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2020 | tmp = ((Pdec *)hw)->PRESCBUF.reg; |
| 2021 | tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; |
| 2022 | tmp |= PDEC_PRESCBUF_PRESCBUF(data); |
| 2023 | ((Pdec *)hw)->PRESCBUF.reg = tmp; |
| 2024 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2025 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2026 | } |
| 2027 | |
| 2028 | static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) |
| 2029 | { |
| 2030 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2031 | ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); |
| 2032 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2033 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2034 | } |
| 2035 | |
| 2036 | static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) |
| 2037 | { |
| 2038 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2039 | ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); |
| 2040 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2041 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2042 | } |
| 2043 | |
| 2044 | static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) |
| 2045 | { |
| 2046 | uint8_t tmp; |
| 2047 | tmp = ((Pdec *)hw)->PRESCBUF.reg; |
| 2048 | tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; |
| 2049 | return tmp; |
| 2050 | } |
| 2051 | |
| 2052 | static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) |
| 2053 | { |
| 2054 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2055 | ((Pdec *)hw)->PRESCBUF.reg |= mask; |
| 2056 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2057 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2058 | } |
| 2059 | |
| 2060 | static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) |
| 2061 | { |
| 2062 | uint8_t tmp; |
| 2063 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2064 | tmp = ((Pdec *)hw)->PRESCBUF.reg; |
| 2065 | tmp &= mask; |
| 2066 | return tmp; |
| 2067 | } |
| 2068 | |
| 2069 | static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) |
| 2070 | { |
| 2071 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2072 | ((Pdec *)hw)->PRESCBUF.reg = data; |
| 2073 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2074 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2075 | } |
| 2076 | |
| 2077 | static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) |
| 2078 | { |
| 2079 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2080 | ((Pdec *)hw)->PRESCBUF.reg &= ~mask; |
| 2081 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2082 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2083 | } |
| 2084 | |
| 2085 | static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) |
| 2086 | { |
| 2087 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2088 | ((Pdec *)hw)->PRESCBUF.reg ^= mask; |
| 2089 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2090 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2091 | } |
| 2092 | |
| 2093 | static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) |
| 2094 | { |
| 2095 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2096 | return ((Pdec *)hw)->PRESCBUF.reg; |
| 2097 | } |
| 2098 | |
| 2099 | static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) |
| 2100 | { |
| 2101 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2102 | ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); |
| 2103 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2104 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2105 | } |
| 2106 | |
| 2107 | static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, |
| 2108 | hri_pdec_filterbuf_reg_t mask) |
| 2109 | { |
| 2110 | uint8_t tmp; |
| 2111 | tmp = ((Pdec *)hw)->FILTERBUF.reg; |
| 2112 | tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; |
| 2113 | return tmp; |
| 2114 | } |
| 2115 | |
| 2116 | static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) |
| 2117 | { |
| 2118 | uint8_t tmp; |
| 2119 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2120 | tmp = ((Pdec *)hw)->FILTERBUF.reg; |
| 2121 | tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; |
| 2122 | tmp |= PDEC_FILTERBUF_FILTERBUF(data); |
| 2123 | ((Pdec *)hw)->FILTERBUF.reg = tmp; |
| 2124 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2125 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2126 | } |
| 2127 | |
| 2128 | static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) |
| 2129 | { |
| 2130 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2131 | ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); |
| 2132 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2133 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2134 | } |
| 2135 | |
| 2136 | static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) |
| 2137 | { |
| 2138 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2139 | ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); |
| 2140 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2141 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2142 | } |
| 2143 | |
| 2144 | static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) |
| 2145 | { |
| 2146 | uint8_t tmp; |
| 2147 | tmp = ((Pdec *)hw)->FILTERBUF.reg; |
| 2148 | tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; |
| 2149 | return tmp; |
| 2150 | } |
| 2151 | |
| 2152 | static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) |
| 2153 | { |
| 2154 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2155 | ((Pdec *)hw)->FILTERBUF.reg |= mask; |
| 2156 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2157 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2158 | } |
| 2159 | |
| 2160 | static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) |
| 2161 | { |
| 2162 | uint8_t tmp; |
| 2163 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2164 | tmp = ((Pdec *)hw)->FILTERBUF.reg; |
| 2165 | tmp &= mask; |
| 2166 | return tmp; |
| 2167 | } |
| 2168 | |
| 2169 | static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) |
| 2170 | { |
| 2171 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2172 | ((Pdec *)hw)->FILTERBUF.reg = data; |
| 2173 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2174 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2175 | } |
| 2176 | |
| 2177 | static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) |
| 2178 | { |
| 2179 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2180 | ((Pdec *)hw)->FILTERBUF.reg &= ~mask; |
| 2181 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2182 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2183 | } |
| 2184 | |
| 2185 | static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) |
| 2186 | { |
| 2187 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2188 | ((Pdec *)hw)->FILTERBUF.reg ^= mask; |
| 2189 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2190 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2191 | } |
| 2192 | |
| 2193 | static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) |
| 2194 | { |
| 2195 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2196 | return ((Pdec *)hw)->FILTERBUF.reg; |
| 2197 | } |
| 2198 | |
| 2199 | static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) |
| 2200 | { |
| 2201 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2202 | ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); |
| 2203 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2204 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2205 | } |
| 2206 | |
| 2207 | static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) |
| 2208 | { |
| 2209 | uint32_t tmp; |
| 2210 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2211 | tmp = ((Pdec *)hw)->COUNT.reg; |
| 2212 | tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; |
| 2213 | return tmp; |
| 2214 | } |
| 2215 | |
| 2216 | static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) |
| 2217 | { |
| 2218 | uint32_t tmp; |
| 2219 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2220 | tmp = ((Pdec *)hw)->COUNT.reg; |
| 2221 | tmp &= ~PDEC_COUNT_COUNT_Msk; |
| 2222 | tmp |= PDEC_COUNT_COUNT(data); |
| 2223 | ((Pdec *)hw)->COUNT.reg = tmp; |
| 2224 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2225 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2226 | } |
| 2227 | |
| 2228 | static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) |
| 2229 | { |
| 2230 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2231 | ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); |
| 2232 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2233 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2234 | } |
| 2235 | |
| 2236 | static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) |
| 2237 | { |
| 2238 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2239 | ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); |
| 2240 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2241 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2242 | } |
| 2243 | |
| 2244 | static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) |
| 2245 | { |
| 2246 | uint32_t tmp; |
| 2247 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2248 | tmp = ((Pdec *)hw)->COUNT.reg; |
| 2249 | tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; |
| 2250 | return tmp; |
| 2251 | } |
| 2252 | |
| 2253 | static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) |
| 2254 | { |
| 2255 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2256 | ((Pdec *)hw)->COUNT.reg |= mask; |
| 2257 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2258 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2259 | } |
| 2260 | |
| 2261 | static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) |
| 2262 | { |
| 2263 | uint32_t tmp; |
| 2264 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2265 | tmp = ((Pdec *)hw)->COUNT.reg; |
| 2266 | tmp &= mask; |
| 2267 | return tmp; |
| 2268 | } |
| 2269 | |
| 2270 | static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) |
| 2271 | { |
| 2272 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2273 | ((Pdec *)hw)->COUNT.reg = data; |
| 2274 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2275 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2276 | } |
| 2277 | |
| 2278 | static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) |
| 2279 | { |
| 2280 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2281 | ((Pdec *)hw)->COUNT.reg &= ~mask; |
| 2282 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2283 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2284 | } |
| 2285 | |
| 2286 | static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) |
| 2287 | { |
| 2288 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2289 | ((Pdec *)hw)->COUNT.reg ^= mask; |
| 2290 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2291 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2292 | } |
| 2293 | |
| 2294 | static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) |
| 2295 | { |
| 2296 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); |
| 2297 | return ((Pdec *)hw)->COUNT.reg; |
| 2298 | } |
| 2299 | |
| 2300 | static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2301 | { |
| 2302 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2303 | ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); |
| 2304 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2305 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2306 | } |
| 2307 | |
| 2308 | static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2309 | { |
| 2310 | uint32_t tmp; |
| 2311 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2312 | tmp = ((Pdec *)hw)->CC[index].reg; |
| 2313 | tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; |
| 2314 | return tmp; |
| 2315 | } |
| 2316 | |
| 2317 | static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) |
| 2318 | { |
| 2319 | uint32_t tmp; |
| 2320 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2321 | tmp = ((Pdec *)hw)->CC[index].reg; |
| 2322 | tmp &= ~PDEC_CC_CC_Msk; |
| 2323 | tmp |= PDEC_CC_CC(data); |
| 2324 | ((Pdec *)hw)->CC[index].reg = tmp; |
| 2325 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2326 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2327 | } |
| 2328 | |
| 2329 | static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2330 | { |
| 2331 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2332 | ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); |
| 2333 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2334 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2335 | } |
| 2336 | |
| 2337 | static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2338 | { |
| 2339 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2340 | ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); |
| 2341 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2342 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2343 | } |
| 2344 | |
| 2345 | static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) |
| 2346 | { |
| 2347 | uint32_t tmp; |
| 2348 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2349 | tmp = ((Pdec *)hw)->CC[index].reg; |
| 2350 | tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; |
| 2351 | return tmp; |
| 2352 | } |
| 2353 | |
| 2354 | static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2355 | { |
| 2356 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2357 | ((Pdec *)hw)->CC[index].reg |= mask; |
| 2358 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2359 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2360 | } |
| 2361 | |
| 2362 | static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2363 | { |
| 2364 | uint32_t tmp; |
| 2365 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2366 | tmp = ((Pdec *)hw)->CC[index].reg; |
| 2367 | tmp &= mask; |
| 2368 | return tmp; |
| 2369 | } |
| 2370 | |
| 2371 | static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) |
| 2372 | { |
| 2373 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2374 | ((Pdec *)hw)->CC[index].reg = data; |
| 2375 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2376 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2377 | } |
| 2378 | |
| 2379 | static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2380 | { |
| 2381 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2382 | ((Pdec *)hw)->CC[index].reg &= ~mask; |
| 2383 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2384 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2385 | } |
| 2386 | |
| 2387 | static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) |
| 2388 | { |
| 2389 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2390 | ((Pdec *)hw)->CC[index].reg ^= mask; |
| 2391 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2392 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2393 | } |
| 2394 | |
| 2395 | static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) |
| 2396 | { |
| 2397 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); |
| 2398 | return ((Pdec *)hw)->CC[index].reg; |
| 2399 | } |
| 2400 | |
| 2401 | static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) |
| 2402 | { |
| 2403 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2404 | ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); |
| 2405 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2406 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2407 | } |
| 2408 | |
| 2409 | static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2410 | hri_pdec_ccbuf_reg_t mask) |
| 2411 | { |
| 2412 | uint32_t tmp; |
| 2413 | tmp = ((Pdec *)hw)->CCBUF[index].reg; |
| 2414 | tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; |
| 2415 | return tmp; |
| 2416 | } |
| 2417 | |
| 2418 | static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) |
| 2419 | { |
| 2420 | uint32_t tmp; |
| 2421 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2422 | tmp = ((Pdec *)hw)->CCBUF[index].reg; |
| 2423 | tmp &= ~PDEC_CCBUF_CCBUF_Msk; |
| 2424 | tmp |= PDEC_CCBUF_CCBUF(data); |
| 2425 | ((Pdec *)hw)->CCBUF[index].reg = tmp; |
| 2426 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2427 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2428 | } |
| 2429 | |
| 2430 | static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) |
| 2431 | { |
| 2432 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2433 | ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); |
| 2434 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2435 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2436 | } |
| 2437 | |
| 2438 | static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) |
| 2439 | { |
| 2440 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2441 | ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); |
| 2442 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2443 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2444 | } |
| 2445 | |
| 2446 | static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) |
| 2447 | { |
| 2448 | uint32_t tmp; |
| 2449 | tmp = ((Pdec *)hw)->CCBUF[index].reg; |
| 2450 | tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; |
| 2451 | return tmp; |
| 2452 | } |
| 2453 | |
| 2454 | static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) |
| 2455 | { |
| 2456 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2457 | ((Pdec *)hw)->CCBUF[index].reg |= mask; |
| 2458 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2459 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2460 | } |
| 2461 | |
| 2462 | static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, |
| 2463 | hri_pdec_ccbuf_reg_t mask) |
| 2464 | { |
| 2465 | uint32_t tmp; |
| 2466 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2467 | tmp = ((Pdec *)hw)->CCBUF[index].reg; |
| 2468 | tmp &= mask; |
| 2469 | return tmp; |
| 2470 | } |
| 2471 | |
| 2472 | static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) |
| 2473 | { |
| 2474 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2475 | ((Pdec *)hw)->CCBUF[index].reg = data; |
| 2476 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2477 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2478 | } |
| 2479 | |
| 2480 | static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) |
| 2481 | { |
| 2482 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2483 | ((Pdec *)hw)->CCBUF[index].reg &= ~mask; |
| 2484 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2485 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2486 | } |
| 2487 | |
| 2488 | static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) |
| 2489 | { |
| 2490 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2491 | ((Pdec *)hw)->CCBUF[index].reg ^= mask; |
| 2492 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2493 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2494 | } |
| 2495 | |
| 2496 | static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) |
| 2497 | { |
| 2498 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2499 | return ((Pdec *)hw)->CCBUF[index].reg; |
| 2500 | } |
| 2501 | |
| 2502 | static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) |
| 2503 | { |
| 2504 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2505 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; |
| 2506 | } |
| 2507 | |
| 2508 | static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) |
| 2509 | { |
| 2510 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2511 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; |
| 2512 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2513 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2514 | } |
| 2515 | |
| 2516 | static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) |
| 2517 | { |
| 2518 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2519 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; |
| 2520 | } |
| 2521 | |
| 2522 | static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) |
| 2523 | { |
| 2524 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2525 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; |
| 2526 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2527 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2528 | } |
| 2529 | |
| 2530 | static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) |
| 2531 | { |
| 2532 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2533 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; |
| 2534 | } |
| 2535 | |
| 2536 | static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) |
| 2537 | { |
| 2538 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2539 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; |
| 2540 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2541 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2542 | } |
| 2543 | |
| 2544 | static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) |
| 2545 | { |
| 2546 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2547 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; |
| 2548 | } |
| 2549 | |
| 2550 | static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) |
| 2551 | { |
| 2552 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2553 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; |
| 2554 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2555 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2556 | } |
| 2557 | |
| 2558 | static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) |
| 2559 | { |
| 2560 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2561 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; |
| 2562 | } |
| 2563 | |
| 2564 | static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) |
| 2565 | { |
| 2566 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2567 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; |
| 2568 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2569 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2570 | } |
| 2571 | |
| 2572 | static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) |
| 2573 | { |
| 2574 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2575 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; |
| 2576 | } |
| 2577 | |
| 2578 | static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) |
| 2579 | { |
| 2580 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2581 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; |
| 2582 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2583 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2584 | } |
| 2585 | |
| 2586 | static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) |
| 2587 | { |
| 2588 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2589 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; |
| 2590 | } |
| 2591 | |
| 2592 | static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) |
| 2593 | { |
| 2594 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2595 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; |
| 2596 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2597 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2598 | } |
| 2599 | |
| 2600 | static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) |
| 2601 | { |
| 2602 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2603 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; |
| 2604 | } |
| 2605 | |
| 2606 | static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) |
| 2607 | { |
| 2608 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2609 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; |
| 2610 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2611 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2612 | } |
| 2613 | |
| 2614 | static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) |
| 2615 | { |
| 2616 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2617 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; |
| 2618 | } |
| 2619 | |
| 2620 | static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) |
| 2621 | { |
| 2622 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2623 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; |
| 2624 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2625 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2626 | } |
| 2627 | |
| 2628 | static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) |
| 2629 | { |
| 2630 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2631 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; |
| 2632 | } |
| 2633 | |
| 2634 | static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) |
| 2635 | { |
| 2636 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2637 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; |
| 2638 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2639 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2640 | } |
| 2641 | |
| 2642 | static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) |
| 2643 | { |
| 2644 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2645 | return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; |
| 2646 | } |
| 2647 | |
| 2648 | static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) |
| 2649 | { |
| 2650 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2651 | ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; |
| 2652 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2653 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2654 | } |
| 2655 | |
| 2656 | static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) |
| 2657 | { |
| 2658 | uint16_t tmp; |
| 2659 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2660 | tmp = ((Pdec *)hw)->STATUS.reg; |
| 2661 | tmp &= mask; |
| 2662 | return tmp; |
| 2663 | } |
| 2664 | |
| 2665 | static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) |
| 2666 | { |
| 2667 | PDEC_CRITICAL_SECTION_ENTER(); |
| 2668 | ((Pdec *)hw)->STATUS.reg = mask; |
| 2669 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2670 | PDEC_CRITICAL_SECTION_LEAVE(); |
| 2671 | } |
| 2672 | |
| 2673 | static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) |
| 2674 | { |
| 2675 | hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); |
| 2676 | return ((Pdec *)hw)->STATUS.reg; |
| 2677 | } |
| 2678 | |
| 2679 | #ifdef __cplusplus |
| 2680 | } |
| 2681 | #endif |
| 2682 | |
| 2683 | #endif /* _HRI_PDEC_E54_H_INCLUDED */ |
| 2684 | #endif /* _SAME54_PDEC_COMPONENT_ */ |