Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM PCC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_PCC_COMPONENT_ |
| 35 | #ifndef _HRI_PCC_E54_H_INCLUDED_ |
| 36 | #define _HRI_PCC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_PCC_CRITICAL_SECTIONS) |
| 46 | #define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define PCC_CRITICAL_SECTION_ENTER() |
| 50 | #define PCC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_pcc_imr_reg_t; |
| 54 | typedef uint32_t hri_pcc_isr_reg_t; |
| 55 | typedef uint32_t hri_pcc_mr_reg_t; |
| 56 | typedef uint32_t hri_pcc_rhr_reg_t; |
| 57 | typedef uint32_t hri_pcc_wpmr_reg_t; |
| 58 | typedef uint32_t hri_pcc_wpsr_reg_t; |
| 59 | |
| 60 | static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) |
| 61 | { |
| 62 | ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; |
| 63 | } |
| 64 | |
| 65 | static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) |
| 66 | { |
| 67 | return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; |
| 68 | } |
| 69 | |
| 70 | static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) |
| 71 | { |
| 72 | if (value == 0x0) { |
| 73 | ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; |
| 74 | } else { |
| 75 | ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) |
| 80 | { |
| 81 | ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; |
| 82 | } |
| 83 | |
| 84 | static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) |
| 85 | { |
| 86 | ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; |
| 87 | } |
| 88 | |
| 89 | static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) |
| 90 | { |
| 91 | return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; |
| 92 | } |
| 93 | |
| 94 | static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) |
| 95 | { |
| 96 | if (value == 0x0) { |
| 97 | ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; |
| 98 | } else { |
| 99 | ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) |
| 104 | { |
| 105 | ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; |
| 106 | } |
| 107 | |
| 108 | static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) |
| 109 | { |
| 110 | ((Pcc *)hw)->IER.reg = mask; |
| 111 | } |
| 112 | |
| 113 | static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) |
| 114 | { |
| 115 | uint32_t tmp; |
| 116 | tmp = ((Pcc *)hw)->IMR.reg; |
| 117 | tmp &= mask; |
| 118 | return tmp; |
| 119 | } |
| 120 | |
| 121 | static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) |
| 122 | { |
| 123 | return ((Pcc *)hw)->IMR.reg; |
| 124 | } |
| 125 | |
| 126 | static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) |
| 127 | { |
| 128 | ((Pcc *)hw)->IER.reg = data; |
| 129 | ((Pcc *)hw)->IDR.reg = ~data; |
| 130 | } |
| 131 | |
| 132 | static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) |
| 133 | { |
| 134 | ((Pcc *)hw)->IDR.reg = mask; |
| 135 | } |
| 136 | |
| 137 | static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) |
| 138 | { |
| 139 | return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; |
| 140 | } |
| 141 | |
| 142 | static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) |
| 143 | { |
| 144 | return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; |
| 145 | } |
| 146 | |
| 147 | static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) |
| 148 | { |
| 149 | uint32_t tmp; |
| 150 | tmp = ((Pcc *)hw)->ISR.reg; |
| 151 | tmp &= mask; |
| 152 | return tmp; |
| 153 | } |
| 154 | |
| 155 | static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) |
| 156 | { |
| 157 | return ((Pcc *)hw)->ISR.reg; |
| 158 | } |
| 159 | |
| 160 | static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) |
| 161 | { |
| 162 | return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; |
| 163 | } |
| 164 | |
| 165 | static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) |
| 166 | { |
| 167 | return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; |
| 168 | } |
| 169 | |
| 170 | static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) |
| 171 | { |
| 172 | uint32_t tmp; |
| 173 | tmp = ((Pcc *)hw)->RHR.reg; |
| 174 | tmp &= mask; |
| 175 | return tmp; |
| 176 | } |
| 177 | |
| 178 | static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) |
| 179 | { |
| 180 | return ((Pcc *)hw)->RHR.reg; |
| 181 | } |
| 182 | |
| 183 | static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) |
| 184 | { |
| 185 | return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; |
| 186 | } |
| 187 | |
| 188 | static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) |
| 189 | { |
| 190 | return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; |
| 191 | } |
| 192 | |
| 193 | static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) |
| 194 | { |
| 195 | return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; |
| 196 | } |
| 197 | |
| 198 | static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) |
| 199 | { |
| 200 | uint32_t tmp; |
| 201 | tmp = ((Pcc *)hw)->WPSR.reg; |
| 202 | tmp &= mask; |
| 203 | return tmp; |
| 204 | } |
| 205 | |
| 206 | static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) |
| 207 | { |
| 208 | return ((Pcc *)hw)->WPSR.reg; |
| 209 | } |
| 210 | |
| 211 | static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) |
| 212 | { |
| 213 | PCC_CRITICAL_SECTION_ENTER(); |
| 214 | ((Pcc *)hw)->MR.reg |= mask; |
| 215 | PCC_CRITICAL_SECTION_LEAVE(); |
| 216 | } |
| 217 | |
| 218 | static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) |
| 219 | { |
| 220 | uint32_t tmp; |
| 221 | tmp = ((Pcc *)hw)->MR.reg; |
| 222 | tmp &= mask; |
| 223 | return tmp; |
| 224 | } |
| 225 | |
| 226 | static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) |
| 227 | { |
| 228 | PCC_CRITICAL_SECTION_ENTER(); |
| 229 | ((Pcc *)hw)->MR.reg = data; |
| 230 | PCC_CRITICAL_SECTION_LEAVE(); |
| 231 | } |
| 232 | |
| 233 | static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) |
| 234 | { |
| 235 | PCC_CRITICAL_SECTION_ENTER(); |
| 236 | ((Pcc *)hw)->MR.reg &= ~mask; |
| 237 | PCC_CRITICAL_SECTION_LEAVE(); |
| 238 | } |
| 239 | |
| 240 | static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) |
| 241 | { |
| 242 | PCC_CRITICAL_SECTION_ENTER(); |
| 243 | ((Pcc *)hw)->MR.reg ^= mask; |
| 244 | PCC_CRITICAL_SECTION_LEAVE(); |
| 245 | } |
| 246 | |
| 247 | static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) |
| 248 | { |
| 249 | return ((Pcc *)hw)->MR.reg; |
| 250 | } |
| 251 | |
| 252 | static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) |
| 253 | { |
| 254 | PCC_CRITICAL_SECTION_ENTER(); |
| 255 | ((Pcc *)hw)->WPMR.reg |= mask; |
| 256 | PCC_CRITICAL_SECTION_LEAVE(); |
| 257 | } |
| 258 | |
| 259 | static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) |
| 260 | { |
| 261 | uint32_t tmp; |
| 262 | tmp = ((Pcc *)hw)->WPMR.reg; |
| 263 | tmp &= mask; |
| 264 | return tmp; |
| 265 | } |
| 266 | |
| 267 | static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) |
| 268 | { |
| 269 | PCC_CRITICAL_SECTION_ENTER(); |
| 270 | ((Pcc *)hw)->WPMR.reg = data; |
| 271 | PCC_CRITICAL_SECTION_LEAVE(); |
| 272 | } |
| 273 | |
| 274 | static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) |
| 275 | { |
| 276 | PCC_CRITICAL_SECTION_ENTER(); |
| 277 | ((Pcc *)hw)->WPMR.reg &= ~mask; |
| 278 | PCC_CRITICAL_SECTION_LEAVE(); |
| 279 | } |
| 280 | |
| 281 | static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) |
| 282 | { |
| 283 | PCC_CRITICAL_SECTION_ENTER(); |
| 284 | ((Pcc *)hw)->WPMR.reg ^= mask; |
| 285 | PCC_CRITICAL_SECTION_LEAVE(); |
| 286 | } |
| 287 | |
| 288 | static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) |
| 289 | { |
| 290 | return ((Pcc *)hw)->WPMR.reg; |
| 291 | } |
| 292 | |
| 293 | #ifdef __cplusplus |
| 294 | } |
| 295 | #endif |
| 296 | |
| 297 | #endif /* _HRI_PCC_E54_H_INCLUDED */ |
| 298 | #endif /* _SAME54_PCC_COMPONENT_ */ |