Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM GCLK |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_GCLK_COMPONENT_ |
| 35 | #ifndef _HRI_GCLK_E54_H_INCLUDED_ |
| 36 | #define _HRI_GCLK_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_GCLK_CRITICAL_SECTIONS) |
| 46 | #define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define GCLK_CRITICAL_SECTION_ENTER() |
| 50 | #define GCLK_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_gclk_genctrl_reg_t; |
| 54 | typedef uint32_t hri_gclk_pchctrl_reg_t; |
| 55 | typedef uint32_t hri_gclk_syncbusy_reg_t; |
| 56 | typedef uint8_t hri_gclk_ctrla_reg_t; |
| 57 | |
| 58 | static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) |
| 59 | { |
| 60 | while (((Gclk *)hw)->SYNCBUSY.reg & reg) { |
| 61 | }; |
| 62 | } |
| 63 | |
| 64 | static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) |
| 65 | { |
| 66 | return ((Gclk *)hw)->SYNCBUSY.reg & reg; |
| 67 | } |
| 68 | |
| 69 | static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 70 | { |
| 71 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; |
| 72 | } |
| 73 | |
| 74 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) |
| 75 | { |
| 76 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; |
| 77 | } |
| 78 | |
| 79 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) |
| 80 | { |
| 81 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; |
| 82 | } |
| 83 | |
| 84 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) |
| 85 | { |
| 86 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; |
| 87 | } |
| 88 | |
| 89 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) |
| 90 | { |
| 91 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; |
| 92 | } |
| 93 | |
| 94 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) |
| 95 | { |
| 96 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; |
| 97 | } |
| 98 | |
| 99 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) |
| 100 | { |
| 101 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; |
| 102 | } |
| 103 | |
| 104 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) |
| 105 | { |
| 106 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; |
| 107 | } |
| 108 | |
| 109 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) |
| 110 | { |
| 111 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; |
| 112 | } |
| 113 | |
| 114 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) |
| 115 | { |
| 116 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; |
| 117 | } |
| 118 | |
| 119 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) |
| 120 | { |
| 121 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; |
| 122 | } |
| 123 | |
| 124 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) |
| 125 | { |
| 126 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; |
| 127 | } |
| 128 | |
| 129 | static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) |
| 130 | { |
| 131 | return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; |
| 132 | } |
| 133 | |
| 134 | static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) |
| 135 | { |
| 136 | uint32_t tmp; |
| 137 | tmp = ((Gclk *)hw)->SYNCBUSY.reg; |
| 138 | tmp &= mask; |
| 139 | return tmp; |
| 140 | } |
| 141 | |
| 142 | static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) |
| 143 | { |
| 144 | return ((Gclk *)hw)->SYNCBUSY.reg; |
| 145 | } |
| 146 | |
| 147 | static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) |
| 148 | { |
| 149 | GCLK_CRITICAL_SECTION_ENTER(); |
| 150 | ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; |
| 151 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 152 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 153 | } |
| 154 | |
| 155 | static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) |
| 156 | { |
| 157 | uint8_t tmp; |
| 158 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 159 | tmp = ((Gclk *)hw)->CTRLA.reg; |
| 160 | tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; |
| 161 | return (bool)tmp; |
| 162 | } |
| 163 | |
| 164 | static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) |
| 165 | { |
| 166 | GCLK_CRITICAL_SECTION_ENTER(); |
| 167 | ((Gclk *)hw)->CTRLA.reg |= mask; |
| 168 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 169 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 170 | } |
| 171 | |
| 172 | static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) |
| 173 | { |
| 174 | uint8_t tmp; |
| 175 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 176 | tmp = ((Gclk *)hw)->CTRLA.reg; |
| 177 | tmp &= mask; |
| 178 | return tmp; |
| 179 | } |
| 180 | |
| 181 | static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) |
| 182 | { |
| 183 | GCLK_CRITICAL_SECTION_ENTER(); |
| 184 | ((Gclk *)hw)->CTRLA.reg = data; |
| 185 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 186 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 187 | } |
| 188 | |
| 189 | static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) |
| 190 | { |
| 191 | GCLK_CRITICAL_SECTION_ENTER(); |
| 192 | ((Gclk *)hw)->CTRLA.reg &= ~mask; |
| 193 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 194 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 195 | } |
| 196 | |
| 197 | static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) |
| 198 | { |
| 199 | GCLK_CRITICAL_SECTION_ENTER(); |
| 200 | ((Gclk *)hw)->CTRLA.reg ^= mask; |
| 201 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 202 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 203 | } |
| 204 | |
| 205 | static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) |
| 206 | { |
| 207 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); |
| 208 | return ((Gclk *)hw)->CTRLA.reg; |
| 209 | } |
| 210 | |
| 211 | static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) |
| 212 | { |
| 213 | GCLK_CRITICAL_SECTION_ENTER(); |
| 214 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; |
| 215 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 216 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 217 | } |
| 218 | |
| 219 | static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) |
| 220 | { |
| 221 | uint32_t tmp; |
| 222 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 223 | tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; |
| 224 | return (bool)tmp; |
| 225 | } |
| 226 | |
| 227 | static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) |
| 228 | { |
| 229 | uint32_t tmp; |
| 230 | GCLK_CRITICAL_SECTION_ENTER(); |
| 231 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 232 | tmp &= ~GCLK_GENCTRL_GENEN; |
| 233 | tmp |= value << GCLK_GENCTRL_GENEN_Pos; |
| 234 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 235 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 236 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 237 | } |
| 238 | |
| 239 | static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) |
| 240 | { |
| 241 | GCLK_CRITICAL_SECTION_ENTER(); |
| 242 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; |
| 243 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 244 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 245 | } |
| 246 | |
| 247 | static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) |
| 248 | { |
| 249 | GCLK_CRITICAL_SECTION_ENTER(); |
| 250 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; |
| 251 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 252 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 253 | } |
| 254 | |
| 255 | static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) |
| 256 | { |
| 257 | GCLK_CRITICAL_SECTION_ENTER(); |
| 258 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; |
| 259 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 260 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 261 | } |
| 262 | |
| 263 | static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) |
| 264 | { |
| 265 | uint32_t tmp; |
| 266 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 267 | tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; |
| 268 | return (bool)tmp; |
| 269 | } |
| 270 | |
| 271 | static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) |
| 272 | { |
| 273 | uint32_t tmp; |
| 274 | GCLK_CRITICAL_SECTION_ENTER(); |
| 275 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 276 | tmp &= ~GCLK_GENCTRL_IDC; |
| 277 | tmp |= value << GCLK_GENCTRL_IDC_Pos; |
| 278 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 279 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 280 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 281 | } |
| 282 | |
| 283 | static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) |
| 284 | { |
| 285 | GCLK_CRITICAL_SECTION_ENTER(); |
| 286 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; |
| 287 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 288 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 289 | } |
| 290 | |
| 291 | static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) |
| 292 | { |
| 293 | GCLK_CRITICAL_SECTION_ENTER(); |
| 294 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; |
| 295 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 296 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 297 | } |
| 298 | |
| 299 | static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) |
| 300 | { |
| 301 | GCLK_CRITICAL_SECTION_ENTER(); |
| 302 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; |
| 303 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 304 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 305 | } |
| 306 | |
| 307 | static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) |
| 308 | { |
| 309 | uint32_t tmp; |
| 310 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 311 | tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; |
| 312 | return (bool)tmp; |
| 313 | } |
| 314 | |
| 315 | static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) |
| 316 | { |
| 317 | uint32_t tmp; |
| 318 | GCLK_CRITICAL_SECTION_ENTER(); |
| 319 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 320 | tmp &= ~GCLK_GENCTRL_OOV; |
| 321 | tmp |= value << GCLK_GENCTRL_OOV_Pos; |
| 322 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 323 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 324 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 325 | } |
| 326 | |
| 327 | static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) |
| 328 | { |
| 329 | GCLK_CRITICAL_SECTION_ENTER(); |
| 330 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; |
| 331 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 332 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 333 | } |
| 334 | |
| 335 | static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) |
| 336 | { |
| 337 | GCLK_CRITICAL_SECTION_ENTER(); |
| 338 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; |
| 339 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 340 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 341 | } |
| 342 | |
| 343 | static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) |
| 344 | { |
| 345 | GCLK_CRITICAL_SECTION_ENTER(); |
| 346 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; |
| 347 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 348 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 349 | } |
| 350 | |
| 351 | static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) |
| 352 | { |
| 353 | uint32_t tmp; |
| 354 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 355 | tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; |
| 356 | return (bool)tmp; |
| 357 | } |
| 358 | |
| 359 | static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) |
| 360 | { |
| 361 | uint32_t tmp; |
| 362 | GCLK_CRITICAL_SECTION_ENTER(); |
| 363 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 364 | tmp &= ~GCLK_GENCTRL_OE; |
| 365 | tmp |= value << GCLK_GENCTRL_OE_Pos; |
| 366 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 367 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 368 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 369 | } |
| 370 | |
| 371 | static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) |
| 372 | { |
| 373 | GCLK_CRITICAL_SECTION_ENTER(); |
| 374 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; |
| 375 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 376 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 377 | } |
| 378 | |
| 379 | static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) |
| 380 | { |
| 381 | GCLK_CRITICAL_SECTION_ENTER(); |
| 382 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; |
| 383 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 384 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 385 | } |
| 386 | |
| 387 | static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) |
| 388 | { |
| 389 | GCLK_CRITICAL_SECTION_ENTER(); |
| 390 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; |
| 391 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 392 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 393 | } |
| 394 | |
| 395 | static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) |
| 396 | { |
| 397 | uint32_t tmp; |
| 398 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 399 | tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; |
| 400 | return (bool)tmp; |
| 401 | } |
| 402 | |
| 403 | static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) |
| 404 | { |
| 405 | uint32_t tmp; |
| 406 | GCLK_CRITICAL_SECTION_ENTER(); |
| 407 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 408 | tmp &= ~GCLK_GENCTRL_DIVSEL; |
| 409 | tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; |
| 410 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 411 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 412 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 413 | } |
| 414 | |
| 415 | static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) |
| 416 | { |
| 417 | GCLK_CRITICAL_SECTION_ENTER(); |
| 418 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; |
| 419 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 420 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 421 | } |
| 422 | |
| 423 | static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) |
| 424 | { |
| 425 | GCLK_CRITICAL_SECTION_ENTER(); |
| 426 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; |
| 427 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 428 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 429 | } |
| 430 | |
| 431 | static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 432 | { |
| 433 | GCLK_CRITICAL_SECTION_ENTER(); |
| 434 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; |
| 435 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 436 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 437 | } |
| 438 | |
| 439 | static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 440 | { |
| 441 | uint32_t tmp; |
| 442 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 443 | tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; |
| 444 | return (bool)tmp; |
| 445 | } |
| 446 | |
| 447 | static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) |
| 448 | { |
| 449 | uint32_t tmp; |
| 450 | GCLK_CRITICAL_SECTION_ENTER(); |
| 451 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 452 | tmp &= ~GCLK_GENCTRL_RUNSTDBY; |
| 453 | tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; |
| 454 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 455 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 456 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 457 | } |
| 458 | |
| 459 | static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 460 | { |
| 461 | GCLK_CRITICAL_SECTION_ENTER(); |
| 462 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; |
| 463 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 464 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 465 | } |
| 466 | |
| 467 | static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 468 | { |
| 469 | GCLK_CRITICAL_SECTION_ENTER(); |
| 470 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; |
| 471 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 472 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 473 | } |
| 474 | |
| 475 | static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 476 | { |
| 477 | GCLK_CRITICAL_SECTION_ENTER(); |
| 478 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); |
| 479 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 480 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 481 | } |
| 482 | |
| 483 | static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, |
| 484 | hri_gclk_genctrl_reg_t mask) |
| 485 | { |
| 486 | uint32_t tmp; |
| 487 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 488 | tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; |
| 489 | return tmp; |
| 490 | } |
| 491 | |
| 492 | static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) |
| 493 | { |
| 494 | uint32_t tmp; |
| 495 | GCLK_CRITICAL_SECTION_ENTER(); |
| 496 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 497 | tmp &= ~GCLK_GENCTRL_SRC_Msk; |
| 498 | tmp |= GCLK_GENCTRL_SRC(data); |
| 499 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 500 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 501 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 502 | } |
| 503 | |
| 504 | static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 505 | { |
| 506 | GCLK_CRITICAL_SECTION_ENTER(); |
| 507 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); |
| 508 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 509 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 510 | } |
| 511 | |
| 512 | static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 513 | { |
| 514 | GCLK_CRITICAL_SECTION_ENTER(); |
| 515 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); |
| 516 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 517 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 518 | } |
| 519 | |
| 520 | static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) |
| 521 | { |
| 522 | uint32_t tmp; |
| 523 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 524 | tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; |
| 525 | return tmp; |
| 526 | } |
| 527 | |
| 528 | static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 529 | { |
| 530 | GCLK_CRITICAL_SECTION_ENTER(); |
| 531 | ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); |
| 532 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 533 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 534 | } |
| 535 | |
| 536 | static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, |
| 537 | hri_gclk_genctrl_reg_t mask) |
| 538 | { |
| 539 | uint32_t tmp; |
| 540 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 541 | tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; |
| 542 | return tmp; |
| 543 | } |
| 544 | |
| 545 | static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) |
| 546 | { |
| 547 | uint32_t tmp; |
| 548 | GCLK_CRITICAL_SECTION_ENTER(); |
| 549 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 550 | tmp &= ~GCLK_GENCTRL_DIV_Msk; |
| 551 | tmp |= GCLK_GENCTRL_DIV(data); |
| 552 | ((Gclk *)hw)->GENCTRL[index].reg = tmp; |
| 553 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 554 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 555 | } |
| 556 | |
| 557 | static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 558 | { |
| 559 | GCLK_CRITICAL_SECTION_ENTER(); |
| 560 | ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); |
| 561 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 562 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 563 | } |
| 564 | |
| 565 | static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 566 | { |
| 567 | GCLK_CRITICAL_SECTION_ENTER(); |
| 568 | ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); |
| 569 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 570 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 571 | } |
| 572 | |
| 573 | static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) |
| 574 | { |
| 575 | uint32_t tmp; |
| 576 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 577 | tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; |
| 578 | return tmp; |
| 579 | } |
| 580 | |
| 581 | static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 582 | { |
| 583 | GCLK_CRITICAL_SECTION_ENTER(); |
| 584 | ((Gclk *)hw)->GENCTRL[index].reg |= mask; |
| 585 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 586 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 587 | } |
| 588 | |
| 589 | static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, |
| 590 | hri_gclk_genctrl_reg_t mask) |
| 591 | { |
| 592 | uint32_t tmp; |
| 593 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 594 | tmp = ((Gclk *)hw)->GENCTRL[index].reg; |
| 595 | tmp &= mask; |
| 596 | return tmp; |
| 597 | } |
| 598 | |
| 599 | static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) |
| 600 | { |
| 601 | GCLK_CRITICAL_SECTION_ENTER(); |
| 602 | ((Gclk *)hw)->GENCTRL[index].reg = data; |
| 603 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 604 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 605 | } |
| 606 | |
| 607 | static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 608 | { |
| 609 | GCLK_CRITICAL_SECTION_ENTER(); |
| 610 | ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; |
| 611 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 612 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 613 | } |
| 614 | |
| 615 | static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) |
| 616 | { |
| 617 | GCLK_CRITICAL_SECTION_ENTER(); |
| 618 | ((Gclk *)hw)->GENCTRL[index].reg ^= mask; |
| 619 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 620 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 621 | } |
| 622 | |
| 623 | static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) |
| 624 | { |
| 625 | hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); |
| 626 | return ((Gclk *)hw)->GENCTRL[index].reg; |
| 627 | } |
| 628 | |
| 629 | static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) |
| 630 | { |
| 631 | GCLK_CRITICAL_SECTION_ENTER(); |
| 632 | ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; |
| 633 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 634 | } |
| 635 | |
| 636 | static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) |
| 637 | { |
| 638 | uint32_t tmp; |
| 639 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 640 | tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; |
| 641 | return (bool)tmp; |
| 642 | } |
| 643 | |
| 644 | static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) |
| 645 | { |
| 646 | uint32_t tmp; |
| 647 | GCLK_CRITICAL_SECTION_ENTER(); |
| 648 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 649 | tmp &= ~GCLK_PCHCTRL_CHEN; |
| 650 | tmp |= value << GCLK_PCHCTRL_CHEN_Pos; |
| 651 | ((Gclk *)hw)->PCHCTRL[index].reg = tmp; |
| 652 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 653 | } |
| 654 | |
| 655 | static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) |
| 656 | { |
| 657 | GCLK_CRITICAL_SECTION_ENTER(); |
| 658 | ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; |
| 659 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 660 | } |
| 661 | |
| 662 | static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) |
| 663 | { |
| 664 | GCLK_CRITICAL_SECTION_ENTER(); |
| 665 | ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; |
| 666 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 667 | } |
| 668 | |
| 669 | static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) |
| 670 | { |
| 671 | GCLK_CRITICAL_SECTION_ENTER(); |
| 672 | ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; |
| 673 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 674 | } |
| 675 | |
| 676 | static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) |
| 677 | { |
| 678 | uint32_t tmp; |
| 679 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 680 | tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; |
| 681 | return (bool)tmp; |
| 682 | } |
| 683 | |
| 684 | static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) |
| 685 | { |
| 686 | uint32_t tmp; |
| 687 | GCLK_CRITICAL_SECTION_ENTER(); |
| 688 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 689 | tmp &= ~GCLK_PCHCTRL_WRTLOCK; |
| 690 | tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; |
| 691 | ((Gclk *)hw)->PCHCTRL[index].reg = tmp; |
| 692 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 693 | } |
| 694 | |
| 695 | static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) |
| 696 | { |
| 697 | GCLK_CRITICAL_SECTION_ENTER(); |
| 698 | ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; |
| 699 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 700 | } |
| 701 | |
| 702 | static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) |
| 703 | { |
| 704 | GCLK_CRITICAL_SECTION_ENTER(); |
| 705 | ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; |
| 706 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 707 | } |
| 708 | |
| 709 | static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) |
| 710 | { |
| 711 | GCLK_CRITICAL_SECTION_ENTER(); |
| 712 | ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); |
| 713 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 714 | } |
| 715 | |
| 716 | static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, |
| 717 | hri_gclk_pchctrl_reg_t mask) |
| 718 | { |
| 719 | uint32_t tmp; |
| 720 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 721 | tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; |
| 722 | return tmp; |
| 723 | } |
| 724 | |
| 725 | static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) |
| 726 | { |
| 727 | uint32_t tmp; |
| 728 | GCLK_CRITICAL_SECTION_ENTER(); |
| 729 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 730 | tmp &= ~GCLK_PCHCTRL_GEN_Msk; |
| 731 | tmp |= GCLK_PCHCTRL_GEN(data); |
| 732 | ((Gclk *)hw)->PCHCTRL[index].reg = tmp; |
| 733 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 734 | } |
| 735 | |
| 736 | static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) |
| 737 | { |
| 738 | GCLK_CRITICAL_SECTION_ENTER(); |
| 739 | ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); |
| 740 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 741 | } |
| 742 | |
| 743 | static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) |
| 744 | { |
| 745 | GCLK_CRITICAL_SECTION_ENTER(); |
| 746 | ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); |
| 747 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 748 | } |
| 749 | |
| 750 | static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) |
| 751 | { |
| 752 | uint32_t tmp; |
| 753 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 754 | tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; |
| 755 | return tmp; |
| 756 | } |
| 757 | |
| 758 | static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) |
| 759 | { |
| 760 | GCLK_CRITICAL_SECTION_ENTER(); |
| 761 | ((Gclk *)hw)->PCHCTRL[index].reg |= mask; |
| 762 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 763 | } |
| 764 | |
| 765 | static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, |
| 766 | hri_gclk_pchctrl_reg_t mask) |
| 767 | { |
| 768 | uint32_t tmp; |
| 769 | tmp = ((Gclk *)hw)->PCHCTRL[index].reg; |
| 770 | tmp &= mask; |
| 771 | return tmp; |
| 772 | } |
| 773 | |
| 774 | static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) |
| 775 | { |
| 776 | GCLK_CRITICAL_SECTION_ENTER(); |
| 777 | ((Gclk *)hw)->PCHCTRL[index].reg = data; |
| 778 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 779 | } |
| 780 | |
| 781 | static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) |
| 782 | { |
| 783 | GCLK_CRITICAL_SECTION_ENTER(); |
| 784 | ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; |
| 785 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 786 | } |
| 787 | |
| 788 | static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) |
| 789 | { |
| 790 | GCLK_CRITICAL_SECTION_ENTER(); |
| 791 | ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; |
| 792 | GCLK_CRITICAL_SECTION_LEAVE(); |
| 793 | } |
| 794 | |
| 795 | static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) |
| 796 | { |
| 797 | return ((Gclk *)hw)->PCHCTRL[index].reg; |
| 798 | } |
| 799 | |
| 800 | #ifdef __cplusplus |
| 801 | } |
| 802 | #endif |
| 803 | |
| 804 | #endif /* _HRI_GCLK_E54_H_INCLUDED */ |
| 805 | #endif /* _SAME54_GCLK_COMPONENT_ */ |