Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM EIC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_EIC_COMPONENT_ |
| 35 | #ifndef _HRI_EIC_E54_H_INCLUDED_ |
| 36 | #define _HRI_EIC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_EIC_CRITICAL_SECTIONS) |
| 46 | #define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define EIC_CRITICAL_SECTION_ENTER() |
| 50 | #define EIC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_eic_nmiflag_reg_t; |
| 54 | typedef uint32_t hri_eic_asynch_reg_t; |
| 55 | typedef uint32_t hri_eic_config_reg_t; |
| 56 | typedef uint32_t hri_eic_debouncen_reg_t; |
| 57 | typedef uint32_t hri_eic_dprescaler_reg_t; |
| 58 | typedef uint32_t hri_eic_evctrl_reg_t; |
| 59 | typedef uint32_t hri_eic_intenset_reg_t; |
| 60 | typedef uint32_t hri_eic_intflag_reg_t; |
| 61 | typedef uint32_t hri_eic_pinstate_reg_t; |
| 62 | typedef uint32_t hri_eic_syncbusy_reg_t; |
| 63 | typedef uint8_t hri_eic_ctrla_reg_t; |
| 64 | typedef uint8_t hri_eic_nmictrl_reg_t; |
| 65 | |
| 66 | static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) |
| 67 | { |
| 68 | while (((Eic *)hw)->SYNCBUSY.reg & reg) { |
| 69 | }; |
| 70 | } |
| 71 | |
| 72 | static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) |
| 73 | { |
| 74 | return ((Eic *)hw)->SYNCBUSY.reg & reg; |
| 75 | } |
| 76 | |
| 77 | static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) |
| 78 | { |
| 79 | return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; |
| 80 | } |
| 81 | |
| 82 | static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) |
| 83 | { |
| 84 | ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; |
| 85 | } |
| 86 | |
| 87 | static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) |
| 88 | { |
| 89 | uint16_t tmp; |
| 90 | tmp = ((Eic *)hw)->NMIFLAG.reg; |
| 91 | tmp &= mask; |
| 92 | return tmp; |
| 93 | } |
| 94 | |
| 95 | static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) |
| 96 | { |
| 97 | return ((Eic *)hw)->NMIFLAG.reg; |
| 98 | } |
| 99 | |
| 100 | static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) |
| 101 | { |
| 102 | ((Eic *)hw)->NMIFLAG.reg = mask; |
| 103 | } |
| 104 | |
| 105 | static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) |
| 106 | { |
| 107 | uint32_t tmp; |
| 108 | tmp = ((Eic *)hw)->INTFLAG.reg; |
| 109 | tmp &= mask; |
| 110 | return tmp; |
| 111 | } |
| 112 | |
| 113 | static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) |
| 114 | { |
| 115 | return ((Eic *)hw)->INTFLAG.reg; |
| 116 | } |
| 117 | |
| 118 | static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) |
| 119 | { |
| 120 | ((Eic *)hw)->INTFLAG.reg = mask; |
| 121 | } |
| 122 | |
| 123 | static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) |
| 124 | { |
| 125 | ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); |
| 126 | } |
| 127 | |
| 128 | static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) |
| 129 | { |
| 130 | uint32_t tmp; |
| 131 | tmp = ((Eic *)hw)->INTENSET.reg; |
| 132 | tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; |
| 133 | return tmp; |
| 134 | } |
| 135 | |
| 136 | static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) |
| 137 | { |
| 138 | uint32_t tmp; |
| 139 | tmp = ((Eic *)hw)->INTENSET.reg; |
| 140 | tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; |
| 141 | return tmp; |
| 142 | } |
| 143 | |
| 144 | static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) |
| 145 | { |
| 146 | ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); |
| 147 | ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); |
| 148 | } |
| 149 | |
| 150 | static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) |
| 151 | { |
| 152 | ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); |
| 153 | } |
| 154 | |
| 155 | static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) |
| 156 | { |
| 157 | ((Eic *)hw)->INTENSET.reg = mask; |
| 158 | } |
| 159 | |
| 160 | static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) |
| 161 | { |
| 162 | uint32_t tmp; |
| 163 | tmp = ((Eic *)hw)->INTENSET.reg; |
| 164 | tmp &= mask; |
| 165 | return tmp; |
| 166 | } |
| 167 | |
| 168 | static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) |
| 169 | { |
| 170 | return ((Eic *)hw)->INTENSET.reg; |
| 171 | } |
| 172 | |
| 173 | static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) |
| 174 | { |
| 175 | ((Eic *)hw)->INTENSET.reg = data; |
| 176 | ((Eic *)hw)->INTENCLR.reg = ~data; |
| 177 | } |
| 178 | |
| 179 | static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) |
| 180 | { |
| 181 | ((Eic *)hw)->INTENCLR.reg = mask; |
| 182 | } |
| 183 | |
| 184 | static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 185 | { |
| 186 | return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; |
| 187 | } |
| 188 | |
| 189 | static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 190 | { |
| 191 | return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; |
| 192 | } |
| 193 | |
| 194 | static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) |
| 195 | { |
| 196 | uint32_t tmp; |
| 197 | tmp = ((Eic *)hw)->SYNCBUSY.reg; |
| 198 | tmp &= mask; |
| 199 | return tmp; |
| 200 | } |
| 201 | |
| 202 | static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) |
| 203 | { |
| 204 | return ((Eic *)hw)->SYNCBUSY.reg; |
| 205 | } |
| 206 | |
| 207 | static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) |
| 208 | { |
| 209 | return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; |
| 210 | } |
| 211 | |
| 212 | static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) |
| 213 | { |
| 214 | return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; |
| 215 | } |
| 216 | |
| 217 | static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) |
| 218 | { |
| 219 | uint32_t tmp; |
| 220 | tmp = ((Eic *)hw)->PINSTATE.reg; |
| 221 | tmp &= mask; |
| 222 | return tmp; |
| 223 | } |
| 224 | |
| 225 | static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) |
| 226 | { |
| 227 | return ((Eic *)hw)->PINSTATE.reg; |
| 228 | } |
| 229 | |
| 230 | static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) |
| 231 | { |
| 232 | EIC_CRITICAL_SECTION_ENTER(); |
| 233 | ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; |
| 234 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); |
| 235 | EIC_CRITICAL_SECTION_LEAVE(); |
| 236 | } |
| 237 | |
| 238 | static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) |
| 239 | { |
| 240 | uint8_t tmp; |
| 241 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); |
| 242 | tmp = ((Eic *)hw)->CTRLA.reg; |
| 243 | tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; |
| 244 | return (bool)tmp; |
| 245 | } |
| 246 | |
| 247 | static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) |
| 248 | { |
| 249 | EIC_CRITICAL_SECTION_ENTER(); |
| 250 | ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; |
| 251 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); |
| 252 | EIC_CRITICAL_SECTION_LEAVE(); |
| 253 | } |
| 254 | |
| 255 | static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) |
| 256 | { |
| 257 | uint8_t tmp; |
| 258 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); |
| 259 | tmp = ((Eic *)hw)->CTRLA.reg; |
| 260 | tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; |
| 261 | return (bool)tmp; |
| 262 | } |
| 263 | |
| 264 | static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 265 | { |
| 266 | uint8_t tmp; |
| 267 | EIC_CRITICAL_SECTION_ENTER(); |
| 268 | tmp = ((Eic *)hw)->CTRLA.reg; |
| 269 | tmp &= ~EIC_CTRLA_ENABLE; |
| 270 | tmp |= value << EIC_CTRLA_ENABLE_Pos; |
| 271 | ((Eic *)hw)->CTRLA.reg = tmp; |
| 272 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); |
| 273 | EIC_CRITICAL_SECTION_LEAVE(); |
| 274 | } |
| 275 | |
| 276 | static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 277 | { |
| 278 | EIC_CRITICAL_SECTION_ENTER(); |
| 279 | ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; |
| 280 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); |
| 281 | EIC_CRITICAL_SECTION_LEAVE(); |
| 282 | } |
| 283 | |
| 284 | static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 285 | { |
| 286 | EIC_CRITICAL_SECTION_ENTER(); |
| 287 | ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; |
| 288 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); |
| 289 | EIC_CRITICAL_SECTION_LEAVE(); |
| 290 | } |
| 291 | |
| 292 | static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) |
| 293 | { |
| 294 | EIC_CRITICAL_SECTION_ENTER(); |
| 295 | ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; |
| 296 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 297 | EIC_CRITICAL_SECTION_LEAVE(); |
| 298 | } |
| 299 | |
| 300 | static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) |
| 301 | { |
| 302 | uint8_t tmp; |
| 303 | tmp = ((Eic *)hw)->CTRLA.reg; |
| 304 | tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; |
| 305 | return (bool)tmp; |
| 306 | } |
| 307 | |
| 308 | static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) |
| 309 | { |
| 310 | uint8_t tmp; |
| 311 | EIC_CRITICAL_SECTION_ENTER(); |
| 312 | tmp = ((Eic *)hw)->CTRLA.reg; |
| 313 | tmp &= ~EIC_CTRLA_CKSEL; |
| 314 | tmp |= value << EIC_CTRLA_CKSEL_Pos; |
| 315 | ((Eic *)hw)->CTRLA.reg = tmp; |
| 316 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 317 | EIC_CRITICAL_SECTION_LEAVE(); |
| 318 | } |
| 319 | |
| 320 | static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) |
| 321 | { |
| 322 | EIC_CRITICAL_SECTION_ENTER(); |
| 323 | ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; |
| 324 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 325 | EIC_CRITICAL_SECTION_LEAVE(); |
| 326 | } |
| 327 | |
| 328 | static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) |
| 329 | { |
| 330 | EIC_CRITICAL_SECTION_ENTER(); |
| 331 | ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; |
| 332 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 333 | EIC_CRITICAL_SECTION_LEAVE(); |
| 334 | } |
| 335 | |
| 336 | static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) |
| 337 | { |
| 338 | EIC_CRITICAL_SECTION_ENTER(); |
| 339 | ((Eic *)hw)->CTRLA.reg |= mask; |
| 340 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 341 | EIC_CRITICAL_SECTION_LEAVE(); |
| 342 | } |
| 343 | |
| 344 | static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) |
| 345 | { |
| 346 | uint8_t tmp; |
| 347 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 348 | tmp = ((Eic *)hw)->CTRLA.reg; |
| 349 | tmp &= mask; |
| 350 | return tmp; |
| 351 | } |
| 352 | |
| 353 | static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) |
| 354 | { |
| 355 | EIC_CRITICAL_SECTION_ENTER(); |
| 356 | ((Eic *)hw)->CTRLA.reg = data; |
| 357 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 358 | EIC_CRITICAL_SECTION_LEAVE(); |
| 359 | } |
| 360 | |
| 361 | static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) |
| 362 | { |
| 363 | EIC_CRITICAL_SECTION_ENTER(); |
| 364 | ((Eic *)hw)->CTRLA.reg &= ~mask; |
| 365 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 366 | EIC_CRITICAL_SECTION_LEAVE(); |
| 367 | } |
| 368 | |
| 369 | static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) |
| 370 | { |
| 371 | EIC_CRITICAL_SECTION_ENTER(); |
| 372 | ((Eic *)hw)->CTRLA.reg ^= mask; |
| 373 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 374 | EIC_CRITICAL_SECTION_LEAVE(); |
| 375 | } |
| 376 | |
| 377 | static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) |
| 378 | { |
| 379 | hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); |
| 380 | return ((Eic *)hw)->CTRLA.reg; |
| 381 | } |
| 382 | |
| 383 | static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) |
| 384 | { |
| 385 | EIC_CRITICAL_SECTION_ENTER(); |
| 386 | ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; |
| 387 | EIC_CRITICAL_SECTION_LEAVE(); |
| 388 | } |
| 389 | |
| 390 | static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) |
| 391 | { |
| 392 | uint8_t tmp; |
| 393 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 394 | tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; |
| 395 | return (bool)tmp; |
| 396 | } |
| 397 | |
| 398 | static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) |
| 399 | { |
| 400 | uint8_t tmp; |
| 401 | EIC_CRITICAL_SECTION_ENTER(); |
| 402 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 403 | tmp &= ~EIC_NMICTRL_NMIFILTEN; |
| 404 | tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; |
| 405 | ((Eic *)hw)->NMICTRL.reg = tmp; |
| 406 | EIC_CRITICAL_SECTION_LEAVE(); |
| 407 | } |
| 408 | |
| 409 | static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) |
| 410 | { |
| 411 | EIC_CRITICAL_SECTION_ENTER(); |
| 412 | ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; |
| 413 | EIC_CRITICAL_SECTION_LEAVE(); |
| 414 | } |
| 415 | |
| 416 | static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) |
| 417 | { |
| 418 | EIC_CRITICAL_SECTION_ENTER(); |
| 419 | ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; |
| 420 | EIC_CRITICAL_SECTION_LEAVE(); |
| 421 | } |
| 422 | |
| 423 | static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) |
| 424 | { |
| 425 | EIC_CRITICAL_SECTION_ENTER(); |
| 426 | ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; |
| 427 | EIC_CRITICAL_SECTION_LEAVE(); |
| 428 | } |
| 429 | |
| 430 | static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) |
| 431 | { |
| 432 | uint8_t tmp; |
| 433 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 434 | tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; |
| 435 | return (bool)tmp; |
| 436 | } |
| 437 | |
| 438 | static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) |
| 439 | { |
| 440 | uint8_t tmp; |
| 441 | EIC_CRITICAL_SECTION_ENTER(); |
| 442 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 443 | tmp &= ~EIC_NMICTRL_NMIASYNCH; |
| 444 | tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; |
| 445 | ((Eic *)hw)->NMICTRL.reg = tmp; |
| 446 | EIC_CRITICAL_SECTION_LEAVE(); |
| 447 | } |
| 448 | |
| 449 | static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) |
| 450 | { |
| 451 | EIC_CRITICAL_SECTION_ENTER(); |
| 452 | ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; |
| 453 | EIC_CRITICAL_SECTION_LEAVE(); |
| 454 | } |
| 455 | |
| 456 | static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) |
| 457 | { |
| 458 | EIC_CRITICAL_SECTION_ENTER(); |
| 459 | ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; |
| 460 | EIC_CRITICAL_SECTION_LEAVE(); |
| 461 | } |
| 462 | |
| 463 | static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 464 | { |
| 465 | EIC_CRITICAL_SECTION_ENTER(); |
| 466 | ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); |
| 467 | EIC_CRITICAL_SECTION_LEAVE(); |
| 468 | } |
| 469 | |
| 470 | static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 471 | { |
| 472 | uint8_t tmp; |
| 473 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 474 | tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; |
| 475 | return tmp; |
| 476 | } |
| 477 | |
| 478 | static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) |
| 479 | { |
| 480 | uint8_t tmp; |
| 481 | EIC_CRITICAL_SECTION_ENTER(); |
| 482 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 483 | tmp &= ~EIC_NMICTRL_NMISENSE_Msk; |
| 484 | tmp |= EIC_NMICTRL_NMISENSE(data); |
| 485 | ((Eic *)hw)->NMICTRL.reg = tmp; |
| 486 | EIC_CRITICAL_SECTION_LEAVE(); |
| 487 | } |
| 488 | |
| 489 | static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 490 | { |
| 491 | EIC_CRITICAL_SECTION_ENTER(); |
| 492 | ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); |
| 493 | EIC_CRITICAL_SECTION_LEAVE(); |
| 494 | } |
| 495 | |
| 496 | static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 497 | { |
| 498 | EIC_CRITICAL_SECTION_ENTER(); |
| 499 | ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); |
| 500 | EIC_CRITICAL_SECTION_LEAVE(); |
| 501 | } |
| 502 | |
| 503 | static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) |
| 504 | { |
| 505 | uint8_t tmp; |
| 506 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 507 | tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; |
| 508 | return tmp; |
| 509 | } |
| 510 | |
| 511 | static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 512 | { |
| 513 | EIC_CRITICAL_SECTION_ENTER(); |
| 514 | ((Eic *)hw)->NMICTRL.reg |= mask; |
| 515 | EIC_CRITICAL_SECTION_LEAVE(); |
| 516 | } |
| 517 | |
| 518 | static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 519 | { |
| 520 | uint8_t tmp; |
| 521 | tmp = ((Eic *)hw)->NMICTRL.reg; |
| 522 | tmp &= mask; |
| 523 | return tmp; |
| 524 | } |
| 525 | |
| 526 | static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) |
| 527 | { |
| 528 | EIC_CRITICAL_SECTION_ENTER(); |
| 529 | ((Eic *)hw)->NMICTRL.reg = data; |
| 530 | EIC_CRITICAL_SECTION_LEAVE(); |
| 531 | } |
| 532 | |
| 533 | static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 534 | { |
| 535 | EIC_CRITICAL_SECTION_ENTER(); |
| 536 | ((Eic *)hw)->NMICTRL.reg &= ~mask; |
| 537 | EIC_CRITICAL_SECTION_LEAVE(); |
| 538 | } |
| 539 | |
| 540 | static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) |
| 541 | { |
| 542 | EIC_CRITICAL_SECTION_ENTER(); |
| 543 | ((Eic *)hw)->NMICTRL.reg ^= mask; |
| 544 | EIC_CRITICAL_SECTION_LEAVE(); |
| 545 | } |
| 546 | |
| 547 | static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) |
| 548 | { |
| 549 | return ((Eic *)hw)->NMICTRL.reg; |
| 550 | } |
| 551 | |
| 552 | static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 553 | { |
| 554 | EIC_CRITICAL_SECTION_ENTER(); |
| 555 | ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); |
| 556 | EIC_CRITICAL_SECTION_LEAVE(); |
| 557 | } |
| 558 | |
| 559 | static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 560 | { |
| 561 | uint32_t tmp; |
| 562 | tmp = ((Eic *)hw)->EVCTRL.reg; |
| 563 | tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; |
| 564 | return tmp; |
| 565 | } |
| 566 | |
| 567 | static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) |
| 568 | { |
| 569 | uint32_t tmp; |
| 570 | EIC_CRITICAL_SECTION_ENTER(); |
| 571 | tmp = ((Eic *)hw)->EVCTRL.reg; |
| 572 | tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; |
| 573 | tmp |= EIC_EVCTRL_EXTINTEO(data); |
| 574 | ((Eic *)hw)->EVCTRL.reg = tmp; |
| 575 | EIC_CRITICAL_SECTION_LEAVE(); |
| 576 | } |
| 577 | |
| 578 | static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 579 | { |
| 580 | EIC_CRITICAL_SECTION_ENTER(); |
| 581 | ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); |
| 582 | EIC_CRITICAL_SECTION_LEAVE(); |
| 583 | } |
| 584 | |
| 585 | static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 586 | { |
| 587 | EIC_CRITICAL_SECTION_ENTER(); |
| 588 | ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); |
| 589 | EIC_CRITICAL_SECTION_LEAVE(); |
| 590 | } |
| 591 | |
| 592 | static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) |
| 593 | { |
| 594 | uint32_t tmp; |
| 595 | tmp = ((Eic *)hw)->EVCTRL.reg; |
| 596 | tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; |
| 597 | return tmp; |
| 598 | } |
| 599 | |
| 600 | static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 601 | { |
| 602 | EIC_CRITICAL_SECTION_ENTER(); |
| 603 | ((Eic *)hw)->EVCTRL.reg |= mask; |
| 604 | EIC_CRITICAL_SECTION_LEAVE(); |
| 605 | } |
| 606 | |
| 607 | static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 608 | { |
| 609 | uint32_t tmp; |
| 610 | tmp = ((Eic *)hw)->EVCTRL.reg; |
| 611 | tmp &= mask; |
| 612 | return tmp; |
| 613 | } |
| 614 | |
| 615 | static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) |
| 616 | { |
| 617 | EIC_CRITICAL_SECTION_ENTER(); |
| 618 | ((Eic *)hw)->EVCTRL.reg = data; |
| 619 | EIC_CRITICAL_SECTION_LEAVE(); |
| 620 | } |
| 621 | |
| 622 | static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 623 | { |
| 624 | EIC_CRITICAL_SECTION_ENTER(); |
| 625 | ((Eic *)hw)->EVCTRL.reg &= ~mask; |
| 626 | EIC_CRITICAL_SECTION_LEAVE(); |
| 627 | } |
| 628 | |
| 629 | static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) |
| 630 | { |
| 631 | EIC_CRITICAL_SECTION_ENTER(); |
| 632 | ((Eic *)hw)->EVCTRL.reg ^= mask; |
| 633 | EIC_CRITICAL_SECTION_LEAVE(); |
| 634 | } |
| 635 | |
| 636 | static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) |
| 637 | { |
| 638 | return ((Eic *)hw)->EVCTRL.reg; |
| 639 | } |
| 640 | |
| 641 | static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) |
| 642 | { |
| 643 | EIC_CRITICAL_SECTION_ENTER(); |
| 644 | ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); |
| 645 | EIC_CRITICAL_SECTION_LEAVE(); |
| 646 | } |
| 647 | |
| 648 | static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) |
| 649 | { |
| 650 | uint32_t tmp; |
| 651 | tmp = ((Eic *)hw)->ASYNCH.reg; |
| 652 | tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; |
| 653 | return tmp; |
| 654 | } |
| 655 | |
| 656 | static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) |
| 657 | { |
| 658 | uint32_t tmp; |
| 659 | EIC_CRITICAL_SECTION_ENTER(); |
| 660 | tmp = ((Eic *)hw)->ASYNCH.reg; |
| 661 | tmp &= ~EIC_ASYNCH_ASYNCH_Msk; |
| 662 | tmp |= EIC_ASYNCH_ASYNCH(data); |
| 663 | ((Eic *)hw)->ASYNCH.reg = tmp; |
| 664 | EIC_CRITICAL_SECTION_LEAVE(); |
| 665 | } |
| 666 | |
| 667 | static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) |
| 668 | { |
| 669 | EIC_CRITICAL_SECTION_ENTER(); |
| 670 | ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); |
| 671 | EIC_CRITICAL_SECTION_LEAVE(); |
| 672 | } |
| 673 | |
| 674 | static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) |
| 675 | { |
| 676 | EIC_CRITICAL_SECTION_ENTER(); |
| 677 | ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); |
| 678 | EIC_CRITICAL_SECTION_LEAVE(); |
| 679 | } |
| 680 | |
| 681 | static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) |
| 682 | { |
| 683 | uint32_t tmp; |
| 684 | tmp = ((Eic *)hw)->ASYNCH.reg; |
| 685 | tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; |
| 686 | return tmp; |
| 687 | } |
| 688 | |
| 689 | static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) |
| 690 | { |
| 691 | EIC_CRITICAL_SECTION_ENTER(); |
| 692 | ((Eic *)hw)->ASYNCH.reg |= mask; |
| 693 | EIC_CRITICAL_SECTION_LEAVE(); |
| 694 | } |
| 695 | |
| 696 | static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) |
| 697 | { |
| 698 | uint32_t tmp; |
| 699 | tmp = ((Eic *)hw)->ASYNCH.reg; |
| 700 | tmp &= mask; |
| 701 | return tmp; |
| 702 | } |
| 703 | |
| 704 | static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) |
| 705 | { |
| 706 | EIC_CRITICAL_SECTION_ENTER(); |
| 707 | ((Eic *)hw)->ASYNCH.reg = data; |
| 708 | EIC_CRITICAL_SECTION_LEAVE(); |
| 709 | } |
| 710 | |
| 711 | static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) |
| 712 | { |
| 713 | EIC_CRITICAL_SECTION_ENTER(); |
| 714 | ((Eic *)hw)->ASYNCH.reg &= ~mask; |
| 715 | EIC_CRITICAL_SECTION_LEAVE(); |
| 716 | } |
| 717 | |
| 718 | static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) |
| 719 | { |
| 720 | EIC_CRITICAL_SECTION_ENTER(); |
| 721 | ((Eic *)hw)->ASYNCH.reg ^= mask; |
| 722 | EIC_CRITICAL_SECTION_LEAVE(); |
| 723 | } |
| 724 | |
| 725 | static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) |
| 726 | { |
| 727 | return ((Eic *)hw)->ASYNCH.reg; |
| 728 | } |
| 729 | |
| 730 | static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) |
| 731 | { |
| 732 | EIC_CRITICAL_SECTION_ENTER(); |
| 733 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; |
| 734 | EIC_CRITICAL_SECTION_LEAVE(); |
| 735 | } |
| 736 | |
| 737 | static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) |
| 738 | { |
| 739 | uint32_t tmp; |
| 740 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 741 | tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; |
| 742 | return (bool)tmp; |
| 743 | } |
| 744 | |
| 745 | static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) |
| 746 | { |
| 747 | uint32_t tmp; |
| 748 | EIC_CRITICAL_SECTION_ENTER(); |
| 749 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 750 | tmp &= ~EIC_CONFIG_FILTEN0; |
| 751 | tmp |= value << EIC_CONFIG_FILTEN0_Pos; |
| 752 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 753 | EIC_CRITICAL_SECTION_LEAVE(); |
| 754 | } |
| 755 | |
| 756 | static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) |
| 757 | { |
| 758 | EIC_CRITICAL_SECTION_ENTER(); |
| 759 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; |
| 760 | EIC_CRITICAL_SECTION_LEAVE(); |
| 761 | } |
| 762 | |
| 763 | static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) |
| 764 | { |
| 765 | EIC_CRITICAL_SECTION_ENTER(); |
| 766 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; |
| 767 | EIC_CRITICAL_SECTION_LEAVE(); |
| 768 | } |
| 769 | |
| 770 | static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) |
| 771 | { |
| 772 | EIC_CRITICAL_SECTION_ENTER(); |
| 773 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; |
| 774 | EIC_CRITICAL_SECTION_LEAVE(); |
| 775 | } |
| 776 | |
| 777 | static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) |
| 778 | { |
| 779 | uint32_t tmp; |
| 780 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 781 | tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; |
| 782 | return (bool)tmp; |
| 783 | } |
| 784 | |
| 785 | static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) |
| 786 | { |
| 787 | uint32_t tmp; |
| 788 | EIC_CRITICAL_SECTION_ENTER(); |
| 789 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 790 | tmp &= ~EIC_CONFIG_FILTEN1; |
| 791 | tmp |= value << EIC_CONFIG_FILTEN1_Pos; |
| 792 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 793 | EIC_CRITICAL_SECTION_LEAVE(); |
| 794 | } |
| 795 | |
| 796 | static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) |
| 797 | { |
| 798 | EIC_CRITICAL_SECTION_ENTER(); |
| 799 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; |
| 800 | EIC_CRITICAL_SECTION_LEAVE(); |
| 801 | } |
| 802 | |
| 803 | static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) |
| 804 | { |
| 805 | EIC_CRITICAL_SECTION_ENTER(); |
| 806 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; |
| 807 | EIC_CRITICAL_SECTION_LEAVE(); |
| 808 | } |
| 809 | |
| 810 | static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) |
| 811 | { |
| 812 | EIC_CRITICAL_SECTION_ENTER(); |
| 813 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; |
| 814 | EIC_CRITICAL_SECTION_LEAVE(); |
| 815 | } |
| 816 | |
| 817 | static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) |
| 818 | { |
| 819 | uint32_t tmp; |
| 820 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 821 | tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; |
| 822 | return (bool)tmp; |
| 823 | } |
| 824 | |
| 825 | static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) |
| 826 | { |
| 827 | uint32_t tmp; |
| 828 | EIC_CRITICAL_SECTION_ENTER(); |
| 829 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 830 | tmp &= ~EIC_CONFIG_FILTEN2; |
| 831 | tmp |= value << EIC_CONFIG_FILTEN2_Pos; |
| 832 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 833 | EIC_CRITICAL_SECTION_LEAVE(); |
| 834 | } |
| 835 | |
| 836 | static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) |
| 837 | { |
| 838 | EIC_CRITICAL_SECTION_ENTER(); |
| 839 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; |
| 840 | EIC_CRITICAL_SECTION_LEAVE(); |
| 841 | } |
| 842 | |
| 843 | static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) |
| 844 | { |
| 845 | EIC_CRITICAL_SECTION_ENTER(); |
| 846 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; |
| 847 | EIC_CRITICAL_SECTION_LEAVE(); |
| 848 | } |
| 849 | |
| 850 | static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) |
| 851 | { |
| 852 | EIC_CRITICAL_SECTION_ENTER(); |
| 853 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; |
| 854 | EIC_CRITICAL_SECTION_LEAVE(); |
| 855 | } |
| 856 | |
| 857 | static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) |
| 858 | { |
| 859 | uint32_t tmp; |
| 860 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 861 | tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; |
| 862 | return (bool)tmp; |
| 863 | } |
| 864 | |
| 865 | static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) |
| 866 | { |
| 867 | uint32_t tmp; |
| 868 | EIC_CRITICAL_SECTION_ENTER(); |
| 869 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 870 | tmp &= ~EIC_CONFIG_FILTEN3; |
| 871 | tmp |= value << EIC_CONFIG_FILTEN3_Pos; |
| 872 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 873 | EIC_CRITICAL_SECTION_LEAVE(); |
| 874 | } |
| 875 | |
| 876 | static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) |
| 877 | { |
| 878 | EIC_CRITICAL_SECTION_ENTER(); |
| 879 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; |
| 880 | EIC_CRITICAL_SECTION_LEAVE(); |
| 881 | } |
| 882 | |
| 883 | static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) |
| 884 | { |
| 885 | EIC_CRITICAL_SECTION_ENTER(); |
| 886 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; |
| 887 | EIC_CRITICAL_SECTION_LEAVE(); |
| 888 | } |
| 889 | |
| 890 | static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) |
| 891 | { |
| 892 | EIC_CRITICAL_SECTION_ENTER(); |
| 893 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; |
| 894 | EIC_CRITICAL_SECTION_LEAVE(); |
| 895 | } |
| 896 | |
| 897 | static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) |
| 898 | { |
| 899 | uint32_t tmp; |
| 900 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 901 | tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; |
| 902 | return (bool)tmp; |
| 903 | } |
| 904 | |
| 905 | static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) |
| 906 | { |
| 907 | uint32_t tmp; |
| 908 | EIC_CRITICAL_SECTION_ENTER(); |
| 909 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 910 | tmp &= ~EIC_CONFIG_FILTEN4; |
| 911 | tmp |= value << EIC_CONFIG_FILTEN4_Pos; |
| 912 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 913 | EIC_CRITICAL_SECTION_LEAVE(); |
| 914 | } |
| 915 | |
| 916 | static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) |
| 917 | { |
| 918 | EIC_CRITICAL_SECTION_ENTER(); |
| 919 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; |
| 920 | EIC_CRITICAL_SECTION_LEAVE(); |
| 921 | } |
| 922 | |
| 923 | static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) |
| 924 | { |
| 925 | EIC_CRITICAL_SECTION_ENTER(); |
| 926 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; |
| 927 | EIC_CRITICAL_SECTION_LEAVE(); |
| 928 | } |
| 929 | |
| 930 | static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) |
| 931 | { |
| 932 | EIC_CRITICAL_SECTION_ENTER(); |
| 933 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; |
| 934 | EIC_CRITICAL_SECTION_LEAVE(); |
| 935 | } |
| 936 | |
| 937 | static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) |
| 938 | { |
| 939 | uint32_t tmp; |
| 940 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 941 | tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; |
| 942 | return (bool)tmp; |
| 943 | } |
| 944 | |
| 945 | static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) |
| 946 | { |
| 947 | uint32_t tmp; |
| 948 | EIC_CRITICAL_SECTION_ENTER(); |
| 949 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 950 | tmp &= ~EIC_CONFIG_FILTEN5; |
| 951 | tmp |= value << EIC_CONFIG_FILTEN5_Pos; |
| 952 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 953 | EIC_CRITICAL_SECTION_LEAVE(); |
| 954 | } |
| 955 | |
| 956 | static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) |
| 957 | { |
| 958 | EIC_CRITICAL_SECTION_ENTER(); |
| 959 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; |
| 960 | EIC_CRITICAL_SECTION_LEAVE(); |
| 961 | } |
| 962 | |
| 963 | static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) |
| 964 | { |
| 965 | EIC_CRITICAL_SECTION_ENTER(); |
| 966 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; |
| 967 | EIC_CRITICAL_SECTION_LEAVE(); |
| 968 | } |
| 969 | |
| 970 | static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) |
| 971 | { |
| 972 | EIC_CRITICAL_SECTION_ENTER(); |
| 973 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; |
| 974 | EIC_CRITICAL_SECTION_LEAVE(); |
| 975 | } |
| 976 | |
| 977 | static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) |
| 978 | { |
| 979 | uint32_t tmp; |
| 980 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 981 | tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; |
| 982 | return (bool)tmp; |
| 983 | } |
| 984 | |
| 985 | static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) |
| 986 | { |
| 987 | uint32_t tmp; |
| 988 | EIC_CRITICAL_SECTION_ENTER(); |
| 989 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 990 | tmp &= ~EIC_CONFIG_FILTEN6; |
| 991 | tmp |= value << EIC_CONFIG_FILTEN6_Pos; |
| 992 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 993 | EIC_CRITICAL_SECTION_LEAVE(); |
| 994 | } |
| 995 | |
| 996 | static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) |
| 997 | { |
| 998 | EIC_CRITICAL_SECTION_ENTER(); |
| 999 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; |
| 1000 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1001 | } |
| 1002 | |
| 1003 | static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) |
| 1004 | { |
| 1005 | EIC_CRITICAL_SECTION_ENTER(); |
| 1006 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; |
| 1007 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1008 | } |
| 1009 | |
| 1010 | static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) |
| 1011 | { |
| 1012 | EIC_CRITICAL_SECTION_ENTER(); |
| 1013 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; |
| 1014 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1015 | } |
| 1016 | |
| 1017 | static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) |
| 1018 | { |
| 1019 | uint32_t tmp; |
| 1020 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1021 | tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; |
| 1022 | return (bool)tmp; |
| 1023 | } |
| 1024 | |
| 1025 | static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) |
| 1026 | { |
| 1027 | uint32_t tmp; |
| 1028 | EIC_CRITICAL_SECTION_ENTER(); |
| 1029 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1030 | tmp &= ~EIC_CONFIG_FILTEN7; |
| 1031 | tmp |= value << EIC_CONFIG_FILTEN7_Pos; |
| 1032 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1033 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1034 | } |
| 1035 | |
| 1036 | static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) |
| 1037 | { |
| 1038 | EIC_CRITICAL_SECTION_ENTER(); |
| 1039 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; |
| 1040 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1041 | } |
| 1042 | |
| 1043 | static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) |
| 1044 | { |
| 1045 | EIC_CRITICAL_SECTION_ENTER(); |
| 1046 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; |
| 1047 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1048 | } |
| 1049 | |
| 1050 | static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1051 | { |
| 1052 | EIC_CRITICAL_SECTION_ENTER(); |
| 1053 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); |
| 1054 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1055 | } |
| 1056 | |
| 1057 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, |
| 1058 | hri_eic_config_reg_t mask) |
| 1059 | { |
| 1060 | uint32_t tmp; |
| 1061 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1062 | tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; |
| 1063 | return tmp; |
| 1064 | } |
| 1065 | |
| 1066 | static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1067 | { |
| 1068 | uint32_t tmp; |
| 1069 | EIC_CRITICAL_SECTION_ENTER(); |
| 1070 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1071 | tmp &= ~EIC_CONFIG_SENSE0_Msk; |
| 1072 | tmp |= EIC_CONFIG_SENSE0(data); |
| 1073 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1074 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1075 | } |
| 1076 | |
| 1077 | static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1078 | { |
| 1079 | EIC_CRITICAL_SECTION_ENTER(); |
| 1080 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); |
| 1081 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1082 | } |
| 1083 | |
| 1084 | static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1085 | { |
| 1086 | EIC_CRITICAL_SECTION_ENTER(); |
| 1087 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); |
| 1088 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1089 | } |
| 1090 | |
| 1091 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) |
| 1092 | { |
| 1093 | uint32_t tmp; |
| 1094 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1095 | tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; |
| 1096 | return tmp; |
| 1097 | } |
| 1098 | |
| 1099 | static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1100 | { |
| 1101 | EIC_CRITICAL_SECTION_ENTER(); |
| 1102 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); |
| 1103 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1104 | } |
| 1105 | |
| 1106 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, |
| 1107 | hri_eic_config_reg_t mask) |
| 1108 | { |
| 1109 | uint32_t tmp; |
| 1110 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1111 | tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; |
| 1112 | return tmp; |
| 1113 | } |
| 1114 | |
| 1115 | static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1116 | { |
| 1117 | uint32_t tmp; |
| 1118 | EIC_CRITICAL_SECTION_ENTER(); |
| 1119 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1120 | tmp &= ~EIC_CONFIG_SENSE1_Msk; |
| 1121 | tmp |= EIC_CONFIG_SENSE1(data); |
| 1122 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1123 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1124 | } |
| 1125 | |
| 1126 | static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1127 | { |
| 1128 | EIC_CRITICAL_SECTION_ENTER(); |
| 1129 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); |
| 1130 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1131 | } |
| 1132 | |
| 1133 | static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1134 | { |
| 1135 | EIC_CRITICAL_SECTION_ENTER(); |
| 1136 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); |
| 1137 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1138 | } |
| 1139 | |
| 1140 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) |
| 1141 | { |
| 1142 | uint32_t tmp; |
| 1143 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1144 | tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; |
| 1145 | return tmp; |
| 1146 | } |
| 1147 | |
| 1148 | static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1149 | { |
| 1150 | EIC_CRITICAL_SECTION_ENTER(); |
| 1151 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); |
| 1152 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1153 | } |
| 1154 | |
| 1155 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, |
| 1156 | hri_eic_config_reg_t mask) |
| 1157 | { |
| 1158 | uint32_t tmp; |
| 1159 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1160 | tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; |
| 1161 | return tmp; |
| 1162 | } |
| 1163 | |
| 1164 | static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1165 | { |
| 1166 | uint32_t tmp; |
| 1167 | EIC_CRITICAL_SECTION_ENTER(); |
| 1168 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1169 | tmp &= ~EIC_CONFIG_SENSE2_Msk; |
| 1170 | tmp |= EIC_CONFIG_SENSE2(data); |
| 1171 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1172 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1173 | } |
| 1174 | |
| 1175 | static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1176 | { |
| 1177 | EIC_CRITICAL_SECTION_ENTER(); |
| 1178 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); |
| 1179 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1180 | } |
| 1181 | |
| 1182 | static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1183 | { |
| 1184 | EIC_CRITICAL_SECTION_ENTER(); |
| 1185 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); |
| 1186 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1187 | } |
| 1188 | |
| 1189 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) |
| 1190 | { |
| 1191 | uint32_t tmp; |
| 1192 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1193 | tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; |
| 1194 | return tmp; |
| 1195 | } |
| 1196 | |
| 1197 | static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1198 | { |
| 1199 | EIC_CRITICAL_SECTION_ENTER(); |
| 1200 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); |
| 1201 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1202 | } |
| 1203 | |
| 1204 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, |
| 1205 | hri_eic_config_reg_t mask) |
| 1206 | { |
| 1207 | uint32_t tmp; |
| 1208 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1209 | tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; |
| 1210 | return tmp; |
| 1211 | } |
| 1212 | |
| 1213 | static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1214 | { |
| 1215 | uint32_t tmp; |
| 1216 | EIC_CRITICAL_SECTION_ENTER(); |
| 1217 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1218 | tmp &= ~EIC_CONFIG_SENSE3_Msk; |
| 1219 | tmp |= EIC_CONFIG_SENSE3(data); |
| 1220 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1221 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1222 | } |
| 1223 | |
| 1224 | static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1225 | { |
| 1226 | EIC_CRITICAL_SECTION_ENTER(); |
| 1227 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); |
| 1228 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1229 | } |
| 1230 | |
| 1231 | static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1232 | { |
| 1233 | EIC_CRITICAL_SECTION_ENTER(); |
| 1234 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); |
| 1235 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1236 | } |
| 1237 | |
| 1238 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) |
| 1239 | { |
| 1240 | uint32_t tmp; |
| 1241 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1242 | tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; |
| 1243 | return tmp; |
| 1244 | } |
| 1245 | |
| 1246 | static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1247 | { |
| 1248 | EIC_CRITICAL_SECTION_ENTER(); |
| 1249 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); |
| 1250 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1251 | } |
| 1252 | |
| 1253 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, |
| 1254 | hri_eic_config_reg_t mask) |
| 1255 | { |
| 1256 | uint32_t tmp; |
| 1257 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1258 | tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; |
| 1259 | return tmp; |
| 1260 | } |
| 1261 | |
| 1262 | static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1263 | { |
| 1264 | uint32_t tmp; |
| 1265 | EIC_CRITICAL_SECTION_ENTER(); |
| 1266 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1267 | tmp &= ~EIC_CONFIG_SENSE4_Msk; |
| 1268 | tmp |= EIC_CONFIG_SENSE4(data); |
| 1269 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1270 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1271 | } |
| 1272 | |
| 1273 | static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1274 | { |
| 1275 | EIC_CRITICAL_SECTION_ENTER(); |
| 1276 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); |
| 1277 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1278 | } |
| 1279 | |
| 1280 | static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1281 | { |
| 1282 | EIC_CRITICAL_SECTION_ENTER(); |
| 1283 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); |
| 1284 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1285 | } |
| 1286 | |
| 1287 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) |
| 1288 | { |
| 1289 | uint32_t tmp; |
| 1290 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1291 | tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; |
| 1292 | return tmp; |
| 1293 | } |
| 1294 | |
| 1295 | static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1296 | { |
| 1297 | EIC_CRITICAL_SECTION_ENTER(); |
| 1298 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); |
| 1299 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1300 | } |
| 1301 | |
| 1302 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, |
| 1303 | hri_eic_config_reg_t mask) |
| 1304 | { |
| 1305 | uint32_t tmp; |
| 1306 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1307 | tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; |
| 1308 | return tmp; |
| 1309 | } |
| 1310 | |
| 1311 | static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1312 | { |
| 1313 | uint32_t tmp; |
| 1314 | EIC_CRITICAL_SECTION_ENTER(); |
| 1315 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1316 | tmp &= ~EIC_CONFIG_SENSE5_Msk; |
| 1317 | tmp |= EIC_CONFIG_SENSE5(data); |
| 1318 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1319 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1320 | } |
| 1321 | |
| 1322 | static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1323 | { |
| 1324 | EIC_CRITICAL_SECTION_ENTER(); |
| 1325 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); |
| 1326 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1327 | } |
| 1328 | |
| 1329 | static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1330 | { |
| 1331 | EIC_CRITICAL_SECTION_ENTER(); |
| 1332 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); |
| 1333 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1334 | } |
| 1335 | |
| 1336 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) |
| 1337 | { |
| 1338 | uint32_t tmp; |
| 1339 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1340 | tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; |
| 1341 | return tmp; |
| 1342 | } |
| 1343 | |
| 1344 | static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1345 | { |
| 1346 | EIC_CRITICAL_SECTION_ENTER(); |
| 1347 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); |
| 1348 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1349 | } |
| 1350 | |
| 1351 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, |
| 1352 | hri_eic_config_reg_t mask) |
| 1353 | { |
| 1354 | uint32_t tmp; |
| 1355 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1356 | tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; |
| 1357 | return tmp; |
| 1358 | } |
| 1359 | |
| 1360 | static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1361 | { |
| 1362 | uint32_t tmp; |
| 1363 | EIC_CRITICAL_SECTION_ENTER(); |
| 1364 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1365 | tmp &= ~EIC_CONFIG_SENSE6_Msk; |
| 1366 | tmp |= EIC_CONFIG_SENSE6(data); |
| 1367 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1368 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1369 | } |
| 1370 | |
| 1371 | static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1372 | { |
| 1373 | EIC_CRITICAL_SECTION_ENTER(); |
| 1374 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); |
| 1375 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1376 | } |
| 1377 | |
| 1378 | static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1379 | { |
| 1380 | EIC_CRITICAL_SECTION_ENTER(); |
| 1381 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); |
| 1382 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1383 | } |
| 1384 | |
| 1385 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) |
| 1386 | { |
| 1387 | uint32_t tmp; |
| 1388 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1389 | tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; |
| 1390 | return tmp; |
| 1391 | } |
| 1392 | |
| 1393 | static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1394 | { |
| 1395 | EIC_CRITICAL_SECTION_ENTER(); |
| 1396 | ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); |
| 1397 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1398 | } |
| 1399 | |
| 1400 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, |
| 1401 | hri_eic_config_reg_t mask) |
| 1402 | { |
| 1403 | uint32_t tmp; |
| 1404 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1405 | tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; |
| 1406 | return tmp; |
| 1407 | } |
| 1408 | |
| 1409 | static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1410 | { |
| 1411 | uint32_t tmp; |
| 1412 | EIC_CRITICAL_SECTION_ENTER(); |
| 1413 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1414 | tmp &= ~EIC_CONFIG_SENSE7_Msk; |
| 1415 | tmp |= EIC_CONFIG_SENSE7(data); |
| 1416 | ((Eic *)hw)->CONFIG[index].reg = tmp; |
| 1417 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1418 | } |
| 1419 | |
| 1420 | static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1421 | { |
| 1422 | EIC_CRITICAL_SECTION_ENTER(); |
| 1423 | ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); |
| 1424 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1425 | } |
| 1426 | |
| 1427 | static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1428 | { |
| 1429 | EIC_CRITICAL_SECTION_ENTER(); |
| 1430 | ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); |
| 1431 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1432 | } |
| 1433 | |
| 1434 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) |
| 1435 | { |
| 1436 | uint32_t tmp; |
| 1437 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1438 | tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; |
| 1439 | return tmp; |
| 1440 | } |
| 1441 | |
| 1442 | static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1443 | { |
| 1444 | EIC_CRITICAL_SECTION_ENTER(); |
| 1445 | ((Eic *)hw)->CONFIG[index].reg |= mask; |
| 1446 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1447 | } |
| 1448 | |
| 1449 | static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, |
| 1450 | hri_eic_config_reg_t mask) |
| 1451 | { |
| 1452 | uint32_t tmp; |
| 1453 | tmp = ((Eic *)hw)->CONFIG[index].reg; |
| 1454 | tmp &= mask; |
| 1455 | return tmp; |
| 1456 | } |
| 1457 | |
| 1458 | static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) |
| 1459 | { |
| 1460 | EIC_CRITICAL_SECTION_ENTER(); |
| 1461 | ((Eic *)hw)->CONFIG[index].reg = data; |
| 1462 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1463 | } |
| 1464 | |
| 1465 | static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1466 | { |
| 1467 | EIC_CRITICAL_SECTION_ENTER(); |
| 1468 | ((Eic *)hw)->CONFIG[index].reg &= ~mask; |
| 1469 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1470 | } |
| 1471 | |
| 1472 | static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) |
| 1473 | { |
| 1474 | EIC_CRITICAL_SECTION_ENTER(); |
| 1475 | ((Eic *)hw)->CONFIG[index].reg ^= mask; |
| 1476 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1477 | } |
| 1478 | |
| 1479 | static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) |
| 1480 | { |
| 1481 | return ((Eic *)hw)->CONFIG[index].reg; |
| 1482 | } |
| 1483 | |
| 1484 | static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) |
| 1485 | { |
| 1486 | EIC_CRITICAL_SECTION_ENTER(); |
| 1487 | ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); |
| 1488 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1489 | } |
| 1490 | |
| 1491 | static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, |
| 1492 | hri_eic_debouncen_reg_t mask) |
| 1493 | { |
| 1494 | uint32_t tmp; |
| 1495 | tmp = ((Eic *)hw)->DEBOUNCEN.reg; |
| 1496 | tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; |
| 1497 | return tmp; |
| 1498 | } |
| 1499 | |
| 1500 | static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) |
| 1501 | { |
| 1502 | uint32_t tmp; |
| 1503 | EIC_CRITICAL_SECTION_ENTER(); |
| 1504 | tmp = ((Eic *)hw)->DEBOUNCEN.reg; |
| 1505 | tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; |
| 1506 | tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); |
| 1507 | ((Eic *)hw)->DEBOUNCEN.reg = tmp; |
| 1508 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1509 | } |
| 1510 | |
| 1511 | static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) |
| 1512 | { |
| 1513 | EIC_CRITICAL_SECTION_ENTER(); |
| 1514 | ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); |
| 1515 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1516 | } |
| 1517 | |
| 1518 | static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) |
| 1519 | { |
| 1520 | EIC_CRITICAL_SECTION_ENTER(); |
| 1521 | ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); |
| 1522 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1523 | } |
| 1524 | |
| 1525 | static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) |
| 1526 | { |
| 1527 | uint32_t tmp; |
| 1528 | tmp = ((Eic *)hw)->DEBOUNCEN.reg; |
| 1529 | tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; |
| 1530 | return tmp; |
| 1531 | } |
| 1532 | |
| 1533 | static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) |
| 1534 | { |
| 1535 | EIC_CRITICAL_SECTION_ENTER(); |
| 1536 | ((Eic *)hw)->DEBOUNCEN.reg |= mask; |
| 1537 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1538 | } |
| 1539 | |
| 1540 | static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) |
| 1541 | { |
| 1542 | uint32_t tmp; |
| 1543 | tmp = ((Eic *)hw)->DEBOUNCEN.reg; |
| 1544 | tmp &= mask; |
| 1545 | return tmp; |
| 1546 | } |
| 1547 | |
| 1548 | static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) |
| 1549 | { |
| 1550 | EIC_CRITICAL_SECTION_ENTER(); |
| 1551 | ((Eic *)hw)->DEBOUNCEN.reg = data; |
| 1552 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1553 | } |
| 1554 | |
| 1555 | static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) |
| 1556 | { |
| 1557 | EIC_CRITICAL_SECTION_ENTER(); |
| 1558 | ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; |
| 1559 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1560 | } |
| 1561 | |
| 1562 | static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) |
| 1563 | { |
| 1564 | EIC_CRITICAL_SECTION_ENTER(); |
| 1565 | ((Eic *)hw)->DEBOUNCEN.reg ^= mask; |
| 1566 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1567 | } |
| 1568 | |
| 1569 | static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) |
| 1570 | { |
| 1571 | return ((Eic *)hw)->DEBOUNCEN.reg; |
| 1572 | } |
| 1573 | |
| 1574 | static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) |
| 1575 | { |
| 1576 | EIC_CRITICAL_SECTION_ENTER(); |
| 1577 | ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; |
| 1578 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1579 | } |
| 1580 | |
| 1581 | static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) |
| 1582 | { |
| 1583 | uint32_t tmp; |
| 1584 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1585 | tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; |
| 1586 | return (bool)tmp; |
| 1587 | } |
| 1588 | |
| 1589 | static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) |
| 1590 | { |
| 1591 | uint32_t tmp; |
| 1592 | EIC_CRITICAL_SECTION_ENTER(); |
| 1593 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1594 | tmp &= ~EIC_DPRESCALER_STATES0; |
| 1595 | tmp |= value << EIC_DPRESCALER_STATES0_Pos; |
| 1596 | ((Eic *)hw)->DPRESCALER.reg = tmp; |
| 1597 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1598 | } |
| 1599 | |
| 1600 | static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) |
| 1601 | { |
| 1602 | EIC_CRITICAL_SECTION_ENTER(); |
| 1603 | ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; |
| 1604 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1605 | } |
| 1606 | |
| 1607 | static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) |
| 1608 | { |
| 1609 | EIC_CRITICAL_SECTION_ENTER(); |
| 1610 | ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; |
| 1611 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1612 | } |
| 1613 | |
| 1614 | static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) |
| 1615 | { |
| 1616 | EIC_CRITICAL_SECTION_ENTER(); |
| 1617 | ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; |
| 1618 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1619 | } |
| 1620 | |
| 1621 | static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) |
| 1622 | { |
| 1623 | uint32_t tmp; |
| 1624 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1625 | tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; |
| 1626 | return (bool)tmp; |
| 1627 | } |
| 1628 | |
| 1629 | static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) |
| 1630 | { |
| 1631 | uint32_t tmp; |
| 1632 | EIC_CRITICAL_SECTION_ENTER(); |
| 1633 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1634 | tmp &= ~EIC_DPRESCALER_STATES1; |
| 1635 | tmp |= value << EIC_DPRESCALER_STATES1_Pos; |
| 1636 | ((Eic *)hw)->DPRESCALER.reg = tmp; |
| 1637 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1638 | } |
| 1639 | |
| 1640 | static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) |
| 1641 | { |
| 1642 | EIC_CRITICAL_SECTION_ENTER(); |
| 1643 | ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; |
| 1644 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1645 | } |
| 1646 | |
| 1647 | static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) |
| 1648 | { |
| 1649 | EIC_CRITICAL_SECTION_ENTER(); |
| 1650 | ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; |
| 1651 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1652 | } |
| 1653 | |
| 1654 | static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) |
| 1655 | { |
| 1656 | EIC_CRITICAL_SECTION_ENTER(); |
| 1657 | ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; |
| 1658 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1659 | } |
| 1660 | |
| 1661 | static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) |
| 1662 | { |
| 1663 | uint32_t tmp; |
| 1664 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1665 | tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; |
| 1666 | return (bool)tmp; |
| 1667 | } |
| 1668 | |
| 1669 | static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) |
| 1670 | { |
| 1671 | uint32_t tmp; |
| 1672 | EIC_CRITICAL_SECTION_ENTER(); |
| 1673 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1674 | tmp &= ~EIC_DPRESCALER_TICKON; |
| 1675 | tmp |= value << EIC_DPRESCALER_TICKON_Pos; |
| 1676 | ((Eic *)hw)->DPRESCALER.reg = tmp; |
| 1677 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1678 | } |
| 1679 | |
| 1680 | static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) |
| 1681 | { |
| 1682 | EIC_CRITICAL_SECTION_ENTER(); |
| 1683 | ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; |
| 1684 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1685 | } |
| 1686 | |
| 1687 | static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) |
| 1688 | { |
| 1689 | EIC_CRITICAL_SECTION_ENTER(); |
| 1690 | ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; |
| 1691 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1692 | } |
| 1693 | |
| 1694 | static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1695 | { |
| 1696 | EIC_CRITICAL_SECTION_ENTER(); |
| 1697 | ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); |
| 1698 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1699 | } |
| 1700 | |
| 1701 | static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, |
| 1702 | hri_eic_dprescaler_reg_t mask) |
| 1703 | { |
| 1704 | uint32_t tmp; |
| 1705 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1706 | tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; |
| 1707 | return tmp; |
| 1708 | } |
| 1709 | |
| 1710 | static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) |
| 1711 | { |
| 1712 | uint32_t tmp; |
| 1713 | EIC_CRITICAL_SECTION_ENTER(); |
| 1714 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1715 | tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; |
| 1716 | tmp |= EIC_DPRESCALER_PRESCALER0(data); |
| 1717 | ((Eic *)hw)->DPRESCALER.reg = tmp; |
| 1718 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1719 | } |
| 1720 | |
| 1721 | static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1722 | { |
| 1723 | EIC_CRITICAL_SECTION_ENTER(); |
| 1724 | ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); |
| 1725 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1726 | } |
| 1727 | |
| 1728 | static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1729 | { |
| 1730 | EIC_CRITICAL_SECTION_ENTER(); |
| 1731 | ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); |
| 1732 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1733 | } |
| 1734 | |
| 1735 | static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) |
| 1736 | { |
| 1737 | uint32_t tmp; |
| 1738 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1739 | tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; |
| 1740 | return tmp; |
| 1741 | } |
| 1742 | |
| 1743 | static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1744 | { |
| 1745 | EIC_CRITICAL_SECTION_ENTER(); |
| 1746 | ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); |
| 1747 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1748 | } |
| 1749 | |
| 1750 | static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, |
| 1751 | hri_eic_dprescaler_reg_t mask) |
| 1752 | { |
| 1753 | uint32_t tmp; |
| 1754 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1755 | tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; |
| 1756 | return tmp; |
| 1757 | } |
| 1758 | |
| 1759 | static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) |
| 1760 | { |
| 1761 | uint32_t tmp; |
| 1762 | EIC_CRITICAL_SECTION_ENTER(); |
| 1763 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1764 | tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; |
| 1765 | tmp |= EIC_DPRESCALER_PRESCALER1(data); |
| 1766 | ((Eic *)hw)->DPRESCALER.reg = tmp; |
| 1767 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1768 | } |
| 1769 | |
| 1770 | static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1771 | { |
| 1772 | EIC_CRITICAL_SECTION_ENTER(); |
| 1773 | ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); |
| 1774 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1775 | } |
| 1776 | |
| 1777 | static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1778 | { |
| 1779 | EIC_CRITICAL_SECTION_ENTER(); |
| 1780 | ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); |
| 1781 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1782 | } |
| 1783 | |
| 1784 | static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) |
| 1785 | { |
| 1786 | uint32_t tmp; |
| 1787 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1788 | tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; |
| 1789 | return tmp; |
| 1790 | } |
| 1791 | |
| 1792 | static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1793 | { |
| 1794 | EIC_CRITICAL_SECTION_ENTER(); |
| 1795 | ((Eic *)hw)->DPRESCALER.reg |= mask; |
| 1796 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1797 | } |
| 1798 | |
| 1799 | static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1800 | { |
| 1801 | uint32_t tmp; |
| 1802 | tmp = ((Eic *)hw)->DPRESCALER.reg; |
| 1803 | tmp &= mask; |
| 1804 | return tmp; |
| 1805 | } |
| 1806 | |
| 1807 | static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) |
| 1808 | { |
| 1809 | EIC_CRITICAL_SECTION_ENTER(); |
| 1810 | ((Eic *)hw)->DPRESCALER.reg = data; |
| 1811 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1812 | } |
| 1813 | |
| 1814 | static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1815 | { |
| 1816 | EIC_CRITICAL_SECTION_ENTER(); |
| 1817 | ((Eic *)hw)->DPRESCALER.reg &= ~mask; |
| 1818 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1819 | } |
| 1820 | |
| 1821 | static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) |
| 1822 | { |
| 1823 | EIC_CRITICAL_SECTION_ENTER(); |
| 1824 | ((Eic *)hw)->DPRESCALER.reg ^= mask; |
| 1825 | EIC_CRITICAL_SECTION_LEAVE(); |
| 1826 | } |
| 1827 | |
| 1828 | static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) |
| 1829 | { |
| 1830 | return ((Eic *)hw)->DPRESCALER.reg; |
| 1831 | } |
| 1832 | |
| 1833 | #ifdef __cplusplus |
| 1834 | } |
| 1835 | #endif |
| 1836 | |
| 1837 | #endif /* _HRI_EIC_E54_H_INCLUDED */ |
| 1838 | #endif /* _SAME54_EIC_COMPONENT_ */ |