Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM DSU |
| 5 | * |
| 6 | * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_DSU_COMPONENT_ |
| 35 | #ifndef _HRI_DSU_E54_H_INCLUDED_ |
| 36 | #define _HRI_DSU_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_DSU_CRITICAL_SECTIONS) |
| 46 | #define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define DSU_CRITICAL_SECTION_ENTER() |
| 50 | #define DSU_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_dsu_addr_reg_t; |
| 54 | typedef uint32_t hri_dsu_cfg_reg_t; |
| 55 | typedef uint32_t hri_dsu_cid0_reg_t; |
| 56 | typedef uint32_t hri_dsu_cid1_reg_t; |
| 57 | typedef uint32_t hri_dsu_cid2_reg_t; |
| 58 | typedef uint32_t hri_dsu_cid3_reg_t; |
| 59 | typedef uint32_t hri_dsu_data_reg_t; |
| 60 | typedef uint32_t hri_dsu_dcc_reg_t; |
| 61 | typedef uint32_t hri_dsu_dcfg_reg_t; |
| 62 | typedef uint32_t hri_dsu_did_reg_t; |
| 63 | typedef uint32_t hri_dsu_end_reg_t; |
| 64 | typedef uint32_t hri_dsu_entry0_reg_t; |
| 65 | typedef uint32_t hri_dsu_entry1_reg_t; |
| 66 | typedef uint32_t hri_dsu_length_reg_t; |
| 67 | typedef uint32_t hri_dsu_memtype_reg_t; |
| 68 | typedef uint32_t hri_dsu_pid0_reg_t; |
| 69 | typedef uint32_t hri_dsu_pid1_reg_t; |
| 70 | typedef uint32_t hri_dsu_pid2_reg_t; |
| 71 | typedef uint32_t hri_dsu_pid3_reg_t; |
| 72 | typedef uint32_t hri_dsu_pid4_reg_t; |
| 73 | typedef uint32_t hri_dsu_pid5_reg_t; |
| 74 | typedef uint32_t hri_dsu_pid6_reg_t; |
| 75 | typedef uint32_t hri_dsu_pid7_reg_t; |
| 76 | typedef uint8_t hri_dsu_ctrl_reg_t; |
| 77 | typedef uint8_t hri_dsu_statusa_reg_t; |
| 78 | typedef uint8_t hri_dsu_statusb_reg_t; |
| 79 | |
| 80 | static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) |
| 81 | { |
| 82 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; |
| 83 | } |
| 84 | |
| 85 | static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) |
| 86 | { |
| 87 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; |
| 88 | } |
| 89 | |
| 90 | static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) |
| 91 | { |
| 92 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; |
| 93 | } |
| 94 | |
| 95 | static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) |
| 96 | { |
| 97 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; |
| 98 | } |
| 99 | |
| 100 | static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) |
| 101 | { |
| 102 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; |
| 103 | } |
| 104 | |
| 105 | static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) |
| 106 | { |
| 107 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; |
| 108 | } |
| 109 | |
| 110 | static inline bool hri_dsu_get_STATUSB_TDCCD0_bit(const void *const hw) |
| 111 | { |
| 112 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD0) >> DSU_STATUSB_TDCCD0_Pos; |
| 113 | } |
| 114 | |
| 115 | static inline bool hri_dsu_get_STATUSB_TDCCD1_bit(const void *const hw) |
| 116 | { |
| 117 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD1) >> DSU_STATUSB_TDCCD1_Pos; |
| 118 | } |
| 119 | |
| 120 | static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) |
| 121 | { |
| 122 | uint8_t tmp; |
| 123 | tmp = ((Dsu *)hw)->STATUSB.reg; |
| 124 | tmp &= mask; |
| 125 | return tmp; |
| 126 | } |
| 127 | |
| 128 | static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) |
| 129 | { |
| 130 | return ((Dsu *)hw)->STATUSB.reg; |
| 131 | } |
| 132 | |
| 133 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 134 | { |
| 135 | return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; |
| 136 | } |
| 137 | |
| 138 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) |
| 139 | { |
| 140 | return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; |
| 141 | } |
| 142 | |
| 143 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 144 | { |
| 145 | return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; |
| 146 | } |
| 147 | |
| 148 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) |
| 149 | { |
| 150 | return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; |
| 151 | } |
| 152 | |
| 153 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 154 | { |
| 155 | return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; |
| 156 | } |
| 157 | |
| 158 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) |
| 159 | { |
| 160 | return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; |
| 161 | } |
| 162 | |
| 163 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 164 | { |
| 165 | return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; |
| 166 | } |
| 167 | |
| 168 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) |
| 169 | { |
| 170 | return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; |
| 171 | } |
| 172 | |
| 173 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 174 | { |
| 175 | return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; |
| 176 | } |
| 177 | |
| 178 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) |
| 179 | { |
| 180 | return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; |
| 181 | } |
| 182 | |
| 183 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 184 | { |
| 185 | return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; |
| 186 | } |
| 187 | |
| 188 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) |
| 189 | { |
| 190 | return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; |
| 191 | } |
| 192 | |
| 193 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) |
| 194 | { |
| 195 | uint32_t tmp; |
| 196 | tmp = ((Dsu *)hw)->DID.reg; |
| 197 | tmp &= mask; |
| 198 | return tmp; |
| 199 | } |
| 200 | |
| 201 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) |
| 202 | { |
| 203 | return ((Dsu *)hw)->DID.reg; |
| 204 | } |
| 205 | |
| 206 | static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) |
| 207 | { |
| 208 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; |
| 209 | } |
| 210 | |
| 211 | static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) |
| 212 | { |
| 213 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; |
| 214 | } |
| 215 | |
| 216 | static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) |
| 217 | { |
| 218 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; |
| 219 | } |
| 220 | |
| 221 | static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) |
| 222 | { |
| 223 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; |
| 224 | } |
| 225 | |
| 226 | static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) |
| 227 | { |
| 228 | uint32_t tmp; |
| 229 | tmp = ((Dsu *)hw)->ENTRY0.reg; |
| 230 | tmp &= mask; |
| 231 | return tmp; |
| 232 | } |
| 233 | |
| 234 | static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) |
| 235 | { |
| 236 | return ((Dsu *)hw)->ENTRY0.reg; |
| 237 | } |
| 238 | |
| 239 | static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) |
| 240 | { |
| 241 | uint32_t tmp; |
| 242 | tmp = ((Dsu *)hw)->ENTRY1.reg; |
| 243 | tmp &= mask; |
| 244 | return tmp; |
| 245 | } |
| 246 | |
| 247 | static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) |
| 248 | { |
| 249 | return ((Dsu *)hw)->ENTRY1.reg; |
| 250 | } |
| 251 | |
| 252 | static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) |
| 253 | { |
| 254 | return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; |
| 255 | } |
| 256 | |
| 257 | static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) |
| 258 | { |
| 259 | return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; |
| 260 | } |
| 261 | |
| 262 | static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) |
| 263 | { |
| 264 | uint32_t tmp; |
| 265 | tmp = ((Dsu *)hw)->END.reg; |
| 266 | tmp &= mask; |
| 267 | return tmp; |
| 268 | } |
| 269 | |
| 270 | static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) |
| 271 | { |
| 272 | return ((Dsu *)hw)->END.reg; |
| 273 | } |
| 274 | |
| 275 | static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) |
| 276 | { |
| 277 | return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; |
| 278 | } |
| 279 | |
| 280 | static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) |
| 281 | { |
| 282 | uint32_t tmp; |
| 283 | tmp = ((Dsu *)hw)->MEMTYPE.reg; |
| 284 | tmp &= mask; |
| 285 | return tmp; |
| 286 | } |
| 287 | |
| 288 | static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) |
| 289 | { |
| 290 | return ((Dsu *)hw)->MEMTYPE.reg; |
| 291 | } |
| 292 | |
| 293 | static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) |
| 294 | { |
| 295 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; |
| 296 | } |
| 297 | |
| 298 | static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) |
| 299 | { |
| 300 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; |
| 301 | } |
| 302 | |
| 303 | static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) |
| 304 | { |
| 305 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; |
| 306 | } |
| 307 | |
| 308 | static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) |
| 309 | { |
| 310 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; |
| 311 | } |
| 312 | |
| 313 | static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) |
| 314 | { |
| 315 | uint32_t tmp; |
| 316 | tmp = ((Dsu *)hw)->PID4.reg; |
| 317 | tmp &= mask; |
| 318 | return tmp; |
| 319 | } |
| 320 | |
| 321 | static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) |
| 322 | { |
| 323 | return ((Dsu *)hw)->PID4.reg; |
| 324 | } |
| 325 | |
| 326 | static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) |
| 327 | { |
| 328 | uint32_t tmp; |
| 329 | tmp = ((Dsu *)hw)->PID5.reg; |
| 330 | tmp &= mask; |
| 331 | return tmp; |
| 332 | } |
| 333 | |
| 334 | static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) |
| 335 | { |
| 336 | return ((Dsu *)hw)->PID5.reg; |
| 337 | } |
| 338 | |
| 339 | static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) |
| 340 | { |
| 341 | uint32_t tmp; |
| 342 | tmp = ((Dsu *)hw)->PID6.reg; |
| 343 | tmp &= mask; |
| 344 | return tmp; |
| 345 | } |
| 346 | |
| 347 | static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) |
| 348 | { |
| 349 | return ((Dsu *)hw)->PID6.reg; |
| 350 | } |
| 351 | |
| 352 | static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) |
| 353 | { |
| 354 | uint32_t tmp; |
| 355 | tmp = ((Dsu *)hw)->PID7.reg; |
| 356 | tmp &= mask; |
| 357 | return tmp; |
| 358 | } |
| 359 | |
| 360 | static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) |
| 361 | { |
| 362 | return ((Dsu *)hw)->PID7.reg; |
| 363 | } |
| 364 | |
| 365 | static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) |
| 366 | { |
| 367 | return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; |
| 368 | } |
| 369 | |
| 370 | static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) |
| 371 | { |
| 372 | return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; |
| 373 | } |
| 374 | |
| 375 | static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) |
| 376 | { |
| 377 | uint32_t tmp; |
| 378 | tmp = ((Dsu *)hw)->PID0.reg; |
| 379 | tmp &= mask; |
| 380 | return tmp; |
| 381 | } |
| 382 | |
| 383 | static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) |
| 384 | { |
| 385 | return ((Dsu *)hw)->PID0.reg; |
| 386 | } |
| 387 | |
| 388 | static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) |
| 389 | { |
| 390 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; |
| 391 | } |
| 392 | |
| 393 | static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) |
| 394 | { |
| 395 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; |
| 396 | } |
| 397 | |
| 398 | static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) |
| 399 | { |
| 400 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; |
| 401 | } |
| 402 | |
| 403 | static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) |
| 404 | { |
| 405 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; |
| 406 | } |
| 407 | |
| 408 | static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) |
| 409 | { |
| 410 | uint32_t tmp; |
| 411 | tmp = ((Dsu *)hw)->PID1.reg; |
| 412 | tmp &= mask; |
| 413 | return tmp; |
| 414 | } |
| 415 | |
| 416 | static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) |
| 417 | { |
| 418 | return ((Dsu *)hw)->PID1.reg; |
| 419 | } |
| 420 | |
| 421 | static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) |
| 422 | { |
| 423 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; |
| 424 | } |
| 425 | |
| 426 | static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) |
| 427 | { |
| 428 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; |
| 429 | } |
| 430 | |
| 431 | static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) |
| 432 | { |
| 433 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; |
| 434 | } |
| 435 | |
| 436 | static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) |
| 437 | { |
| 438 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; |
| 439 | } |
| 440 | |
| 441 | static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) |
| 442 | { |
| 443 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; |
| 444 | } |
| 445 | |
| 446 | static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) |
| 447 | { |
| 448 | uint32_t tmp; |
| 449 | tmp = ((Dsu *)hw)->PID2.reg; |
| 450 | tmp &= mask; |
| 451 | return tmp; |
| 452 | } |
| 453 | |
| 454 | static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) |
| 455 | { |
| 456 | return ((Dsu *)hw)->PID2.reg; |
| 457 | } |
| 458 | |
| 459 | static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) |
| 460 | { |
| 461 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; |
| 462 | } |
| 463 | |
| 464 | static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) |
| 465 | { |
| 466 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; |
| 467 | } |
| 468 | |
| 469 | static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) |
| 470 | { |
| 471 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; |
| 472 | } |
| 473 | |
| 474 | static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) |
| 475 | { |
| 476 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; |
| 477 | } |
| 478 | |
| 479 | static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) |
| 480 | { |
| 481 | uint32_t tmp; |
| 482 | tmp = ((Dsu *)hw)->PID3.reg; |
| 483 | tmp &= mask; |
| 484 | return tmp; |
| 485 | } |
| 486 | |
| 487 | static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) |
| 488 | { |
| 489 | return ((Dsu *)hw)->PID3.reg; |
| 490 | } |
| 491 | |
| 492 | static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) |
| 493 | { |
| 494 | return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; |
| 495 | } |
| 496 | |
| 497 | static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) |
| 498 | { |
| 499 | return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; |
| 500 | } |
| 501 | |
| 502 | static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) |
| 503 | { |
| 504 | uint32_t tmp; |
| 505 | tmp = ((Dsu *)hw)->CID0.reg; |
| 506 | tmp &= mask; |
| 507 | return tmp; |
| 508 | } |
| 509 | |
| 510 | static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) |
| 511 | { |
| 512 | return ((Dsu *)hw)->CID0.reg; |
| 513 | } |
| 514 | |
| 515 | static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) |
| 516 | { |
| 517 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; |
| 518 | } |
| 519 | |
| 520 | static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) |
| 521 | { |
| 522 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; |
| 523 | } |
| 524 | |
| 525 | static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) |
| 526 | { |
| 527 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; |
| 528 | } |
| 529 | |
| 530 | static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) |
| 531 | { |
| 532 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; |
| 533 | } |
| 534 | |
| 535 | static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) |
| 536 | { |
| 537 | uint32_t tmp; |
| 538 | tmp = ((Dsu *)hw)->CID1.reg; |
| 539 | tmp &= mask; |
| 540 | return tmp; |
| 541 | } |
| 542 | |
| 543 | static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) |
| 544 | { |
| 545 | return ((Dsu *)hw)->CID1.reg; |
| 546 | } |
| 547 | |
| 548 | static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) |
| 549 | { |
| 550 | return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; |
| 551 | } |
| 552 | |
| 553 | static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) |
| 554 | { |
| 555 | return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; |
| 556 | } |
| 557 | |
| 558 | static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) |
| 559 | { |
| 560 | uint32_t tmp; |
| 561 | tmp = ((Dsu *)hw)->CID2.reg; |
| 562 | tmp &= mask; |
| 563 | return tmp; |
| 564 | } |
| 565 | |
| 566 | static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) |
| 567 | { |
| 568 | return ((Dsu *)hw)->CID2.reg; |
| 569 | } |
| 570 | |
| 571 | static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) |
| 572 | { |
| 573 | return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; |
| 574 | } |
| 575 | |
| 576 | static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) |
| 577 | { |
| 578 | return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; |
| 579 | } |
| 580 | |
| 581 | static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) |
| 582 | { |
| 583 | uint32_t tmp; |
| 584 | tmp = ((Dsu *)hw)->CID3.reg; |
| 585 | tmp &= mask; |
| 586 | return tmp; |
| 587 | } |
| 588 | |
| 589 | static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) |
| 590 | { |
| 591 | return ((Dsu *)hw)->CID3.reg; |
| 592 | } |
| 593 | |
| 594 | static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 595 | { |
| 596 | DSU_CRITICAL_SECTION_ENTER(); |
| 597 | ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); |
| 598 | DSU_CRITICAL_SECTION_LEAVE(); |
| 599 | } |
| 600 | |
| 601 | static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 602 | { |
| 603 | uint32_t tmp; |
| 604 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 605 | tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; |
| 606 | return tmp; |
| 607 | } |
| 608 | |
| 609 | static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) |
| 610 | { |
| 611 | uint32_t tmp; |
| 612 | DSU_CRITICAL_SECTION_ENTER(); |
| 613 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 614 | tmp &= ~DSU_ADDR_AMOD_Msk; |
| 615 | tmp |= DSU_ADDR_AMOD(data); |
| 616 | ((Dsu *)hw)->ADDR.reg = tmp; |
| 617 | DSU_CRITICAL_SECTION_LEAVE(); |
| 618 | } |
| 619 | |
| 620 | static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 621 | { |
| 622 | DSU_CRITICAL_SECTION_ENTER(); |
| 623 | ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); |
| 624 | DSU_CRITICAL_SECTION_LEAVE(); |
| 625 | } |
| 626 | |
| 627 | static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 628 | { |
| 629 | DSU_CRITICAL_SECTION_ENTER(); |
| 630 | ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); |
| 631 | DSU_CRITICAL_SECTION_LEAVE(); |
| 632 | } |
| 633 | |
| 634 | static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) |
| 635 | { |
| 636 | uint32_t tmp; |
| 637 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 638 | tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; |
| 639 | return tmp; |
| 640 | } |
| 641 | |
| 642 | static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 643 | { |
| 644 | DSU_CRITICAL_SECTION_ENTER(); |
| 645 | ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); |
| 646 | DSU_CRITICAL_SECTION_LEAVE(); |
| 647 | } |
| 648 | |
| 649 | static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 650 | { |
| 651 | uint32_t tmp; |
| 652 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 653 | tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; |
| 654 | return tmp; |
| 655 | } |
| 656 | |
| 657 | static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) |
| 658 | { |
| 659 | uint32_t tmp; |
| 660 | DSU_CRITICAL_SECTION_ENTER(); |
| 661 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 662 | tmp &= ~DSU_ADDR_ADDR_Msk; |
| 663 | tmp |= DSU_ADDR_ADDR(data); |
| 664 | ((Dsu *)hw)->ADDR.reg = tmp; |
| 665 | DSU_CRITICAL_SECTION_LEAVE(); |
| 666 | } |
| 667 | |
| 668 | static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 669 | { |
| 670 | DSU_CRITICAL_SECTION_ENTER(); |
| 671 | ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); |
| 672 | DSU_CRITICAL_SECTION_LEAVE(); |
| 673 | } |
| 674 | |
| 675 | static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 676 | { |
| 677 | DSU_CRITICAL_SECTION_ENTER(); |
| 678 | ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); |
| 679 | DSU_CRITICAL_SECTION_LEAVE(); |
| 680 | } |
| 681 | |
| 682 | static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) |
| 683 | { |
| 684 | uint32_t tmp; |
| 685 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 686 | tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; |
| 687 | return tmp; |
| 688 | } |
| 689 | |
| 690 | static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 691 | { |
| 692 | DSU_CRITICAL_SECTION_ENTER(); |
| 693 | ((Dsu *)hw)->ADDR.reg |= mask; |
| 694 | DSU_CRITICAL_SECTION_LEAVE(); |
| 695 | } |
| 696 | |
| 697 | static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 698 | { |
| 699 | uint32_t tmp; |
| 700 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 701 | tmp &= mask; |
| 702 | return tmp; |
| 703 | } |
| 704 | |
| 705 | static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) |
| 706 | { |
| 707 | DSU_CRITICAL_SECTION_ENTER(); |
| 708 | ((Dsu *)hw)->ADDR.reg = data; |
| 709 | DSU_CRITICAL_SECTION_LEAVE(); |
| 710 | } |
| 711 | |
| 712 | static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 713 | { |
| 714 | DSU_CRITICAL_SECTION_ENTER(); |
| 715 | ((Dsu *)hw)->ADDR.reg &= ~mask; |
| 716 | DSU_CRITICAL_SECTION_LEAVE(); |
| 717 | } |
| 718 | |
| 719 | static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 720 | { |
| 721 | DSU_CRITICAL_SECTION_ENTER(); |
| 722 | ((Dsu *)hw)->ADDR.reg ^= mask; |
| 723 | DSU_CRITICAL_SECTION_LEAVE(); |
| 724 | } |
| 725 | |
| 726 | static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) |
| 727 | { |
| 728 | return ((Dsu *)hw)->ADDR.reg; |
| 729 | } |
| 730 | |
| 731 | static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 732 | { |
| 733 | DSU_CRITICAL_SECTION_ENTER(); |
| 734 | ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); |
| 735 | DSU_CRITICAL_SECTION_LEAVE(); |
| 736 | } |
| 737 | |
| 738 | static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 739 | { |
| 740 | uint32_t tmp; |
| 741 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 742 | tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; |
| 743 | return tmp; |
| 744 | } |
| 745 | |
| 746 | static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) |
| 747 | { |
| 748 | uint32_t tmp; |
| 749 | DSU_CRITICAL_SECTION_ENTER(); |
| 750 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 751 | tmp &= ~DSU_LENGTH_LENGTH_Msk; |
| 752 | tmp |= DSU_LENGTH_LENGTH(data); |
| 753 | ((Dsu *)hw)->LENGTH.reg = tmp; |
| 754 | DSU_CRITICAL_SECTION_LEAVE(); |
| 755 | } |
| 756 | |
| 757 | static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 758 | { |
| 759 | DSU_CRITICAL_SECTION_ENTER(); |
| 760 | ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); |
| 761 | DSU_CRITICAL_SECTION_LEAVE(); |
| 762 | } |
| 763 | |
| 764 | static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 765 | { |
| 766 | DSU_CRITICAL_SECTION_ENTER(); |
| 767 | ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); |
| 768 | DSU_CRITICAL_SECTION_LEAVE(); |
| 769 | } |
| 770 | |
| 771 | static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) |
| 772 | { |
| 773 | uint32_t tmp; |
| 774 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 775 | tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; |
| 776 | return tmp; |
| 777 | } |
| 778 | |
| 779 | static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 780 | { |
| 781 | DSU_CRITICAL_SECTION_ENTER(); |
| 782 | ((Dsu *)hw)->LENGTH.reg |= mask; |
| 783 | DSU_CRITICAL_SECTION_LEAVE(); |
| 784 | } |
| 785 | |
| 786 | static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 787 | { |
| 788 | uint32_t tmp; |
| 789 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 790 | tmp &= mask; |
| 791 | return tmp; |
| 792 | } |
| 793 | |
| 794 | static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) |
| 795 | { |
| 796 | DSU_CRITICAL_SECTION_ENTER(); |
| 797 | ((Dsu *)hw)->LENGTH.reg = data; |
| 798 | DSU_CRITICAL_SECTION_LEAVE(); |
| 799 | } |
| 800 | |
| 801 | static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 802 | { |
| 803 | DSU_CRITICAL_SECTION_ENTER(); |
| 804 | ((Dsu *)hw)->LENGTH.reg &= ~mask; |
| 805 | DSU_CRITICAL_SECTION_LEAVE(); |
| 806 | } |
| 807 | |
| 808 | static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 809 | { |
| 810 | DSU_CRITICAL_SECTION_ENTER(); |
| 811 | ((Dsu *)hw)->LENGTH.reg ^= mask; |
| 812 | DSU_CRITICAL_SECTION_LEAVE(); |
| 813 | } |
| 814 | |
| 815 | static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) |
| 816 | { |
| 817 | return ((Dsu *)hw)->LENGTH.reg; |
| 818 | } |
| 819 | |
| 820 | static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 821 | { |
| 822 | DSU_CRITICAL_SECTION_ENTER(); |
| 823 | ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); |
| 824 | DSU_CRITICAL_SECTION_LEAVE(); |
| 825 | } |
| 826 | |
| 827 | static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 828 | { |
| 829 | uint32_t tmp; |
| 830 | tmp = ((Dsu *)hw)->DATA.reg; |
| 831 | tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; |
| 832 | return tmp; |
| 833 | } |
| 834 | |
| 835 | static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) |
| 836 | { |
| 837 | uint32_t tmp; |
| 838 | DSU_CRITICAL_SECTION_ENTER(); |
| 839 | tmp = ((Dsu *)hw)->DATA.reg; |
| 840 | tmp &= ~DSU_DATA_DATA_Msk; |
| 841 | tmp |= DSU_DATA_DATA(data); |
| 842 | ((Dsu *)hw)->DATA.reg = tmp; |
| 843 | DSU_CRITICAL_SECTION_LEAVE(); |
| 844 | } |
| 845 | |
| 846 | static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 847 | { |
| 848 | DSU_CRITICAL_SECTION_ENTER(); |
| 849 | ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); |
| 850 | DSU_CRITICAL_SECTION_LEAVE(); |
| 851 | } |
| 852 | |
| 853 | static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 854 | { |
| 855 | DSU_CRITICAL_SECTION_ENTER(); |
| 856 | ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); |
| 857 | DSU_CRITICAL_SECTION_LEAVE(); |
| 858 | } |
| 859 | |
| 860 | static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) |
| 861 | { |
| 862 | uint32_t tmp; |
| 863 | tmp = ((Dsu *)hw)->DATA.reg; |
| 864 | tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; |
| 865 | return tmp; |
| 866 | } |
| 867 | |
| 868 | static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 869 | { |
| 870 | DSU_CRITICAL_SECTION_ENTER(); |
| 871 | ((Dsu *)hw)->DATA.reg |= mask; |
| 872 | DSU_CRITICAL_SECTION_LEAVE(); |
| 873 | } |
| 874 | |
| 875 | static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 876 | { |
| 877 | uint32_t tmp; |
| 878 | tmp = ((Dsu *)hw)->DATA.reg; |
| 879 | tmp &= mask; |
| 880 | return tmp; |
| 881 | } |
| 882 | |
| 883 | static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) |
| 884 | { |
| 885 | DSU_CRITICAL_SECTION_ENTER(); |
| 886 | ((Dsu *)hw)->DATA.reg = data; |
| 887 | DSU_CRITICAL_SECTION_LEAVE(); |
| 888 | } |
| 889 | |
| 890 | static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 891 | { |
| 892 | DSU_CRITICAL_SECTION_ENTER(); |
| 893 | ((Dsu *)hw)->DATA.reg &= ~mask; |
| 894 | DSU_CRITICAL_SECTION_LEAVE(); |
| 895 | } |
| 896 | |
| 897 | static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 898 | { |
| 899 | DSU_CRITICAL_SECTION_ENTER(); |
| 900 | ((Dsu *)hw)->DATA.reg ^= mask; |
| 901 | DSU_CRITICAL_SECTION_LEAVE(); |
| 902 | } |
| 903 | |
| 904 | static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) |
| 905 | { |
| 906 | return ((Dsu *)hw)->DATA.reg; |
| 907 | } |
| 908 | |
| 909 | static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 910 | { |
| 911 | DSU_CRITICAL_SECTION_ENTER(); |
| 912 | ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); |
| 913 | DSU_CRITICAL_SECTION_LEAVE(); |
| 914 | } |
| 915 | |
| 916 | static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 917 | { |
| 918 | uint32_t tmp; |
| 919 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 920 | tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; |
| 921 | return tmp; |
| 922 | } |
| 923 | |
| 924 | static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) |
| 925 | { |
| 926 | uint32_t tmp; |
| 927 | DSU_CRITICAL_SECTION_ENTER(); |
| 928 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 929 | tmp &= ~DSU_DCC_DATA_Msk; |
| 930 | tmp |= DSU_DCC_DATA(data); |
| 931 | ((Dsu *)hw)->DCC[index].reg = tmp; |
| 932 | DSU_CRITICAL_SECTION_LEAVE(); |
| 933 | } |
| 934 | |
| 935 | static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 936 | { |
| 937 | DSU_CRITICAL_SECTION_ENTER(); |
| 938 | ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); |
| 939 | DSU_CRITICAL_SECTION_LEAVE(); |
| 940 | } |
| 941 | |
| 942 | static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 943 | { |
| 944 | DSU_CRITICAL_SECTION_ENTER(); |
| 945 | ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); |
| 946 | DSU_CRITICAL_SECTION_LEAVE(); |
| 947 | } |
| 948 | |
| 949 | static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) |
| 950 | { |
| 951 | uint32_t tmp; |
| 952 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 953 | tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; |
| 954 | return tmp; |
| 955 | } |
| 956 | |
| 957 | static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 958 | { |
| 959 | DSU_CRITICAL_SECTION_ENTER(); |
| 960 | ((Dsu *)hw)->DCC[index].reg |= mask; |
| 961 | DSU_CRITICAL_SECTION_LEAVE(); |
| 962 | } |
| 963 | |
| 964 | static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 965 | { |
| 966 | uint32_t tmp; |
| 967 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 968 | tmp &= mask; |
| 969 | return tmp; |
| 970 | } |
| 971 | |
| 972 | static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) |
| 973 | { |
| 974 | DSU_CRITICAL_SECTION_ENTER(); |
| 975 | ((Dsu *)hw)->DCC[index].reg = data; |
| 976 | DSU_CRITICAL_SECTION_LEAVE(); |
| 977 | } |
| 978 | |
| 979 | static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 980 | { |
| 981 | DSU_CRITICAL_SECTION_ENTER(); |
| 982 | ((Dsu *)hw)->DCC[index].reg &= ~mask; |
| 983 | DSU_CRITICAL_SECTION_LEAVE(); |
| 984 | } |
| 985 | |
| 986 | static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 987 | { |
| 988 | DSU_CRITICAL_SECTION_ENTER(); |
| 989 | ((Dsu *)hw)->DCC[index].reg ^= mask; |
| 990 | DSU_CRITICAL_SECTION_LEAVE(); |
| 991 | } |
| 992 | |
| 993 | static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) |
| 994 | { |
| 995 | return ((Dsu *)hw)->DCC[index].reg; |
| 996 | } |
| 997 | |
| 998 | static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) |
| 999 | { |
| 1000 | DSU_CRITICAL_SECTION_ENTER(); |
| 1001 | ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; |
| 1002 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1003 | } |
| 1004 | |
| 1005 | static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) |
| 1006 | { |
| 1007 | uint32_t tmp; |
| 1008 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1009 | tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; |
| 1010 | return (bool)tmp; |
| 1011 | } |
| 1012 | |
| 1013 | static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) |
| 1014 | { |
| 1015 | uint32_t tmp; |
| 1016 | DSU_CRITICAL_SECTION_ENTER(); |
| 1017 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1018 | tmp &= ~DSU_CFG_ETBRAMEN; |
| 1019 | tmp |= value << DSU_CFG_ETBRAMEN_Pos; |
| 1020 | ((Dsu *)hw)->CFG.reg = tmp; |
| 1021 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1022 | } |
| 1023 | |
| 1024 | static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) |
| 1025 | { |
| 1026 | DSU_CRITICAL_SECTION_ENTER(); |
| 1027 | ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; |
| 1028 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1029 | } |
| 1030 | |
| 1031 | static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) |
| 1032 | { |
| 1033 | DSU_CRITICAL_SECTION_ENTER(); |
| 1034 | ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; |
| 1035 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1036 | } |
| 1037 | |
| 1038 | static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1039 | { |
| 1040 | DSU_CRITICAL_SECTION_ENTER(); |
| 1041 | ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); |
| 1042 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1043 | } |
| 1044 | |
| 1045 | static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1046 | { |
| 1047 | uint32_t tmp; |
| 1048 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1049 | tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; |
| 1050 | return tmp; |
| 1051 | } |
| 1052 | |
| 1053 | static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) |
| 1054 | { |
| 1055 | uint32_t tmp; |
| 1056 | DSU_CRITICAL_SECTION_ENTER(); |
| 1057 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1058 | tmp &= ~DSU_CFG_LQOS_Msk; |
| 1059 | tmp |= DSU_CFG_LQOS(data); |
| 1060 | ((Dsu *)hw)->CFG.reg = tmp; |
| 1061 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1062 | } |
| 1063 | |
| 1064 | static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1065 | { |
| 1066 | DSU_CRITICAL_SECTION_ENTER(); |
| 1067 | ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); |
| 1068 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1069 | } |
| 1070 | |
| 1071 | static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1072 | { |
| 1073 | DSU_CRITICAL_SECTION_ENTER(); |
| 1074 | ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); |
| 1075 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1076 | } |
| 1077 | |
| 1078 | static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) |
| 1079 | { |
| 1080 | uint32_t tmp; |
| 1081 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1082 | tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; |
| 1083 | return tmp; |
| 1084 | } |
| 1085 | |
| 1086 | static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1087 | { |
| 1088 | DSU_CRITICAL_SECTION_ENTER(); |
| 1089 | ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); |
| 1090 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1091 | } |
| 1092 | |
| 1093 | static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1094 | { |
| 1095 | uint32_t tmp; |
| 1096 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1097 | tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; |
| 1098 | return tmp; |
| 1099 | } |
| 1100 | |
| 1101 | static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) |
| 1102 | { |
| 1103 | uint32_t tmp; |
| 1104 | DSU_CRITICAL_SECTION_ENTER(); |
| 1105 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1106 | tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; |
| 1107 | tmp |= DSU_CFG_DCCDMALEVEL(data); |
| 1108 | ((Dsu *)hw)->CFG.reg = tmp; |
| 1109 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1110 | } |
| 1111 | |
| 1112 | static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1113 | { |
| 1114 | DSU_CRITICAL_SECTION_ENTER(); |
| 1115 | ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); |
| 1116 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1117 | } |
| 1118 | |
| 1119 | static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1120 | { |
| 1121 | DSU_CRITICAL_SECTION_ENTER(); |
| 1122 | ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); |
| 1123 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1124 | } |
| 1125 | |
| 1126 | static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) |
| 1127 | { |
| 1128 | uint32_t tmp; |
| 1129 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1130 | tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; |
| 1131 | return tmp; |
| 1132 | } |
| 1133 | |
| 1134 | static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1135 | { |
| 1136 | DSU_CRITICAL_SECTION_ENTER(); |
| 1137 | ((Dsu *)hw)->CFG.reg |= mask; |
| 1138 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1139 | } |
| 1140 | |
| 1141 | static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1142 | { |
| 1143 | uint32_t tmp; |
| 1144 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1145 | tmp &= mask; |
| 1146 | return tmp; |
| 1147 | } |
| 1148 | |
| 1149 | static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) |
| 1150 | { |
| 1151 | DSU_CRITICAL_SECTION_ENTER(); |
| 1152 | ((Dsu *)hw)->CFG.reg = data; |
| 1153 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1154 | } |
| 1155 | |
| 1156 | static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1157 | { |
| 1158 | DSU_CRITICAL_SECTION_ENTER(); |
| 1159 | ((Dsu *)hw)->CFG.reg &= ~mask; |
| 1160 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1161 | } |
| 1162 | |
| 1163 | static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1164 | { |
| 1165 | DSU_CRITICAL_SECTION_ENTER(); |
| 1166 | ((Dsu *)hw)->CFG.reg ^= mask; |
| 1167 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1168 | } |
| 1169 | |
| 1170 | static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) |
| 1171 | { |
| 1172 | return ((Dsu *)hw)->CFG.reg; |
| 1173 | } |
| 1174 | |
| 1175 | static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1176 | { |
| 1177 | DSU_CRITICAL_SECTION_ENTER(); |
| 1178 | ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); |
| 1179 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1180 | } |
| 1181 | |
| 1182 | static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1183 | { |
| 1184 | uint32_t tmp; |
| 1185 | tmp = ((Dsu *)hw)->DCFG[index].reg; |
| 1186 | tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; |
| 1187 | return tmp; |
| 1188 | } |
| 1189 | |
| 1190 | static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) |
| 1191 | { |
| 1192 | uint32_t tmp; |
| 1193 | DSU_CRITICAL_SECTION_ENTER(); |
| 1194 | tmp = ((Dsu *)hw)->DCFG[index].reg; |
| 1195 | tmp &= ~DSU_DCFG_DCFG_Msk; |
| 1196 | tmp |= DSU_DCFG_DCFG(data); |
| 1197 | ((Dsu *)hw)->DCFG[index].reg = tmp; |
| 1198 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1199 | } |
| 1200 | |
| 1201 | static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1202 | { |
| 1203 | DSU_CRITICAL_SECTION_ENTER(); |
| 1204 | ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); |
| 1205 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1206 | } |
| 1207 | |
| 1208 | static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1209 | { |
| 1210 | DSU_CRITICAL_SECTION_ENTER(); |
| 1211 | ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); |
| 1212 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1213 | } |
| 1214 | |
| 1215 | static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) |
| 1216 | { |
| 1217 | uint32_t tmp; |
| 1218 | tmp = ((Dsu *)hw)->DCFG[index].reg; |
| 1219 | tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; |
| 1220 | return tmp; |
| 1221 | } |
| 1222 | |
| 1223 | static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1224 | { |
| 1225 | DSU_CRITICAL_SECTION_ENTER(); |
| 1226 | ((Dsu *)hw)->DCFG[index].reg |= mask; |
| 1227 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1228 | } |
| 1229 | |
| 1230 | static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1231 | { |
| 1232 | uint32_t tmp; |
| 1233 | tmp = ((Dsu *)hw)->DCFG[index].reg; |
| 1234 | tmp &= mask; |
| 1235 | return tmp; |
| 1236 | } |
| 1237 | |
| 1238 | static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) |
| 1239 | { |
| 1240 | DSU_CRITICAL_SECTION_ENTER(); |
| 1241 | ((Dsu *)hw)->DCFG[index].reg = data; |
| 1242 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1243 | } |
| 1244 | |
| 1245 | static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1246 | { |
| 1247 | DSU_CRITICAL_SECTION_ENTER(); |
| 1248 | ((Dsu *)hw)->DCFG[index].reg &= ~mask; |
| 1249 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1250 | } |
| 1251 | |
| 1252 | static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) |
| 1253 | { |
| 1254 | DSU_CRITICAL_SECTION_ENTER(); |
| 1255 | ((Dsu *)hw)->DCFG[index].reg ^= mask; |
| 1256 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1257 | } |
| 1258 | |
| 1259 | static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) |
| 1260 | { |
| 1261 | return ((Dsu *)hw)->DCFG[index].reg; |
| 1262 | } |
| 1263 | |
| 1264 | static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) |
| 1265 | { |
| 1266 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; |
| 1267 | } |
| 1268 | |
| 1269 | static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) |
| 1270 | { |
| 1271 | DSU_CRITICAL_SECTION_ENTER(); |
| 1272 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; |
| 1273 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1274 | } |
| 1275 | |
| 1276 | static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) |
| 1277 | { |
| 1278 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; |
| 1279 | } |
| 1280 | |
| 1281 | static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) |
| 1282 | { |
| 1283 | DSU_CRITICAL_SECTION_ENTER(); |
| 1284 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; |
| 1285 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1286 | } |
| 1287 | |
| 1288 | static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) |
| 1289 | { |
| 1290 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; |
| 1291 | } |
| 1292 | |
| 1293 | static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) |
| 1294 | { |
| 1295 | DSU_CRITICAL_SECTION_ENTER(); |
| 1296 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; |
| 1297 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1298 | } |
| 1299 | |
| 1300 | static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) |
| 1301 | { |
| 1302 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; |
| 1303 | } |
| 1304 | |
| 1305 | static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) |
| 1306 | { |
| 1307 | DSU_CRITICAL_SECTION_ENTER(); |
| 1308 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; |
| 1309 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1310 | } |
| 1311 | |
| 1312 | static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) |
| 1313 | { |
| 1314 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; |
| 1315 | } |
| 1316 | |
| 1317 | static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) |
| 1318 | { |
| 1319 | DSU_CRITICAL_SECTION_ENTER(); |
| 1320 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; |
| 1321 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1322 | } |
| 1323 | |
| 1324 | static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) |
| 1325 | { |
| 1326 | uint8_t tmp; |
| 1327 | tmp = ((Dsu *)hw)->STATUSA.reg; |
| 1328 | tmp &= mask; |
| 1329 | return tmp; |
| 1330 | } |
| 1331 | |
| 1332 | static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) |
| 1333 | { |
| 1334 | DSU_CRITICAL_SECTION_ENTER(); |
| 1335 | ((Dsu *)hw)->STATUSA.reg = mask; |
| 1336 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1337 | } |
| 1338 | |
| 1339 | static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) |
| 1340 | { |
| 1341 | return ((Dsu *)hw)->STATUSA.reg; |
| 1342 | } |
| 1343 | |
| 1344 | static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) |
| 1345 | { |
| 1346 | DSU_CRITICAL_SECTION_ENTER(); |
| 1347 | ((Dsu *)hw)->CTRL.reg = data; |
| 1348 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1349 | } |
| 1350 | |
| 1351 | #ifdef __cplusplus |
| 1352 | } |
| 1353 | #endif |
| 1354 | |
| 1355 | #endif /* _HRI_DSU_E54_H_INCLUDED */ |
| 1356 | #endif /* _SAME54_DSU_COMPONENT_ */ |