Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM CMCC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_CMCC_COMPONENT_ |
| 35 | #ifndef _HRI_CMCC_E54_H_INCLUDED_ |
| 36 | #define _HRI_CMCC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_CMCC_CRITICAL_SECTIONS) |
| 46 | #define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define CMCC_CRITICAL_SECTION_ENTER() |
| 50 | #define CMCC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_cmcc_cfg_reg_t; |
| 54 | typedef uint32_t hri_cmcc_ctrl_reg_t; |
| 55 | typedef uint32_t hri_cmcc_lckway_reg_t; |
| 56 | typedef uint32_t hri_cmcc_maint0_reg_t; |
| 57 | typedef uint32_t hri_cmcc_maint1_reg_t; |
| 58 | typedef uint32_t hri_cmcc_mcfg_reg_t; |
| 59 | typedef uint32_t hri_cmcc_mctrl_reg_t; |
| 60 | typedef uint32_t hri_cmcc_men_reg_t; |
| 61 | typedef uint32_t hri_cmcc_msr_reg_t; |
| 62 | typedef uint32_t hri_cmcc_sr_reg_t; |
| 63 | typedef uint32_t hri_cmcc_type_reg_t; |
| 64 | |
| 65 | static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) |
| 66 | { |
| 67 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; |
| 68 | } |
| 69 | |
| 70 | static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) |
| 71 | { |
| 72 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; |
| 73 | } |
| 74 | |
| 75 | static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) |
| 76 | { |
| 77 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; |
| 78 | } |
| 79 | |
| 80 | static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) |
| 81 | { |
| 82 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; |
| 83 | } |
| 84 | |
| 85 | static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) |
| 86 | { |
| 87 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; |
| 88 | } |
| 89 | |
| 90 | static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) |
| 91 | { |
| 92 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; |
| 93 | } |
| 94 | |
| 95 | static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) |
| 96 | { |
| 97 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; |
| 98 | } |
| 99 | |
| 100 | static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) |
| 101 | { |
| 102 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; |
| 103 | } |
| 104 | |
| 105 | static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) |
| 106 | { |
| 107 | return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; |
| 108 | } |
| 109 | |
| 110 | static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) |
| 111 | { |
| 112 | uint32_t tmp; |
| 113 | tmp = ((Cmcc *)hw)->TYPE.reg; |
| 114 | tmp &= mask; |
| 115 | return tmp; |
| 116 | } |
| 117 | |
| 118 | static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) |
| 119 | { |
| 120 | return ((Cmcc *)hw)->TYPE.reg; |
| 121 | } |
| 122 | |
| 123 | static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) |
| 124 | { |
| 125 | return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; |
| 126 | } |
| 127 | |
| 128 | static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) |
| 129 | { |
| 130 | uint32_t tmp; |
| 131 | tmp = ((Cmcc *)hw)->SR.reg; |
| 132 | tmp &= mask; |
| 133 | return tmp; |
| 134 | } |
| 135 | |
| 136 | static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) |
| 137 | { |
| 138 | return ((Cmcc *)hw)->SR.reg; |
| 139 | } |
| 140 | |
| 141 | static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) |
| 142 | { |
| 143 | return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; |
| 144 | } |
| 145 | |
| 146 | static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) |
| 147 | { |
| 148 | return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; |
| 149 | } |
| 150 | |
| 151 | static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) |
| 152 | { |
| 153 | uint32_t tmp; |
| 154 | tmp = ((Cmcc *)hw)->MSR.reg; |
| 155 | tmp &= mask; |
| 156 | return tmp; |
| 157 | } |
| 158 | |
| 159 | static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) |
| 160 | { |
| 161 | return ((Cmcc *)hw)->MSR.reg; |
| 162 | } |
| 163 | |
| 164 | static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) |
| 165 | { |
| 166 | CMCC_CRITICAL_SECTION_ENTER(); |
| 167 | ((Cmcc *)hw)->CFG.reg |= mask; |
| 168 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 169 | } |
| 170 | |
| 171 | static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) |
| 172 | { |
| 173 | uint32_t tmp; |
| 174 | tmp = ((Cmcc *)hw)->CFG.reg; |
| 175 | tmp &= mask; |
| 176 | return tmp; |
| 177 | } |
| 178 | |
| 179 | static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) |
| 180 | { |
| 181 | CMCC_CRITICAL_SECTION_ENTER(); |
| 182 | ((Cmcc *)hw)->CFG.reg = data; |
| 183 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 184 | } |
| 185 | |
| 186 | static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) |
| 187 | { |
| 188 | CMCC_CRITICAL_SECTION_ENTER(); |
| 189 | ((Cmcc *)hw)->CFG.reg &= ~mask; |
| 190 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 191 | } |
| 192 | |
| 193 | static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) |
| 194 | { |
| 195 | CMCC_CRITICAL_SECTION_ENTER(); |
| 196 | ((Cmcc *)hw)->CFG.reg ^= mask; |
| 197 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 198 | } |
| 199 | |
| 200 | static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) |
| 201 | { |
| 202 | return ((Cmcc *)hw)->CFG.reg; |
| 203 | } |
| 204 | |
| 205 | static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) |
| 206 | { |
| 207 | CMCC_CRITICAL_SECTION_ENTER(); |
| 208 | ((Cmcc *)hw)->LCKWAY.reg |= mask; |
| 209 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 210 | } |
| 211 | |
| 212 | static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) |
| 213 | { |
| 214 | uint32_t tmp; |
| 215 | tmp = ((Cmcc *)hw)->LCKWAY.reg; |
| 216 | tmp &= mask; |
| 217 | return tmp; |
| 218 | } |
| 219 | |
| 220 | static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) |
| 221 | { |
| 222 | CMCC_CRITICAL_SECTION_ENTER(); |
| 223 | ((Cmcc *)hw)->LCKWAY.reg = data; |
| 224 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 225 | } |
| 226 | |
| 227 | static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) |
| 228 | { |
| 229 | CMCC_CRITICAL_SECTION_ENTER(); |
| 230 | ((Cmcc *)hw)->LCKWAY.reg &= ~mask; |
| 231 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 232 | } |
| 233 | |
| 234 | static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) |
| 235 | { |
| 236 | CMCC_CRITICAL_SECTION_ENTER(); |
| 237 | ((Cmcc *)hw)->LCKWAY.reg ^= mask; |
| 238 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 239 | } |
| 240 | |
| 241 | static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) |
| 242 | { |
| 243 | return ((Cmcc *)hw)->LCKWAY.reg; |
| 244 | } |
| 245 | |
| 246 | static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) |
| 247 | { |
| 248 | CMCC_CRITICAL_SECTION_ENTER(); |
| 249 | ((Cmcc *)hw)->MCFG.reg |= mask; |
| 250 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 251 | } |
| 252 | |
| 253 | static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) |
| 254 | { |
| 255 | uint32_t tmp; |
| 256 | tmp = ((Cmcc *)hw)->MCFG.reg; |
| 257 | tmp &= mask; |
| 258 | return tmp; |
| 259 | } |
| 260 | |
| 261 | static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) |
| 262 | { |
| 263 | CMCC_CRITICAL_SECTION_ENTER(); |
| 264 | ((Cmcc *)hw)->MCFG.reg = data; |
| 265 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 266 | } |
| 267 | |
| 268 | static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) |
| 269 | { |
| 270 | CMCC_CRITICAL_SECTION_ENTER(); |
| 271 | ((Cmcc *)hw)->MCFG.reg &= ~mask; |
| 272 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 273 | } |
| 274 | |
| 275 | static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) |
| 276 | { |
| 277 | CMCC_CRITICAL_SECTION_ENTER(); |
| 278 | ((Cmcc *)hw)->MCFG.reg ^= mask; |
| 279 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 280 | } |
| 281 | |
| 282 | static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) |
| 283 | { |
| 284 | return ((Cmcc *)hw)->MCFG.reg; |
| 285 | } |
| 286 | |
| 287 | static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) |
| 288 | { |
| 289 | CMCC_CRITICAL_SECTION_ENTER(); |
| 290 | ((Cmcc *)hw)->MEN.reg |= mask; |
| 291 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 292 | } |
| 293 | |
| 294 | static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) |
| 295 | { |
| 296 | uint32_t tmp; |
| 297 | tmp = ((Cmcc *)hw)->MEN.reg; |
| 298 | tmp &= mask; |
| 299 | return tmp; |
| 300 | } |
| 301 | |
| 302 | static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) |
| 303 | { |
| 304 | CMCC_CRITICAL_SECTION_ENTER(); |
| 305 | ((Cmcc *)hw)->MEN.reg = data; |
| 306 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 307 | } |
| 308 | |
| 309 | static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) |
| 310 | { |
| 311 | CMCC_CRITICAL_SECTION_ENTER(); |
| 312 | ((Cmcc *)hw)->MEN.reg &= ~mask; |
| 313 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 314 | } |
| 315 | |
| 316 | static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) |
| 317 | { |
| 318 | CMCC_CRITICAL_SECTION_ENTER(); |
| 319 | ((Cmcc *)hw)->MEN.reg ^= mask; |
| 320 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 321 | } |
| 322 | |
| 323 | static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) |
| 324 | { |
| 325 | return ((Cmcc *)hw)->MEN.reg; |
| 326 | } |
| 327 | |
| 328 | static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) |
| 329 | { |
| 330 | CMCC_CRITICAL_SECTION_ENTER(); |
| 331 | ((Cmcc *)hw)->CTRL.reg = data; |
| 332 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 333 | } |
| 334 | |
| 335 | static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) |
| 336 | { |
| 337 | CMCC_CRITICAL_SECTION_ENTER(); |
| 338 | ((Cmcc *)hw)->MAINT0.reg = data; |
| 339 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 340 | } |
| 341 | |
| 342 | static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) |
| 343 | { |
| 344 | CMCC_CRITICAL_SECTION_ENTER(); |
| 345 | ((Cmcc *)hw)->MAINT1.reg = data; |
| 346 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 347 | } |
| 348 | |
| 349 | static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) |
| 350 | { |
| 351 | CMCC_CRITICAL_SECTION_ENTER(); |
| 352 | ((Cmcc *)hw)->MCTRL.reg = data; |
| 353 | CMCC_CRITICAL_SECTION_LEAVE(); |
| 354 | } |
| 355 | |
| 356 | #ifdef __cplusplus |
| 357 | } |
| 358 | #endif |
| 359 | |
| 360 | #endif /* _HRI_CMCC_E54_H_INCLUDED */ |
| 361 | #endif /* _SAME54_CMCC_COMPONENT_ */ |