Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /* |
Kévin Redon | 78d2f44 | 2019-01-24 18:45:59 +0100 | [diff] [blame] | 2 | * Copyright (C) 2019 sysmocom -s.f.m.c. GmbH, Author: Kevin Redon <kredon@sysmocom.de> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version 2 |
| 7 | * of the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 17 | */ |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 18 | |
Harald Welte | 1b9a5b8 | 2019-02-24 23:04:45 +0100 | [diff] [blame] | 19 | #include <stdlib.h> |
| 20 | #include <stdio.h> |
Kévin Redon | 072951b | 2019-05-02 15:17:46 +0200 | [diff] [blame^] | 21 | #include <math.h> |
Harald Welte | f53f226 | 2019-02-24 11:01:08 +0100 | [diff] [blame] | 22 | #include <parts.h> |
| 23 | #include <hal_cache.h> |
Harald Welte | 93f628a | 2019-02-24 14:32:30 +0100 | [diff] [blame] | 24 | #include <hri_port_e54.h> |
Harald Welte | f53f226 | 2019-02-24 11:01:08 +0100 | [diff] [blame] | 25 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 26 | #include "atmel_start.h" |
| 27 | #include "atmel_start_pins.h" |
Kévin Redon | 072951b | 2019-05-02 15:17:46 +0200 | [diff] [blame^] | 28 | #include "config/hpl_gclk_config.h" |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 29 | |
Harald Welte | c3f170d | 2019-02-24 09:06:59 +0100 | [diff] [blame] | 30 | #include "i2c_bitbang.h" |
| 31 | #include "octsim_i2c.h" |
| 32 | #include "ncn8025.h" |
| 33 | |
Harald Welte | ff9f4ce | 2019-02-24 22:51:09 +0100 | [diff] [blame] | 34 | #include "command.h" |
| 35 | |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 36 | // TODO put declaration in more global file |
| 37 | // TODO for now SIM7 is not present because used for debug |
| 38 | static struct usart_async_descriptor* SIM_peripheral_descriptors[] = {&SIM0, &SIM1, &SIM2, &SIM3, &SIM4, &SIM5, &SIM6, NULL}; |
| 39 | |
| 40 | static void SIM_rx_cb(const struct usart_async_descriptor *const io_descr) |
| 41 | { |
| 42 | } |
Kévin Redon | 78d2f44 | 2019-01-24 18:45:59 +0100 | [diff] [blame] | 43 | |
Kévin Redon | 072951b | 2019-05-02 15:17:46 +0200 | [diff] [blame^] | 44 | /** possible clock sources for the SERCOM peripheral |
| 45 | * warning: the definition must match the GCLK configuration |
| 46 | */ |
| 47 | static const uint8_t sercom_glck_sources[] = {GCLK_PCHCTRL_GEN_GCLK2_Val, GCLK_PCHCTRL_GEN_GCLK4_Val, GCLK_PCHCTRL_GEN_GCLK6_Val}; |
| 48 | |
| 49 | /** possible clock frequencies in MHz for the SERCOM peripheral |
| 50 | * warning: the definition must match the GCLK configuration |
| 51 | */ |
| 52 | static const double sercom_glck_freqs[] = {100E6 / CONF_GCLK_GEN_2_DIV, 100E6 / CONF_GCLK_GEN_4_DIV, 120E6 / CONF_GCLK_GEN_6_DIV}; |
| 53 | |
| 54 | /** the GCLK ID for the SERCOM SIM peripherals |
| 55 | * @note: used as index for PCHCTRL |
| 56 | */ |
| 57 | static const uint8_t SIM_peripheral_GCLK_ID[] = {SERCOM0_GCLK_ID_CORE, SERCOM1_GCLK_ID_CORE, SERCOM2_GCLK_ID_CORE, SERCOM3_GCLK_ID_CORE, SERCOM4_GCLK_ID_CORE, SERCOM5_GCLK_ID_CORE, SERCOM6_GCLK_ID_CORE, SERCOM7_GCLK_ID_CORE}; |
| 58 | |
Harald Welte | c3f170d | 2019-02-24 09:06:59 +0100 | [diff] [blame] | 59 | static void board_init() |
| 60 | { |
| 61 | int i; |
| 62 | |
| 63 | for (i = 0; i < 4; i++) |
| 64 | i2c_init(&i2c[i]); |
| 65 | |
Harald Welte | 255da5e | 2019-04-16 18:19:53 +0200 | [diff] [blame] | 66 | for (i = 0; i < 8; i++) |
Harald Welte | c3f170d | 2019-02-24 09:06:59 +0100 | [diff] [blame] | 67 | ncn8025_init(i); |
Harald Welte | f53f226 | 2019-02-24 11:01:08 +0100 | [diff] [blame] | 68 | |
| 69 | cache_init(); |
| 70 | cache_enable(CMCC); |
Harald Welte | 93f628a | 2019-02-24 14:32:30 +0100 | [diff] [blame] | 71 | |
| 72 | /* increase drive strength of 20Mhz SIM clock output to 8mA |
| 73 | * (there are 8 inputs + traces to drive!) */ |
| 74 | hri_port_set_PINCFG_DRVSTR_bit(PORT, 0, 11); |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 75 | |
| 76 | // enable SIM interfaces |
| 77 | for (uint8_t i = 0; i < ARRAY_SIZE(SIM_peripheral_descriptors); i++) { |
| 78 | if (NULL == SIM_peripheral_descriptors[i]) { |
| 79 | continue; |
| 80 | } |
| 81 | usart_async_register_callback(SIM_peripheral_descriptors[i], USART_ASYNC_RXC_CB, SIM_rx_cb); // required for RX to work, even if the callback does nothing |
| 82 | usart_async_enable(SIM_peripheral_descriptors[i]); |
| 83 | } |
Harald Welte | c3f170d | 2019-02-24 09:06:59 +0100 | [diff] [blame] | 84 | } |
| 85 | |
Harald Welte | 1b9a5b8 | 2019-02-24 23:04:45 +0100 | [diff] [blame] | 86 | static int validate_slotnr(int argc, char **argv, int idx) |
| 87 | { |
| 88 | int slotnr; |
| 89 | if (argc < idx+1) { |
| 90 | printf("You have to specify the slot number (0..7)\r\n"); |
| 91 | return -1; |
| 92 | } |
| 93 | slotnr = atoi(argv[idx]); |
| 94 | if (slotnr < 0 || slotnr > 7) { |
| 95 | printf("You have to specify the slot number (0..7)\r\n"); |
| 96 | return -1; |
| 97 | } |
| 98 | return slotnr; |
| 99 | } |
| 100 | |
Kévin Redon | 072951b | 2019-05-02 15:17:46 +0200 | [diff] [blame^] | 101 | /** change baud rate of card slot |
| 102 | * @param[in] slotnr slot number for which the baud rate should be set |
| 103 | * @param[in] baudrate baud rate in bps to set |
| 104 | * @return if the baud rate has been set, else a parameter is out of range |
| 105 | */ |
| 106 | static bool slot_set_baudrate(uint8_t slotnr, uint32_t baudrate) |
| 107 | { |
| 108 | ASSERT(slotnr < ARRAY_SIZE(SIM_peripheral_descriptors)); |
| 109 | |
| 110 | // calculate the error corresponding to the clock sources |
| 111 | uint16_t bauds[ARRAY_SIZE(sercom_glck_freqs)]; |
| 112 | double errors[ARRAY_SIZE(sercom_glck_freqs)]; |
| 113 | for (uint8_t i = 0; i < ARRAY_SIZE(sercom_glck_freqs); i++) { |
| 114 | double freq = sercom_glck_freqs[i]; // remember possible SERCOM frequency |
| 115 | uint32_t min = freq / (2 * (255 + 1)); // calculate the minimum baud rate for this frequency |
| 116 | uint32_t max = freq / (2 * (0 + 1)); // calculate the maximum baud rate for this frequency |
| 117 | if (baudrate < min || baudrate > max) { // baud rate it out of supported range |
| 118 | errors[i] = NAN; |
| 119 | } else { |
| 120 | uint16_t baud = round(freq / (2 * baudrate) - 1); |
| 121 | bauds[i] = baud; |
| 122 | double actual = freq / (2 * (baud + 1)); |
| 123 | errors[i] = fabs(1.0 - (actual / baudrate)); |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | // find the smallest error |
| 128 | uint8_t best = ARRAY_SIZE(sercom_glck_freqs); |
| 129 | for (uint8_t i = 0; i < ARRAY_SIZE(sercom_glck_freqs); i++) { |
| 130 | if (isnan(errors[i])) { |
| 131 | continue; |
| 132 | } |
| 133 | if (best >= ARRAY_SIZE(sercom_glck_freqs)) { |
| 134 | best = i; |
| 135 | } else if (errors[i] < errors[best]) { |
| 136 | best = i; |
| 137 | } |
| 138 | } |
| 139 | if (best >= ARRAY_SIZE(sercom_glck_freqs)) { // found no clock supporting this baud rate |
| 140 | return false; |
| 141 | } |
| 142 | |
| 143 | // set clock and baud rate |
| 144 | struct usart_async_descriptor* slot = SIM_peripheral_descriptors[slotnr]; // get slot |
| 145 | if (NULL == slot) { |
| 146 | return false; |
| 147 | } |
| 148 | printf("(%u) switching SERCOM clock to GCLK%u (freq = %lu kHz) and baud rate to %lu bps (baud = %u)\r\n", slotnr, (best + 1) * 2, (uint32_t)(round(sercom_glck_freqs[best] / 1000)), baudrate, bauds[best]); |
| 149 | while (!usart_async_is_tx_empty(slot)); // wait for transmission to complete (WARNING no timeout) |
| 150 | usart_async_disable(slot); // disable SERCOM peripheral |
| 151 | hri_gclk_clear_PCHCTRL_reg(GCLK, SIM_peripheral_GCLK_ID[slotnr], (1 << GCLK_PCHCTRL_CHEN_Pos)); // disable clock for this peripheral |
| 152 | while (hri_gclk_get_PCHCTRL_reg(GCLK, SIM_peripheral_GCLK_ID[slotnr], (1 << GCLK_PCHCTRL_CHEN_Pos))); // wait until clock is really disabled |
| 153 | // it does not seem we need to completely disable the peripheral using hri_mclk_clear_APBDMASK_SERCOMn_bit |
| 154 | hri_gclk_write_PCHCTRL_reg(GCLK, SIM_peripheral_GCLK_ID[slotnr], sercom_glck_sources[best] | (1 << GCLK_PCHCTRL_CHEN_Pos)); // set peripheral core clock and re-enable it |
| 155 | usart_async_set_baud_rate(slot, bauds[best]); // set the new baud rate |
| 156 | usart_async_enable(slot); // re-enable SERCOM peripheral |
| 157 | |
| 158 | return true; |
| 159 | } |
| 160 | |
Harald Welte | 1b9a5b8 | 2019-02-24 23:04:45 +0100 | [diff] [blame] | 161 | DEFUN(sim_status, cmd_sim_status, "sim-status", "Get state of specified NCN8025") |
| 162 | { |
| 163 | struct ncn8025_settings settings; |
| 164 | int slotnr = validate_slotnr(argc, argv, 1); |
| 165 | if (slotnr < 0) |
| 166 | return; |
| 167 | ncn8025_get(slotnr, &settings); |
| 168 | printf("SIM%d: ", slotnr); |
| 169 | ncn8025_dump(&settings); |
| 170 | printf("\r\n"); |
| 171 | } |
| 172 | |
| 173 | DEFUN(sim_power, cmd_sim_power, "sim-power", "Enable/disable SIM card power") |
| 174 | { |
| 175 | struct ncn8025_settings settings; |
| 176 | int slotnr = validate_slotnr(argc, argv, 1); |
| 177 | int enable; |
| 178 | |
| 179 | if (slotnr < 0) |
| 180 | return; |
| 181 | |
| 182 | if (argc < 3) { |
| 183 | printf("You have to specify 0=disable or 1=enable\r\n"); |
| 184 | return; |
| 185 | } |
| 186 | enable = atoi(argv[2]); |
| 187 | ncn8025_get(slotnr, &settings); |
| 188 | if (enable) |
| 189 | settings.cmdvcc = true; |
| 190 | else |
| 191 | settings.cmdvcc = false; |
| 192 | ncn8025_set(slotnr, &settings); |
| 193 | } |
| 194 | |
| 195 | DEFUN(sim_reset, cmd_sim_reset, "sim-reset", "Enable/disable SIM reset") |
| 196 | { |
| 197 | struct ncn8025_settings settings; |
| 198 | int slotnr = validate_slotnr(argc, argv, 1); |
| 199 | int enable; |
| 200 | |
| 201 | if (slotnr < 0) |
| 202 | return; |
| 203 | |
| 204 | if (argc < 3) { |
| 205 | printf("You have to specify 0=disable or 1=enable\r\n"); |
| 206 | return; |
| 207 | } |
| 208 | enable = atoi(argv[2]); |
| 209 | ncn8025_get(slotnr, &settings); |
| 210 | if (enable) |
| 211 | settings.rstin = true; |
| 212 | else |
| 213 | settings.rstin = false; |
| 214 | ncn8025_set(slotnr, &settings); |
| 215 | } |
| 216 | |
| 217 | DEFUN(sim_clkdiv, cmd_sim_clkdiv, "sim-clkdiv", "Set SIM clock divider (1,2,4,8)") |
| 218 | { |
| 219 | struct ncn8025_settings settings; |
| 220 | int slotnr = validate_slotnr(argc, argv, 1); |
| 221 | int clkdiv; |
| 222 | |
| 223 | if (slotnr < 0) |
| 224 | return; |
| 225 | |
| 226 | if (argc < 3) { |
| 227 | printf("You have to specify a valid divider (1,2,4,8)\r\n"); |
| 228 | return; |
| 229 | } |
| 230 | clkdiv = atoi(argv[2]); |
| 231 | if (clkdiv != 1 && clkdiv != 2 && clkdiv != 4 && clkdiv != 8) { |
| 232 | printf("You have to specify a valid divider (1,2,4,8)\r\n"); |
| 233 | return; |
| 234 | } |
| 235 | ncn8025_get(slotnr, &settings); |
| 236 | switch (clkdiv) { |
| 237 | case 1: |
| 238 | settings.clkdiv = SIM_CLKDIV_1; |
| 239 | break; |
| 240 | case 2: |
| 241 | settings.clkdiv = SIM_CLKDIV_2; |
| 242 | break; |
| 243 | case 4: |
| 244 | settings.clkdiv = SIM_CLKDIV_4; |
| 245 | break; |
| 246 | case 8: |
| 247 | settings.clkdiv = SIM_CLKDIV_8; |
| 248 | break; |
| 249 | } |
| 250 | ncn8025_set(slotnr, &settings); |
| 251 | } |
| 252 | |
| 253 | DEFUN(sim_voltage, cmd_sim_voltage, "sim-voltage", "Set SIM voltage (5/3/1.8)") |
| 254 | { |
| 255 | struct ncn8025_settings settings; |
| 256 | int slotnr = validate_slotnr(argc, argv, 1); |
| 257 | |
| 258 | if (slotnr < 0) |
| 259 | return; |
| 260 | |
| 261 | if (argc < 3) { |
| 262 | printf("You have to specify a valid voltage (5/3/1.8)\r\n"); |
| 263 | return; |
| 264 | } |
| 265 | ncn8025_get(slotnr, &settings); |
| 266 | if (!strcmp(argv[2], "5")) |
| 267 | settings.vsel = SIM_VOLT_5V0; |
| 268 | else if (!strcmp(argv[2], "3")) |
| 269 | settings.vsel = SIM_VOLT_3V0; |
| 270 | else if (!strcmp(argv[2], "1.8")) |
| 271 | settings.vsel = SIM_VOLT_1V8; |
| 272 | else { |
| 273 | printf("You have to specify a valid voltage (5/3/1.8)\r\n"); |
| 274 | return; |
| 275 | } |
| 276 | ncn8025_set(slotnr, &settings); |
| 277 | } |
| 278 | |
| 279 | DEFUN(sim_led, cmd_sim_led, "sim-led", "Set SIM LED (1=on, 0=off)") |
| 280 | { |
| 281 | struct ncn8025_settings settings; |
| 282 | int slotnr = validate_slotnr(argc, argv, 1); |
| 283 | |
| 284 | if (slotnr < 0) |
| 285 | return; |
| 286 | |
| 287 | if (argc < 3) { |
| 288 | printf("You have to specify 0=disable or 1=enable\r\n"); |
| 289 | return; |
| 290 | } |
| 291 | ncn8025_get(slotnr, &settings); |
| 292 | if (atoi(argv[2])) |
| 293 | settings.led = true; |
| 294 | else |
| 295 | settings.led = false; |
| 296 | ncn8025_set(slotnr, &settings); |
| 297 | } |
| 298 | |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 299 | DEFUN(sim_atr, cmd_sim_atr, "sim-atr", "Read ATR from SIM card") |
| 300 | { |
| 301 | struct ncn8025_settings settings; |
| 302 | int slotnr = validate_slotnr(argc, argv, 1); |
Harald Welte | 1b9a5b8 | 2019-02-24 23:04:45 +0100 | [diff] [blame] | 303 | |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 304 | if (slotnr < 0 || slotnr >= ARRAY_SIZE(SIM_peripheral_descriptors) || NULL == SIM_peripheral_descriptors[slotnr]) { |
| 305 | return; |
| 306 | } |
| 307 | |
| 308 | // check if card is present (and read current settings) |
| 309 | ncn8025_get(slotnr, &settings); |
| 310 | if (!settings.simpres) { |
| 311 | printf("no card present in slot %d, aborting\r\n", slotnr); |
| 312 | return; |
| 313 | } |
| 314 | |
| 315 | // switch card off (assert reset and disable power) |
| 316 | // note: ISO/IEC 7816-3:2006 section 6.4 provides the deactivation sequence, but not the minimum corresponding times |
| 317 | settings.rstin = true; |
| 318 | settings.cmdvcc = false; |
Harald Welte | dcf5783 | 2019-04-17 17:29:41 +0200 | [diff] [blame] | 319 | settings.led = true; |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 320 | ncn8025_set(slotnr, &settings); |
| 321 | |
| 322 | // TODO wait some time for card to be completely deactivated |
| 323 | usart_async_flush_rx_buffer(SIM_peripheral_descriptors[slotnr]); // flush RX buffer to start from scratch |
| 324 | |
Kévin Redon | 072951b | 2019-05-02 15:17:46 +0200 | [diff] [blame^] | 325 | slot_set_baudrate(slotnr, 2500000 / (372 / 1)); // set USART baud rate to match the interface (f = 2.5 MHz) and card default settings (Fd = 372, Dd = 1) |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 326 | // set clock to lowest frequency (20 MHz / 8 = 2.5 MHz) |
| 327 | // note: according to ISO/IEC 7816-3:2006 section 5.2.3 the minimum value is 1 MHz, and maximum is 5 MHz during activation |
| 328 | settings.clkdiv = SIM_CLKDIV_8; |
| 329 | // set card voltage to 3.0 V (the most supported) |
| 330 | // note: according to ISO/IEC 7816-3:2006 no voltage should damage the card, and you should cycle from low to high |
| 331 | settings.vsel = SIM_VOLT_3V0; |
| 332 | // provide power (the NCN8025 should perform the activation according to spec) |
| 333 | // note: activation sequence is documented in ISO/IEC 7816-3:2006 section 6.2 |
| 334 | settings.cmdvcc = true; |
| 335 | ncn8025_set(slotnr, &settings); |
| 336 | |
| 337 | // wait for Tb=400 cycles before re-asserting reset |
| 338 | delay_us(400 * 10000 / 2500); // 400 cycles * 1000 for us, 2.5 MHz / 1000 for us |
| 339 | |
| 340 | // de-assert reset to switch card back on |
| 341 | settings.rstin = false; |
| 342 | ncn8025_set(slotnr, &settings); |
| 343 | |
| 344 | // wait for Tc=40000 cycles for transmission to start |
| 345 | uint32_t cycles = 40000; |
| 346 | while (cycles && !usart_async_is_rx_not_empty(SIM_peripheral_descriptors[slotnr])) { |
| 347 | delay_us(10); |
| 348 | cycles -= 25; // 10 us = 25 cycles at 2.5 MHz |
| 349 | } |
| 350 | if (!usart_async_is_rx_not_empty(SIM_peripheral_descriptors[slotnr])) { |
| 351 | delay_us(12 * 372 / 1 / 2); // wait more than one byte (approximate freq down to 2 MHz) |
| 352 | } |
| 353 | // verify if one byte has been received |
| 354 | if (!usart_async_is_rx_not_empty(SIM_peripheral_descriptors[slotnr])) { |
| 355 | printf("card in slot %d is not responding, aborting\r\n", slotnr); |
| 356 | return; |
| 357 | } |
| 358 | |
| 359 | // read ATR (just do it until there is no traffic anymore) |
| 360 | // TODO the ATR should be parsed to read the right number of bytes |
Harald Welte | 0772581 | 2019-04-17 17:30:28 +0200 | [diff] [blame] | 361 | printf("(%d) ATR: ", slotnr); |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 362 | uint8_t atr_byte; |
| 363 | while (usart_async_is_rx_not_empty(SIM_peripheral_descriptors[slotnr])) { |
| 364 | if (1 == io_read(&SIM_peripheral_descriptors[slotnr]->io, &atr_byte, 1)) { |
| 365 | printf("%02x ", atr_byte); |
| 366 | } |
| 367 | uint16_t wt = 9600; // waiting time in ETU |
| 368 | while (wt && !usart_async_is_rx_not_empty(SIM_peripheral_descriptors[slotnr])) { |
| 369 | delay_us(149); // wait for 1 ETU (372 / 1 / 2.5 MHz = 148.8 us) |
| 370 | wt--; |
| 371 | } |
| 372 | } |
| 373 | printf("\r\n"); |
Harald Welte | dcf5783 | 2019-04-17 17:29:41 +0200 | [diff] [blame] | 374 | |
| 375 | /* disable VCC and LED, re-enable RST */ |
| 376 | settings.cmdvcc = false; |
| 377 | settings.rstin = true; |
| 378 | settings.led = false; |
| 379 | ncn8025_set(slotnr, &settings); |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 380 | } |
Harald Welte | 1b9a5b8 | 2019-02-24 23:04:45 +0100 | [diff] [blame] | 381 | |
Harald Welte | 67b2aba | 2019-04-16 20:47:22 +0200 | [diff] [blame] | 382 | extern void testmode_init(void); |
Harald Welte | 1b9a5b8 | 2019-02-24 23:04:45 +0100 | [diff] [blame] | 383 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 384 | int main(void) |
| 385 | { |
| 386 | atmel_start_init(); |
Kévin Redon | 78d2f44 | 2019-01-24 18:45:59 +0100 | [diff] [blame] | 387 | |
Kévin Redon | 8e53800 | 2019-01-30 11:19:19 +0100 | [diff] [blame] | 388 | usb_start(); |
| 389 | |
Harald Welte | c3f170d | 2019-02-24 09:06:59 +0100 | [diff] [blame] | 390 | board_init(); |
Harald Welte | ff9f4ce | 2019-02-24 22:51:09 +0100 | [diff] [blame] | 391 | command_init("sysmoOCTSIM> "); |
Harald Welte | 1b9a5b8 | 2019-02-24 23:04:45 +0100 | [diff] [blame] | 392 | command_register(&cmd_sim_status); |
| 393 | command_register(&cmd_sim_power); |
| 394 | command_register(&cmd_sim_reset); |
| 395 | command_register(&cmd_sim_clkdiv); |
| 396 | command_register(&cmd_sim_voltage); |
| 397 | command_register(&cmd_sim_led); |
Kévin Redon | c89bb8c | 2019-04-17 01:20:23 +0200 | [diff] [blame] | 398 | command_register(&cmd_sim_atr); |
Harald Welte | 67b2aba | 2019-04-16 20:47:22 +0200 | [diff] [blame] | 399 | testmode_init(); |
Harald Welte | c3f170d | 2019-02-24 09:06:59 +0100 | [diff] [blame] | 400 | |
Harald Welte | 361ed20 | 2019-02-24 21:15:39 +0100 | [diff] [blame] | 401 | printf("\r\n\r\nsysmocom sysmoOCTSIM\r\n"); |
Harald Welte | e7aa534 | 2019-04-16 21:11:14 +0200 | [diff] [blame] | 402 | |
| 403 | command_print_prompt(); |
Kévin Redon | 8e53800 | 2019-01-30 11:19:19 +0100 | [diff] [blame] | 404 | while (true) { // main loop |
Harald Welte | ff9f4ce | 2019-02-24 22:51:09 +0100 | [diff] [blame] | 405 | command_try_recv(); |
Kévin Redon | 8e53800 | 2019-01-30 11:19:19 +0100 | [diff] [blame] | 406 | } |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 407 | } |