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gerrit.osmocom.org / osmo-ccid-firmware / 059d1b0eec6fc1bc16ab84ce3fb606e52f52b8ff / . / sysmoOCTSIM / include / instance / tcc4.h
blob: 6709d38eb35cc3e133eff445bbd27edf3c4e4727 [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief Instance description for TCC4
5 *
6 * Copyright (c) 2018 Microchip Technology Inc.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * \asf_license_stop
27 *
28 */
29
30#ifndef _SAME54_TCC4_INSTANCE_
31#define _SAME54_TCC4_INSTANCE_
32
33/* ========== Register definition for TCC4 peripheral ========== */
34#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35#define REG_TCC4_CTRLA (0x43001000) /**< \brief (TCC4) Control A */
36#define REG_TCC4_CTRLBCLR (0x43001004) /**< \brief (TCC4) Control B Clear */
37#define REG_TCC4_CTRLBSET (0x43001005) /**< \brief (TCC4) Control B Set */
38#define REG_TCC4_SYNCBUSY (0x43001008) /**< \brief (TCC4) Synchronization Busy */
39#define REG_TCC4_FCTRLA (0x4300100C) /**< \brief (TCC4) Recoverable Fault A Configuration */
40#define REG_TCC4_FCTRLB (0x43001010) /**< \brief (TCC4) Recoverable Fault B Configuration */
41#define REG_TCC4_DRVCTRL (0x43001018) /**< \brief (TCC4) Driver Control */
42#define REG_TCC4_DBGCTRL (0x4300101E) /**< \brief (TCC4) Debug Control */
43#define REG_TCC4_EVCTRL (0x43001020) /**< \brief (TCC4) Event Control */
44#define REG_TCC4_INTENCLR (0x43001024) /**< \brief (TCC4) Interrupt Enable Clear */
45#define REG_TCC4_INTENSET (0x43001028) /**< \brief (TCC4) Interrupt Enable Set */
46#define REG_TCC4_INTFLAG (0x4300102C) /**< \brief (TCC4) Interrupt Flag Status and Clear */
47#define REG_TCC4_STATUS (0x43001030) /**< \brief (TCC4) Status */
48#define REG_TCC4_COUNT (0x43001034) /**< \brief (TCC4) Count */
49#define REG_TCC4_WAVE (0x4300103C) /**< \brief (TCC4) Waveform Control */
50#define REG_TCC4_PER (0x43001040) /**< \brief (TCC4) Period */
51#define REG_TCC4_CC0 (0x43001044) /**< \brief (TCC4) Compare and Capture 0 */
52#define REG_TCC4_CC1 (0x43001048) /**< \brief (TCC4) Compare and Capture 1 */
53#define REG_TCC4_PERBUF (0x4300106C) /**< \brief (TCC4) Period Buffer */
54#define REG_TCC4_CCBUF0 (0x43001070) /**< \brief (TCC4) Compare and Capture Buffer 0 */
55#define REG_TCC4_CCBUF1 (0x43001074) /**< \brief (TCC4) Compare and Capture Buffer 1 */
56#else
57#define REG_TCC4_CTRLA (*(RwReg *)0x43001000UL) /**< \brief (TCC4) Control A */
58#define REG_TCC4_CTRLBCLR (*(RwReg8 *)0x43001004UL) /**< \brief (TCC4) Control B Clear */
59#define REG_TCC4_CTRLBSET (*(RwReg8 *)0x43001005UL) /**< \brief (TCC4) Control B Set */
60#define REG_TCC4_SYNCBUSY (*(RoReg *)0x43001008UL) /**< \brief (TCC4) Synchronization Busy */
61#define REG_TCC4_FCTRLA (*(RwReg *)0x4300100CUL) /**< \brief (TCC4) Recoverable Fault A Configuration */
62#define REG_TCC4_FCTRLB (*(RwReg *)0x43001010UL) /**< \brief (TCC4) Recoverable Fault B Configuration */
63#define REG_TCC4_DRVCTRL (*(RwReg *)0x43001018UL) /**< \brief (TCC4) Driver Control */
64#define REG_TCC4_DBGCTRL (*(RwReg8 *)0x4300101EUL) /**< \brief (TCC4) Debug Control */
65#define REG_TCC4_EVCTRL (*(RwReg *)0x43001020UL) /**< \brief (TCC4) Event Control */
66#define REG_TCC4_INTENCLR (*(RwReg *)0x43001024UL) /**< \brief (TCC4) Interrupt Enable Clear */
67#define REG_TCC4_INTENSET (*(RwReg *)0x43001028UL) /**< \brief (TCC4) Interrupt Enable Set */
68#define REG_TCC4_INTFLAG (*(RwReg *)0x4300102CUL) /**< \brief (TCC4) Interrupt Flag Status and Clear */
69#define REG_TCC4_STATUS (*(RwReg *)0x43001030UL) /**< \brief (TCC4) Status */
70#define REG_TCC4_COUNT (*(RwReg *)0x43001034UL) /**< \brief (TCC4) Count */
71#define REG_TCC4_WAVE (*(RwReg *)0x4300103CUL) /**< \brief (TCC4) Waveform Control */
72#define REG_TCC4_PER (*(RwReg *)0x43001040UL) /**< \brief (TCC4) Period */
73#define REG_TCC4_CC0 (*(RwReg *)0x43001044UL) /**< \brief (TCC4) Compare and Capture 0 */
74#define REG_TCC4_CC1 (*(RwReg *)0x43001048UL) /**< \brief (TCC4) Compare and Capture 1 */
75#define REG_TCC4_PERBUF (*(RwReg *)0x4300106CUL) /**< \brief (TCC4) Period Buffer */
76#define REG_TCC4_CCBUF0 (*(RwReg *)0x43001070UL) /**< \brief (TCC4) Compare and Capture Buffer 0 */
77#define REG_TCC4_CCBUF1 (*(RwReg *)0x43001074UL) /**< \brief (TCC4) Compare and Capture Buffer 1 */
78#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
79
80/* ========== Instance parameters for TCC4 peripheral ========== */
81#define TCC4_CC_NUM 2 // Number of Compare/Capture units
82#define TCC4_DITHERING 0 // Dithering feature implemented
83#define TCC4_DMAC_ID_MC_0 42
84#define TCC4_DMAC_ID_MC_1 43
85#define TCC4_DMAC_ID_MC_LSB 42
86#define TCC4_DMAC_ID_MC_MSB 43
87#define TCC4_DMAC_ID_MC_SIZE 2
88#define TCC4_DMAC_ID_OVF 41 // DMA overflow/underflow/retrigger trigger
89#define TCC4_DTI 0 // Dead-Time-Insertion feature implemented
90#define TCC4_EXT 0 // Coding of implemented extended features
91#define TCC4_GCLK_ID 38 // Index of Generic Clock
92#define TCC4_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
93#define TCC4_OTMX 0 // Output Matrix feature implemented
94#define TCC4_OW_NUM 2 // Number of Output Waveforms
95#define TCC4_PG 0 // Pattern Generation feature implemented
96#define TCC4_SIZE 16
97#define TCC4_SWAP 0 // DTI outputs swap feature implemented
98
99#endif /* _SAME54_TCC4_INSTANCE_ */