| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for OSC32KCTRL |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_OSC32KCTRL_INSTANCE_ |
| 31 | #define _SAME54_OSC32KCTRL_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for OSC32KCTRL peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ |
| 36 | #define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ |
| 37 | #define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ |
| 38 | #define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */ |
| 39 | #define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */ |
| 40 | #define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| 41 | #define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ |
| 42 | #define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */ |
| 43 | #define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| 44 | #else |
| 45 | #define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ |
| 46 | #define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ |
| 47 | #define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ |
| 48 | #define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */ |
| 49 | #define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */ |
| 50 | #define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| 51 | #define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ |
| 52 | #define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */ |
| 53 | #define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| 54 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 55 | |
| 56 | /* ========== Instance parameters for OSC32KCTRL peripheral ========== */ |
| 57 | #define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 0 // OSC32K coarse calibration size |
| 58 | |
| 59 | #endif /* _SAME54_OSC32KCTRL_INSTANCE_ */ |