Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM NVIC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_NVIC_COMPONENT_ |
| 35 | #ifndef _HRI_NVIC_E54_H_INCLUDED_ |
| 36 | #define _HRI_NVIC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_NVIC_CRITICAL_SECTIONS) |
| 46 | #define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define NVIC_CRITICAL_SECTION_ENTER() |
| 50 | #define NVIC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_nvic_iabr_reg_t; |
| 54 | typedef uint32_t hri_nvic_icer_reg_t; |
| 55 | typedef uint32_t hri_nvic_icpr_reg_t; |
| 56 | typedef uint32_t hri_nvic_iser_reg_t; |
| 57 | typedef uint32_t hri_nvic_ispr_reg_t; |
| 58 | typedef uint32_t hri_nvic_stir_reg_t; |
| 59 | typedef uint8_t hri_nvic_ip_reg_t; |
| 60 | |
| 61 | static inline void hri_nvic_set_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask) |
| 62 | { |
| 63 | NVIC_CRITICAL_SECTION_ENTER(); |
| 64 | ((Nvic *)hw)->ISER[index].reg |= mask; |
| 65 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 66 | } |
| 67 | |
| 68 | static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask) |
| 69 | { |
| 70 | uint32_t tmp; |
| 71 | tmp = ((Nvic *)hw)->ISER[index].reg; |
| 72 | tmp &= mask; |
| 73 | return tmp; |
| 74 | } |
| 75 | |
| 76 | static inline void hri_nvic_write_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t data) |
| 77 | { |
| 78 | NVIC_CRITICAL_SECTION_ENTER(); |
| 79 | ((Nvic *)hw)->ISER[index].reg = data; |
| 80 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 81 | } |
| 82 | |
| 83 | static inline void hri_nvic_clear_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask) |
| 84 | { |
| 85 | NVIC_CRITICAL_SECTION_ENTER(); |
| 86 | ((Nvic *)hw)->ISER[index].reg &= ~mask; |
| 87 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 88 | } |
| 89 | |
| 90 | static inline void hri_nvic_toggle_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask) |
| 91 | { |
| 92 | NVIC_CRITICAL_SECTION_ENTER(); |
| 93 | ((Nvic *)hw)->ISER[index].reg ^= mask; |
| 94 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 95 | } |
| 96 | |
| 97 | static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw, uint8_t index) |
| 98 | { |
| 99 | return ((Nvic *)hw)->ISER[index].reg; |
| 100 | } |
| 101 | |
| 102 | static inline void hri_nvic_set_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask) |
| 103 | { |
| 104 | NVIC_CRITICAL_SECTION_ENTER(); |
| 105 | ((Nvic *)hw)->ICER[index].reg |= mask; |
| 106 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 107 | } |
| 108 | |
| 109 | static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask) |
| 110 | { |
| 111 | uint32_t tmp; |
| 112 | tmp = ((Nvic *)hw)->ICER[index].reg; |
| 113 | tmp &= mask; |
| 114 | return tmp; |
| 115 | } |
| 116 | |
| 117 | static inline void hri_nvic_write_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t data) |
| 118 | { |
| 119 | NVIC_CRITICAL_SECTION_ENTER(); |
| 120 | ((Nvic *)hw)->ICER[index].reg = data; |
| 121 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 122 | } |
| 123 | |
| 124 | static inline void hri_nvic_clear_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask) |
| 125 | { |
| 126 | NVIC_CRITICAL_SECTION_ENTER(); |
| 127 | ((Nvic *)hw)->ICER[index].reg &= ~mask; |
| 128 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 129 | } |
| 130 | |
| 131 | static inline void hri_nvic_toggle_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask) |
| 132 | { |
| 133 | NVIC_CRITICAL_SECTION_ENTER(); |
| 134 | ((Nvic *)hw)->ICER[index].reg ^= mask; |
| 135 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 136 | } |
| 137 | |
| 138 | static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw, uint8_t index) |
| 139 | { |
| 140 | return ((Nvic *)hw)->ICER[index].reg; |
| 141 | } |
| 142 | |
| 143 | static inline void hri_nvic_set_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask) |
| 144 | { |
| 145 | NVIC_CRITICAL_SECTION_ENTER(); |
| 146 | ((Nvic *)hw)->ISPR[index].reg |= mask; |
| 147 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 148 | } |
| 149 | |
| 150 | static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask) |
| 151 | { |
| 152 | uint32_t tmp; |
| 153 | tmp = ((Nvic *)hw)->ISPR[index].reg; |
| 154 | tmp &= mask; |
| 155 | return tmp; |
| 156 | } |
| 157 | |
| 158 | static inline void hri_nvic_write_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t data) |
| 159 | { |
| 160 | NVIC_CRITICAL_SECTION_ENTER(); |
| 161 | ((Nvic *)hw)->ISPR[index].reg = data; |
| 162 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 163 | } |
| 164 | |
| 165 | static inline void hri_nvic_clear_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask) |
| 166 | { |
| 167 | NVIC_CRITICAL_SECTION_ENTER(); |
| 168 | ((Nvic *)hw)->ISPR[index].reg &= ~mask; |
| 169 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 170 | } |
| 171 | |
| 172 | static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask) |
| 173 | { |
| 174 | NVIC_CRITICAL_SECTION_ENTER(); |
| 175 | ((Nvic *)hw)->ISPR[index].reg ^= mask; |
| 176 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 177 | } |
| 178 | |
| 179 | static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw, uint8_t index) |
| 180 | { |
| 181 | return ((Nvic *)hw)->ISPR[index].reg; |
| 182 | } |
| 183 | |
| 184 | static inline void hri_nvic_set_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask) |
| 185 | { |
| 186 | NVIC_CRITICAL_SECTION_ENTER(); |
| 187 | ((Nvic *)hw)->ICPR[index].reg |= mask; |
| 188 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 189 | } |
| 190 | |
| 191 | static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask) |
| 192 | { |
| 193 | uint32_t tmp; |
| 194 | tmp = ((Nvic *)hw)->ICPR[index].reg; |
| 195 | tmp &= mask; |
| 196 | return tmp; |
| 197 | } |
| 198 | |
| 199 | static inline void hri_nvic_write_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t data) |
| 200 | { |
| 201 | NVIC_CRITICAL_SECTION_ENTER(); |
| 202 | ((Nvic *)hw)->ICPR[index].reg = data; |
| 203 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 204 | } |
| 205 | |
| 206 | static inline void hri_nvic_clear_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask) |
| 207 | { |
| 208 | NVIC_CRITICAL_SECTION_ENTER(); |
| 209 | ((Nvic *)hw)->ICPR[index].reg &= ~mask; |
| 210 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 211 | } |
| 212 | |
| 213 | static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask) |
| 214 | { |
| 215 | NVIC_CRITICAL_SECTION_ENTER(); |
| 216 | ((Nvic *)hw)->ICPR[index].reg ^= mask; |
| 217 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 218 | } |
| 219 | |
| 220 | static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw, uint8_t index) |
| 221 | { |
| 222 | return ((Nvic *)hw)->ICPR[index].reg; |
| 223 | } |
| 224 | |
| 225 | static inline void hri_nvic_set_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask) |
| 226 | { |
| 227 | NVIC_CRITICAL_SECTION_ENTER(); |
| 228 | ((Nvic *)hw)->IABR[index].reg |= mask; |
| 229 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 230 | } |
| 231 | |
| 232 | static inline hri_nvic_iabr_reg_t hri_nvic_get_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask) |
| 233 | { |
| 234 | uint32_t tmp; |
| 235 | tmp = ((Nvic *)hw)->IABR[index].reg; |
| 236 | tmp &= mask; |
| 237 | return tmp; |
| 238 | } |
| 239 | |
| 240 | static inline void hri_nvic_write_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t data) |
| 241 | { |
| 242 | NVIC_CRITICAL_SECTION_ENTER(); |
| 243 | ((Nvic *)hw)->IABR[index].reg = data; |
| 244 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 245 | } |
| 246 | |
| 247 | static inline void hri_nvic_clear_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask) |
| 248 | { |
| 249 | NVIC_CRITICAL_SECTION_ENTER(); |
| 250 | ((Nvic *)hw)->IABR[index].reg &= ~mask; |
| 251 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 252 | } |
| 253 | |
| 254 | static inline void hri_nvic_toggle_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask) |
| 255 | { |
| 256 | NVIC_CRITICAL_SECTION_ENTER(); |
| 257 | ((Nvic *)hw)->IABR[index].reg ^= mask; |
| 258 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 259 | } |
| 260 | |
| 261 | static inline hri_nvic_iabr_reg_t hri_nvic_read_IABR_reg(const void *const hw, uint8_t index) |
| 262 | { |
| 263 | return ((Nvic *)hw)->IABR[index].reg; |
| 264 | } |
| 265 | |
| 266 | static inline void hri_nvic_set_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask) |
| 267 | { |
| 268 | NVIC_CRITICAL_SECTION_ENTER(); |
| 269 | ((Nvic *)hw)->IP[index].reg |= mask; |
| 270 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 271 | } |
| 272 | |
| 273 | static inline hri_nvic_ip_reg_t hri_nvic_get_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask) |
| 274 | { |
| 275 | uint8_t tmp; |
| 276 | tmp = ((Nvic *)hw)->IP[index].reg; |
| 277 | tmp &= mask; |
| 278 | return tmp; |
| 279 | } |
| 280 | |
| 281 | static inline void hri_nvic_write_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t data) |
| 282 | { |
| 283 | NVIC_CRITICAL_SECTION_ENTER(); |
| 284 | ((Nvic *)hw)->IP[index].reg = data; |
| 285 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 286 | } |
| 287 | |
| 288 | static inline void hri_nvic_clear_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask) |
| 289 | { |
| 290 | NVIC_CRITICAL_SECTION_ENTER(); |
| 291 | ((Nvic *)hw)->IP[index].reg &= ~mask; |
| 292 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 293 | } |
| 294 | |
| 295 | static inline void hri_nvic_toggle_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask) |
| 296 | { |
| 297 | NVIC_CRITICAL_SECTION_ENTER(); |
| 298 | ((Nvic *)hw)->IP[index].reg ^= mask; |
| 299 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 300 | } |
| 301 | |
| 302 | static inline hri_nvic_ip_reg_t hri_nvic_read_IP_reg(const void *const hw, uint8_t index) |
| 303 | { |
| 304 | return ((Nvic *)hw)->IP[index].reg; |
| 305 | } |
| 306 | |
| 307 | static inline void hri_nvic_write_STIR_reg(const void *const hw, hri_nvic_stir_reg_t data) |
| 308 | { |
| 309 | NVIC_CRITICAL_SECTION_ENTER(); |
| 310 | ((Nvic *)hw)->STIR.reg = data; |
| 311 | NVIC_CRITICAL_SECTION_LEAVE(); |
| 312 | } |
| 313 | |
| 314 | #ifdef __cplusplus |
| 315 | } |
| 316 | #endif |
| 317 | |
| 318 | #endif /* _HRI_NVIC_E54_H_INCLUDED */ |
| 319 | #endif /* _SAME54_NVIC_COMPONENT_ */ |