Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM GMAC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_GMAC_COMPONENT_ |
| 35 | #ifndef _HRI_GMAC_E54_H_INCLUDED_ |
| 36 | #define _HRI_GMAC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_GMAC_CRITICAL_SECTIONS) |
| 46 | #define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define GMAC_CRITICAL_SECTION_ENTER() |
| 50 | #define GMAC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_gmac_ae_reg_t; |
| 54 | typedef uint32_t hri_gmac_bcfr_reg_t; |
| 55 | typedef uint32_t hri_gmac_bcft_reg_t; |
| 56 | typedef uint32_t hri_gmac_bfr64_reg_t; |
| 57 | typedef uint32_t hri_gmac_bft64_reg_t; |
| 58 | typedef uint32_t hri_gmac_cse_reg_t; |
| 59 | typedef uint32_t hri_gmac_dcfgr_reg_t; |
| 60 | typedef uint32_t hri_gmac_dtf_reg_t; |
| 61 | typedef uint32_t hri_gmac_ec_reg_t; |
| 62 | typedef uint32_t hri_gmac_efrn_reg_t; |
| 63 | typedef uint32_t hri_gmac_efrsh_reg_t; |
| 64 | typedef uint32_t hri_gmac_efrsl_reg_t; |
| 65 | typedef uint32_t hri_gmac_eftn_reg_t; |
| 66 | typedef uint32_t hri_gmac_eftsh_reg_t; |
| 67 | typedef uint32_t hri_gmac_eftsl_reg_t; |
| 68 | typedef uint32_t hri_gmac_fcse_reg_t; |
| 69 | typedef uint32_t hri_gmac_fr_reg_t; |
| 70 | typedef uint32_t hri_gmac_ft_reg_t; |
| 71 | typedef uint32_t hri_gmac_gtbft1518_reg_t; |
| 72 | typedef uint32_t hri_gmac_hrb_reg_t; |
| 73 | typedef uint32_t hri_gmac_hrt_reg_t; |
| 74 | typedef uint32_t hri_gmac_ihce_reg_t; |
| 75 | typedef uint32_t hri_gmac_imr_reg_t; |
| 76 | typedef uint32_t hri_gmac_ipgs_reg_t; |
| 77 | typedef uint32_t hri_gmac_isr_reg_t; |
| 78 | typedef uint32_t hri_gmac_jr_reg_t; |
| 79 | typedef uint32_t hri_gmac_lc_reg_t; |
| 80 | typedef uint32_t hri_gmac_lffe_reg_t; |
| 81 | typedef uint32_t hri_gmac_man_reg_t; |
| 82 | typedef uint32_t hri_gmac_mcf_reg_t; |
| 83 | typedef uint32_t hri_gmac_mfr_reg_t; |
| 84 | typedef uint32_t hri_gmac_mft_reg_t; |
| 85 | typedef uint32_t hri_gmac_ncfgr_reg_t; |
| 86 | typedef uint32_t hri_gmac_ncr_reg_t; |
| 87 | typedef uint32_t hri_gmac_nsc_reg_t; |
| 88 | typedef uint32_t hri_gmac_nsr_reg_t; |
| 89 | typedef uint32_t hri_gmac_ofr_reg_t; |
| 90 | typedef uint32_t hri_gmac_orhi_reg_t; |
| 91 | typedef uint32_t hri_gmac_orlo_reg_t; |
| 92 | typedef uint32_t hri_gmac_othi_reg_t; |
| 93 | typedef uint32_t hri_gmac_otlo_reg_t; |
| 94 | typedef uint32_t hri_gmac_pefrn_reg_t; |
| 95 | typedef uint32_t hri_gmac_pefrsh_reg_t; |
| 96 | typedef uint32_t hri_gmac_pefrsl_reg_t; |
| 97 | typedef uint32_t hri_gmac_peftn_reg_t; |
| 98 | typedef uint32_t hri_gmac_peftsh_reg_t; |
| 99 | typedef uint32_t hri_gmac_peftsl_reg_t; |
| 100 | typedef uint32_t hri_gmac_pfr_reg_t; |
| 101 | typedef uint32_t hri_gmac_pft_reg_t; |
| 102 | typedef uint32_t hri_gmac_rbqb_reg_t; |
| 103 | typedef uint32_t hri_gmac_rjfml_reg_t; |
| 104 | typedef uint32_t hri_gmac_rlpiti_reg_t; |
| 105 | typedef uint32_t hri_gmac_rlpitr_reg_t; |
| 106 | typedef uint32_t hri_gmac_roe_reg_t; |
| 107 | typedef uint32_t hri_gmac_rpq_reg_t; |
| 108 | typedef uint32_t hri_gmac_rpsf_reg_t; |
| 109 | typedef uint32_t hri_gmac_rre_reg_t; |
| 110 | typedef uint32_t hri_gmac_rse_reg_t; |
| 111 | typedef uint32_t hri_gmac_rsr_reg_t; |
| 112 | typedef uint32_t hri_gmac_sab_reg_t; |
| 113 | typedef uint32_t hri_gmac_samb1_reg_t; |
| 114 | typedef uint32_t hri_gmac_samt1_reg_t; |
| 115 | typedef uint32_t hri_gmac_sat_reg_t; |
| 116 | typedef uint32_t hri_gmac_scf_reg_t; |
| 117 | typedef uint32_t hri_gmac_sch_reg_t; |
| 118 | typedef uint32_t hri_gmac_scl_reg_t; |
| 119 | typedef uint32_t hri_gmac_svlan_reg_t; |
| 120 | typedef uint32_t hri_gmac_ta_reg_t; |
| 121 | typedef uint32_t hri_gmac_tbfr1023_reg_t; |
| 122 | typedef uint32_t hri_gmac_tbfr127_reg_t; |
| 123 | typedef uint32_t hri_gmac_tbfr1518_reg_t; |
| 124 | typedef uint32_t hri_gmac_tbfr255_reg_t; |
| 125 | typedef uint32_t hri_gmac_tbfr511_reg_t; |
| 126 | typedef uint32_t hri_gmac_tbft1023_reg_t; |
| 127 | typedef uint32_t hri_gmac_tbft127_reg_t; |
| 128 | typedef uint32_t hri_gmac_tbft1518_reg_t; |
| 129 | typedef uint32_t hri_gmac_tbft255_reg_t; |
| 130 | typedef uint32_t hri_gmac_tbft511_reg_t; |
| 131 | typedef uint32_t hri_gmac_tbqb_reg_t; |
| 132 | typedef uint32_t hri_gmac_tce_reg_t; |
| 133 | typedef uint32_t hri_gmac_ti_reg_t; |
| 134 | typedef uint32_t hri_gmac_tidm_reg_t; |
| 135 | typedef uint32_t hri_gmac_tisubn_reg_t; |
| 136 | typedef uint32_t hri_gmac_tlpiti_reg_t; |
| 137 | typedef uint32_t hri_gmac_tlpitr_reg_t; |
| 138 | typedef uint32_t hri_gmac_tmxbfr_reg_t; |
| 139 | typedef uint32_t hri_gmac_tn_reg_t; |
| 140 | typedef uint32_t hri_gmac_tpfcp_reg_t; |
| 141 | typedef uint32_t hri_gmac_tpq_reg_t; |
| 142 | typedef uint32_t hri_gmac_tpsf_reg_t; |
| 143 | typedef uint32_t hri_gmac_tsh_reg_t; |
| 144 | typedef uint32_t hri_gmac_tsl_reg_t; |
| 145 | typedef uint32_t hri_gmac_tsr_reg_t; |
| 146 | typedef uint32_t hri_gmac_tssn_reg_t; |
| 147 | typedef uint32_t hri_gmac_tsssl_reg_t; |
| 148 | typedef uint32_t hri_gmac_tur_reg_t; |
| 149 | typedef uint32_t hri_gmac_uce_reg_t; |
| 150 | typedef uint32_t hri_gmac_ufr_reg_t; |
| 151 | typedef uint32_t hri_gmac_ur_reg_t; |
| 152 | typedef uint32_t hri_gmac_wol_reg_t; |
| 153 | typedef uint32_t hri_gmacsa_sab_reg_t; |
| 154 | typedef uint32_t hri_gmacsa_sat_reg_t; |
| 155 | |
| 156 | static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) |
| 157 | { |
| 158 | GMAC_CRITICAL_SECTION_ENTER(); |
| 159 | ((GmacSa *)hw)->SAB.reg |= mask; |
| 160 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 161 | } |
| 162 | |
| 163 | static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) |
| 164 | { |
| 165 | uint32_t tmp; |
| 166 | tmp = ((GmacSa *)hw)->SAB.reg; |
| 167 | tmp &= mask; |
| 168 | return tmp; |
| 169 | } |
| 170 | |
| 171 | static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) |
| 172 | { |
| 173 | GMAC_CRITICAL_SECTION_ENTER(); |
| 174 | ((GmacSa *)hw)->SAB.reg = data; |
| 175 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 176 | } |
| 177 | |
| 178 | static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) |
| 179 | { |
| 180 | GMAC_CRITICAL_SECTION_ENTER(); |
| 181 | ((GmacSa *)hw)->SAB.reg &= ~mask; |
| 182 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 183 | } |
| 184 | |
| 185 | static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) |
| 186 | { |
| 187 | GMAC_CRITICAL_SECTION_ENTER(); |
| 188 | ((GmacSa *)hw)->SAB.reg ^= mask; |
| 189 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 190 | } |
| 191 | |
| 192 | static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) |
| 193 | { |
| 194 | return ((GmacSa *)hw)->SAB.reg; |
| 195 | } |
| 196 | |
| 197 | static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) |
| 198 | { |
| 199 | GMAC_CRITICAL_SECTION_ENTER(); |
| 200 | ((GmacSa *)hw)->SAT.reg |= mask; |
| 201 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 202 | } |
| 203 | |
| 204 | static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) |
| 205 | { |
| 206 | uint32_t tmp; |
| 207 | tmp = ((GmacSa *)hw)->SAT.reg; |
| 208 | tmp &= mask; |
| 209 | return tmp; |
| 210 | } |
| 211 | |
| 212 | static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) |
| 213 | { |
| 214 | GMAC_CRITICAL_SECTION_ENTER(); |
| 215 | ((GmacSa *)hw)->SAT.reg = data; |
| 216 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 217 | } |
| 218 | |
| 219 | static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) |
| 220 | { |
| 221 | GMAC_CRITICAL_SECTION_ENTER(); |
| 222 | ((GmacSa *)hw)->SAT.reg &= ~mask; |
| 223 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 224 | } |
| 225 | |
| 226 | static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) |
| 227 | { |
| 228 | GMAC_CRITICAL_SECTION_ENTER(); |
| 229 | ((GmacSa *)hw)->SAT.reg ^= mask; |
| 230 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 231 | } |
| 232 | |
| 233 | static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) |
| 234 | { |
| 235 | return ((GmacSa *)hw)->SAT.reg; |
| 236 | } |
| 237 | |
| 238 | static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) |
| 239 | { |
| 240 | GMAC_CRITICAL_SECTION_ENTER(); |
| 241 | ((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask; |
| 242 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 243 | } |
| 244 | |
| 245 | static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, |
| 246 | hri_gmac_sab_reg_t mask) |
| 247 | { |
| 248 | uint32_t tmp; |
| 249 | tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg; |
| 250 | tmp &= mask; |
| 251 | return tmp; |
| 252 | } |
| 253 | |
| 254 | static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) |
| 255 | { |
| 256 | GMAC_CRITICAL_SECTION_ENTER(); |
| 257 | ((Gmac *)hw)->Sa[submodule_index].SAB.reg = data; |
| 258 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 259 | } |
| 260 | |
| 261 | static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) |
| 262 | { |
| 263 | GMAC_CRITICAL_SECTION_ENTER(); |
| 264 | ((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask; |
| 265 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 266 | } |
| 267 | |
| 268 | static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) |
| 269 | { |
| 270 | GMAC_CRITICAL_SECTION_ENTER(); |
| 271 | ((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask; |
| 272 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 273 | } |
| 274 | |
| 275 | static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) |
| 276 | { |
| 277 | return ((Gmac *)hw)->Sa[submodule_index].SAB.reg; |
| 278 | } |
| 279 | |
| 280 | static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) |
| 281 | { |
| 282 | GMAC_CRITICAL_SECTION_ENTER(); |
| 283 | ((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask; |
| 284 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 285 | } |
| 286 | |
| 287 | static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, |
| 288 | hri_gmac_sat_reg_t mask) |
| 289 | { |
| 290 | uint32_t tmp; |
| 291 | tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg; |
| 292 | tmp &= mask; |
| 293 | return tmp; |
| 294 | } |
| 295 | |
| 296 | static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) |
| 297 | { |
| 298 | GMAC_CRITICAL_SECTION_ENTER(); |
| 299 | ((Gmac *)hw)->Sa[submodule_index].SAT.reg = data; |
| 300 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 301 | } |
| 302 | |
| 303 | static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) |
| 304 | { |
| 305 | GMAC_CRITICAL_SECTION_ENTER(); |
| 306 | ((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask; |
| 307 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 308 | } |
| 309 | |
| 310 | static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) |
| 311 | { |
| 312 | GMAC_CRITICAL_SECTION_ENTER(); |
| 313 | ((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask; |
| 314 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 315 | } |
| 316 | |
| 317 | static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) |
| 318 | { |
| 319 | return ((Gmac *)hw)->Sa[submodule_index].SAT.reg; |
| 320 | } |
| 321 | |
| 322 | static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) |
| 323 | { |
| 324 | ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; |
| 325 | } |
| 326 | |
| 327 | static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) |
| 328 | { |
| 329 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; |
| 330 | } |
| 331 | |
| 332 | static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) |
| 333 | { |
| 334 | if (value == 0x0) { |
| 335 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; |
| 336 | } else { |
| 337 | ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) |
| 342 | { |
| 343 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; |
| 344 | } |
| 345 | |
| 346 | static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) |
| 347 | { |
| 348 | ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; |
| 349 | } |
| 350 | |
| 351 | static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) |
| 352 | { |
| 353 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; |
| 354 | } |
| 355 | |
| 356 | static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) |
| 357 | { |
| 358 | if (value == 0x0) { |
| 359 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; |
| 360 | } else { |
| 361 | ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; |
| 362 | } |
| 363 | } |
| 364 | |
| 365 | static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) |
| 366 | { |
| 367 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; |
| 368 | } |
| 369 | |
| 370 | static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) |
| 371 | { |
| 372 | ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; |
| 373 | } |
| 374 | |
| 375 | static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) |
| 376 | { |
| 377 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; |
| 378 | } |
| 379 | |
| 380 | static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) |
| 381 | { |
| 382 | if (value == 0x0) { |
| 383 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; |
| 384 | } else { |
| 385 | ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) |
| 390 | { |
| 391 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; |
| 392 | } |
| 393 | |
| 394 | static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) |
| 395 | { |
| 396 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; |
| 397 | } |
| 398 | |
| 399 | static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) |
| 400 | { |
| 401 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; |
| 402 | } |
| 403 | |
| 404 | static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) |
| 405 | { |
| 406 | if (value == 0x0) { |
| 407 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; |
| 408 | } else { |
| 409 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) |
| 414 | { |
| 415 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; |
| 416 | } |
| 417 | |
| 418 | static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) |
| 419 | { |
| 420 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; |
| 421 | } |
| 422 | |
| 423 | static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) |
| 424 | { |
| 425 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; |
| 426 | } |
| 427 | |
| 428 | static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) |
| 429 | { |
| 430 | if (value == 0x0) { |
| 431 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; |
| 432 | } else { |
| 433 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) |
| 438 | { |
| 439 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; |
| 440 | } |
| 441 | |
| 442 | static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) |
| 443 | { |
| 444 | ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; |
| 445 | } |
| 446 | |
| 447 | static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) |
| 448 | { |
| 449 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; |
| 450 | } |
| 451 | |
| 452 | static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) |
| 453 | { |
| 454 | if (value == 0x0) { |
| 455 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; |
| 456 | } else { |
| 457 | ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) |
| 462 | { |
| 463 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; |
| 464 | } |
| 465 | |
| 466 | static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) |
| 467 | { |
| 468 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; |
| 469 | } |
| 470 | |
| 471 | static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) |
| 472 | { |
| 473 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; |
| 474 | } |
| 475 | |
| 476 | static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) |
| 477 | { |
| 478 | if (value == 0x0) { |
| 479 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; |
| 480 | } else { |
| 481 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; |
| 482 | } |
| 483 | } |
| 484 | |
| 485 | static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) |
| 486 | { |
| 487 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; |
| 488 | } |
| 489 | |
| 490 | static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) |
| 491 | { |
| 492 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; |
| 493 | } |
| 494 | |
| 495 | static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) |
| 496 | { |
| 497 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; |
| 498 | } |
| 499 | |
| 500 | static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) |
| 501 | { |
| 502 | if (value == 0x0) { |
| 503 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; |
| 504 | } else { |
| 505 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) |
| 510 | { |
| 511 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; |
| 512 | } |
| 513 | |
| 514 | static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) |
| 515 | { |
| 516 | ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; |
| 517 | } |
| 518 | |
| 519 | static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) |
| 520 | { |
| 521 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; |
| 522 | } |
| 523 | |
| 524 | static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) |
| 525 | { |
| 526 | if (value == 0x0) { |
| 527 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; |
| 528 | } else { |
| 529 | ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) |
| 534 | { |
| 535 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; |
| 536 | } |
| 537 | |
| 538 | static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) |
| 539 | { |
| 540 | ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; |
| 541 | } |
| 542 | |
| 543 | static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) |
| 544 | { |
| 545 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; |
| 546 | } |
| 547 | |
| 548 | static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) |
| 549 | { |
| 550 | if (value == 0x0) { |
| 551 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; |
| 552 | } else { |
| 553 | ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) |
| 558 | { |
| 559 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; |
| 560 | } |
| 561 | |
| 562 | static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) |
| 563 | { |
| 564 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; |
| 565 | } |
| 566 | |
| 567 | static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) |
| 568 | { |
| 569 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; |
| 570 | } |
| 571 | |
| 572 | static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) |
| 573 | { |
| 574 | if (value == 0x0) { |
| 575 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; |
| 576 | } else { |
| 577 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) |
| 582 | { |
| 583 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; |
| 584 | } |
| 585 | |
| 586 | static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) |
| 587 | { |
| 588 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; |
| 589 | } |
| 590 | |
| 591 | static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) |
| 592 | { |
| 593 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; |
| 594 | } |
| 595 | |
| 596 | static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) |
| 597 | { |
| 598 | if (value == 0x0) { |
| 599 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; |
| 600 | } else { |
| 601 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; |
| 602 | } |
| 603 | } |
| 604 | |
| 605 | static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) |
| 606 | { |
| 607 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; |
| 608 | } |
| 609 | |
| 610 | static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) |
| 611 | { |
| 612 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; |
| 613 | } |
| 614 | |
| 615 | static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) |
| 616 | { |
| 617 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; |
| 618 | } |
| 619 | |
| 620 | static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) |
| 621 | { |
| 622 | if (value == 0x0) { |
| 623 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; |
| 624 | } else { |
| 625 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) |
| 630 | { |
| 631 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; |
| 632 | } |
| 633 | |
| 634 | static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) |
| 635 | { |
| 636 | ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; |
| 637 | } |
| 638 | |
| 639 | static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) |
| 640 | { |
| 641 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; |
| 642 | } |
| 643 | |
| 644 | static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) |
| 645 | { |
| 646 | if (value == 0x0) { |
| 647 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; |
| 648 | } else { |
| 649 | ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; |
| 650 | } |
| 651 | } |
| 652 | |
| 653 | static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) |
| 654 | { |
| 655 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; |
| 656 | } |
| 657 | |
| 658 | static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) |
| 659 | { |
| 660 | ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; |
| 661 | } |
| 662 | |
| 663 | static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) |
| 664 | { |
| 665 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; |
| 666 | } |
| 667 | |
| 668 | static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) |
| 669 | { |
| 670 | if (value == 0x0) { |
| 671 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; |
| 672 | } else { |
| 673 | ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) |
| 678 | { |
| 679 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; |
| 680 | } |
| 681 | |
| 682 | static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) |
| 683 | { |
| 684 | ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; |
| 685 | } |
| 686 | |
| 687 | static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) |
| 688 | { |
| 689 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; |
| 690 | } |
| 691 | |
| 692 | static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) |
| 693 | { |
| 694 | if (value == 0x0) { |
| 695 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; |
| 696 | } else { |
| 697 | ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) |
| 702 | { |
| 703 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; |
| 704 | } |
| 705 | |
| 706 | static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) |
| 707 | { |
| 708 | ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; |
| 709 | } |
| 710 | |
| 711 | static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) |
| 712 | { |
| 713 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; |
| 714 | } |
| 715 | |
| 716 | static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) |
| 717 | { |
| 718 | if (value == 0x0) { |
| 719 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; |
| 720 | } else { |
| 721 | ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; |
| 722 | } |
| 723 | } |
| 724 | |
| 725 | static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) |
| 726 | { |
| 727 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; |
| 728 | } |
| 729 | |
| 730 | static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) |
| 731 | { |
| 732 | ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; |
| 733 | } |
| 734 | |
| 735 | static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) |
| 736 | { |
| 737 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; |
| 738 | } |
| 739 | |
| 740 | static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) |
| 741 | { |
| 742 | if (value == 0x0) { |
| 743 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; |
| 744 | } else { |
| 745 | ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; |
| 746 | } |
| 747 | } |
| 748 | |
| 749 | static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) |
| 750 | { |
| 751 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; |
| 752 | } |
| 753 | |
| 754 | static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) |
| 755 | { |
| 756 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; |
| 757 | } |
| 758 | |
| 759 | static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) |
| 760 | { |
| 761 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; |
| 762 | } |
| 763 | |
| 764 | static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) |
| 765 | { |
| 766 | if (value == 0x0) { |
| 767 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; |
| 768 | } else { |
| 769 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) |
| 774 | { |
| 775 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; |
| 776 | } |
| 777 | |
| 778 | static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) |
| 779 | { |
| 780 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; |
| 781 | } |
| 782 | |
| 783 | static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) |
| 784 | { |
| 785 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; |
| 786 | } |
| 787 | |
| 788 | static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) |
| 789 | { |
| 790 | if (value == 0x0) { |
| 791 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; |
| 792 | } else { |
| 793 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) |
| 798 | { |
| 799 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; |
| 800 | } |
| 801 | |
| 802 | static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) |
| 803 | { |
| 804 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; |
| 805 | } |
| 806 | |
| 807 | static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) |
| 808 | { |
| 809 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; |
| 810 | } |
| 811 | |
| 812 | static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) |
| 813 | { |
| 814 | if (value == 0x0) { |
| 815 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; |
| 816 | } else { |
| 817 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; |
| 818 | } |
| 819 | } |
| 820 | |
| 821 | static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) |
| 822 | { |
| 823 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; |
| 824 | } |
| 825 | |
| 826 | static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) |
| 827 | { |
| 828 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; |
| 829 | } |
| 830 | |
| 831 | static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) |
| 832 | { |
| 833 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; |
| 834 | } |
| 835 | |
| 836 | static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) |
| 837 | { |
| 838 | if (value == 0x0) { |
| 839 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; |
| 840 | } else { |
| 841 | ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; |
| 842 | } |
| 843 | } |
| 844 | |
| 845 | static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) |
| 846 | { |
| 847 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; |
| 848 | } |
| 849 | |
| 850 | static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) |
| 851 | { |
| 852 | ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; |
| 853 | } |
| 854 | |
| 855 | static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) |
| 856 | { |
| 857 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; |
| 858 | } |
| 859 | |
| 860 | static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) |
| 861 | { |
| 862 | if (value == 0x0) { |
| 863 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; |
| 864 | } else { |
| 865 | ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; |
| 866 | } |
| 867 | } |
| 868 | |
| 869 | static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) |
| 870 | { |
| 871 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; |
| 872 | } |
| 873 | |
| 874 | static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) |
| 875 | { |
| 876 | ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; |
| 877 | } |
| 878 | |
| 879 | static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) |
| 880 | { |
| 881 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; |
| 882 | } |
| 883 | |
| 884 | static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) |
| 885 | { |
| 886 | if (value == 0x0) { |
| 887 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; |
| 888 | } else { |
| 889 | ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; |
| 890 | } |
| 891 | } |
| 892 | |
| 893 | static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) |
| 894 | { |
| 895 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; |
| 896 | } |
| 897 | |
| 898 | static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw) |
| 899 | { |
| 900 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; |
| 901 | } |
| 902 | |
| 903 | static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw) |
| 904 | { |
| 905 | return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos; |
| 906 | } |
| 907 | |
| 908 | static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value) |
| 909 | { |
| 910 | if (value == 0x0) { |
| 911 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; |
| 912 | } else { |
| 913 | ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; |
| 914 | } |
| 915 | } |
| 916 | |
| 917 | static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw) |
| 918 | { |
| 919 | ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; |
| 920 | } |
| 921 | |
| 922 | static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) |
| 923 | { |
| 924 | ((Gmac *)hw)->IER.reg = mask; |
| 925 | } |
| 926 | |
| 927 | static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) |
| 928 | { |
| 929 | uint32_t tmp; |
| 930 | tmp = ((Gmac *)hw)->IMR.reg; |
| 931 | tmp &= mask; |
| 932 | return tmp; |
| 933 | } |
| 934 | |
| 935 | static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) |
| 936 | { |
| 937 | return ((Gmac *)hw)->IMR.reg; |
| 938 | } |
| 939 | |
| 940 | static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) |
| 941 | { |
| 942 | ((Gmac *)hw)->IER.reg = data; |
| 943 | ((Gmac *)hw)->IDR.reg = ~data; |
| 944 | } |
| 945 | |
| 946 | static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) |
| 947 | { |
| 948 | ((Gmac *)hw)->IDR.reg = mask; |
| 949 | } |
| 950 | |
| 951 | static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) |
| 952 | { |
| 953 | return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos; |
| 954 | } |
| 955 | |
| 956 | static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) |
| 957 | { |
| 958 | return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos; |
| 959 | } |
| 960 | |
| 961 | static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) |
| 962 | { |
| 963 | uint32_t tmp; |
| 964 | tmp = ((Gmac *)hw)->NSR.reg; |
| 965 | tmp &= mask; |
| 966 | return tmp; |
| 967 | } |
| 968 | |
| 969 | static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) |
| 970 | { |
| 971 | return ((Gmac *)hw)->NSR.reg; |
| 972 | } |
| 973 | |
| 974 | static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) |
| 975 | { |
| 976 | return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; |
| 977 | } |
| 978 | |
| 979 | static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) |
| 980 | { |
| 981 | return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; |
| 982 | } |
| 983 | |
| 984 | static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) |
| 985 | { |
| 986 | uint32_t tmp; |
| 987 | tmp = ((Gmac *)hw)->RPQ.reg; |
| 988 | tmp &= mask; |
| 989 | return tmp; |
| 990 | } |
| 991 | |
| 992 | static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) |
| 993 | { |
| 994 | return ((Gmac *)hw)->RPQ.reg; |
| 995 | } |
| 996 | |
| 997 | static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) |
| 998 | { |
| 999 | return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; |
| 1000 | } |
| 1001 | |
| 1002 | static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) |
| 1003 | { |
| 1004 | return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; |
| 1005 | } |
| 1006 | |
| 1007 | static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) |
| 1008 | { |
| 1009 | uint32_t tmp; |
| 1010 | tmp = ((Gmac *)hw)->EFTSH.reg; |
| 1011 | tmp &= mask; |
| 1012 | return tmp; |
| 1013 | } |
| 1014 | |
| 1015 | static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) |
| 1016 | { |
| 1017 | return ((Gmac *)hw)->EFTSH.reg; |
| 1018 | } |
| 1019 | |
| 1020 | static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) |
| 1021 | { |
| 1022 | return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; |
| 1023 | } |
| 1024 | |
| 1025 | static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) |
| 1026 | { |
| 1027 | return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; |
| 1028 | } |
| 1029 | |
| 1030 | static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) |
| 1031 | { |
| 1032 | uint32_t tmp; |
| 1033 | tmp = ((Gmac *)hw)->EFRSH.reg; |
| 1034 | tmp &= mask; |
| 1035 | return tmp; |
| 1036 | } |
| 1037 | |
| 1038 | static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) |
| 1039 | { |
| 1040 | return ((Gmac *)hw)->EFRSH.reg; |
| 1041 | } |
| 1042 | |
| 1043 | static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) |
| 1044 | { |
| 1045 | return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; |
| 1046 | } |
| 1047 | |
| 1048 | static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) |
| 1049 | { |
| 1050 | return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; |
| 1051 | } |
| 1052 | |
| 1053 | static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) |
| 1054 | { |
| 1055 | uint32_t tmp; |
| 1056 | tmp = ((Gmac *)hw)->PEFTSH.reg; |
| 1057 | tmp &= mask; |
| 1058 | return tmp; |
| 1059 | } |
| 1060 | |
| 1061 | static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) |
| 1062 | { |
| 1063 | return ((Gmac *)hw)->PEFTSH.reg; |
| 1064 | } |
| 1065 | |
| 1066 | static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) |
| 1067 | { |
| 1068 | return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; |
| 1069 | } |
| 1070 | |
| 1071 | static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) |
| 1072 | { |
| 1073 | return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; |
| 1074 | } |
| 1075 | |
| 1076 | static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) |
| 1077 | { |
| 1078 | uint32_t tmp; |
| 1079 | tmp = ((Gmac *)hw)->PEFRSH.reg; |
| 1080 | tmp &= mask; |
| 1081 | return tmp; |
| 1082 | } |
| 1083 | |
| 1084 | static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) |
| 1085 | { |
| 1086 | return ((Gmac *)hw)->PEFRSH.reg; |
| 1087 | } |
| 1088 | |
| 1089 | static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) |
| 1090 | { |
| 1091 | return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; |
| 1092 | } |
| 1093 | |
| 1094 | static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) |
| 1095 | { |
| 1096 | return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; |
| 1097 | } |
| 1098 | |
| 1099 | static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) |
| 1100 | { |
| 1101 | uint32_t tmp; |
| 1102 | tmp = ((Gmac *)hw)->OTLO.reg; |
| 1103 | tmp &= mask; |
| 1104 | return tmp; |
| 1105 | } |
| 1106 | |
| 1107 | static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) |
| 1108 | { |
| 1109 | return ((Gmac *)hw)->OTLO.reg; |
| 1110 | } |
| 1111 | |
| 1112 | static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) |
| 1113 | { |
| 1114 | return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; |
| 1115 | } |
| 1116 | |
| 1117 | static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) |
| 1118 | { |
| 1119 | return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; |
| 1120 | } |
| 1121 | |
| 1122 | static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) |
| 1123 | { |
| 1124 | uint32_t tmp; |
| 1125 | tmp = ((Gmac *)hw)->OTHI.reg; |
| 1126 | tmp &= mask; |
| 1127 | return tmp; |
| 1128 | } |
| 1129 | |
| 1130 | static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) |
| 1131 | { |
| 1132 | return ((Gmac *)hw)->OTHI.reg; |
| 1133 | } |
| 1134 | |
| 1135 | static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) |
| 1136 | { |
| 1137 | return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; |
| 1138 | } |
| 1139 | |
| 1140 | static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) |
| 1141 | { |
| 1142 | return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; |
| 1143 | } |
| 1144 | |
| 1145 | static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) |
| 1146 | { |
| 1147 | uint32_t tmp; |
| 1148 | tmp = ((Gmac *)hw)->FT.reg; |
| 1149 | tmp &= mask; |
| 1150 | return tmp; |
| 1151 | } |
| 1152 | |
| 1153 | static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) |
| 1154 | { |
| 1155 | return ((Gmac *)hw)->FT.reg; |
| 1156 | } |
| 1157 | |
| 1158 | static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) |
| 1159 | { |
| 1160 | return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; |
| 1161 | } |
| 1162 | |
| 1163 | static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) |
| 1164 | { |
| 1165 | return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; |
| 1166 | } |
| 1167 | |
| 1168 | static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) |
| 1169 | { |
| 1170 | uint32_t tmp; |
| 1171 | tmp = ((Gmac *)hw)->BCFT.reg; |
| 1172 | tmp &= mask; |
| 1173 | return tmp; |
| 1174 | } |
| 1175 | |
| 1176 | static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) |
| 1177 | { |
| 1178 | return ((Gmac *)hw)->BCFT.reg; |
| 1179 | } |
| 1180 | |
| 1181 | static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) |
| 1182 | { |
| 1183 | return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; |
| 1184 | } |
| 1185 | |
| 1186 | static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) |
| 1187 | { |
| 1188 | return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; |
| 1189 | } |
| 1190 | |
| 1191 | static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) |
| 1192 | { |
| 1193 | uint32_t tmp; |
| 1194 | tmp = ((Gmac *)hw)->MFT.reg; |
| 1195 | tmp &= mask; |
| 1196 | return tmp; |
| 1197 | } |
| 1198 | |
| 1199 | static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) |
| 1200 | { |
| 1201 | return ((Gmac *)hw)->MFT.reg; |
| 1202 | } |
| 1203 | |
| 1204 | static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) |
| 1205 | { |
| 1206 | return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; |
| 1207 | } |
| 1208 | |
| 1209 | static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) |
| 1210 | { |
| 1211 | return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; |
| 1212 | } |
| 1213 | |
| 1214 | static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) |
| 1215 | { |
| 1216 | uint32_t tmp; |
| 1217 | tmp = ((Gmac *)hw)->PFT.reg; |
| 1218 | tmp &= mask; |
| 1219 | return tmp; |
| 1220 | } |
| 1221 | |
| 1222 | static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) |
| 1223 | { |
| 1224 | return ((Gmac *)hw)->PFT.reg; |
| 1225 | } |
| 1226 | |
| 1227 | static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) |
| 1228 | { |
| 1229 | return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; |
| 1230 | } |
| 1231 | |
| 1232 | static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) |
| 1233 | { |
| 1234 | return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; |
| 1235 | } |
| 1236 | |
| 1237 | static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) |
| 1238 | { |
| 1239 | uint32_t tmp; |
| 1240 | tmp = ((Gmac *)hw)->BFT64.reg; |
| 1241 | tmp &= mask; |
| 1242 | return tmp; |
| 1243 | } |
| 1244 | |
| 1245 | static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) |
| 1246 | { |
| 1247 | return ((Gmac *)hw)->BFT64.reg; |
| 1248 | } |
| 1249 | |
| 1250 | static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) |
| 1251 | { |
| 1252 | return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; |
| 1253 | } |
| 1254 | |
| 1255 | static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) |
| 1256 | { |
| 1257 | return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; |
| 1258 | } |
| 1259 | |
| 1260 | static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) |
| 1261 | { |
| 1262 | uint32_t tmp; |
| 1263 | tmp = ((Gmac *)hw)->TBFT127.reg; |
| 1264 | tmp &= mask; |
| 1265 | return tmp; |
| 1266 | } |
| 1267 | |
| 1268 | static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) |
| 1269 | { |
| 1270 | return ((Gmac *)hw)->TBFT127.reg; |
| 1271 | } |
| 1272 | |
| 1273 | static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) |
| 1274 | { |
| 1275 | return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; |
| 1276 | } |
| 1277 | |
| 1278 | static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) |
| 1279 | { |
| 1280 | return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; |
| 1281 | } |
| 1282 | |
| 1283 | static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) |
| 1284 | { |
| 1285 | uint32_t tmp; |
| 1286 | tmp = ((Gmac *)hw)->TBFT255.reg; |
| 1287 | tmp &= mask; |
| 1288 | return tmp; |
| 1289 | } |
| 1290 | |
| 1291 | static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) |
| 1292 | { |
| 1293 | return ((Gmac *)hw)->TBFT255.reg; |
| 1294 | } |
| 1295 | |
| 1296 | static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) |
| 1297 | { |
| 1298 | return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; |
| 1299 | } |
| 1300 | |
| 1301 | static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) |
| 1302 | { |
| 1303 | return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; |
| 1304 | } |
| 1305 | |
| 1306 | static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) |
| 1307 | { |
| 1308 | uint32_t tmp; |
| 1309 | tmp = ((Gmac *)hw)->TBFT511.reg; |
| 1310 | tmp &= mask; |
| 1311 | return tmp; |
| 1312 | } |
| 1313 | |
| 1314 | static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) |
| 1315 | { |
| 1316 | return ((Gmac *)hw)->TBFT511.reg; |
| 1317 | } |
| 1318 | |
| 1319 | static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) |
| 1320 | { |
| 1321 | return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; |
| 1322 | } |
| 1323 | |
| 1324 | static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) |
| 1325 | { |
| 1326 | return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; |
| 1327 | } |
| 1328 | |
| 1329 | static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) |
| 1330 | { |
| 1331 | uint32_t tmp; |
| 1332 | tmp = ((Gmac *)hw)->TBFT1023.reg; |
| 1333 | tmp &= mask; |
| 1334 | return tmp; |
| 1335 | } |
| 1336 | |
| 1337 | static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) |
| 1338 | { |
| 1339 | return ((Gmac *)hw)->TBFT1023.reg; |
| 1340 | } |
| 1341 | |
| 1342 | static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) |
| 1343 | { |
| 1344 | return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; |
| 1345 | } |
| 1346 | |
| 1347 | static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) |
| 1348 | { |
| 1349 | return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; |
| 1350 | } |
| 1351 | |
| 1352 | static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) |
| 1353 | { |
| 1354 | uint32_t tmp; |
| 1355 | tmp = ((Gmac *)hw)->TBFT1518.reg; |
| 1356 | tmp &= mask; |
| 1357 | return tmp; |
| 1358 | } |
| 1359 | |
| 1360 | static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) |
| 1361 | { |
| 1362 | return ((Gmac *)hw)->TBFT1518.reg; |
| 1363 | } |
| 1364 | |
| 1365 | static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, |
| 1366 | hri_gmac_gtbft1518_reg_t mask) |
| 1367 | { |
| 1368 | return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; |
| 1369 | } |
| 1370 | |
| 1371 | static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) |
| 1372 | { |
| 1373 | return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; |
| 1374 | } |
| 1375 | |
| 1376 | static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) |
| 1377 | { |
| 1378 | uint32_t tmp; |
| 1379 | tmp = ((Gmac *)hw)->GTBFT1518.reg; |
| 1380 | tmp &= mask; |
| 1381 | return tmp; |
| 1382 | } |
| 1383 | |
| 1384 | static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) |
| 1385 | { |
| 1386 | return ((Gmac *)hw)->GTBFT1518.reg; |
| 1387 | } |
| 1388 | |
| 1389 | static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) |
| 1390 | { |
| 1391 | return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; |
| 1392 | } |
| 1393 | |
| 1394 | static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) |
| 1395 | { |
| 1396 | return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; |
| 1397 | } |
| 1398 | |
| 1399 | static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) |
| 1400 | { |
| 1401 | uint32_t tmp; |
| 1402 | tmp = ((Gmac *)hw)->TUR.reg; |
| 1403 | tmp &= mask; |
| 1404 | return tmp; |
| 1405 | } |
| 1406 | |
| 1407 | static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) |
| 1408 | { |
| 1409 | return ((Gmac *)hw)->TUR.reg; |
| 1410 | } |
| 1411 | |
| 1412 | static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) |
| 1413 | { |
| 1414 | return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; |
| 1415 | } |
| 1416 | |
| 1417 | static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) |
| 1418 | { |
| 1419 | return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; |
| 1420 | } |
| 1421 | |
| 1422 | static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) |
| 1423 | { |
| 1424 | uint32_t tmp; |
| 1425 | tmp = ((Gmac *)hw)->SCF.reg; |
| 1426 | tmp &= mask; |
| 1427 | return tmp; |
| 1428 | } |
| 1429 | |
| 1430 | static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) |
| 1431 | { |
| 1432 | return ((Gmac *)hw)->SCF.reg; |
| 1433 | } |
| 1434 | |
| 1435 | static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) |
| 1436 | { |
| 1437 | return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; |
| 1438 | } |
| 1439 | |
| 1440 | static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) |
| 1441 | { |
| 1442 | return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; |
| 1443 | } |
| 1444 | |
| 1445 | static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) |
| 1446 | { |
| 1447 | uint32_t tmp; |
| 1448 | tmp = ((Gmac *)hw)->MCF.reg; |
| 1449 | tmp &= mask; |
| 1450 | return tmp; |
| 1451 | } |
| 1452 | |
| 1453 | static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) |
| 1454 | { |
| 1455 | return ((Gmac *)hw)->MCF.reg; |
| 1456 | } |
| 1457 | |
| 1458 | static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) |
| 1459 | { |
| 1460 | return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; |
| 1461 | } |
| 1462 | |
| 1463 | static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) |
| 1464 | { |
| 1465 | return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; |
| 1466 | } |
| 1467 | |
| 1468 | static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) |
| 1469 | { |
| 1470 | uint32_t tmp; |
| 1471 | tmp = ((Gmac *)hw)->EC.reg; |
| 1472 | tmp &= mask; |
| 1473 | return tmp; |
| 1474 | } |
| 1475 | |
| 1476 | static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) |
| 1477 | { |
| 1478 | return ((Gmac *)hw)->EC.reg; |
| 1479 | } |
| 1480 | |
| 1481 | static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) |
| 1482 | { |
| 1483 | return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; |
| 1484 | } |
| 1485 | |
| 1486 | static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) |
| 1487 | { |
| 1488 | return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; |
| 1489 | } |
| 1490 | |
| 1491 | static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) |
| 1492 | { |
| 1493 | uint32_t tmp; |
| 1494 | tmp = ((Gmac *)hw)->LC.reg; |
| 1495 | tmp &= mask; |
| 1496 | return tmp; |
| 1497 | } |
| 1498 | |
| 1499 | static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) |
| 1500 | { |
| 1501 | return ((Gmac *)hw)->LC.reg; |
| 1502 | } |
| 1503 | |
| 1504 | static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) |
| 1505 | { |
| 1506 | return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; |
| 1507 | } |
| 1508 | |
| 1509 | static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) |
| 1510 | { |
| 1511 | return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; |
| 1512 | } |
| 1513 | |
| 1514 | static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) |
| 1515 | { |
| 1516 | uint32_t tmp; |
| 1517 | tmp = ((Gmac *)hw)->DTF.reg; |
| 1518 | tmp &= mask; |
| 1519 | return tmp; |
| 1520 | } |
| 1521 | |
| 1522 | static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) |
| 1523 | { |
| 1524 | return ((Gmac *)hw)->DTF.reg; |
| 1525 | } |
| 1526 | |
| 1527 | static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) |
| 1528 | { |
| 1529 | return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; |
| 1530 | } |
| 1531 | |
| 1532 | static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) |
| 1533 | { |
| 1534 | return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; |
| 1535 | } |
| 1536 | |
| 1537 | static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) |
| 1538 | { |
| 1539 | uint32_t tmp; |
| 1540 | tmp = ((Gmac *)hw)->CSE.reg; |
| 1541 | tmp &= mask; |
| 1542 | return tmp; |
| 1543 | } |
| 1544 | |
| 1545 | static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) |
| 1546 | { |
| 1547 | return ((Gmac *)hw)->CSE.reg; |
| 1548 | } |
| 1549 | |
| 1550 | static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) |
| 1551 | { |
| 1552 | return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; |
| 1553 | } |
| 1554 | |
| 1555 | static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) |
| 1556 | { |
| 1557 | return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; |
| 1558 | } |
| 1559 | |
| 1560 | static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) |
| 1561 | { |
| 1562 | uint32_t tmp; |
| 1563 | tmp = ((Gmac *)hw)->ORLO.reg; |
| 1564 | tmp &= mask; |
| 1565 | return tmp; |
| 1566 | } |
| 1567 | |
| 1568 | static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) |
| 1569 | { |
| 1570 | return ((Gmac *)hw)->ORLO.reg; |
| 1571 | } |
| 1572 | |
| 1573 | static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) |
| 1574 | { |
| 1575 | return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; |
| 1576 | } |
| 1577 | |
| 1578 | static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) |
| 1579 | { |
| 1580 | return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; |
| 1581 | } |
| 1582 | |
| 1583 | static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) |
| 1584 | { |
| 1585 | uint32_t tmp; |
| 1586 | tmp = ((Gmac *)hw)->ORHI.reg; |
| 1587 | tmp &= mask; |
| 1588 | return tmp; |
| 1589 | } |
| 1590 | |
| 1591 | static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) |
| 1592 | { |
| 1593 | return ((Gmac *)hw)->ORHI.reg; |
| 1594 | } |
| 1595 | |
| 1596 | static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) |
| 1597 | { |
| 1598 | return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; |
| 1599 | } |
| 1600 | |
| 1601 | static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) |
| 1602 | { |
| 1603 | return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; |
| 1604 | } |
| 1605 | |
| 1606 | static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) |
| 1607 | { |
| 1608 | uint32_t tmp; |
| 1609 | tmp = ((Gmac *)hw)->FR.reg; |
| 1610 | tmp &= mask; |
| 1611 | return tmp; |
| 1612 | } |
| 1613 | |
| 1614 | static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) |
| 1615 | { |
| 1616 | return ((Gmac *)hw)->FR.reg; |
| 1617 | } |
| 1618 | |
| 1619 | static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) |
| 1620 | { |
| 1621 | return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; |
| 1622 | } |
| 1623 | |
| 1624 | static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) |
| 1625 | { |
| 1626 | return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; |
| 1627 | } |
| 1628 | |
| 1629 | static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) |
| 1630 | { |
| 1631 | uint32_t tmp; |
| 1632 | tmp = ((Gmac *)hw)->BCFR.reg; |
| 1633 | tmp &= mask; |
| 1634 | return tmp; |
| 1635 | } |
| 1636 | |
| 1637 | static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) |
| 1638 | { |
| 1639 | return ((Gmac *)hw)->BCFR.reg; |
| 1640 | } |
| 1641 | |
| 1642 | static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) |
| 1643 | { |
| 1644 | return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; |
| 1645 | } |
| 1646 | |
| 1647 | static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) |
| 1648 | { |
| 1649 | return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; |
| 1650 | } |
| 1651 | |
| 1652 | static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) |
| 1653 | { |
| 1654 | uint32_t tmp; |
| 1655 | tmp = ((Gmac *)hw)->MFR.reg; |
| 1656 | tmp &= mask; |
| 1657 | return tmp; |
| 1658 | } |
| 1659 | |
| 1660 | static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) |
| 1661 | { |
| 1662 | return ((Gmac *)hw)->MFR.reg; |
| 1663 | } |
| 1664 | |
| 1665 | static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) |
| 1666 | { |
| 1667 | return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; |
| 1668 | } |
| 1669 | |
| 1670 | static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) |
| 1671 | { |
| 1672 | return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; |
| 1673 | } |
| 1674 | |
| 1675 | static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) |
| 1676 | { |
| 1677 | uint32_t tmp; |
| 1678 | tmp = ((Gmac *)hw)->PFR.reg; |
| 1679 | tmp &= mask; |
| 1680 | return tmp; |
| 1681 | } |
| 1682 | |
| 1683 | static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) |
| 1684 | { |
| 1685 | return ((Gmac *)hw)->PFR.reg; |
| 1686 | } |
| 1687 | |
| 1688 | static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) |
| 1689 | { |
| 1690 | return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; |
| 1691 | } |
| 1692 | |
| 1693 | static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) |
| 1694 | { |
| 1695 | return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; |
| 1696 | } |
| 1697 | |
| 1698 | static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) |
| 1699 | { |
| 1700 | uint32_t tmp; |
| 1701 | tmp = ((Gmac *)hw)->BFR64.reg; |
| 1702 | tmp &= mask; |
| 1703 | return tmp; |
| 1704 | } |
| 1705 | |
| 1706 | static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) |
| 1707 | { |
| 1708 | return ((Gmac *)hw)->BFR64.reg; |
| 1709 | } |
| 1710 | |
| 1711 | static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) |
| 1712 | { |
| 1713 | return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; |
| 1714 | } |
| 1715 | |
| 1716 | static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) |
| 1717 | { |
| 1718 | return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; |
| 1719 | } |
| 1720 | |
| 1721 | static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) |
| 1722 | { |
| 1723 | uint32_t tmp; |
| 1724 | tmp = ((Gmac *)hw)->TBFR127.reg; |
| 1725 | tmp &= mask; |
| 1726 | return tmp; |
| 1727 | } |
| 1728 | |
| 1729 | static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) |
| 1730 | { |
| 1731 | return ((Gmac *)hw)->TBFR127.reg; |
| 1732 | } |
| 1733 | |
| 1734 | static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) |
| 1735 | { |
| 1736 | return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; |
| 1737 | } |
| 1738 | |
| 1739 | static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) |
| 1740 | { |
| 1741 | return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; |
| 1742 | } |
| 1743 | |
| 1744 | static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) |
| 1745 | { |
| 1746 | uint32_t tmp; |
| 1747 | tmp = ((Gmac *)hw)->TBFR255.reg; |
| 1748 | tmp &= mask; |
| 1749 | return tmp; |
| 1750 | } |
| 1751 | |
| 1752 | static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) |
| 1753 | { |
| 1754 | return ((Gmac *)hw)->TBFR255.reg; |
| 1755 | } |
| 1756 | |
| 1757 | static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) |
| 1758 | { |
| 1759 | return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; |
| 1760 | } |
| 1761 | |
| 1762 | static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) |
| 1763 | { |
| 1764 | return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; |
| 1765 | } |
| 1766 | |
| 1767 | static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) |
| 1768 | { |
| 1769 | uint32_t tmp; |
| 1770 | tmp = ((Gmac *)hw)->TBFR511.reg; |
| 1771 | tmp &= mask; |
| 1772 | return tmp; |
| 1773 | } |
| 1774 | |
| 1775 | static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) |
| 1776 | { |
| 1777 | return ((Gmac *)hw)->TBFR511.reg; |
| 1778 | } |
| 1779 | |
| 1780 | static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) |
| 1781 | { |
| 1782 | return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; |
| 1783 | } |
| 1784 | |
| 1785 | static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) |
| 1786 | { |
| 1787 | return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; |
| 1788 | } |
| 1789 | |
| 1790 | static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) |
| 1791 | { |
| 1792 | uint32_t tmp; |
| 1793 | tmp = ((Gmac *)hw)->TBFR1023.reg; |
| 1794 | tmp &= mask; |
| 1795 | return tmp; |
| 1796 | } |
| 1797 | |
| 1798 | static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) |
| 1799 | { |
| 1800 | return ((Gmac *)hw)->TBFR1023.reg; |
| 1801 | } |
| 1802 | |
| 1803 | static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) |
| 1804 | { |
| 1805 | return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; |
| 1806 | } |
| 1807 | |
| 1808 | static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) |
| 1809 | { |
| 1810 | return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; |
| 1811 | } |
| 1812 | |
| 1813 | static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) |
| 1814 | { |
| 1815 | uint32_t tmp; |
| 1816 | tmp = ((Gmac *)hw)->TBFR1518.reg; |
| 1817 | tmp &= mask; |
| 1818 | return tmp; |
| 1819 | } |
| 1820 | |
| 1821 | static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) |
| 1822 | { |
| 1823 | return ((Gmac *)hw)->TBFR1518.reg; |
| 1824 | } |
| 1825 | |
| 1826 | static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) |
| 1827 | { |
| 1828 | return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; |
| 1829 | } |
| 1830 | |
| 1831 | static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) |
| 1832 | { |
| 1833 | return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; |
| 1834 | } |
| 1835 | |
| 1836 | static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) |
| 1837 | { |
| 1838 | uint32_t tmp; |
| 1839 | tmp = ((Gmac *)hw)->TMXBFR.reg; |
| 1840 | tmp &= mask; |
| 1841 | return tmp; |
| 1842 | } |
| 1843 | |
| 1844 | static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) |
| 1845 | { |
| 1846 | return ((Gmac *)hw)->TMXBFR.reg; |
| 1847 | } |
| 1848 | |
| 1849 | static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) |
| 1850 | { |
| 1851 | return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; |
| 1852 | } |
| 1853 | |
| 1854 | static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) |
| 1855 | { |
| 1856 | return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; |
| 1857 | } |
| 1858 | |
| 1859 | static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) |
| 1860 | { |
| 1861 | uint32_t tmp; |
| 1862 | tmp = ((Gmac *)hw)->UFR.reg; |
| 1863 | tmp &= mask; |
| 1864 | return tmp; |
| 1865 | } |
| 1866 | |
| 1867 | static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) |
| 1868 | { |
| 1869 | return ((Gmac *)hw)->UFR.reg; |
| 1870 | } |
| 1871 | |
| 1872 | static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) |
| 1873 | { |
| 1874 | return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; |
| 1875 | } |
| 1876 | |
| 1877 | static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) |
| 1878 | { |
| 1879 | return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; |
| 1880 | } |
| 1881 | |
| 1882 | static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) |
| 1883 | { |
| 1884 | uint32_t tmp; |
| 1885 | tmp = ((Gmac *)hw)->OFR.reg; |
| 1886 | tmp &= mask; |
| 1887 | return tmp; |
| 1888 | } |
| 1889 | |
| 1890 | static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) |
| 1891 | { |
| 1892 | return ((Gmac *)hw)->OFR.reg; |
| 1893 | } |
| 1894 | |
| 1895 | static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) |
| 1896 | { |
| 1897 | return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; |
| 1898 | } |
| 1899 | |
| 1900 | static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) |
| 1901 | { |
| 1902 | return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; |
| 1903 | } |
| 1904 | |
| 1905 | static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) |
| 1906 | { |
| 1907 | uint32_t tmp; |
| 1908 | tmp = ((Gmac *)hw)->JR.reg; |
| 1909 | tmp &= mask; |
| 1910 | return tmp; |
| 1911 | } |
| 1912 | |
| 1913 | static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) |
| 1914 | { |
| 1915 | return ((Gmac *)hw)->JR.reg; |
| 1916 | } |
| 1917 | |
| 1918 | static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) |
| 1919 | { |
| 1920 | return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; |
| 1921 | } |
| 1922 | |
| 1923 | static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) |
| 1924 | { |
| 1925 | return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; |
| 1926 | } |
| 1927 | |
| 1928 | static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) |
| 1929 | { |
| 1930 | uint32_t tmp; |
| 1931 | tmp = ((Gmac *)hw)->FCSE.reg; |
| 1932 | tmp &= mask; |
| 1933 | return tmp; |
| 1934 | } |
| 1935 | |
| 1936 | static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) |
| 1937 | { |
| 1938 | return ((Gmac *)hw)->FCSE.reg; |
| 1939 | } |
| 1940 | |
| 1941 | static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) |
| 1942 | { |
| 1943 | return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; |
| 1944 | } |
| 1945 | |
| 1946 | static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) |
| 1947 | { |
| 1948 | return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; |
| 1949 | } |
| 1950 | |
| 1951 | static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) |
| 1952 | { |
| 1953 | uint32_t tmp; |
| 1954 | tmp = ((Gmac *)hw)->LFFE.reg; |
| 1955 | tmp &= mask; |
| 1956 | return tmp; |
| 1957 | } |
| 1958 | |
| 1959 | static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) |
| 1960 | { |
| 1961 | return ((Gmac *)hw)->LFFE.reg; |
| 1962 | } |
| 1963 | |
| 1964 | static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) |
| 1965 | { |
| 1966 | return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; |
| 1967 | } |
| 1968 | |
| 1969 | static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) |
| 1970 | { |
| 1971 | return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; |
| 1972 | } |
| 1973 | |
| 1974 | static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) |
| 1975 | { |
| 1976 | uint32_t tmp; |
| 1977 | tmp = ((Gmac *)hw)->RSE.reg; |
| 1978 | tmp &= mask; |
| 1979 | return tmp; |
| 1980 | } |
| 1981 | |
| 1982 | static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) |
| 1983 | { |
| 1984 | return ((Gmac *)hw)->RSE.reg; |
| 1985 | } |
| 1986 | |
| 1987 | static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) |
| 1988 | { |
| 1989 | return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; |
| 1990 | } |
| 1991 | |
| 1992 | static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) |
| 1993 | { |
| 1994 | return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; |
| 1995 | } |
| 1996 | |
| 1997 | static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) |
| 1998 | { |
| 1999 | uint32_t tmp; |
| 2000 | tmp = ((Gmac *)hw)->AE.reg; |
| 2001 | tmp &= mask; |
| 2002 | return tmp; |
| 2003 | } |
| 2004 | |
| 2005 | static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) |
| 2006 | { |
| 2007 | return ((Gmac *)hw)->AE.reg; |
| 2008 | } |
| 2009 | |
| 2010 | static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) |
| 2011 | { |
| 2012 | return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; |
| 2013 | } |
| 2014 | |
| 2015 | static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) |
| 2016 | { |
| 2017 | return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; |
| 2018 | } |
| 2019 | |
| 2020 | static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) |
| 2021 | { |
| 2022 | uint32_t tmp; |
| 2023 | tmp = ((Gmac *)hw)->RRE.reg; |
| 2024 | tmp &= mask; |
| 2025 | return tmp; |
| 2026 | } |
| 2027 | |
| 2028 | static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) |
| 2029 | { |
| 2030 | return ((Gmac *)hw)->RRE.reg; |
| 2031 | } |
| 2032 | |
| 2033 | static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) |
| 2034 | { |
| 2035 | return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; |
| 2036 | } |
| 2037 | |
| 2038 | static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) |
| 2039 | { |
| 2040 | return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; |
| 2041 | } |
| 2042 | |
| 2043 | static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) |
| 2044 | { |
| 2045 | uint32_t tmp; |
| 2046 | tmp = ((Gmac *)hw)->ROE.reg; |
| 2047 | tmp &= mask; |
| 2048 | return tmp; |
| 2049 | } |
| 2050 | |
| 2051 | static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) |
| 2052 | { |
| 2053 | return ((Gmac *)hw)->ROE.reg; |
| 2054 | } |
| 2055 | |
| 2056 | static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) |
| 2057 | { |
| 2058 | return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; |
| 2059 | } |
| 2060 | |
| 2061 | static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) |
| 2062 | { |
| 2063 | return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; |
| 2064 | } |
| 2065 | |
| 2066 | static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) |
| 2067 | { |
| 2068 | uint32_t tmp; |
| 2069 | tmp = ((Gmac *)hw)->IHCE.reg; |
| 2070 | tmp &= mask; |
| 2071 | return tmp; |
| 2072 | } |
| 2073 | |
| 2074 | static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) |
| 2075 | { |
| 2076 | return ((Gmac *)hw)->IHCE.reg; |
| 2077 | } |
| 2078 | |
| 2079 | static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) |
| 2080 | { |
| 2081 | return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; |
| 2082 | } |
| 2083 | |
| 2084 | static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) |
| 2085 | { |
| 2086 | return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; |
| 2087 | } |
| 2088 | |
| 2089 | static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) |
| 2090 | { |
| 2091 | uint32_t tmp; |
| 2092 | tmp = ((Gmac *)hw)->TCE.reg; |
| 2093 | tmp &= mask; |
| 2094 | return tmp; |
| 2095 | } |
| 2096 | |
| 2097 | static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) |
| 2098 | { |
| 2099 | return ((Gmac *)hw)->TCE.reg; |
| 2100 | } |
| 2101 | |
| 2102 | static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) |
| 2103 | { |
| 2104 | return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; |
| 2105 | } |
| 2106 | |
| 2107 | static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) |
| 2108 | { |
| 2109 | return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; |
| 2110 | } |
| 2111 | |
| 2112 | static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) |
| 2113 | { |
| 2114 | uint32_t tmp; |
| 2115 | tmp = ((Gmac *)hw)->UCE.reg; |
| 2116 | tmp &= mask; |
| 2117 | return tmp; |
| 2118 | } |
| 2119 | |
| 2120 | static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) |
| 2121 | { |
| 2122 | return ((Gmac *)hw)->UCE.reg; |
| 2123 | } |
| 2124 | |
| 2125 | static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) |
| 2126 | { |
| 2127 | return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; |
| 2128 | } |
| 2129 | |
| 2130 | static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) |
| 2131 | { |
| 2132 | return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; |
| 2133 | } |
| 2134 | |
| 2135 | static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) |
| 2136 | { |
| 2137 | uint32_t tmp; |
| 2138 | tmp = ((Gmac *)hw)->EFTSL.reg; |
| 2139 | tmp &= mask; |
| 2140 | return tmp; |
| 2141 | } |
| 2142 | |
| 2143 | static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) |
| 2144 | { |
| 2145 | return ((Gmac *)hw)->EFTSL.reg; |
| 2146 | } |
| 2147 | |
| 2148 | static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) |
| 2149 | { |
| 2150 | return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; |
| 2151 | } |
| 2152 | |
| 2153 | static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) |
| 2154 | { |
| 2155 | return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; |
| 2156 | } |
| 2157 | |
| 2158 | static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) |
| 2159 | { |
| 2160 | uint32_t tmp; |
| 2161 | tmp = ((Gmac *)hw)->EFTN.reg; |
| 2162 | tmp &= mask; |
| 2163 | return tmp; |
| 2164 | } |
| 2165 | |
| 2166 | static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) |
| 2167 | { |
| 2168 | return ((Gmac *)hw)->EFTN.reg; |
| 2169 | } |
| 2170 | |
| 2171 | static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) |
| 2172 | { |
| 2173 | return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; |
| 2174 | } |
| 2175 | |
| 2176 | static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) |
| 2177 | { |
| 2178 | return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; |
| 2179 | } |
| 2180 | |
| 2181 | static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) |
| 2182 | { |
| 2183 | uint32_t tmp; |
| 2184 | tmp = ((Gmac *)hw)->EFRSL.reg; |
| 2185 | tmp &= mask; |
| 2186 | return tmp; |
| 2187 | } |
| 2188 | |
| 2189 | static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) |
| 2190 | { |
| 2191 | return ((Gmac *)hw)->EFRSL.reg; |
| 2192 | } |
| 2193 | |
| 2194 | static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) |
| 2195 | { |
| 2196 | return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; |
| 2197 | } |
| 2198 | |
| 2199 | static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) |
| 2200 | { |
| 2201 | return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; |
| 2202 | } |
| 2203 | |
| 2204 | static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) |
| 2205 | { |
| 2206 | uint32_t tmp; |
| 2207 | tmp = ((Gmac *)hw)->EFRN.reg; |
| 2208 | tmp &= mask; |
| 2209 | return tmp; |
| 2210 | } |
| 2211 | |
| 2212 | static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) |
| 2213 | { |
| 2214 | return ((Gmac *)hw)->EFRN.reg; |
| 2215 | } |
| 2216 | |
| 2217 | static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) |
| 2218 | { |
| 2219 | return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; |
| 2220 | } |
| 2221 | |
| 2222 | static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) |
| 2223 | { |
| 2224 | return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; |
| 2225 | } |
| 2226 | |
| 2227 | static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) |
| 2228 | { |
| 2229 | uint32_t tmp; |
| 2230 | tmp = ((Gmac *)hw)->PEFTSL.reg; |
| 2231 | tmp &= mask; |
| 2232 | return tmp; |
| 2233 | } |
| 2234 | |
| 2235 | static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) |
| 2236 | { |
| 2237 | return ((Gmac *)hw)->PEFTSL.reg; |
| 2238 | } |
| 2239 | |
| 2240 | static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) |
| 2241 | { |
| 2242 | return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; |
| 2243 | } |
| 2244 | |
| 2245 | static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) |
| 2246 | { |
| 2247 | return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; |
| 2248 | } |
| 2249 | |
| 2250 | static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) |
| 2251 | { |
| 2252 | uint32_t tmp; |
| 2253 | tmp = ((Gmac *)hw)->PEFTN.reg; |
| 2254 | tmp &= mask; |
| 2255 | return tmp; |
| 2256 | } |
| 2257 | |
| 2258 | static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) |
| 2259 | { |
| 2260 | return ((Gmac *)hw)->PEFTN.reg; |
| 2261 | } |
| 2262 | |
| 2263 | static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) |
| 2264 | { |
| 2265 | return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; |
| 2266 | } |
| 2267 | |
| 2268 | static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) |
| 2269 | { |
| 2270 | return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; |
| 2271 | } |
| 2272 | |
| 2273 | static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) |
| 2274 | { |
| 2275 | uint32_t tmp; |
| 2276 | tmp = ((Gmac *)hw)->PEFRSL.reg; |
| 2277 | tmp &= mask; |
| 2278 | return tmp; |
| 2279 | } |
| 2280 | |
| 2281 | static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) |
| 2282 | { |
| 2283 | return ((Gmac *)hw)->PEFRSL.reg; |
| 2284 | } |
| 2285 | |
| 2286 | static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) |
| 2287 | { |
| 2288 | return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; |
| 2289 | } |
| 2290 | |
| 2291 | static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) |
| 2292 | { |
| 2293 | return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; |
| 2294 | } |
| 2295 | |
| 2296 | static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) |
| 2297 | { |
| 2298 | uint32_t tmp; |
| 2299 | tmp = ((Gmac *)hw)->PEFRN.reg; |
| 2300 | tmp &= mask; |
| 2301 | return tmp; |
| 2302 | } |
| 2303 | |
| 2304 | static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) |
| 2305 | { |
| 2306 | return ((Gmac *)hw)->PEFRN.reg; |
| 2307 | } |
| 2308 | |
| 2309 | static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask) |
| 2310 | { |
| 2311 | return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos; |
| 2312 | } |
| 2313 | |
| 2314 | static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw) |
| 2315 | { |
| 2316 | return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos; |
| 2317 | } |
| 2318 | |
| 2319 | static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask) |
| 2320 | { |
| 2321 | uint32_t tmp; |
| 2322 | tmp = ((Gmac *)hw)->RLPITR.reg; |
| 2323 | tmp &= mask; |
| 2324 | return tmp; |
| 2325 | } |
| 2326 | |
| 2327 | static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw) |
| 2328 | { |
| 2329 | return ((Gmac *)hw)->RLPITR.reg; |
| 2330 | } |
| 2331 | |
| 2332 | static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask) |
| 2333 | { |
| 2334 | return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos; |
| 2335 | } |
| 2336 | |
| 2337 | static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw) |
| 2338 | { |
| 2339 | return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos; |
| 2340 | } |
| 2341 | |
| 2342 | static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask) |
| 2343 | { |
| 2344 | uint32_t tmp; |
| 2345 | tmp = ((Gmac *)hw)->RLPITI.reg; |
| 2346 | tmp &= mask; |
| 2347 | return tmp; |
| 2348 | } |
| 2349 | |
| 2350 | static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw) |
| 2351 | { |
| 2352 | return ((Gmac *)hw)->RLPITI.reg; |
| 2353 | } |
| 2354 | |
| 2355 | static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask) |
| 2356 | { |
| 2357 | return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos; |
| 2358 | } |
| 2359 | |
| 2360 | static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw) |
| 2361 | { |
| 2362 | return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos; |
| 2363 | } |
| 2364 | |
| 2365 | static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask) |
| 2366 | { |
| 2367 | uint32_t tmp; |
| 2368 | tmp = ((Gmac *)hw)->TLPITR.reg; |
| 2369 | tmp &= mask; |
| 2370 | return tmp; |
| 2371 | } |
| 2372 | |
| 2373 | static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw) |
| 2374 | { |
| 2375 | return ((Gmac *)hw)->TLPITR.reg; |
| 2376 | } |
| 2377 | |
| 2378 | static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask) |
| 2379 | { |
| 2380 | return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos; |
| 2381 | } |
| 2382 | |
| 2383 | static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw) |
| 2384 | { |
| 2385 | return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos; |
| 2386 | } |
| 2387 | |
| 2388 | static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask) |
| 2389 | { |
| 2390 | uint32_t tmp; |
| 2391 | tmp = ((Gmac *)hw)->TLPITI.reg; |
| 2392 | tmp &= mask; |
| 2393 | return tmp; |
| 2394 | } |
| 2395 | |
| 2396 | static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw) |
| 2397 | { |
| 2398 | return ((Gmac *)hw)->TLPITI.reg; |
| 2399 | } |
| 2400 | |
| 2401 | static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) |
| 2402 | { |
| 2403 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2404 | ((Gmac *)hw)->NCR.reg |= mask; |
| 2405 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2406 | } |
| 2407 | |
| 2408 | static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) |
| 2409 | { |
| 2410 | uint32_t tmp; |
| 2411 | tmp = ((Gmac *)hw)->NCR.reg; |
| 2412 | tmp &= mask; |
| 2413 | return tmp; |
| 2414 | } |
| 2415 | |
| 2416 | static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) |
| 2417 | { |
| 2418 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2419 | ((Gmac *)hw)->NCR.reg = data; |
| 2420 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2421 | } |
| 2422 | |
| 2423 | static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) |
| 2424 | { |
| 2425 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2426 | ((Gmac *)hw)->NCR.reg &= ~mask; |
| 2427 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2428 | } |
| 2429 | |
| 2430 | static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) |
| 2431 | { |
| 2432 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2433 | ((Gmac *)hw)->NCR.reg ^= mask; |
| 2434 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2435 | } |
| 2436 | |
| 2437 | static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) |
| 2438 | { |
| 2439 | return ((Gmac *)hw)->NCR.reg; |
| 2440 | } |
| 2441 | |
| 2442 | static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) |
| 2443 | { |
| 2444 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2445 | ((Gmac *)hw)->NCFGR.reg |= mask; |
| 2446 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2447 | } |
| 2448 | |
| 2449 | static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) |
| 2450 | { |
| 2451 | uint32_t tmp; |
| 2452 | tmp = ((Gmac *)hw)->NCFGR.reg; |
| 2453 | tmp &= mask; |
| 2454 | return tmp; |
| 2455 | } |
| 2456 | |
| 2457 | static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) |
| 2458 | { |
| 2459 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2460 | ((Gmac *)hw)->NCFGR.reg = data; |
| 2461 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2462 | } |
| 2463 | |
| 2464 | static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) |
| 2465 | { |
| 2466 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2467 | ((Gmac *)hw)->NCFGR.reg &= ~mask; |
| 2468 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2469 | } |
| 2470 | |
| 2471 | static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) |
| 2472 | { |
| 2473 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2474 | ((Gmac *)hw)->NCFGR.reg ^= mask; |
| 2475 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2476 | } |
| 2477 | |
| 2478 | static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) |
| 2479 | { |
| 2480 | return ((Gmac *)hw)->NCFGR.reg; |
| 2481 | } |
| 2482 | |
| 2483 | static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) |
| 2484 | { |
| 2485 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2486 | ((Gmac *)hw)->UR.reg |= mask; |
| 2487 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2488 | } |
| 2489 | |
| 2490 | static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) |
| 2491 | { |
| 2492 | uint32_t tmp; |
| 2493 | tmp = ((Gmac *)hw)->UR.reg; |
| 2494 | tmp &= mask; |
| 2495 | return tmp; |
| 2496 | } |
| 2497 | |
| 2498 | static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) |
| 2499 | { |
| 2500 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2501 | ((Gmac *)hw)->UR.reg = data; |
| 2502 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2503 | } |
| 2504 | |
| 2505 | static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) |
| 2506 | { |
| 2507 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2508 | ((Gmac *)hw)->UR.reg &= ~mask; |
| 2509 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2510 | } |
| 2511 | |
| 2512 | static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) |
| 2513 | { |
| 2514 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2515 | ((Gmac *)hw)->UR.reg ^= mask; |
| 2516 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2517 | } |
| 2518 | |
| 2519 | static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) |
| 2520 | { |
| 2521 | return ((Gmac *)hw)->UR.reg; |
| 2522 | } |
| 2523 | |
| 2524 | static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) |
| 2525 | { |
| 2526 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2527 | ((Gmac *)hw)->DCFGR.reg |= mask; |
| 2528 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2529 | } |
| 2530 | |
| 2531 | static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) |
| 2532 | { |
| 2533 | uint32_t tmp; |
| 2534 | tmp = ((Gmac *)hw)->DCFGR.reg; |
| 2535 | tmp &= mask; |
| 2536 | return tmp; |
| 2537 | } |
| 2538 | |
| 2539 | static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) |
| 2540 | { |
| 2541 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2542 | ((Gmac *)hw)->DCFGR.reg = data; |
| 2543 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2544 | } |
| 2545 | |
| 2546 | static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) |
| 2547 | { |
| 2548 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2549 | ((Gmac *)hw)->DCFGR.reg &= ~mask; |
| 2550 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2551 | } |
| 2552 | |
| 2553 | static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) |
| 2554 | { |
| 2555 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2556 | ((Gmac *)hw)->DCFGR.reg ^= mask; |
| 2557 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2558 | } |
| 2559 | |
| 2560 | static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) |
| 2561 | { |
| 2562 | return ((Gmac *)hw)->DCFGR.reg; |
| 2563 | } |
| 2564 | |
| 2565 | static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) |
| 2566 | { |
| 2567 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2568 | ((Gmac *)hw)->TSR.reg |= mask; |
| 2569 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2570 | } |
| 2571 | |
| 2572 | static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) |
| 2573 | { |
| 2574 | uint32_t tmp; |
| 2575 | tmp = ((Gmac *)hw)->TSR.reg; |
| 2576 | tmp &= mask; |
| 2577 | return tmp; |
| 2578 | } |
| 2579 | |
| 2580 | static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) |
| 2581 | { |
| 2582 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2583 | ((Gmac *)hw)->TSR.reg = data; |
| 2584 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2585 | } |
| 2586 | |
| 2587 | static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) |
| 2588 | { |
| 2589 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2590 | ((Gmac *)hw)->TSR.reg &= ~mask; |
| 2591 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2592 | } |
| 2593 | |
| 2594 | static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) |
| 2595 | { |
| 2596 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2597 | ((Gmac *)hw)->TSR.reg ^= mask; |
| 2598 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2599 | } |
| 2600 | |
| 2601 | static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) |
| 2602 | { |
| 2603 | return ((Gmac *)hw)->TSR.reg; |
| 2604 | } |
| 2605 | |
| 2606 | static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) |
| 2607 | { |
| 2608 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2609 | ((Gmac *)hw)->RBQB.reg |= mask; |
| 2610 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2611 | } |
| 2612 | |
| 2613 | static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) |
| 2614 | { |
| 2615 | uint32_t tmp; |
| 2616 | tmp = ((Gmac *)hw)->RBQB.reg; |
| 2617 | tmp &= mask; |
| 2618 | return tmp; |
| 2619 | } |
| 2620 | |
| 2621 | static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) |
| 2622 | { |
| 2623 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2624 | ((Gmac *)hw)->RBQB.reg = data; |
| 2625 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2626 | } |
| 2627 | |
| 2628 | static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) |
| 2629 | { |
| 2630 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2631 | ((Gmac *)hw)->RBQB.reg &= ~mask; |
| 2632 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2633 | } |
| 2634 | |
| 2635 | static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) |
| 2636 | { |
| 2637 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2638 | ((Gmac *)hw)->RBQB.reg ^= mask; |
| 2639 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2640 | } |
| 2641 | |
| 2642 | static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) |
| 2643 | { |
| 2644 | return ((Gmac *)hw)->RBQB.reg; |
| 2645 | } |
| 2646 | |
| 2647 | static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) |
| 2648 | { |
| 2649 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2650 | ((Gmac *)hw)->TBQB.reg |= mask; |
| 2651 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2652 | } |
| 2653 | |
| 2654 | static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) |
| 2655 | { |
| 2656 | uint32_t tmp; |
| 2657 | tmp = ((Gmac *)hw)->TBQB.reg; |
| 2658 | tmp &= mask; |
| 2659 | return tmp; |
| 2660 | } |
| 2661 | |
| 2662 | static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) |
| 2663 | { |
| 2664 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2665 | ((Gmac *)hw)->TBQB.reg = data; |
| 2666 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2667 | } |
| 2668 | |
| 2669 | static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) |
| 2670 | { |
| 2671 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2672 | ((Gmac *)hw)->TBQB.reg &= ~mask; |
| 2673 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2674 | } |
| 2675 | |
| 2676 | static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) |
| 2677 | { |
| 2678 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2679 | ((Gmac *)hw)->TBQB.reg ^= mask; |
| 2680 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2681 | } |
| 2682 | |
| 2683 | static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) |
| 2684 | { |
| 2685 | return ((Gmac *)hw)->TBQB.reg; |
| 2686 | } |
| 2687 | |
| 2688 | static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) |
| 2689 | { |
| 2690 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2691 | ((Gmac *)hw)->RSR.reg |= mask; |
| 2692 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2693 | } |
| 2694 | |
| 2695 | static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) |
| 2696 | { |
| 2697 | uint32_t tmp; |
| 2698 | tmp = ((Gmac *)hw)->RSR.reg; |
| 2699 | tmp &= mask; |
| 2700 | return tmp; |
| 2701 | } |
| 2702 | |
| 2703 | static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) |
| 2704 | { |
| 2705 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2706 | ((Gmac *)hw)->RSR.reg = data; |
| 2707 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2708 | } |
| 2709 | |
| 2710 | static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) |
| 2711 | { |
| 2712 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2713 | ((Gmac *)hw)->RSR.reg &= ~mask; |
| 2714 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2715 | } |
| 2716 | |
| 2717 | static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) |
| 2718 | { |
| 2719 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2720 | ((Gmac *)hw)->RSR.reg ^= mask; |
| 2721 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2722 | } |
| 2723 | |
| 2724 | static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) |
| 2725 | { |
| 2726 | return ((Gmac *)hw)->RSR.reg; |
| 2727 | } |
| 2728 | |
| 2729 | static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) |
| 2730 | { |
| 2731 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2732 | ((Gmac *)hw)->ISR.reg |= mask; |
| 2733 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2734 | } |
| 2735 | |
| 2736 | static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) |
| 2737 | { |
| 2738 | uint32_t tmp; |
| 2739 | tmp = ((Gmac *)hw)->ISR.reg; |
| 2740 | tmp &= mask; |
| 2741 | return tmp; |
| 2742 | } |
| 2743 | |
| 2744 | static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data) |
| 2745 | { |
| 2746 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2747 | ((Gmac *)hw)->ISR.reg = data; |
| 2748 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2749 | } |
| 2750 | |
| 2751 | static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) |
| 2752 | { |
| 2753 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2754 | ((Gmac *)hw)->ISR.reg &= ~mask; |
| 2755 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2756 | } |
| 2757 | |
| 2758 | static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) |
| 2759 | { |
| 2760 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2761 | ((Gmac *)hw)->ISR.reg ^= mask; |
| 2762 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2763 | } |
| 2764 | |
| 2765 | static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) |
| 2766 | { |
| 2767 | return ((Gmac *)hw)->ISR.reg; |
| 2768 | } |
| 2769 | |
| 2770 | static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) |
| 2771 | { |
| 2772 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2773 | ((Gmac *)hw)->MAN.reg |= mask; |
| 2774 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2775 | } |
| 2776 | |
| 2777 | static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) |
| 2778 | { |
| 2779 | uint32_t tmp; |
| 2780 | tmp = ((Gmac *)hw)->MAN.reg; |
| 2781 | tmp &= mask; |
| 2782 | return tmp; |
| 2783 | } |
| 2784 | |
| 2785 | static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) |
| 2786 | { |
| 2787 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2788 | ((Gmac *)hw)->MAN.reg = data; |
| 2789 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2790 | } |
| 2791 | |
| 2792 | static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) |
| 2793 | { |
| 2794 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2795 | ((Gmac *)hw)->MAN.reg &= ~mask; |
| 2796 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2797 | } |
| 2798 | |
| 2799 | static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) |
| 2800 | { |
| 2801 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2802 | ((Gmac *)hw)->MAN.reg ^= mask; |
| 2803 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2804 | } |
| 2805 | |
| 2806 | static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) |
| 2807 | { |
| 2808 | return ((Gmac *)hw)->MAN.reg; |
| 2809 | } |
| 2810 | |
| 2811 | static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) |
| 2812 | { |
| 2813 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2814 | ((Gmac *)hw)->TPQ.reg |= mask; |
| 2815 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2816 | } |
| 2817 | |
| 2818 | static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) |
| 2819 | { |
| 2820 | uint32_t tmp; |
| 2821 | tmp = ((Gmac *)hw)->TPQ.reg; |
| 2822 | tmp &= mask; |
| 2823 | return tmp; |
| 2824 | } |
| 2825 | |
| 2826 | static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) |
| 2827 | { |
| 2828 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2829 | ((Gmac *)hw)->TPQ.reg = data; |
| 2830 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2831 | } |
| 2832 | |
| 2833 | static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) |
| 2834 | { |
| 2835 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2836 | ((Gmac *)hw)->TPQ.reg &= ~mask; |
| 2837 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2838 | } |
| 2839 | |
| 2840 | static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) |
| 2841 | { |
| 2842 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2843 | ((Gmac *)hw)->TPQ.reg ^= mask; |
| 2844 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2845 | } |
| 2846 | |
| 2847 | static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) |
| 2848 | { |
| 2849 | return ((Gmac *)hw)->TPQ.reg; |
| 2850 | } |
| 2851 | |
| 2852 | static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) |
| 2853 | { |
| 2854 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2855 | ((Gmac *)hw)->TPSF.reg |= mask; |
| 2856 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2857 | } |
| 2858 | |
| 2859 | static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) |
| 2860 | { |
| 2861 | uint32_t tmp; |
| 2862 | tmp = ((Gmac *)hw)->TPSF.reg; |
| 2863 | tmp &= mask; |
| 2864 | return tmp; |
| 2865 | } |
| 2866 | |
| 2867 | static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) |
| 2868 | { |
| 2869 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2870 | ((Gmac *)hw)->TPSF.reg = data; |
| 2871 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2872 | } |
| 2873 | |
| 2874 | static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) |
| 2875 | { |
| 2876 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2877 | ((Gmac *)hw)->TPSF.reg &= ~mask; |
| 2878 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2879 | } |
| 2880 | |
| 2881 | static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) |
| 2882 | { |
| 2883 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2884 | ((Gmac *)hw)->TPSF.reg ^= mask; |
| 2885 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2886 | } |
| 2887 | |
| 2888 | static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) |
| 2889 | { |
| 2890 | return ((Gmac *)hw)->TPSF.reg; |
| 2891 | } |
| 2892 | |
| 2893 | static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) |
| 2894 | { |
| 2895 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2896 | ((Gmac *)hw)->RPSF.reg |= mask; |
| 2897 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2898 | } |
| 2899 | |
| 2900 | static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) |
| 2901 | { |
| 2902 | uint32_t tmp; |
| 2903 | tmp = ((Gmac *)hw)->RPSF.reg; |
| 2904 | tmp &= mask; |
| 2905 | return tmp; |
| 2906 | } |
| 2907 | |
| 2908 | static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) |
| 2909 | { |
| 2910 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2911 | ((Gmac *)hw)->RPSF.reg = data; |
| 2912 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2913 | } |
| 2914 | |
| 2915 | static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) |
| 2916 | { |
| 2917 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2918 | ((Gmac *)hw)->RPSF.reg &= ~mask; |
| 2919 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2920 | } |
| 2921 | |
| 2922 | static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) |
| 2923 | { |
| 2924 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2925 | ((Gmac *)hw)->RPSF.reg ^= mask; |
| 2926 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2927 | } |
| 2928 | |
| 2929 | static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) |
| 2930 | { |
| 2931 | return ((Gmac *)hw)->RPSF.reg; |
| 2932 | } |
| 2933 | |
| 2934 | static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) |
| 2935 | { |
| 2936 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2937 | ((Gmac *)hw)->RJFML.reg |= mask; |
| 2938 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2939 | } |
| 2940 | |
| 2941 | static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) |
| 2942 | { |
| 2943 | uint32_t tmp; |
| 2944 | tmp = ((Gmac *)hw)->RJFML.reg; |
| 2945 | tmp &= mask; |
| 2946 | return tmp; |
| 2947 | } |
| 2948 | |
| 2949 | static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) |
| 2950 | { |
| 2951 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2952 | ((Gmac *)hw)->RJFML.reg = data; |
| 2953 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2954 | } |
| 2955 | |
| 2956 | static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) |
| 2957 | { |
| 2958 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2959 | ((Gmac *)hw)->RJFML.reg &= ~mask; |
| 2960 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2961 | } |
| 2962 | |
| 2963 | static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) |
| 2964 | { |
| 2965 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2966 | ((Gmac *)hw)->RJFML.reg ^= mask; |
| 2967 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2968 | } |
| 2969 | |
| 2970 | static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) |
| 2971 | { |
| 2972 | return ((Gmac *)hw)->RJFML.reg; |
| 2973 | } |
| 2974 | |
| 2975 | static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) |
| 2976 | { |
| 2977 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2978 | ((Gmac *)hw)->HRB.reg |= mask; |
| 2979 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2980 | } |
| 2981 | |
| 2982 | static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) |
| 2983 | { |
| 2984 | uint32_t tmp; |
| 2985 | tmp = ((Gmac *)hw)->HRB.reg; |
| 2986 | tmp &= mask; |
| 2987 | return tmp; |
| 2988 | } |
| 2989 | |
| 2990 | static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) |
| 2991 | { |
| 2992 | GMAC_CRITICAL_SECTION_ENTER(); |
| 2993 | ((Gmac *)hw)->HRB.reg = data; |
| 2994 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 2995 | } |
| 2996 | |
| 2997 | static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) |
| 2998 | { |
| 2999 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3000 | ((Gmac *)hw)->HRB.reg &= ~mask; |
| 3001 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3002 | } |
| 3003 | |
| 3004 | static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) |
| 3005 | { |
| 3006 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3007 | ((Gmac *)hw)->HRB.reg ^= mask; |
| 3008 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3009 | } |
| 3010 | |
| 3011 | static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) |
| 3012 | { |
| 3013 | return ((Gmac *)hw)->HRB.reg; |
| 3014 | } |
| 3015 | |
| 3016 | static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) |
| 3017 | { |
| 3018 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3019 | ((Gmac *)hw)->HRT.reg |= mask; |
| 3020 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3021 | } |
| 3022 | |
| 3023 | static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) |
| 3024 | { |
| 3025 | uint32_t tmp; |
| 3026 | tmp = ((Gmac *)hw)->HRT.reg; |
| 3027 | tmp &= mask; |
| 3028 | return tmp; |
| 3029 | } |
| 3030 | |
| 3031 | static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) |
| 3032 | { |
| 3033 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3034 | ((Gmac *)hw)->HRT.reg = data; |
| 3035 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3036 | } |
| 3037 | |
| 3038 | static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) |
| 3039 | { |
| 3040 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3041 | ((Gmac *)hw)->HRT.reg &= ~mask; |
| 3042 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3043 | } |
| 3044 | |
| 3045 | static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) |
| 3046 | { |
| 3047 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3048 | ((Gmac *)hw)->HRT.reg ^= mask; |
| 3049 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3050 | } |
| 3051 | |
| 3052 | static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) |
| 3053 | { |
| 3054 | return ((Gmac *)hw)->HRT.reg; |
| 3055 | } |
| 3056 | |
| 3057 | static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) |
| 3058 | { |
| 3059 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3060 | ((Gmac *)hw)->TIDM[index].reg |= mask; |
| 3061 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3062 | } |
| 3063 | |
| 3064 | static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) |
| 3065 | { |
| 3066 | uint32_t tmp; |
| 3067 | tmp = ((Gmac *)hw)->TIDM[index].reg; |
| 3068 | tmp &= mask; |
| 3069 | return tmp; |
| 3070 | } |
| 3071 | |
| 3072 | static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data) |
| 3073 | { |
| 3074 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3075 | ((Gmac *)hw)->TIDM[index].reg = data; |
| 3076 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3077 | } |
| 3078 | |
| 3079 | static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) |
| 3080 | { |
| 3081 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3082 | ((Gmac *)hw)->TIDM[index].reg &= ~mask; |
| 3083 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3084 | } |
| 3085 | |
| 3086 | static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) |
| 3087 | { |
| 3088 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3089 | ((Gmac *)hw)->TIDM[index].reg ^= mask; |
| 3090 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3091 | } |
| 3092 | |
| 3093 | static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index) |
| 3094 | { |
| 3095 | return ((Gmac *)hw)->TIDM[index].reg; |
| 3096 | } |
| 3097 | |
| 3098 | static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) |
| 3099 | { |
| 3100 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3101 | ((Gmac *)hw)->WOL.reg |= mask; |
| 3102 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3103 | } |
| 3104 | |
| 3105 | static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) |
| 3106 | { |
| 3107 | uint32_t tmp; |
| 3108 | tmp = ((Gmac *)hw)->WOL.reg; |
| 3109 | tmp &= mask; |
| 3110 | return tmp; |
| 3111 | } |
| 3112 | |
| 3113 | static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) |
| 3114 | { |
| 3115 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3116 | ((Gmac *)hw)->WOL.reg = data; |
| 3117 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3118 | } |
| 3119 | |
| 3120 | static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) |
| 3121 | { |
| 3122 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3123 | ((Gmac *)hw)->WOL.reg &= ~mask; |
| 3124 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3125 | } |
| 3126 | |
| 3127 | static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) |
| 3128 | { |
| 3129 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3130 | ((Gmac *)hw)->WOL.reg ^= mask; |
| 3131 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3132 | } |
| 3133 | |
| 3134 | static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) |
| 3135 | { |
| 3136 | return ((Gmac *)hw)->WOL.reg; |
| 3137 | } |
| 3138 | |
| 3139 | static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) |
| 3140 | { |
| 3141 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3142 | ((Gmac *)hw)->IPGS.reg |= mask; |
| 3143 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3144 | } |
| 3145 | |
| 3146 | static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) |
| 3147 | { |
| 3148 | uint32_t tmp; |
| 3149 | tmp = ((Gmac *)hw)->IPGS.reg; |
| 3150 | tmp &= mask; |
| 3151 | return tmp; |
| 3152 | } |
| 3153 | |
| 3154 | static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) |
| 3155 | { |
| 3156 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3157 | ((Gmac *)hw)->IPGS.reg = data; |
| 3158 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3159 | } |
| 3160 | |
| 3161 | static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) |
| 3162 | { |
| 3163 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3164 | ((Gmac *)hw)->IPGS.reg &= ~mask; |
| 3165 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3166 | } |
| 3167 | |
| 3168 | static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) |
| 3169 | { |
| 3170 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3171 | ((Gmac *)hw)->IPGS.reg ^= mask; |
| 3172 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3173 | } |
| 3174 | |
| 3175 | static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) |
| 3176 | { |
| 3177 | return ((Gmac *)hw)->IPGS.reg; |
| 3178 | } |
| 3179 | |
| 3180 | static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) |
| 3181 | { |
| 3182 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3183 | ((Gmac *)hw)->SVLAN.reg |= mask; |
| 3184 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3185 | } |
| 3186 | |
| 3187 | static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) |
| 3188 | { |
| 3189 | uint32_t tmp; |
| 3190 | tmp = ((Gmac *)hw)->SVLAN.reg; |
| 3191 | tmp &= mask; |
| 3192 | return tmp; |
| 3193 | } |
| 3194 | |
| 3195 | static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) |
| 3196 | { |
| 3197 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3198 | ((Gmac *)hw)->SVLAN.reg = data; |
| 3199 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3200 | } |
| 3201 | |
| 3202 | static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) |
| 3203 | { |
| 3204 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3205 | ((Gmac *)hw)->SVLAN.reg &= ~mask; |
| 3206 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3207 | } |
| 3208 | |
| 3209 | static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) |
| 3210 | { |
| 3211 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3212 | ((Gmac *)hw)->SVLAN.reg ^= mask; |
| 3213 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3214 | } |
| 3215 | |
| 3216 | static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) |
| 3217 | { |
| 3218 | return ((Gmac *)hw)->SVLAN.reg; |
| 3219 | } |
| 3220 | |
| 3221 | static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) |
| 3222 | { |
| 3223 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3224 | ((Gmac *)hw)->TPFCP.reg |= mask; |
| 3225 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3226 | } |
| 3227 | |
| 3228 | static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) |
| 3229 | { |
| 3230 | uint32_t tmp; |
| 3231 | tmp = ((Gmac *)hw)->TPFCP.reg; |
| 3232 | tmp &= mask; |
| 3233 | return tmp; |
| 3234 | } |
| 3235 | |
| 3236 | static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) |
| 3237 | { |
| 3238 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3239 | ((Gmac *)hw)->TPFCP.reg = data; |
| 3240 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3241 | } |
| 3242 | |
| 3243 | static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) |
| 3244 | { |
| 3245 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3246 | ((Gmac *)hw)->TPFCP.reg &= ~mask; |
| 3247 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3248 | } |
| 3249 | |
| 3250 | static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) |
| 3251 | { |
| 3252 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3253 | ((Gmac *)hw)->TPFCP.reg ^= mask; |
| 3254 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3255 | } |
| 3256 | |
| 3257 | static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) |
| 3258 | { |
| 3259 | return ((Gmac *)hw)->TPFCP.reg; |
| 3260 | } |
| 3261 | |
| 3262 | static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) |
| 3263 | { |
| 3264 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3265 | ((Gmac *)hw)->SAMB1.reg |= mask; |
| 3266 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3267 | } |
| 3268 | |
| 3269 | static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) |
| 3270 | { |
| 3271 | uint32_t tmp; |
| 3272 | tmp = ((Gmac *)hw)->SAMB1.reg; |
| 3273 | tmp &= mask; |
| 3274 | return tmp; |
| 3275 | } |
| 3276 | |
| 3277 | static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) |
| 3278 | { |
| 3279 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3280 | ((Gmac *)hw)->SAMB1.reg = data; |
| 3281 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3282 | } |
| 3283 | |
| 3284 | static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) |
| 3285 | { |
| 3286 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3287 | ((Gmac *)hw)->SAMB1.reg &= ~mask; |
| 3288 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3289 | } |
| 3290 | |
| 3291 | static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) |
| 3292 | { |
| 3293 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3294 | ((Gmac *)hw)->SAMB1.reg ^= mask; |
| 3295 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3296 | } |
| 3297 | |
| 3298 | static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) |
| 3299 | { |
| 3300 | return ((Gmac *)hw)->SAMB1.reg; |
| 3301 | } |
| 3302 | |
| 3303 | static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) |
| 3304 | { |
| 3305 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3306 | ((Gmac *)hw)->SAMT1.reg |= mask; |
| 3307 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3308 | } |
| 3309 | |
| 3310 | static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) |
| 3311 | { |
| 3312 | uint32_t tmp; |
| 3313 | tmp = ((Gmac *)hw)->SAMT1.reg; |
| 3314 | tmp &= mask; |
| 3315 | return tmp; |
| 3316 | } |
| 3317 | |
| 3318 | static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) |
| 3319 | { |
| 3320 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3321 | ((Gmac *)hw)->SAMT1.reg = data; |
| 3322 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3323 | } |
| 3324 | |
| 3325 | static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) |
| 3326 | { |
| 3327 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3328 | ((Gmac *)hw)->SAMT1.reg &= ~mask; |
| 3329 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3330 | } |
| 3331 | |
| 3332 | static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) |
| 3333 | { |
| 3334 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3335 | ((Gmac *)hw)->SAMT1.reg ^= mask; |
| 3336 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3337 | } |
| 3338 | |
| 3339 | static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) |
| 3340 | { |
| 3341 | return ((Gmac *)hw)->SAMT1.reg; |
| 3342 | } |
| 3343 | |
| 3344 | static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) |
| 3345 | { |
| 3346 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3347 | ((Gmac *)hw)->NSC.reg |= mask; |
| 3348 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3349 | } |
| 3350 | |
| 3351 | static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) |
| 3352 | { |
| 3353 | uint32_t tmp; |
| 3354 | tmp = ((Gmac *)hw)->NSC.reg; |
| 3355 | tmp &= mask; |
| 3356 | return tmp; |
| 3357 | } |
| 3358 | |
| 3359 | static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) |
| 3360 | { |
| 3361 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3362 | ((Gmac *)hw)->NSC.reg = data; |
| 3363 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3364 | } |
| 3365 | |
| 3366 | static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) |
| 3367 | { |
| 3368 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3369 | ((Gmac *)hw)->NSC.reg &= ~mask; |
| 3370 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3371 | } |
| 3372 | |
| 3373 | static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) |
| 3374 | { |
| 3375 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3376 | ((Gmac *)hw)->NSC.reg ^= mask; |
| 3377 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3378 | } |
| 3379 | |
| 3380 | static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) |
| 3381 | { |
| 3382 | return ((Gmac *)hw)->NSC.reg; |
| 3383 | } |
| 3384 | |
| 3385 | static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) |
| 3386 | { |
| 3387 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3388 | ((Gmac *)hw)->SCL.reg |= mask; |
| 3389 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3390 | } |
| 3391 | |
| 3392 | static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) |
| 3393 | { |
| 3394 | uint32_t tmp; |
| 3395 | tmp = ((Gmac *)hw)->SCL.reg; |
| 3396 | tmp &= mask; |
| 3397 | return tmp; |
| 3398 | } |
| 3399 | |
| 3400 | static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) |
| 3401 | { |
| 3402 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3403 | ((Gmac *)hw)->SCL.reg = data; |
| 3404 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3405 | } |
| 3406 | |
| 3407 | static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) |
| 3408 | { |
| 3409 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3410 | ((Gmac *)hw)->SCL.reg &= ~mask; |
| 3411 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3412 | } |
| 3413 | |
| 3414 | static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) |
| 3415 | { |
| 3416 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3417 | ((Gmac *)hw)->SCL.reg ^= mask; |
| 3418 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3419 | } |
| 3420 | |
| 3421 | static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) |
| 3422 | { |
| 3423 | return ((Gmac *)hw)->SCL.reg; |
| 3424 | } |
| 3425 | |
| 3426 | static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) |
| 3427 | { |
| 3428 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3429 | ((Gmac *)hw)->SCH.reg |= mask; |
| 3430 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3431 | } |
| 3432 | |
| 3433 | static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) |
| 3434 | { |
| 3435 | uint32_t tmp; |
| 3436 | tmp = ((Gmac *)hw)->SCH.reg; |
| 3437 | tmp &= mask; |
| 3438 | return tmp; |
| 3439 | } |
| 3440 | |
| 3441 | static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) |
| 3442 | { |
| 3443 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3444 | ((Gmac *)hw)->SCH.reg = data; |
| 3445 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3446 | } |
| 3447 | |
| 3448 | static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) |
| 3449 | { |
| 3450 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3451 | ((Gmac *)hw)->SCH.reg &= ~mask; |
| 3452 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3453 | } |
| 3454 | |
| 3455 | static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) |
| 3456 | { |
| 3457 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3458 | ((Gmac *)hw)->SCH.reg ^= mask; |
| 3459 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3460 | } |
| 3461 | |
| 3462 | static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) |
| 3463 | { |
| 3464 | return ((Gmac *)hw)->SCH.reg; |
| 3465 | } |
| 3466 | |
| 3467 | static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) |
| 3468 | { |
| 3469 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3470 | ((Gmac *)hw)->TISUBN.reg |= mask; |
| 3471 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3472 | } |
| 3473 | |
| 3474 | static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) |
| 3475 | { |
| 3476 | uint32_t tmp; |
| 3477 | tmp = ((Gmac *)hw)->TISUBN.reg; |
| 3478 | tmp &= mask; |
| 3479 | return tmp; |
| 3480 | } |
| 3481 | |
| 3482 | static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) |
| 3483 | { |
| 3484 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3485 | ((Gmac *)hw)->TISUBN.reg = data; |
| 3486 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3487 | } |
| 3488 | |
| 3489 | static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) |
| 3490 | { |
| 3491 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3492 | ((Gmac *)hw)->TISUBN.reg &= ~mask; |
| 3493 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3494 | } |
| 3495 | |
| 3496 | static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) |
| 3497 | { |
| 3498 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3499 | ((Gmac *)hw)->TISUBN.reg ^= mask; |
| 3500 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3501 | } |
| 3502 | |
| 3503 | static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) |
| 3504 | { |
| 3505 | return ((Gmac *)hw)->TISUBN.reg; |
| 3506 | } |
| 3507 | |
| 3508 | static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) |
| 3509 | { |
| 3510 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3511 | ((Gmac *)hw)->TSH.reg |= mask; |
| 3512 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3513 | } |
| 3514 | |
| 3515 | static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) |
| 3516 | { |
| 3517 | uint32_t tmp; |
| 3518 | tmp = ((Gmac *)hw)->TSH.reg; |
| 3519 | tmp &= mask; |
| 3520 | return tmp; |
| 3521 | } |
| 3522 | |
| 3523 | static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) |
| 3524 | { |
| 3525 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3526 | ((Gmac *)hw)->TSH.reg = data; |
| 3527 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3528 | } |
| 3529 | |
| 3530 | static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) |
| 3531 | { |
| 3532 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3533 | ((Gmac *)hw)->TSH.reg &= ~mask; |
| 3534 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3535 | } |
| 3536 | |
| 3537 | static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) |
| 3538 | { |
| 3539 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3540 | ((Gmac *)hw)->TSH.reg ^= mask; |
| 3541 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3542 | } |
| 3543 | |
| 3544 | static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) |
| 3545 | { |
| 3546 | return ((Gmac *)hw)->TSH.reg; |
| 3547 | } |
| 3548 | |
| 3549 | static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) |
| 3550 | { |
| 3551 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3552 | ((Gmac *)hw)->TSSSL.reg |= mask; |
| 3553 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3554 | } |
| 3555 | |
| 3556 | static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) |
| 3557 | { |
| 3558 | uint32_t tmp; |
| 3559 | tmp = ((Gmac *)hw)->TSSSL.reg; |
| 3560 | tmp &= mask; |
| 3561 | return tmp; |
| 3562 | } |
| 3563 | |
| 3564 | static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data) |
| 3565 | { |
| 3566 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3567 | ((Gmac *)hw)->TSSSL.reg = data; |
| 3568 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3569 | } |
| 3570 | |
| 3571 | static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) |
| 3572 | { |
| 3573 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3574 | ((Gmac *)hw)->TSSSL.reg &= ~mask; |
| 3575 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3576 | } |
| 3577 | |
| 3578 | static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) |
| 3579 | { |
| 3580 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3581 | ((Gmac *)hw)->TSSSL.reg ^= mask; |
| 3582 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3583 | } |
| 3584 | |
| 3585 | static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw) |
| 3586 | { |
| 3587 | return ((Gmac *)hw)->TSSSL.reg; |
| 3588 | } |
| 3589 | |
| 3590 | static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) |
| 3591 | { |
| 3592 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3593 | ((Gmac *)hw)->TSSN.reg |= mask; |
| 3594 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3595 | } |
| 3596 | |
| 3597 | static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) |
| 3598 | { |
| 3599 | uint32_t tmp; |
| 3600 | tmp = ((Gmac *)hw)->TSSN.reg; |
| 3601 | tmp &= mask; |
| 3602 | return tmp; |
| 3603 | } |
| 3604 | |
| 3605 | static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data) |
| 3606 | { |
| 3607 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3608 | ((Gmac *)hw)->TSSN.reg = data; |
| 3609 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3610 | } |
| 3611 | |
| 3612 | static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) |
| 3613 | { |
| 3614 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3615 | ((Gmac *)hw)->TSSN.reg &= ~mask; |
| 3616 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3617 | } |
| 3618 | |
| 3619 | static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) |
| 3620 | { |
| 3621 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3622 | ((Gmac *)hw)->TSSN.reg ^= mask; |
| 3623 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3624 | } |
| 3625 | |
| 3626 | static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw) |
| 3627 | { |
| 3628 | return ((Gmac *)hw)->TSSN.reg; |
| 3629 | } |
| 3630 | |
| 3631 | static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) |
| 3632 | { |
| 3633 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3634 | ((Gmac *)hw)->TSL.reg |= mask; |
| 3635 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3636 | } |
| 3637 | |
| 3638 | static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) |
| 3639 | { |
| 3640 | uint32_t tmp; |
| 3641 | tmp = ((Gmac *)hw)->TSL.reg; |
| 3642 | tmp &= mask; |
| 3643 | return tmp; |
| 3644 | } |
| 3645 | |
| 3646 | static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) |
| 3647 | { |
| 3648 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3649 | ((Gmac *)hw)->TSL.reg = data; |
| 3650 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3651 | } |
| 3652 | |
| 3653 | static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) |
| 3654 | { |
| 3655 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3656 | ((Gmac *)hw)->TSL.reg &= ~mask; |
| 3657 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3658 | } |
| 3659 | |
| 3660 | static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) |
| 3661 | { |
| 3662 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3663 | ((Gmac *)hw)->TSL.reg ^= mask; |
| 3664 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3665 | } |
| 3666 | |
| 3667 | static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) |
| 3668 | { |
| 3669 | return ((Gmac *)hw)->TSL.reg; |
| 3670 | } |
| 3671 | |
| 3672 | static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) |
| 3673 | { |
| 3674 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3675 | ((Gmac *)hw)->TN.reg |= mask; |
| 3676 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3677 | } |
| 3678 | |
| 3679 | static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) |
| 3680 | { |
| 3681 | uint32_t tmp; |
| 3682 | tmp = ((Gmac *)hw)->TN.reg; |
| 3683 | tmp &= mask; |
| 3684 | return tmp; |
| 3685 | } |
| 3686 | |
| 3687 | static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) |
| 3688 | { |
| 3689 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3690 | ((Gmac *)hw)->TN.reg = data; |
| 3691 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3692 | } |
| 3693 | |
| 3694 | static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) |
| 3695 | { |
| 3696 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3697 | ((Gmac *)hw)->TN.reg &= ~mask; |
| 3698 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3699 | } |
| 3700 | |
| 3701 | static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) |
| 3702 | { |
| 3703 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3704 | ((Gmac *)hw)->TN.reg ^= mask; |
| 3705 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3706 | } |
| 3707 | |
| 3708 | static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) |
| 3709 | { |
| 3710 | return ((Gmac *)hw)->TN.reg; |
| 3711 | } |
| 3712 | |
| 3713 | static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) |
| 3714 | { |
| 3715 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3716 | ((Gmac *)hw)->TI.reg |= mask; |
| 3717 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3718 | } |
| 3719 | |
| 3720 | static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) |
| 3721 | { |
| 3722 | uint32_t tmp; |
| 3723 | tmp = ((Gmac *)hw)->TI.reg; |
| 3724 | tmp &= mask; |
| 3725 | return tmp; |
| 3726 | } |
| 3727 | |
| 3728 | static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) |
| 3729 | { |
| 3730 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3731 | ((Gmac *)hw)->TI.reg = data; |
| 3732 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3733 | } |
| 3734 | |
| 3735 | static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) |
| 3736 | { |
| 3737 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3738 | ((Gmac *)hw)->TI.reg &= ~mask; |
| 3739 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3740 | } |
| 3741 | |
| 3742 | static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) |
| 3743 | { |
| 3744 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3745 | ((Gmac *)hw)->TI.reg ^= mask; |
| 3746 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3747 | } |
| 3748 | |
| 3749 | static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) |
| 3750 | { |
| 3751 | return ((Gmac *)hw)->TI.reg; |
| 3752 | } |
| 3753 | |
| 3754 | static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) |
| 3755 | { |
| 3756 | GMAC_CRITICAL_SECTION_ENTER(); |
| 3757 | ((Gmac *)hw)->TA.reg = data; |
| 3758 | GMAC_CRITICAL_SECTION_LEAVE(); |
| 3759 | } |
| 3760 | |
| 3761 | #ifdef __cplusplus |
| 3762 | } |
| 3763 | #endif |
| 3764 | |
| 3765 | #endif /* _HRI_GMAC_E54_H_INCLUDED */ |
| 3766 | #endif /* _SAME54_GMAC_COMPONENT_ */ |