Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /* Auto-generated config file hpl_usb_config.h */ |
| 2 | #ifndef HPL_USB_CONFIG_H |
| 3 | #define HPL_USB_CONFIG_H |
| 4 | |
| 5 | // <<< Use Configuration Wizard in Context Menu >>> |
| 6 | |
| 7 | #define CONF_USB_N_0 0 |
| 8 | #define CONF_USB_N_1 1 |
| 9 | #define CONF_USB_N_2 2 |
| 10 | #define CONF_USB_N_3 3 |
| 11 | #define CONF_USB_N_4 4 |
| 12 | #define CONF_USB_N_5 5 |
| 13 | #define CONF_USB_N_6 6 |
| 14 | #define CONF_USB_N_7 7 |
| 15 | #define CONF_USB_N_8 8 |
| 16 | #define CONF_USB_N_9 9 |
| 17 | #define CONF_USB_N_10 10 |
| 18 | #define CONF_USB_N_11 11 |
| 19 | #define CONF_USB_N_12 12 |
| 20 | #define CONF_USB_N_13 13 |
| 21 | #define CONF_USB_N_14 14 |
| 22 | #define CONF_USB_N_15 15 |
| 23 | |
| 24 | #define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) |
| 25 | #define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) |
| 26 | |
| 27 | // <h> USB Device HAL Configuration |
| 28 | |
| 29 | // <y> Max number of endpoints supported |
| 30 | // <i> Limits the number of endpoints (described by EP address) can be used in app. |
| 31 | // <CONF_USB_N_1"> 1 (EP0 only) |
| 32 | // <CONF_USB_N_2"> 2 (EP0 + 1 endpoint) |
| 33 | // <CONF_USB_N_3"> 3 (EP0 + 2 endpoints) |
| 34 | // <CONF_USB_N_4"> 4 (EP0 + 3 endpoints) |
| 35 | // <CONF_USB_N_5"> 5 (EP0 + 4 endpoints) |
| 36 | // <CONF_USB_N_6"> 6 (EP0 + 5 endpoints) |
| 37 | // <CONF_USB_N_7"> 7 (EP0 + 6 endpoints) |
| 38 | // <CONF_USB_N_8"> 8 (EP0 + 7 endpoints) |
| 39 | // <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config) |
| 40 | // <id> usbd_num_ep_sp |
| 41 | #ifndef CONF_USB_D_NUM_EP_SP |
Harald Welte | 34a8706 | 2019-04-19 22:33:36 +0200 | [diff] [blame] | 42 | #define CONF_USB_D_NUM_EP_SP CONF_USB_N_6 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 43 | #endif |
| 44 | |
| 45 | // </h> |
| 46 | |
| 47 | // <y> Max Endpoint Number supported |
| 48 | // <i> Limits the max endpoint number. |
| 49 | // <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. |
| 50 | // <i> Reduce the value according to specific device design, to cut-off memory usage. |
| 51 | // <CONF_USB_N_0"> 0 (only EP0) |
| 52 | // <CONF_USB_N_1"> 1 (EP 0x81 or 0x01) |
| 53 | // <CONF_USB_N_2"> 2 (EP 0x82 or 0x02) |
| 54 | // <CONF_USB_N_3"> 3 (EP 0x83 or 0x03) |
| 55 | // <CONF_USB_N_4"> 4 (EP 0x84 or 0x04) |
| 56 | // <CONF_USB_N_5"> 5 (EP 0x85 or 0x05) |
| 57 | // <CONF_USB_N_6"> 6 (EP 0x86 or 0x06) |
| 58 | // <CONF_USB_N_7"> 7 (EP 0x87 or 0x07) |
| 59 | // <CONF_USB_EP_N_MAX"> Max possible (by HW) |
| 60 | // <i> The number of physical endpoints - 1 |
| 61 | // <id> usbd_arch_max_ep_n |
| 62 | #ifndef CONF_USB_D_MAX_EP_N |
Harald Welte | 34a8706 | 2019-04-19 22:33:36 +0200 | [diff] [blame] | 63 | #define CONF_USB_D_MAX_EP_N CONF_USB_N_4 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 64 | #endif |
| 65 | |
| 66 | // <y> USB Speed Limit |
| 67 | // <i> Limits the working speed of the device. |
| 68 | // <USB_SPEED_FS"> Full speed |
| 69 | // <USB_SPEED_LS"> Low Speed |
| 70 | // <id> usbd_arch_speed |
| 71 | #ifndef CONF_USB_D_SPEED |
| 72 | #define CONF_USB_D_SPEED USB_SPEED_FS |
| 73 | #endif |
| 74 | |
| 75 | // <o> Cache buffer size for EP0 |
| 76 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 77 | // <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. |
| 78 | // <8=> Cached by 8 bytes buffer |
| 79 | // <16=> Cached by 16 bytes buffer |
| 80 | // <32=> Cached by 32 bytes buffer |
| 81 | // <64=> Cached by 64 bytes buffer |
| 82 | // <id> usb_arch_ep0_cache |
| 83 | #ifndef CONF_USB_EP0_CACHE |
| 84 | #define CONF_USB_EP0_CACHE 64 |
| 85 | #endif |
| 86 | |
| 87 | // <h> Cache configuration EP1 |
| 88 | // <o> Cache buffer size for EP1 OUT |
| 89 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 90 | // <i> This cache must be allocated if you plan to use the endpoint as control endpoint. |
| 91 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 92 | // <0=> No cache |
| 93 | // <8=> Cached by 8 bytes buffer |
| 94 | // <16=> Cached by 16 bytes buffer |
| 95 | // <32=> Cached by 32 bytes buffer |
| 96 | // <64=> Cached by 64 bytes buffer |
| 97 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 98 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 99 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 100 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 101 | // <id> usb_arch_ep1_cache |
| 102 | #ifndef CONF_USB_EP1_CACHE |
| 103 | #define CONF_USB_EP1_CACHE 64 |
| 104 | #endif |
| 105 | |
| 106 | // <o> Cache buffer size for EP1 IN |
| 107 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 108 | // <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. |
| 109 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 110 | // <0=> No cache |
| 111 | // <8=> Cached by 8 bytes buffer |
| 112 | // <16=> Cached by 16 bytes buffer |
| 113 | // <32=> Cached by 32 bytes buffer |
| 114 | // <64=> Cached by 64 bytes buffer |
| 115 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 116 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 117 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 118 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 119 | // <id> usb_ep1_I_CACHE |
| 120 | #ifndef CONF_USB_EP1_I_CACHE |
| 121 | #define CONF_USB_EP1_I_CACHE 0 |
| 122 | #endif |
| 123 | // </h> |
| 124 | |
| 125 | // <h> Cache configuration EP2 |
| 126 | // <o> Cache buffer size for EP2 OUT |
| 127 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 128 | // <i> This cache must be allocated if you plan to use the endpoint as control endpoint. |
| 129 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 130 | // <0=> No cache |
| 131 | // <8=> Cached by 8 bytes buffer |
| 132 | // <16=> Cached by 16 bytes buffer |
| 133 | // <32=> Cached by 32 bytes buffer |
| 134 | // <64=> Cached by 64 bytes buffer |
| 135 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 136 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 137 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 138 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 139 | // <id> usb_arch_ep2_cache |
| 140 | #ifndef CONF_USB_EP2_CACHE |
| 141 | #define CONF_USB_EP2_CACHE 64 |
| 142 | #endif |
| 143 | |
| 144 | // <o> Cache buffer size for EP2 IN |
| 145 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 146 | // <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. |
| 147 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 148 | // <0=> No cache |
| 149 | // <8=> Cached by 8 bytes buffer |
| 150 | // <16=> Cached by 16 bytes buffer |
| 151 | // <32=> Cached by 32 bytes buffer |
| 152 | // <64=> Cached by 64 bytes buffer |
| 153 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 154 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 155 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 156 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 157 | // <id> usb_ep2_I_CACHE |
| 158 | #ifndef CONF_USB_EP2_I_CACHE |
| 159 | #define CONF_USB_EP2_I_CACHE 0 |
| 160 | #endif |
| 161 | // </h> |
| 162 | |
| 163 | // <h> Cache configuration EP3 |
| 164 | // <o> Cache buffer size for EP3 OUT |
| 165 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 166 | // <i> This cache must be allocated if you plan to use the endpoint as control endpoint. |
| 167 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 168 | // <0=> No cache |
| 169 | // <8=> Cached by 8 bytes buffer |
| 170 | // <16=> Cached by 16 bytes buffer |
| 171 | // <32=> Cached by 32 bytes buffer |
| 172 | // <64=> Cached by 64 bytes buffer |
| 173 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 174 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 175 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 176 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 177 | // <id> usb_arch_ep3_cache |
| 178 | #ifndef CONF_USB_EP3_CACHE |
| 179 | #define CONF_USB_EP3_CACHE 64 |
| 180 | #endif |
| 181 | |
| 182 | // <o> Cache buffer size for EP3 IN |
| 183 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 184 | // <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. |
| 185 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 186 | // <0=> No cache |
| 187 | // <8=> Cached by 8 bytes buffer |
| 188 | // <16=> Cached by 16 bytes buffer |
| 189 | // <32=> Cached by 32 bytes buffer |
| 190 | // <64=> Cached by 64 bytes buffer |
| 191 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 192 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 193 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 194 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 195 | // <id> usb_ep3_I_CACHE |
| 196 | #ifndef CONF_USB_EP3_I_CACHE |
| 197 | #define CONF_USB_EP3_I_CACHE 0 |
| 198 | #endif |
| 199 | // </h> |
| 200 | |
| 201 | // <h> Cache configuration EP4 |
| 202 | // <o> Cache buffer size for EP4 OUT |
| 203 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 204 | // <i> This cache must be allocated if you plan to use the endpoint as control endpoint. |
| 205 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 206 | // <0=> No cache |
| 207 | // <8=> Cached by 8 bytes buffer |
| 208 | // <16=> Cached by 16 bytes buffer |
| 209 | // <32=> Cached by 32 bytes buffer |
| 210 | // <64=> Cached by 64 bytes buffer |
| 211 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 212 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 213 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 214 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 215 | // <id> usb_arch_ep4_cache |
| 216 | #ifndef CONF_USB_EP4_CACHE |
| 217 | #define CONF_USB_EP4_CACHE 64 |
| 218 | #endif |
| 219 | |
| 220 | // <o> Cache buffer size for EP4 IN |
| 221 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 222 | // <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. |
| 223 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 224 | // <0=> No cache |
| 225 | // <8=> Cached by 8 bytes buffer |
| 226 | // <16=> Cached by 16 bytes buffer |
| 227 | // <32=> Cached by 32 bytes buffer |
| 228 | // <64=> Cached by 64 bytes buffer |
| 229 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 230 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 231 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 232 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 233 | // <id> usb_ep4_I_CACHE |
| 234 | #ifndef CONF_USB_EP4_I_CACHE |
| 235 | #define CONF_USB_EP4_I_CACHE 0 |
| 236 | #endif |
| 237 | // </h> |
| 238 | |
| 239 | // <h> Cache configuration EP5 |
| 240 | // <o> Cache buffer size for EP5 OUT |
| 241 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 242 | // <i> This cache must be allocated if you plan to use the endpoint as control endpoint. |
| 243 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 244 | // <0=> No cache |
| 245 | // <8=> Cached by 8 bytes buffer |
| 246 | // <16=> Cached by 16 bytes buffer |
| 247 | // <32=> Cached by 32 bytes buffer |
| 248 | // <64=> Cached by 64 bytes buffer |
| 249 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 250 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 251 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 252 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 253 | // <id> usb_arch_ep5_cache |
| 254 | #ifndef CONF_USB_EP5_CACHE |
| 255 | #define CONF_USB_EP5_CACHE 64 |
| 256 | #endif |
| 257 | |
| 258 | // <o> Cache buffer size for EP5 IN |
| 259 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 260 | // <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. |
| 261 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 262 | // <0=> No cache |
| 263 | // <8=> Cached by 8 bytes buffer |
| 264 | // <16=> Cached by 16 bytes buffer |
| 265 | // <32=> Cached by 32 bytes buffer |
| 266 | // <64=> Cached by 64 bytes buffer |
| 267 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 268 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 269 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 270 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 271 | // <id> usb_ep5_I_CACHE |
| 272 | #ifndef CONF_USB_EP5_I_CACHE |
| 273 | #define CONF_USB_EP5_I_CACHE 0 |
| 274 | #endif |
| 275 | // </h> |
| 276 | |
| 277 | // <h> Cache configuration EP6 |
| 278 | // <o> Cache buffer size for EP6 OUT |
| 279 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 280 | // <i> This cache must be allocated if you plan to use the endpoint as control endpoint. |
| 281 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 282 | // <0=> No cache |
| 283 | // <8=> Cached by 8 bytes buffer |
| 284 | // <16=> Cached by 16 bytes buffer |
| 285 | // <32=> Cached by 32 bytes buffer |
| 286 | // <64=> Cached by 64 bytes buffer |
| 287 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 288 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 289 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 290 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 291 | // <id> usb_arch_ep6_cache |
| 292 | #ifndef CONF_USB_EP6_CACHE |
| 293 | #define CONF_USB_EP6_CACHE 64 |
| 294 | #endif |
| 295 | |
| 296 | // <o> Cache buffer size for EP6 IN |
| 297 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 298 | // <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. |
| 299 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 300 | // <0=> No cache |
| 301 | // <8=> Cached by 8 bytes buffer |
| 302 | // <16=> Cached by 16 bytes buffer |
| 303 | // <32=> Cached by 32 bytes buffer |
| 304 | // <64=> Cached by 64 bytes buffer |
| 305 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 306 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 307 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 308 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 309 | // <id> usb_ep6_I_CACHE |
| 310 | #ifndef CONF_USB_EP6_I_CACHE |
| 311 | #define CONF_USB_EP6_I_CACHE 0 |
| 312 | #endif |
| 313 | // </h> |
| 314 | |
| 315 | // <h> Cache configuration EP7 |
| 316 | // <o> Cache buffer size for EP7 OUT |
| 317 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 318 | // <i> This cache must be allocated if you plan to use the endpoint as control endpoint. |
| 319 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 320 | // <0=> No cache |
| 321 | // <8=> Cached by 8 bytes buffer |
| 322 | // <16=> Cached by 16 bytes buffer |
| 323 | // <32=> Cached by 32 bytes buffer |
| 324 | // <64=> Cached by 64 bytes buffer |
| 325 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 326 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 327 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 328 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 329 | // <id> usb_arch_ep7_cache |
| 330 | #ifndef CONF_USB_EP7_CACHE |
| 331 | #define CONF_USB_EP7_CACHE 64 |
| 332 | #endif |
| 333 | |
| 334 | // <o> Cache buffer size for EP7 IN |
| 335 | // <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. |
| 336 | // <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. |
| 337 | // <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size |
| 338 | // <0=> No cache |
| 339 | // <8=> Cached by 8 bytes buffer |
| 340 | // <16=> Cached by 16 bytes buffer |
| 341 | // <32=> Cached by 32 bytes buffer |
| 342 | // <64=> Cached by 64 bytes buffer |
| 343 | // <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 344 | // <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 345 | // <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) |
| 346 | // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) |
| 347 | // <id> usb_ep7_I_CACHE |
| 348 | #ifndef CONF_USB_EP7_I_CACHE |
| 349 | #define CONF_USB_EP7_I_CACHE 0 |
| 350 | #endif |
| 351 | // </h> |
| 352 | |
| 353 | // <<< end of configuration section >>> |
| 354 | |
| 355 | #endif // HPL_USB_CONFIG_H |