| format_version: '2' |
| name: sysmoOCTSIM |
| versions: |
| api: '1.0' |
| backend: 1.5.122 |
| commit: 820baecf7dd115d94b0d42ee3b0b9d6ba2da7113 |
| content: 1.0.1405 |
| content_pack_name: acme-packs-all |
| format: '2' |
| frontend: 1.5.1826 |
| board: |
| identifier: CustomBoard |
| device: SAME54N19A-AF |
| details: null |
| application: null |
| middlewares: |
| USB_CHAPTER_9: |
| user_label: USB_CHAPTER_9 |
| configuration: {} |
| definition: Atmel:USB:0.0.1::USB_Chapter_9 |
| functionality: USB_Chapter_9 |
| api: USB:Protocol:Core |
| dependencies: {} |
| USB_CLASS_CDC: |
| user_label: USB_CLASS_CDC |
| configuration: {} |
| definition: Atmel:USB:0.0.1::USB_Class_CDC |
| functionality: USB_Class_CDC |
| api: USB:Protocol:CDC |
| dependencies: |
| USB Chapter 9: USB_CHAPTER_9 |
| USB_DEVICE_STACK_CORE_INSTANCE: |
| user_label: USB_DEVICE_STACK_CORE_INSTANCE |
| configuration: |
| usbd_hs_sp: false |
| definition: Atmel:USB:0.0.1::USB_Device_Core |
| functionality: USB_Device_Core |
| api: USB:Device:Core |
| dependencies: |
| USB Chapter 9: USB_CHAPTER_9 |
| USB Device instance: USB_DEVICE_INSTANCE |
| USB_DEVICE_CDC_ACM: |
| user_label: USB_DEVICE_CDC_ACM |
| configuration: |
| usb_cdcd_acm_bcddevice: 256 |
| usb_cdcd_acm_bcdusb: USB 2.0 version |
| usb_cdcd_acm_bconfigval: 1 |
| usb_cdcd_acm_bmattri: Bus power supply, not support for remote wakeup |
| usb_cdcd_acm_bmaxpksz0: 64 bytes |
| usb_cdcd_acm_bmaxpower: 50 |
| usb_cdcd_acm_bnumconfig: 1 |
| usb_cdcd_acm_comm_baltset: 0 |
| usb_cdcd_acm_comm_bifcnum: 0 |
| usb_cdcd_acm_comm_iifc: 0 |
| usb_cdcd_acm_comm_int_interval: 10 |
| usb_cdcd_acm_comm_int_maxpksz: 64 bytes |
| usb_cdcd_acm_data_baltset: 0 |
| usb_cdcd_acm_data_bifcnum: 1 |
| usb_cdcd_acm_data_buckout_maxpksz: 64 bytes |
| usb_cdcd_acm_data_buckout_maxpksz_hs: 512 bytes |
| usb_cdcd_acm_data_builin_maxpksz: 64 bytes |
| usb_cdcd_acm_data_builin_maxpksz_hs: 512 bytes |
| usb_cdcd_acm_data_bulkin_epaddr: EndpointAddress = 0x81 |
| usb_cdcd_acm_data_bulkout_epaddr: EndpointAddress = 0x01 |
| usb_cdcd_acm_data_iifc: 0 |
| usb_cdcd_acm_epaddr: EndpointAddress = 0x82 |
| usb_cdcd_acm_iconfig_en: false |
| usb_cdcd_acm_iconfig_str: '' |
| usb_cdcd_acm_idproduct: 24897 |
| usb_cdcd_acm_idvender: 7504 |
| usb_cdcd_acm_imanufact_en: true |
| usb_cdcd_acm_imanufact_str: sysmocom |
| usb_cdcd_acm_iproduct_en: true |
| usb_cdcd_acm_iproduct_str: sysmoOCTSIM |
| usb_cdcd_acm_iserialnum_en: false |
| usb_cdcd_acm_iserialnum_str: 123456789ABCDEF |
| usb_cdcd_acm_langid: '0x0409' |
| usb_cdcd_acm_str_en: true |
| definition: Atmel:USB:0.0.1::USB_Device_CDC_ACM |
| functionality: USB_Device_CDC_ACM |
| api: USB:Device:CDC_ACM |
| dependencies: |
| USB Device Stack Core Instance: USB_DEVICE_STACK_CORE_INSTANCE |
| USB Class CDC: USB_CLASS_CDC |
| M2M_DMA_0: |
| user_label: M2M_DMA_0 |
| configuration: |
| conf_channel: 0 |
| definition: Atmel:MEMORY_DMA:0.0.1::M2M_DMA |
| functionality: M2M_DMA |
| api: DMA:M2M:Core |
| dependencies: |
| DMAC: DMAC |
| STDIO_REDIRECT_0: |
| user_label: STDIO_REDIRECT_0 |
| configuration: {} |
| definition: Atmel:STDIO_redirect:0.0.1::STDIO_Redirect |
| functionality: STDIO_Redirect |
| api: STDIO:Redirect:IO |
| dependencies: |
| Target IO: UART_debug |
| drivers: |
| CMCC: |
| user_label: CMCC |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC |
| functionality: System |
| api: HAL:HPL:CMCC |
| configuration: |
| cache_size: 4 KB |
| cmcc_advanced_configuration: false |
| cmcc_clock_gating_disable: false |
| cmcc_data_cache_disable: false |
| cmcc_enable: false |
| cmcc_inst_cache_disable: false |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: null |
| DMAC: |
| user_label: DMAC |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC |
| functionality: System |
| api: HAL:HPL:DMAC |
| configuration: |
| dmac_beatsize_0: 8-bit bus transfer |
| dmac_beatsize_1: 8-bit bus transfer |
| dmac_beatsize_10: 8-bit bus transfer |
| dmac_beatsize_11: 8-bit bus transfer |
| dmac_beatsize_12: 8-bit bus transfer |
| dmac_beatsize_13: 8-bit bus transfer |
| dmac_beatsize_14: 8-bit bus transfer |
| dmac_beatsize_15: 8-bit bus transfer |
| dmac_beatsize_16: 8-bit bus transfer |
| dmac_beatsize_17: 8-bit bus transfer |
| dmac_beatsize_18: 8-bit bus transfer |
| dmac_beatsize_19: 8-bit bus transfer |
| dmac_beatsize_2: 8-bit bus transfer |
| dmac_beatsize_20: 8-bit bus transfer |
| dmac_beatsize_21: 8-bit bus transfer |
| dmac_beatsize_22: 8-bit bus transfer |
| dmac_beatsize_23: 8-bit bus transfer |
| dmac_beatsize_24: 8-bit bus transfer |
| dmac_beatsize_25: 8-bit bus transfer |
| dmac_beatsize_26: 8-bit bus transfer |
| dmac_beatsize_27: 8-bit bus transfer |
| dmac_beatsize_28: 8-bit bus transfer |
| dmac_beatsize_29: 8-bit bus transfer |
| dmac_beatsize_3: 8-bit bus transfer |
| dmac_beatsize_30: 8-bit bus transfer |
| dmac_beatsize_31: 8-bit bus transfer |
| dmac_beatsize_4: 8-bit bus transfer |
| dmac_beatsize_5: 8-bit bus transfer |
| dmac_beatsize_6: 8-bit bus transfer |
| dmac_beatsize_7: 8-bit bus transfer |
| dmac_beatsize_8: 8-bit bus transfer |
| dmac_beatsize_9: 8-bit bus transfer |
| dmac_blockact_0: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_1: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_10: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_11: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_12: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_13: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_14: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_15: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_16: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_17: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_18: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_19: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_2: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_20: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_21: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_22: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_23: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_24: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_25: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_26: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_27: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_28: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_29: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_3: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_30: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_31: Channel will be disabled if it is the last block transfer |
| in the transaction |
| dmac_blockact_4: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_5: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_6: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_7: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_8: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_blockact_9: Channel will be disabled if it is the last block transfer in |
| the transaction |
| dmac_channel_0_settings: true |
| dmac_channel_10_settings: false |
| dmac_channel_11_settings: false |
| dmac_channel_12_settings: false |
| dmac_channel_13_settings: false |
| dmac_channel_14_settings: false |
| dmac_channel_15_settings: false |
| dmac_channel_16_settings: false |
| dmac_channel_17_settings: false |
| dmac_channel_18_settings: false |
| dmac_channel_19_settings: false |
| dmac_channel_1_settings: false |
| dmac_channel_20_settings: false |
| dmac_channel_21_settings: false |
| dmac_channel_22_settings: false |
| dmac_channel_23_settings: false |
| dmac_channel_24_settings: false |
| dmac_channel_25_settings: false |
| dmac_channel_26_settings: false |
| dmac_channel_27_settings: false |
| dmac_channel_28_settings: false |
| dmac_channel_29_settings: false |
| dmac_channel_2_settings: false |
| dmac_channel_30_settings: false |
| dmac_channel_31_settings: false |
| dmac_channel_3_settings: false |
| dmac_channel_4_settings: false |
| dmac_channel_5_settings: false |
| dmac_channel_6_settings: false |
| dmac_channel_7_settings: false |
| dmac_channel_8_settings: false |
| dmac_channel_9_settings: false |
| dmac_dbgrun: false |
| dmac_dstinc_0: true |
| dmac_dstinc_1: false |
| dmac_dstinc_10: false |
| dmac_dstinc_11: false |
| dmac_dstinc_12: false |
| dmac_dstinc_13: false |
| dmac_dstinc_14: false |
| dmac_dstinc_15: false |
| dmac_dstinc_16: false |
| dmac_dstinc_17: false |
| dmac_dstinc_18: false |
| dmac_dstinc_19: false |
| dmac_dstinc_2: false |
| dmac_dstinc_20: false |
| dmac_dstinc_21: false |
| dmac_dstinc_22: false |
| dmac_dstinc_23: false |
| dmac_dstinc_24: false |
| dmac_dstinc_25: false |
| dmac_dstinc_26: false |
| dmac_dstinc_27: false |
| dmac_dstinc_28: false |
| dmac_dstinc_29: false |
| dmac_dstinc_3: false |
| dmac_dstinc_30: false |
| dmac_dstinc_31: false |
| dmac_dstinc_4: false |
| dmac_dstinc_5: false |
| dmac_dstinc_6: false |
| dmac_dstinc_7: false |
| dmac_dstinc_8: false |
| dmac_dstinc_9: false |
| dmac_enable: true |
| dmac_evact_0: No action |
| dmac_evact_1: No action |
| dmac_evact_10: No action |
| dmac_evact_11: No action |
| dmac_evact_12: No action |
| dmac_evact_13: No action |
| dmac_evact_14: No action |
| dmac_evact_15: No action |
| dmac_evact_16: No action |
| dmac_evact_17: No action |
| dmac_evact_18: No action |
| dmac_evact_19: No action |
| dmac_evact_2: No action |
| dmac_evact_20: No action |
| dmac_evact_21: No action |
| dmac_evact_22: No action |
| dmac_evact_23: No action |
| dmac_evact_24: No action |
| dmac_evact_25: No action |
| dmac_evact_26: No action |
| dmac_evact_27: No action |
| dmac_evact_28: No action |
| dmac_evact_29: No action |
| dmac_evact_3: No action |
| dmac_evact_30: No action |
| dmac_evact_31: No action |
| dmac_evact_4: No action |
| dmac_evact_5: No action |
| dmac_evact_6: No action |
| dmac_evact_7: No action |
| dmac_evact_8: No action |
| dmac_evact_9: No action |
| dmac_evie_0: false |
| dmac_evie_1: false |
| dmac_evie_10: false |
| dmac_evie_11: false |
| dmac_evie_12: false |
| dmac_evie_13: false |
| dmac_evie_14: false |
| dmac_evie_15: false |
| dmac_evie_16: false |
| dmac_evie_17: false |
| dmac_evie_18: false |
| dmac_evie_19: false |
| dmac_evie_2: false |
| dmac_evie_20: false |
| dmac_evie_21: false |
| dmac_evie_22: false |
| dmac_evie_23: false |
| dmac_evie_24: false |
| dmac_evie_25: false |
| dmac_evie_26: false |
| dmac_evie_27: false |
| dmac_evie_28: false |
| dmac_evie_29: false |
| dmac_evie_3: false |
| dmac_evie_30: false |
| dmac_evie_31: false |
| dmac_evie_4: false |
| dmac_evie_5: false |
| dmac_evie_6: false |
| dmac_evie_7: false |
| dmac_evie_8: false |
| dmac_evie_9: false |
| dmac_evoe_0: false |
| dmac_evoe_1: false |
| dmac_evoe_10: false |
| dmac_evoe_11: false |
| dmac_evoe_12: false |
| dmac_evoe_13: false |
| dmac_evoe_14: false |
| dmac_evoe_15: false |
| dmac_evoe_16: false |
| dmac_evoe_17: false |
| dmac_evoe_18: false |
| dmac_evoe_19: false |
| dmac_evoe_2: false |
| dmac_evoe_20: false |
| dmac_evoe_21: false |
| dmac_evoe_22: false |
| dmac_evoe_23: false |
| dmac_evoe_24: false |
| dmac_evoe_25: false |
| dmac_evoe_26: false |
| dmac_evoe_27: false |
| dmac_evoe_28: false |
| dmac_evoe_29: false |
| dmac_evoe_3: false |
| dmac_evoe_30: false |
| dmac_evoe_31: false |
| dmac_evoe_4: false |
| dmac_evoe_5: false |
| dmac_evoe_6: false |
| dmac_evoe_7: false |
| dmac_evoe_8: false |
| dmac_evoe_9: false |
| dmac_evosel_0: Event generation disabled |
| dmac_evosel_1: Event generation disabled |
| dmac_evosel_10: Event generation disabled |
| dmac_evosel_11: Event generation disabled |
| dmac_evosel_12: Event generation disabled |
| dmac_evosel_13: Event generation disabled |
| dmac_evosel_14: Event generation disabled |
| dmac_evosel_15: Event generation disabled |
| dmac_evosel_16: Event generation disabled |
| dmac_evosel_17: Event generation disabled |
| dmac_evosel_18: Event generation disabled |
| dmac_evosel_19: Event generation disabled |
| dmac_evosel_2: Event generation disabled |
| dmac_evosel_20: Event generation disabled |
| dmac_evosel_21: Event generation disabled |
| dmac_evosel_22: Event generation disabled |
| dmac_evosel_23: Event generation disabled |
| dmac_evosel_24: Event generation disabled |
| dmac_evosel_25: Event generation disabled |
| dmac_evosel_26: Event generation disabled |
| dmac_evosel_27: Event generation disabled |
| dmac_evosel_28: Event generation disabled |
| dmac_evosel_29: Event generation disabled |
| dmac_evosel_3: Event generation disabled |
| dmac_evosel_30: Event generation disabled |
| dmac_evosel_31: Event generation disabled |
| dmac_evosel_4: Event generation disabled |
| dmac_evosel_5: Event generation disabled |
| dmac_evosel_6: Event generation disabled |
| dmac_evosel_7: Event generation disabled |
| dmac_evosel_8: Event generation disabled |
| dmac_evosel_9: Event generation disabled |
| dmac_lvl_0: Channel priority 0 |
| dmac_lvl_1: Channel priority 0 |
| dmac_lvl_10: Channel priority 0 |
| dmac_lvl_11: Channel priority 0 |
| dmac_lvl_12: Channel priority 0 |
| dmac_lvl_13: Channel priority 0 |
| dmac_lvl_14: Channel priority 0 |
| dmac_lvl_15: Channel priority 0 |
| dmac_lvl_16: Channel priority 0 |
| dmac_lvl_17: Channel priority 0 |
| dmac_lvl_18: Channel priority 0 |
| dmac_lvl_19: Channel priority 0 |
| dmac_lvl_2: Channel priority 0 |
| dmac_lvl_20: Channel priority 0 |
| dmac_lvl_21: Channel priority 0 |
| dmac_lvl_22: Channel priority 0 |
| dmac_lvl_23: Channel priority 0 |
| dmac_lvl_24: Channel priority 0 |
| dmac_lvl_25: Channel priority 0 |
| dmac_lvl_26: Channel priority 0 |
| dmac_lvl_27: Channel priority 0 |
| dmac_lvl_28: Channel priority 0 |
| dmac_lvl_29: Channel priority 0 |
| dmac_lvl_3: Channel priority 0 |
| dmac_lvl_30: Channel priority 0 |
| dmac_lvl_31: Channel priority 0 |
| dmac_lvl_4: Channel priority 0 |
| dmac_lvl_5: Channel priority 0 |
| dmac_lvl_6: Channel priority 0 |
| dmac_lvl_7: Channel priority 0 |
| dmac_lvl_8: Channel priority 0 |
| dmac_lvl_9: Channel priority 0 |
| dmac_lvlen0: true |
| dmac_lvlen1: true |
| dmac_lvlen2: true |
| dmac_lvlen3: true |
| dmac_lvlpri0: 0 |
| dmac_lvlpri1: 0 |
| dmac_lvlpri2: 0 |
| dmac_lvlpri3: 0 |
| dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 |
| dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 |
| dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 |
| dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 |
| dmac_runstdby_0: false |
| dmac_runstdby_1: false |
| dmac_runstdby_10: false |
| dmac_runstdby_11: false |
| dmac_runstdby_12: false |
| dmac_runstdby_13: false |
| dmac_runstdby_14: false |
| dmac_runstdby_15: false |
| dmac_runstdby_16: false |
| dmac_runstdby_17: false |
| dmac_runstdby_18: false |
| dmac_runstdby_19: false |
| dmac_runstdby_2: false |
| dmac_runstdby_20: false |
| dmac_runstdby_21: false |
| dmac_runstdby_22: false |
| dmac_runstdby_23: false |
| dmac_runstdby_24: false |
| dmac_runstdby_25: false |
| dmac_runstdby_26: false |
| dmac_runstdby_27: false |
| dmac_runstdby_28: false |
| dmac_runstdby_29: false |
| dmac_runstdby_3: false |
| dmac_runstdby_30: false |
| dmac_runstdby_31: false |
| dmac_runstdby_4: false |
| dmac_runstdby_5: false |
| dmac_runstdby_6: false |
| dmac_runstdby_7: false |
| dmac_runstdby_8: false |
| dmac_runstdby_9: false |
| dmac_srcinc_0: true |
| dmac_srcinc_1: false |
| dmac_srcinc_10: false |
| dmac_srcinc_11: false |
| dmac_srcinc_12: false |
| dmac_srcinc_13: false |
| dmac_srcinc_14: false |
| dmac_srcinc_15: false |
| dmac_srcinc_16: false |
| dmac_srcinc_17: false |
| dmac_srcinc_18: false |
| dmac_srcinc_19: false |
| dmac_srcinc_2: false |
| dmac_srcinc_20: false |
| dmac_srcinc_21: false |
| dmac_srcinc_22: false |
| dmac_srcinc_23: false |
| dmac_srcinc_24: false |
| dmac_srcinc_25: false |
| dmac_srcinc_26: false |
| dmac_srcinc_27: false |
| dmac_srcinc_28: false |
| dmac_srcinc_29: false |
| dmac_srcinc_3: false |
| dmac_srcinc_30: false |
| dmac_srcinc_31: false |
| dmac_srcinc_4: false |
| dmac_srcinc_5: false |
| dmac_srcinc_6: false |
| dmac_srcinc_7: false |
| dmac_srcinc_8: false |
| dmac_srcinc_9: false |
| dmac_stepsel_0: Step size settings apply to the destination address |
| dmac_stepsel_1: Step size settings apply to the destination address |
| dmac_stepsel_10: Step size settings apply to the destination address |
| dmac_stepsel_11: Step size settings apply to the destination address |
| dmac_stepsel_12: Step size settings apply to the destination address |
| dmac_stepsel_13: Step size settings apply to the destination address |
| dmac_stepsel_14: Step size settings apply to the destination address |
| dmac_stepsel_15: Step size settings apply to the destination address |
| dmac_stepsel_16: Step size settings apply to the destination address |
| dmac_stepsel_17: Step size settings apply to the destination address |
| dmac_stepsel_18: Step size settings apply to the destination address |
| dmac_stepsel_19: Step size settings apply to the destination address |
| dmac_stepsel_2: Step size settings apply to the destination address |
| dmac_stepsel_20: Step size settings apply to the destination address |
| dmac_stepsel_21: Step size settings apply to the destination address |
| dmac_stepsel_22: Step size settings apply to the destination address |
| dmac_stepsel_23: Step size settings apply to the destination address |
| dmac_stepsel_24: Step size settings apply to the destination address |
| dmac_stepsel_25: Step size settings apply to the destination address |
| dmac_stepsel_26: Step size settings apply to the destination address |
| dmac_stepsel_27: Step size settings apply to the destination address |
| dmac_stepsel_28: Step size settings apply to the destination address |
| dmac_stepsel_29: Step size settings apply to the destination address |
| dmac_stepsel_3: Step size settings apply to the destination address |
| dmac_stepsel_30: Step size settings apply to the destination address |
| dmac_stepsel_31: Step size settings apply to the destination address |
| dmac_stepsel_4: Step size settings apply to the destination address |
| dmac_stepsel_5: Step size settings apply to the destination address |
| dmac_stepsel_6: Step size settings apply to the destination address |
| dmac_stepsel_7: Step size settings apply to the destination address |
| dmac_stepsel_8: Step size settings apply to the destination address |
| dmac_stepsel_9: Step size settings apply to the destination address |
| dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 |
| dmac_trifsrc_0: Only software/event triggers |
| dmac_trifsrc_1: Only software/event triggers |
| dmac_trifsrc_10: Only software/event triggers |
| dmac_trifsrc_11: Only software/event triggers |
| dmac_trifsrc_12: Only software/event triggers |
| dmac_trifsrc_13: Only software/event triggers |
| dmac_trifsrc_14: Only software/event triggers |
| dmac_trifsrc_15: Only software/event triggers |
| dmac_trifsrc_16: Only software/event triggers |
| dmac_trifsrc_17: Only software/event triggers |
| dmac_trifsrc_18: Only software/event triggers |
| dmac_trifsrc_19: Only software/event triggers |
| dmac_trifsrc_2: Only software/event triggers |
| dmac_trifsrc_20: Only software/event triggers |
| dmac_trifsrc_21: Only software/event triggers |
| dmac_trifsrc_22: Only software/event triggers |
| dmac_trifsrc_23: Only software/event triggers |
| dmac_trifsrc_24: Only software/event triggers |
| dmac_trifsrc_25: Only software/event triggers |
| dmac_trifsrc_26: Only software/event triggers |
| dmac_trifsrc_27: Only software/event triggers |
| dmac_trifsrc_28: Only software/event triggers |
| dmac_trifsrc_29: Only software/event triggers |
| dmac_trifsrc_3: Only software/event triggers |
| dmac_trifsrc_30: Only software/event triggers |
| dmac_trifsrc_31: Only software/event triggers |
| dmac_trifsrc_4: Only software/event triggers |
| dmac_trifsrc_5: Only software/event triggers |
| dmac_trifsrc_6: Only software/event triggers |
| dmac_trifsrc_7: Only software/event triggers |
| dmac_trifsrc_8: Only software/event triggers |
| dmac_trifsrc_9: Only software/event triggers |
| dmac_trigact_0: One trigger required for each block transfer |
| dmac_trigact_1: One trigger required for each block transfer |
| dmac_trigact_10: One trigger required for each block transfer |
| dmac_trigact_11: One trigger required for each block transfer |
| dmac_trigact_12: One trigger required for each block transfer |
| dmac_trigact_13: One trigger required for each block transfer |
| dmac_trigact_14: One trigger required for each block transfer |
| dmac_trigact_15: One trigger required for each block transfer |
| dmac_trigact_16: One trigger required for each block transfer |
| dmac_trigact_17: One trigger required for each block transfer |
| dmac_trigact_18: One trigger required for each block transfer |
| dmac_trigact_19: One trigger required for each block transfer |
| dmac_trigact_2: One trigger required for each block transfer |
| dmac_trigact_20: One trigger required for each block transfer |
| dmac_trigact_21: One trigger required for each block transfer |
| dmac_trigact_22: One trigger required for each block transfer |
| dmac_trigact_23: One trigger required for each block transfer |
| dmac_trigact_24: One trigger required for each block transfer |
| dmac_trigact_25: One trigger required for each block transfer |
| dmac_trigact_26: One trigger required for each block transfer |
| dmac_trigact_27: One trigger required for each block transfer |
| dmac_trigact_28: One trigger required for each block transfer |
| dmac_trigact_29: One trigger required for each block transfer |
| dmac_trigact_3: One trigger required for each block transfer |
| dmac_trigact_30: One trigger required for each block transfer |
| dmac_trigact_31: One trigger required for each block transfer |
| dmac_trigact_4: One trigger required for each block transfer |
| dmac_trigact_5: One trigger required for each block transfer |
| dmac_trigact_6: One trigger required for each block transfer |
| dmac_trigact_7: One trigger required for each block transfer |
| dmac_trigact_8: One trigger required for each block transfer |
| dmac_trigact_9: One trigger required for each block transfer |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: null |
| GCLK: |
| user_label: GCLK |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK |
| functionality: System |
| api: HAL:HPL:GCLK |
| configuration: |
| enable_gclk_gen_0: true |
| enable_gclk_gen_1: true |
| enable_gclk_gen_10: false |
| enable_gclk_gen_11: true |
| enable_gclk_gen_2: true |
| enable_gclk_gen_3: true |
| enable_gclk_gen_4: false |
| enable_gclk_gen_5: true |
| enable_gclk_gen_6: false |
| enable_gclk_gen_7: false |
| enable_gclk_gen_8: false |
| enable_gclk_gen_9: false |
| gclk_arch_gen_0_enable: true |
| gclk_arch_gen_0_idc: false |
| gclk_arch_gen_0_oe: false |
| gclk_arch_gen_0_oov: false |
| gclk_arch_gen_0_runstdby: false |
| gclk_arch_gen_10_enable: false |
| gclk_arch_gen_10_idc: false |
| gclk_arch_gen_10_oe: false |
| gclk_arch_gen_10_oov: false |
| gclk_arch_gen_10_runstdby: false |
| gclk_arch_gen_11_enable: true |
| gclk_arch_gen_11_idc: false |
| gclk_arch_gen_11_oe: false |
| gclk_arch_gen_11_oov: false |
| gclk_arch_gen_11_runstdby: false |
| gclk_arch_gen_1_enable: true |
| gclk_arch_gen_1_idc: false |
| gclk_arch_gen_1_oe: false |
| gclk_arch_gen_1_oov: false |
| gclk_arch_gen_1_runstdby: false |
| gclk_arch_gen_2_enable: true |
| gclk_arch_gen_2_idc: false |
| gclk_arch_gen_2_oe: false |
| gclk_arch_gen_2_oov: false |
| gclk_arch_gen_2_runstdby: false |
| gclk_arch_gen_3_enable: true |
| gclk_arch_gen_3_idc: false |
| gclk_arch_gen_3_oe: false |
| gclk_arch_gen_3_oov: false |
| gclk_arch_gen_3_runstdby: false |
| gclk_arch_gen_4_enable: false |
| gclk_arch_gen_4_idc: false |
| gclk_arch_gen_4_oe: false |
| gclk_arch_gen_4_oov: false |
| gclk_arch_gen_4_runstdby: false |
| gclk_arch_gen_5_enable: true |
| gclk_arch_gen_5_idc: false |
| gclk_arch_gen_5_oe: true |
| gclk_arch_gen_5_oov: false |
| gclk_arch_gen_5_runstdby: false |
| gclk_arch_gen_6_enable: false |
| gclk_arch_gen_6_idc: false |
| gclk_arch_gen_6_oe: false |
| gclk_arch_gen_6_oov: false |
| gclk_arch_gen_6_runstdby: false |
| gclk_arch_gen_7_enable: false |
| gclk_arch_gen_7_idc: false |
| gclk_arch_gen_7_oe: false |
| gclk_arch_gen_7_oov: false |
| gclk_arch_gen_7_runstdby: false |
| gclk_arch_gen_8_enable: false |
| gclk_arch_gen_8_idc: false |
| gclk_arch_gen_8_oe: false |
| gclk_arch_gen_8_oov: false |
| gclk_arch_gen_8_runstdby: false |
| gclk_arch_gen_9_enable: false |
| gclk_arch_gen_9_idc: false |
| gclk_arch_gen_9_oe: false |
| gclk_arch_gen_9_oov: false |
| gclk_arch_gen_9_runstdby: false |
| gclk_gen_0_div: 1 |
| gclk_gen_0_div_sel: false |
| gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) |
| gclk_gen_10_div: 1 |
| gclk_gen_10_div_sel: false |
| gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) |
| gclk_gen_11_div: 6 |
| gclk_gen_11_div_sel: false |
| gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) |
| gclk_gen_1_div: 1 |
| gclk_gen_1_div_sel: false |
| gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) |
| gclk_gen_2_div: 1 |
| gclk_gen_2_div_sel: false |
| gclk_gen_2_oscillator: Digital Phase Locked Loop (DPLL1) |
| gclk_gen_3_div: 1 |
| gclk_gen_3_div_sel: false |
| gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) |
| gclk_gen_4_div: 1 |
| gclk_gen_4_div_sel: false |
| gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) |
| gclk_gen_5_div: 5 |
| gclk_gen_5_div_sel: false |
| gclk_gen_5_oscillator: Digital Phase Locked Loop (DPLL1) |
| gclk_gen_6_div: 1 |
| gclk_gen_6_div_sel: false |
| gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) |
| gclk_gen_7_div: 1 |
| gclk_gen_7_div_sel: false |
| gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) |
| gclk_gen_8_div: 1 |
| gclk_gen_8_div_sel: false |
| gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) |
| gclk_gen_9_div: 1 |
| gclk_gen_9_div_sel: false |
| gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: null |
| MCLK: |
| user_label: MCLK |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK |
| functionality: System |
| api: HAL:HPL:MCLK |
| configuration: |
| cpu_clock_source: Generic clock generator 0 |
| cpu_div: '1' |
| enable_cpu_clock: true |
| mclk_arch_bupdiv: Divide by 8 |
| mclk_arch_hsdiv: Divide by 1 |
| mclk_arch_lpdiv: Divide by 4 |
| nvm_wait_states: '0' |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: |
| nodes: |
| - name: CPU |
| input: CPU |
| external: false |
| external_frequency: 0 |
| configuration: {} |
| OSC32KCTRL: |
| user_label: OSC32KCTRL |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL |
| functionality: System |
| api: HAL:HPL:OSC32KCTRL |
| configuration: |
| enable_osculp32k: true |
| enable_rtc_source: false |
| enable_xosc32k: true |
| osculp32k_calib: 0 |
| osculp32k_calib_enable: false |
| rtc_1khz_selection: false |
| rtc_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K) |
| xosc32k_arch_cfden: false |
| xosc32k_arch_cfdeo: false |
| xosc32k_arch_cgm: Standard mode |
| xosc32k_arch_en1k: false |
| xosc32k_arch_en32k: true |
| xosc32k_arch_enable: true |
| xosc32k_arch_ondemand: true |
| xosc32k_arch_runstdby: false |
| xosc32k_arch_startup: 62592us |
| xosc32k_arch_swben: false |
| xosc32k_arch_xtalen: true |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: null |
| OSCCTRL: |
| user_label: OSCCTRL |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL |
| functionality: System |
| api: HAL:HPL:OSCCTRL |
| configuration: |
| dfll_arch_bplckc: false |
| dfll_arch_calibration: false |
| dfll_arch_ccdis: true |
| dfll_arch_coarse: 31 |
| dfll_arch_cstep: 1 |
| dfll_arch_enable: true |
| dfll_arch_fine: 128 |
| dfll_arch_fstep: 1 |
| dfll_arch_llaw: false |
| dfll_arch_ondemand: false |
| dfll_arch_qldis: false |
| dfll_arch_runstdby: false |
| dfll_arch_stable: false |
| dfll_arch_usbcrm: true |
| dfll_arch_waitlock: false |
| dfll_mode: Closed Loop Mode |
| dfll_mul: 48000 |
| dfll_ref_clock: Generic clock generator 3 |
| enable_dfll: true |
| enable_fdpll0: true |
| enable_fdpll1: true |
| enable_xosc0: false |
| enable_xosc1: true |
| fdpll0_arch_dcoen: false |
| fdpll0_arch_enable: true |
| fdpll0_arch_filter: 0 |
| fdpll0_arch_lbypass: false |
| fdpll0_arch_ltime: No time-out, automatic lock |
| fdpll0_arch_ondemand: false |
| fdpll0_arch_refclk: XOSC1 clock reference |
| fdpll0_arch_runstdby: false |
| fdpll0_arch_wuf: false |
| fdpll0_clock_dcofilter: 0 |
| fdpll0_clock_div: 2 |
| fdpll0_ldr: 59 |
| fdpll0_ldrfrac: 0 |
| fdpll0_ref_clock: Generic clock generator 11 |
| fdpll1_arch_dcoen: false |
| fdpll1_arch_enable: true |
| fdpll1_arch_filter: 0 |
| fdpll1_arch_lbypass: false |
| fdpll1_arch_ltime: No time-out, automatic lock |
| fdpll1_arch_ondemand: false |
| fdpll1_arch_refclk: XOSC1 clock reference |
| fdpll1_arch_runstdby: false |
| fdpll1_arch_wuf: false |
| fdpll1_clock_dcofilter: 0 |
| fdpll1_clock_div: 2 |
| fdpll1_ldr: 49 |
| fdpll1_ldrfrac: 0 |
| fdpll1_ref_clock: Generic clock generator 11 |
| xosc0_arch_cfden: false |
| xosc0_arch_enable: false |
| xosc0_arch_enalc: false |
| xosc0_arch_lowbufgain: false |
| xosc0_arch_ondemand: false |
| xosc0_arch_runstdby: false |
| xosc0_arch_startup: 31us |
| xosc0_arch_swben: false |
| xosc0_arch_xtalen: false |
| xosc0_frequency: 12000000 |
| xosc1_arch_cfden: false |
| xosc1_arch_enable: true |
| xosc1_arch_enalc: false |
| xosc1_arch_lowbufgain: false |
| xosc1_arch_ondemand: false |
| xosc1_arch_runstdby: false |
| xosc1_arch_startup: 31us |
| xosc1_arch_swben: false |
| xosc1_arch_xtalen: true |
| xosc1_frequency: 12000000 |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: null |
| PORT: |
| user_label: PORT |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::PORT::driver_config_definition::PORT::HAL:HPL:PORT |
| functionality: System |
| api: HAL:HPL:PORT |
| configuration: |
| enable_port_input_event_0: false |
| enable_port_input_event_1: false |
| enable_port_input_event_2: false |
| enable_port_input_event_3: false |
| porta_event_action_0: Output register of pin will be set to level of event |
| porta_event_action_1: Output register of pin will be set to level of event |
| porta_event_action_2: Output register of pin will be set to level of event |
| porta_event_action_3: Output register of pin will be set to level of event |
| porta_event_pin_identifier_0: 0 |
| porta_event_pin_identifier_1: 0 |
| porta_event_pin_identifier_2: 0 |
| porta_event_pin_identifier_3: 0 |
| porta_input_event_enable_0: false |
| porta_input_event_enable_1: false |
| porta_input_event_enable_2: false |
| porta_input_event_enable_3: false |
| portb_event_action_0: Output register of pin will be set to level of event |
| portb_event_action_1: Output register of pin will be set to level of event |
| portb_event_action_2: Output register of pin will be set to level of event |
| portb_event_action_3: Output register of pin will be set to level of event |
| portb_event_pin_identifier_0: 0 |
| portb_event_pin_identifier_1: 0 |
| portb_event_pin_identifier_2: 0 |
| portb_event_pin_identifier_3: 0 |
| portb_input_event_enable_0: false |
| portb_input_event_enable_1: false |
| portb_input_event_enable_2: false |
| portb_input_event_enable_3: false |
| portc_event_action_0: Output register of pin will be set to level of event |
| portc_event_action_1: Output register of pin will be set to level of event |
| portc_event_action_2: Output register of pin will be set to level of event |
| portc_event_action_3: Output register of pin will be set to level of event |
| portc_event_pin_identifier_0: 0 |
| portc_event_pin_identifier_1: 0 |
| portc_event_pin_identifier_2: 0 |
| portc_event_pin_identifier_3: 0 |
| portc_input_event_enable_0: false |
| portc_input_event_enable_1: false |
| portc_input_event_enable_2: false |
| portc_input_event_enable_3: false |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: null |
| RAMECC: |
| user_label: RAMECC |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC |
| functionality: System |
| api: HAL:HPL:RAMECC |
| configuration: {} |
| optional_signals: [] |
| variant: null |
| clocks: |
| domain_group: null |
| SIM0: |
| user_label: SIM0 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM0::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async |
| functionality: USART |
| api: HAL:Driver:USART_Async |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_ibon: false |
| usart_arch_runstdby: false |
| usart_arch_sfde: false |
| usart_baud_rate: 9600 |
| usart_character_size: 8 bits |
| usart_dsnack: The successive receive NACK is disable. |
| usart_gtime: 2-bit times |
| usart_inack: NACK is transmitted when a parity error is received. |
| usart_inverse_enabled: false |
| usart_iso7816_type: T=0 |
| usart_maxiter: 7 |
| usart_parity: Even parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=2, RXPO=0 |
| required_signals: |
| - name: SERCOM0/PAD/0 |
| pad: PA04 |
| label: RX/TX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| SIM1: |
| user_label: SIM1 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM1::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async |
| functionality: USART |
| api: HAL:Driver:USART_Async |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_ibon: false |
| usart_arch_runstdby: false |
| usart_arch_sfde: false |
| usart_baud_rate: 9600 |
| usart_character_size: 8 bits |
| usart_dsnack: The successive receive NACK is disable. |
| usart_gtime: 2-bit times |
| usart_inack: NACK is transmitted when a parity error is received. |
| usart_inverse_enabled: false |
| usart_iso7816_type: T=0 |
| usart_maxiter: 7 |
| usart_parity: Even parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=2, RXPO=0 |
| required_signals: |
| - name: SERCOM1/PAD/0 |
| pad: PA16 |
| label: RX/TX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| SIM2: |
| user_label: SIM2 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM2::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async |
| functionality: USART |
| api: HAL:Driver:USART_Async |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_ibon: false |
| usart_arch_runstdby: false |
| usart_arch_sfde: false |
| usart_baud_rate: 9600 |
| usart_character_size: 8 bits |
| usart_dsnack: The successive receive NACK is disable. |
| usart_gtime: 2-bit times |
| usart_inack: NACK is transmitted when a parity error is received. |
| usart_inverse_enabled: false |
| usart_iso7816_type: T=0 |
| usart_maxiter: 7 |
| usart_parity: Even parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=2, RXPO=0 |
| required_signals: |
| - name: SERCOM2/PAD/0 |
| pad: PA09 |
| label: RX/TX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| SIM3: |
| user_label: SIM3 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM3::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async |
| functionality: USART |
| api: HAL:Driver:USART_Async |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_ibon: false |
| usart_arch_runstdby: false |
| usart_arch_sfde: false |
| usart_baud_rate: 9600 |
| usart_character_size: 8 bits |
| usart_dsnack: The successive receive NACK is disable. |
| usart_gtime: 2-bit times |
| usart_inack: NACK is transmitted when a parity error is received. |
| usart_inverse_enabled: false |
| usart_iso7816_type: T=0 |
| usart_maxiter: 7 |
| usart_parity: Even parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=2, RXPO=0 |
| required_signals: |
| - name: SERCOM3/PAD/0 |
| pad: PB20 |
| label: RX/TX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| SIM4: |
| user_label: SIM4 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM4::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async |
| functionality: USART |
| api: HAL:Driver:USART_Async |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_ibon: false |
| usart_arch_runstdby: false |
| usart_arch_sfde: false |
| usart_baud_rate: 9600 |
| usart_character_size: 8 bits |
| usart_dsnack: The successive receive NACK is disable. |
| usart_gtime: 2-bit times |
| usart_inack: NACK is transmitted when a parity error is received. |
| usart_inverse_enabled: false |
| usart_iso7816_type: T=0 |
| usart_maxiter: 7 |
| usart_parity: Even parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=2, RXPO=0 |
| required_signals: |
| - name: SERCOM4/PAD/0 |
| pad: PB08 |
| label: RX/TX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| SIM5: |
| user_label: SIM5 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM5::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async |
| functionality: USART |
| api: HAL:Driver:USART_Async |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_ibon: false |
| usart_arch_runstdby: false |
| usart_arch_sfde: false |
| usart_baud_rate: 9600 |
| usart_character_size: 8 bits |
| usart_dsnack: The successive receive NACK is disable. |
| usart_gtime: 2-bit times |
| usart_inack: NACK is transmitted when a parity error is received. |
| usart_inverse_enabled: false |
| usart_iso7816_type: T=0 |
| usart_maxiter: 7 |
| usart_parity: Even parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=2, RXPO=0 |
| required_signals: |
| - name: SERCOM5/PAD/0 |
| pad: PB16 |
| label: RX/TX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| SIM6: |
| user_label: SIM6 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM6::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async |
| functionality: USART |
| api: HAL:Driver:USART_Async |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_ibon: false |
| usart_arch_runstdby: false |
| usart_arch_sfde: false |
| usart_baud_rate: 9600 |
| usart_character_size: 8 bits |
| usart_dsnack: The successive receive NACK is disable. |
| usart_gtime: 2-bit times |
| usart_inack: NACK is transmitted when a parity error is received. |
| usart_inverse_enabled: false |
| usart_iso7816_type: T=0 |
| usart_maxiter: 7 |
| usart_parity: Even parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=2, RXPO=0 |
| required_signals: |
| - name: SERCOM6/PAD/0 |
| pad: PC16 |
| label: RX/TX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| UART_debug: |
| user_label: UART_debug |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM7::driver_config_definition::UART::HAL:Driver:USART.Sync |
| functionality: USART |
| api: HAL:Driver:USART_Sync |
| configuration: |
| usart_advanced: false |
| usart_arch_clock_mode: USART with internal clock |
| usart_arch_cloden: false |
| usart_arch_dbgstop: Keep running |
| usart_arch_dord: LSB is transmitted first |
| usart_arch_enc: No encoding |
| usart_arch_fractional: 0 |
| usart_arch_ibon: false |
| usart_arch_lin_slave_enable: Disable |
| usart_arch_runstdby: false |
| usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) |
| usart_arch_sampr: 16x arithmetic |
| usart_arch_sfde: false |
| usart_baud_rate: 921600 |
| usart_character_size: 8 bits |
| usart_parity: No parity |
| usart_rx_enable: true |
| usart_stop_bit: One stop bit |
| usart_tx_enable: true |
| optional_signals: [] |
| variant: |
| specification: TXPO=0, RXPO=1, CMODE=0 |
| required_signals: |
| - name: SERCOM7/PAD/0 |
| pad: PB30 |
| label: TX |
| - name: SERCOM7/PAD/1 |
| pad: PB31 |
| label: RX |
| clocks: |
| domain_group: |
| nodes: |
| - name: Core |
| input: Generic clock generator 2 |
| external: false |
| external_frequency: 0 |
| - name: Slow |
| input: Generic clock generator 3 |
| external: false |
| external_frequency: 0 |
| configuration: |
| core_gclk_selection: Generic clock generator 2 |
| slow_gclk_selection: Generic clock generator 3 |
| USB_DEVICE_INSTANCE: |
| user_label: USB_DEVICE_INSTANCE |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device |
| functionality: USB |
| api: HAL:Driver:USB_Device |
| configuration: |
| usb_arch_ep0_cache: Cached by 64 bytes buffer |
| usb_arch_ep1_cache: Cached by 64 bytes buffer |
| usb_arch_ep2_cache: Cached by 64 bytes buffer |
| usb_arch_ep3_cache: Cached by 64 bytes buffer |
| usb_arch_ep4_cache: Cached by 64 bytes buffer |
| usb_arch_ep5_cache: Cached by 64 bytes buffer |
| usb_arch_ep6_cache: Cached by 64 bytes buffer |
| usb_arch_ep7_cache: Cached by 64 bytes buffer |
| usb_ep1_I_CACHE: No cache |
| usb_ep2_I_CACHE: No cache |
| usb_ep3_I_CACHE: No cache |
| usb_ep4_I_CACHE: No cache |
| usb_ep5_I_CACHE: No cache |
| usb_ep6_I_CACHE: No cache |
| usb_ep7_I_CACHE: No cache |
| usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02) |
| usbd_arch_speed: Full speed |
| usbd_num_ep_sp: 4 (EP0 + 3 endpoints) |
| optional_signals: [] |
| variant: |
| specification: default |
| required_signals: |
| - name: USB/DM |
| pad: PA24 |
| label: Data- |
| - name: USB/DP |
| pad: PA25 |
| label: Data+ |
| clocks: |
| domain_group: |
| nodes: |
| - name: USB |
| input: Generic clock generator 1 |
| external: false |
| external_frequency: 0 |
| configuration: |
| usb_gclk_selection: Generic clock generator 1 |
| pads: |
| SIM0_INT: |
| name: PC00 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC00 |
| mode: Digital input |
| user_label: SIM0_INT |
| configuration: null |
| SIM1_INT: |
| name: PC01 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC01 |
| mode: Digital input |
| user_label: SIM1_INT |
| configuration: null |
| SIM2_INT: |
| name: PC02 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC02 |
| mode: Digital input |
| user_label: SIM2_INT |
| configuration: null |
| SIM3_INT: |
| name: PC03 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC03 |
| mode: Digital input |
| user_label: SIM3_INT |
| configuration: null |
| SIM4_INT: |
| name: PA02 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA02 |
| mode: Digital input |
| user_label: SIM4_INT |
| configuration: null |
| SIM5_INT: |
| name: PA03 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA03 |
| mode: Digital input |
| user_label: SIM5_INT |
| configuration: null |
| SIM6_INT: |
| name: PB04 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB04 |
| mode: Digital input |
| user_label: SIM6_INT |
| configuration: null |
| SIM7_INT: |
| name: PB05 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB05 |
| mode: Digital input |
| user_label: SIM7_INT |
| configuration: null |
| SCL3: |
| name: PB06 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB06 |
| mode: Digital output |
| user_label: SCL3 |
| configuration: null |
| SDA3: |
| name: PB07 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB07 |
| mode: Digital output |
| user_label: SDA3 |
| configuration: null |
| SIM4_IO: |
| name: PB08 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB08 |
| mode: Peripheral IO |
| user_label: SIM4_IO |
| configuration: null |
| SIM0_IO: |
| name: PA04 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA04 |
| mode: Peripheral IO |
| user_label: SIM0_IO |
| configuration: null |
| SIM2_IO: |
| name: PA09 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA09 |
| mode: Peripheral IO |
| user_label: SIM2_IO |
| configuration: null |
| SIMCLK_20MHZ: |
| name: PA11 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA11 |
| mode: Advanced |
| user_label: SIMCLK_20MHZ |
| configuration: |
| pad_direction: Out |
| pad_function: M |
| pad_initial_level: Low |
| pad_pull_config: 'Off' |
| SCL1: |
| name: PB14 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB14 |
| mode: Digital output |
| user_label: SCL1 |
| configuration: null |
| SDA1: |
| name: PB15 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB15 |
| mode: Digital output |
| user_label: SDA1 |
| configuration: null |
| SWITCH: |
| name: PC14 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC14 |
| mode: Digital input |
| user_label: SWITCH |
| configuration: null |
| MUX_STAT: |
| name: PC15 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC15 |
| mode: Digital input |
| user_label: MUX_STAT |
| configuration: null |
| SIM1_IO: |
| name: PA16 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA16 |
| mode: Peripheral IO |
| user_label: SIM1_IO |
| configuration: null |
| SIM6_IO: |
| name: PC16 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC16 |
| mode: Peripheral IO |
| user_label: SIM6_IO |
| configuration: null |
| SIM5_IO: |
| name: PB16 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB16 |
| mode: Peripheral IO |
| user_label: SIM5_IO |
| configuration: null |
| SIM3_IO: |
| name: PB20 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB20 |
| mode: Peripheral IO |
| user_label: SIM3_IO |
| configuration: null |
| VB0: |
| name: PA20 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA20 |
| mode: Digital input |
| user_label: VB0 |
| configuration: null |
| VB1: |
| name: PA21 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA21 |
| mode: Digital input |
| user_label: VB1 |
| configuration: null |
| VB2: |
| name: PA22 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA22 |
| mode: Digital input |
| user_label: VB2 |
| configuration: null |
| VB3: |
| name: PA23 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA23 |
| mode: Digital input |
| user_label: VB3 |
| configuration: null |
| USBUP_D_N: |
| name: PA24 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA24 |
| mode: Advanced |
| user_label: USBUP_D_N |
| configuration: null |
| USBUP_D_P: |
| name: PA25 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA25 |
| mode: Advanced |
| user_label: USBUP_D_P |
| configuration: null |
| USER_LED: |
| name: PC26 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC26 |
| mode: Digital output |
| user_label: USER_LED |
| configuration: null |
| SCL4: |
| name: PC27 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC27 |
| mode: Digital output |
| user_label: SCL4 |
| configuration: null |
| SDA4: |
| name: PC28 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC28 |
| mode: Digital output |
| user_label: SDA4 |
| configuration: null |
| UART_TX: |
| name: PB30 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB30 |
| mode: Peripheral IO |
| user_label: UART_TX |
| configuration: null |
| UART_RX: |
| name: PB31 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB31 |
| mode: Peripheral IO |
| user_label: UART_RX |
| configuration: null |
| SCL2: |
| name: PB02 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB02 |
| mode: Digital output |
| user_label: SCL2 |
| configuration: null |
| SDA2: |
| name: PB03 |
| definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB03 |
| mode: Digital output |
| user_label: SDA2 |
| configuration: null |
| toolchain_options: [] |