Harald Welte | 9fe1f9f | 2018-11-29 13:47:39 +0100 | [diff] [blame] | 1 | === start: test_crc === |
| 2 | iuup_initialization: Header CRC = 0x37 |
| 3 | iuup_initialization: Payload CRC = 0x399 |
| 4 | iuup_initialization_ack: Header CRC = 0x09 |
| 5 | iuup_initialization_ack: Payload CRC = 0x399 |
| 6 | === end: test_crc === |
| 7 | sys={0.000000}, clock_override_set |
| 8 | _tinit_timeout_retrans_transport_prim_cb() |
| 9 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 10 | sys={1.000000}, clock_override_set |
| 11 | _tinit_timeout_retrans_transport_prim_cb() |
| 12 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 13 | sys={2.000000}, clock_override_set |
| 14 | _tinit_timeout_retrans_transport_prim_cb() |
| 15 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 16 | sys={3.000000}, clock_override_set |
| 17 | _tinit_timeout_retrans_transport_prim_cb() |
| 18 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 19 | sys={4.000000}, clock_override_set |
| 20 | _tinit_timeout_retrans_user_prim_cb() |
| 21 | sys={0.000000}, clock_override_set |
| 22 | _init_nack_retrans_transport_prim_cb() |
| 23 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 24 | _init_nack_retrans_transport_prim_cb() |
| 25 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 26 | _init_nack_retrans_transport_prim_cb() |
| 27 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 28 | _init_nack_retrans_transport_prim_cb() |
| 29 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 30 | _init_nack_retrans_user_prim_cb() |
| 31 | sys={0.000000}, clock_override_set |
| 32 | _init_ack_transport_prim_cb() |
| 33 | Transport: DL len=22: e0 00 df 99 16 00 51 67 3c 01 27 00 00 82 00 00 00 17 10 00 01 00 |
| 34 | _init_ack_user_prim_cb() |
| 35 | User: UL len=31: 08 55 6d 94 4c 71 a1 a0 81 e7 ea d2 04 24 44 80 00 0e cd 82 b8 11 18 00 00 97 c4 79 4e 77 40 |
| 36 | _init_ack_transport_prim_cb() |
| 37 | Transport: DL len=35: 01 00 e3 ff 08 55 6d 94 4c 71 a1 a0 81 e7 ea d2 04 24 44 80 00 0e cd 82 b8 11 18 00 00 97 c4 79 4e 77 40 |
| 38 | sys={0.000000}, clock_override_set |
| 39 | _passive_init_transport_prim_cb() |
| 40 | Transport: DL len=4: e4 00 24 00 |
| 41 | _passive_init_user_prim_cb() |
| 42 | User: UL len=31: 08 55 6d 94 4c 71 a1 a0 81 e7 ea d2 04 24 44 80 00 0e cd 82 b8 11 18 00 00 97 c4 79 4e 77 40 |
| 43 | _passive_init_transport_prim_cb() |
| 44 | Transport: DL len=35: 01 00 e3 ff 08 55 6d 94 4c 71 a1 a0 81 e7 ea d2 04 24 44 80 00 0e cd 82 b8 11 18 00 00 97 c4 79 4e 77 40 |
| 45 | OK. |