fix various typos all over the code
Change-Id: Ic8392a951bf94f67b51e35bed95d0e856f7a9250
diff --git a/docs/library.rst b/docs/library.rst
index e2e24a7..f531ec5 100644
--- a/docs/library.rst
+++ b/docs/library.rst
@@ -33,7 +33,7 @@
calypso / OsmocomBB transport
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-This allows the use of the SIM slot of an an OsmocomBB compatible phone with the TI Calypso chipset,
+This allows the use of the SIM slot of an OsmocomBB compatible phone with the TI Calypso chipset,
using the L1CTL interface to talk to the layer1.bin firmware on the phone.
.. automodule:: pySim.transport.calypso
@@ -67,7 +67,7 @@
This transport implements interfacing smart cards via
very simplistic UART readers. These readers basically
wire together the Rx+Tx pins of a RS232 UART, provide
-a fixed crystal oscilator for clock, and operate the UART
+a fixed crystal oscillator for clock, and operate the UART
at 9600 bps. These readers are sometimes called `Phoenix`.
.. automodule:: pySim.transport.serial