msc: expect TC_attached_imsi_lu_unknown_tmsi to pass
The "VLR evil twin" problem has been fixed in osmo-msc.git:
https://gerrit.osmocom.org/c/osmo-msc/+/36452
https://cgit.osmocom.org/osmo-msc/commit/?id=2fd69e15d36d5a8e87029741ad66632c57d24cd4
And the testcase is finally passing now.
Change-Id: I57a277fa7e6e0d10ff38e23f416ace87472e6602
Related: OS#4721
diff --git a/msc/expected-results.xml b/msc/expected-results.xml
index b6e0bb2..aad96a7 100644
--- a/msc/expected-results.xml
+++ b/msc/expected-results.xml
@@ -27,12 +27,7 @@
<testcase classname='MSC_Tests' name='TC_lu_disconnect' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_lu_by_imei' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_lu_by_tmsi_noauth_unknown' time='MASKED'/>
- <testcase classname='MSC_Tests' name='TC_attached_imsi_lu_unknown_tmsi' time='MASKED'>
- <failure type='fail-verdict'>Expected LU ACK, but received REJ
- MSC_Tests.ttcn:MASKED MSC_Tests control part
- MSC_Tests.ttcn:MASKED TC_attached_imsi_lu_unknown_tmsi testcase
- </failure>
- </testcase>
+ <testcase classname='MSC_Tests' name='TC_attached_imsi_lu_unknown_tmsi' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_imsi_detach_by_imsi' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_imsi_detach_by_tmsi' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_imsi_detach_by_imei' time='MASKED'/>