BTS_Tests: increate Tguard to 30.0s for TC_rsl_ms_pwr_dyn_up
A comment in f_TC_rsl_ms_pwr_dyn_up() states:
> By default, the MS power loop gets triggered every 4th SACCH block (1.92s).
> We need 9 * 4 dB steps to get from 0 dBm to 33 dBm, so 9 * 1.92s total.
> Add an extra offset to avoid race conditions: +1.92s.
so the alt statement is expected to block for 19.2s, while the guard
timer is set to 20.0s by default. This is not enough, given that
f_TC_rsl_ms_pwr_dyn_up() also needs to wait for the first SACCH block
before entering the alt statement.
Let's give it more time to run in order to avoid sporadic failures.
Change-Id: Ib7de8383c95ac9e00560f786ec4c56f79f7d81bc
Related: OS#5635
1 file changed