update expected-results.xml
Change-Id: Ib4399aa488afd917e3eda5e79d56ea3797ef7c78
diff --git a/pcu/expected-results.xml b/pcu/expected-results.xml
index ce12807..11906d9 100644
--- a/pcu/expected-results.xml
+++ b/pcu/expected-results.xml
@@ -1,13 +1,11 @@
<?xml version="1.0"?>
-<testsuite name='Titan' tests='46' failures='2' errors='0' skipped='0' inconc='0' time='MASKED'>
+<testsuite name='Titan' tests='70' failures='3' errors='1' skipped='0' inconc='0' time='MASKED'>
<testcase classname='PCU_Tests' name='TC_pcuif_suspend' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_pcuif_suspend_active_tbf' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ta_ptcch_idle' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ta_rach_imm_ass' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ta_idle_dl_tbf_ass' time='MASKED'>
- <failure type='fail-verdict'>Timing Advance value doesn't match
- PCU_Tests.ttcn:MASKED PCU_Tests control part
- PCU_Tests.ttcn:MASKED TC_ta_idle_dl_tbf_ass testcase
- </failure>
+ <error type='DTE'></error>
</testcase>
<testcase classname='PCU_Tests' name='TC_ta_ptcch_ul_multi_tbf' time='MASKED'>
<failure type='fail-verdict'>Failed to match Timing Advance Index for #0
@@ -18,6 +16,13 @@
<testcase classname='PCU_Tests' name='TC_cs_lqual_ul_tbf' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_cs_initial_ul' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_cs_max_ul' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_cs_initial_dl' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_cs_max_dl' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_dl_cs1_to_cs4' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_mcs_initial_ul' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_mcs_max_ul' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_mcs_initial_dl' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_mcs_max_dl' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_t3169' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_t3193' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_countdown_procedure' time='MASKED'/>
@@ -39,8 +44,13 @@
<testcase classname='PCU_Tests' name='TC_paging_ps_from_sgsn_sign_ptmsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_ps_from_sgsn_sign' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_ps_from_sgsn_ptp' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_paging_cs_multi_ms_imsi_tmsi' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_paging_cs_multi_ms_imsi' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_paging_cs_multi_ms_tmsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_bssgp_dl_unitdata_with_valid_imsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_bssgp_dl_unitdata_with_invalid_imsi' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_dl_gprs_data_no_llc_ui_dummy' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_dl_egprs_data_no_llc_ui_dummy' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_signalling' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_one_phase' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_two_phase' time='MASKED'/>
@@ -48,6 +58,27 @@
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_reject_emergency' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_reject_exhaustion' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mo_ping_pong_with_ul_racap_egprs_only' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_pcuif_fh_imm_ass_ul_egprs' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_pcuif_fh_imm_ass_ul' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_pcuif_fh_imm_ass_dl' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_pcuif_fh_pkt_ass_ul' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_pcuif_fh_pkt_ass_dl' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_multitrx_multims_alloc' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_dl_multislot_tbf_ms_class_from_sgsn' time='MASKED'>
+ <failure type='fail-verdict'>Expected 8 PDCH slots allocated but got 4
+ PCU_Tests.ttcn:MASKED PCU_Tests control part
+ PCU_Tests.ttcn:MASKED TC_dl_multislot_tbf_ms_class_from_sgsn testcase
+ </failure>
+ </testcase>
+ <testcase classname='PCU_Tests' name='TC_dl_multislot_tbf_ms_class_from_2phase' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_ul_multislot_tbf_ms_class_from_2phase' time='MASKED'>
+ <failure type='fail-verdict'>Expected 8 PDCH slot allocated but got 1
+ PCU_Tests.ttcn:MASKED PCU_Tests control part
+ PCU_Tests.ttcn:MASKED TC_ul_multislot_tbf_ms_class_from_2phase testcase
+ </failure>
+ </testcase>
+ <testcase classname='PCU_Tests' name='TC_multiplex_dl_gprs_egprs' time='MASKED'/>
+ <testcase classname='PCU_Tests' name='TC_pcuif_info_ind_subsequent' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_reset' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_reset_retrans' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_alive' time='MASKED'/>