1. 26ca5bc uhd: remove external clock polarity setting by kurtis.heimerl · 13 years ago
  2. d3e2590 uhd: verify setting of master clock rate by kurtis.heimerl · 13 years ago
  3. 2b28c69 uhd: remove uhd type argument by kurtis.heimerl · 13 years ago
  4. 495d3c8 uhd: flush receive buffer should return true on timeout by kurtis.heimerl · 13 years ago
  5. 6cb348b uhd: log asynchronous errors as errors by kurtis.heimerl · 13 years ago
  6. 7ac54b1 transceiver: simplify transmit power control by kurtis.heimerl · 13 years ago
  7. d4be074 uhd: reorganize error handling, exit when non-recoverable by kurtis.heimerl · 13 years ago
  8. 13074c9 uhd: enable automatic alignment updates by kurtis.heimerl · 13 years ago
  9. 187b03d uhd: cleanup startup timestamp alignment by kurtis.heimerl · 13 years ago
  10. 6829210 uhd: rework handling of timestamp errors by kurtis.heimerl · 13 years ago
  11. c7cb817 uhd: fix timestamp conversion bug on 32-bit architectures by kurtis.heimerl · 13 years ago
  12. a14d4be uhd: reset sample clock when time goes non-monotonic by kurtis.heimerl · 13 years ago
  13. 24481de uhd: move static functions into the uhd_device class by kurtis.heimerl · 13 years ago
  14. 02d0405 uhd: set and shadow settings through interface by kurtis.heimerl · 13 years ago
  15. 9933644 uhd: set receive gain during initialization by kurtis.heimerl · 13 years ago
  16. be6abe1 uhd: set hardware side delay offset for e100 by kurtis.heimerl · 13 years ago
  17. 3cc1da9 uhd: log useful information on monotonic errors by kurtis.heimerl · 13 years ago
  18. c491997 uhd: only the E100 supports FPGA timestamps and adjustable clock rate by kurtis.heimerl · 13 years ago
  19. 33f748f uhd: flush initial receive samples by kurtis.heimerl · 13 years ago
  20. 965e757 uhd: add 52 MHz transceiver support by kurtis.heimerl · 13 years ago