Reverting r2342
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2424 19bc5d8c-e614-43d4-8b26-e1612bc8e597
diff --git a/Transceiver52M/USRPDevice.cpp b/Transceiver52M/USRPDevice.cpp
index 89e967e..7644cc7 100644
--- a/Transceiver52M/USRPDevice.cpp
+++ b/Transceiver52M/USRPDevice.cpp
@@ -133,17 +133,17 @@
if (R==0) return false;
writeLock.lock();
- m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
+ m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
write_it((R & ~0x3) | 1));
- m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
+ m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
write_it((control & ~0x3) | 0));
usleep(10000);
- m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
+ m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
write_it((N & ~0x3) | 2));
writeLock.unlock();
- if (m_uRx->read_io(0) & PLL_LOCK_DETECT) return true;
- if (m_uRx->read_io(0) & PLL_LOCK_DETECT) return true;
+ if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
+ if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
return false;
}
@@ -197,9 +197,6 @@
m_uRx.reset();
return false;
}
- m_uRx->_write_oe(0,0,0xffff);
- m_uRx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
- m_uRx->write_io(0,(POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
}
try {
@@ -216,10 +213,6 @@
return false;
}
- m_uTx->_write_oe(0,0,0xffff);
- m_uTx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
- m_uTx->write_io(0,(POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
-
if (m_uTx->fpga_master_clock_freq() != masterClockRate)
{
LOG(ALERT) << "WRONG FPGA clock freq = " << m_uTx->fpga_master_clock_freq()
@@ -255,13 +248,9 @@
writeLock.lock();
// power up and configure daughterboards
m_uTx->_write_oe(0,0,0xffff);
-
m_uTx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
- //m_uTx->write_io(0,(POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
- //m_uTx->write_io(0,ENABLE,(RX_TXN | ENABLE));
- //m_uTx->write_io(0,(RX_TXN | ENABLE), (RX_TXN | ENABLE));//only for litie
- m_uTx->write_io(0,ENABLE,(POWER_UP|RX_TXN|ENABLE)); /* POWER_UP inverted */
-
+ m_uTx->write_io(0,(~POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
+ m_uTx->write_io(0,ENABLE,(RX_TXN | ENABLE));
m_uTx->_write_fpga_reg(FR_ATR_MASK_0 ,0);//RX_TXN|ENABLE);
m_uTx->_write_fpga_reg(FR_ATR_TXVAL_0,0);//,0 |ENABLE);
m_uTx->_write_fpga_reg(FR_ATR_RXVAL_0,0);//,RX_TXN|0);
@@ -275,20 +264,17 @@
if (!skipRx) {
writeLock.lock();
- m_uRx->_write_fpga_reg(FR_ATR_MASK_0 + 1*3,0);
- m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 1*3,0);
- m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 1*3,0);
- m_uRx->_write_fpga_reg(41,0);
+ m_uRx->_write_fpga_reg(FR_ATR_MASK_0 + 3*3,0);
+ m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 3*3,0);
+ m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 3*3,0);
m_uRx->_write_fpga_reg(43,0);
- m_uRx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
- m_uRx->write_io(0,(POWER_UP|RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE));
+ m_uRx->_write_oe(1,(POWER_UP|RX_TXN|ENABLE), 0xffff);
+ m_uRx->write_io(1,(~POWER_UP|RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE));
//m_uRx->write_io(1,0,RX2_RX1N); // using Tx/Rx/
- m_uRx->write_io(0,RX2_RX1N,RX2_RX1N); // using Rx2
- m_uRx->set_adc_buffer_bypass(0,true);
- m_uRx->set_adc_buffer_bypass(1,true);
- m_uRx->set_pga(0,m_uRx->pga_max()); // should be 20dB
- m_uRx->set_pga(1,m_uRx->pga_max());
- m_uRx->set_mux(0x00000010);
+ m_uRx->write_io(1,RX2_RX1N,RX2_RX1N); // using Rx2
+ m_uRx->set_adc_buffer_bypass(2,true);
+ m_uRx->set_adc_buffer_bypass(3,true);
+ m_uRx->set_mux(0x00000032);
writeLock.unlock();
// FIXME -- This should be configurable.
setRxGain(47); //maxRxGain());
@@ -325,7 +311,7 @@
// power down
m_uTx->write_io(0,(~POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
- m_uRx->write_io(0,~POWER_UP,(POWER_UP|ENABLE));
+ m_uRx->write_io(1,~POWER_UP,(POWER_UP|ENABLE));
delete[] currData;
@@ -365,15 +351,15 @@
double rfMax = 70.0;
if (dB > rfMax) {
- m_uRx->set_pga(0,dB-rfMax);
- m_uRx->set_pga(1,dB-rfMax);
+ m_uRx->set_pga(2,dB-rfMax);
+ m_uRx->set_pga(3,dB-rfMax);
dB = rfMax;
}
else {
- m_uRx->set_pga(0,0);
- m_uRx->set_pga(1,0);
+ m_uRx->set_pga(2,0);
+ m_uRx->set_pga(3,0);
}
- m_uRx->write_aux_dac(0,0,
+ m_uRx->write_aux_dac(1,0,
(int) ceil((1.2 + 0.02 - (dB/rfMax))*4096.0/3.3));
LOG(DEBUG) << "Setting DAC voltage to " << (1.2+0.02 - (dB/rfMax)) << " " << (int) ceil((1.2 + 0.02 - (dB/rfMax))*4096.0/3.3);
@@ -552,7 +538,7 @@
#ifndef SWLOOPBACK
if (!m_uTx) return 0;
- static uint32_t outData[128*200];
+ static uint32_t outData[128*20];
for (int i = 0; i < len*2; i++) {
buf[i] = host_to_usrp_short(buf[i]);
@@ -603,7 +589,7 @@
#ifndef SWLOOPBACK
short data[] = {0x00,0x02,0x00,0x00};
uint32_t *wordPtr = (uint32_t *) data;
- //*wordPtr = host_to_usrp_u32(*wordPtr);
+ *wordPtr = host_to_usrp_u32(*wordPtr);
bool tmpUnderrun;
if (writeSamples((short *) data,1,&tmpUnderrun,timestamp & 0x0ffffffffll,true)) {
pingTimestamp = timestamp;
@@ -622,7 +608,6 @@
if (!tx_setFreq(wFreq+1*LO_OFFSET,&actFreq)) return false;
bool retVal = m_uTx->set_tx_freq(0,(wFreq-actFreq));
LOG(INFO) << "set TX: " << wFreq-actFreq << " actual TX: " << m_uTx->tx_freq(0);
- //m_uTx->write_io(0,RX_TXN,RX_TXN);
return retVal;
};
@@ -637,7 +622,6 @@
if (!rx_setFreq(wFreq-2*LO_OFFSET,&actFreq)) return false;
bool retVal = m_uRx->set_rx_freq(0,(wFreq-actFreq));
LOG(DEBUG) << "set RX: " << wFreq-actFreq << " actual RX: " << m_uRx->rx_freq(0);
- //m_uRx->write_io(0,RX_TXN,RX_TXN);
return retVal;
};
diff --git a/Transceiver52M/USRPDevice.h b/Transceiver52M/USRPDevice.h
index 0fa4180..19aa043 100644
--- a/Transceiver52M/USRPDevice.h
+++ b/Transceiver52M/USRPDevice.h
@@ -215,10 +215,10 @@
bool setRxFreq(double wFreq);
/** Returns the starting write Timestamp*/
- TIMESTAMP initialWriteTimestamp(void) { return 40000;}
+ TIMESTAMP initialWriteTimestamp(void) { return 20000;}
/** Returns the starting read Timestamp*/
- TIMESTAMP initialReadTimestamp(void) { return 40000;}
+ TIMESTAMP initialReadTimestamp(void) { return 20000;}
/** returns the full-scale transmit amplitude **/
double fullScaleInputValue() {return 13500.0;}