| commit | 1cc9505011eeacda0b74e73159820a6c2242cc48 | [log] [tgz] |
|---|---|---|
| author | Tom Tsou <tom.tsou@ettus.com> | Thu Aug 11 15:15:04 2016 -0700 |
| committer | Tom Tsou <tom.tsou@ettus.com> | Thu Aug 11 15:17:55 2016 -0700 |
| tree | aacb3dc502286977fc63ec266c145844dbbd670b | |
| parent | aa15d62a8cac2bfa30a336b76cd18f3b9647dd0d [diff] |
uhd: Set default Rx sampling to 4 sps Matching Tx and Rx sample rates reduces run-to-run timing variability due to DDC/DUC timing ambiguity within the UHD FPGA. Make this the default setting. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>