alloc: Load balancing for algo A
Currently only the first enabled PDCH will be used. Beside the
throughput this will also limit the number of TBFs:
- number of UL TBFs <= 7
- number of DL TBFs <= 32
This commit changes the allocation algorithm to use the PDCH with the
least number of attached TBFs. This will improve the troughput in
both directions and the UL limits:
- number of UL TBFs <= min(32, N_PDCH * 7) UL TBFs
Ticket: #1794
Sponsored-by: On-Waves ehf
diff --git a/src/gprs_rlcmac_ts_alloc.cpp b/src/gprs_rlcmac_ts_alloc.cpp
index 29749b8..2ba920a 100644
--- a/src/gprs_rlcmac_ts_alloc.cpp
+++ b/src/gprs_rlcmac_ts_alloc.cpp
@@ -26,6 +26,7 @@
#include <gprs_ms.h>
#include <errno.h>
+#include <values.h>
/* 3GPP TS 05.02 Annex B.1 */
@@ -99,10 +100,13 @@
return -1;
}
-static int find_enabled_pdch(struct gprs_rlcmac_trx *trx, const uint8_t start_ts)
+static int find_possible_pdchs(struct gprs_rlcmac_trx *trx,
+ uint8_t mask, const char *mask_reason = NULL)
{
- int ts;
- for (ts = start_ts; ts < 8; ts++) {
+ unsigned ts;
+ int valid_ts_set = 0;
+
+ for (ts = 0; ts < ARRAY_SIZE(trx->pdch); ts++) {
struct gprs_rlcmac_pdch *pdch;
pdch = &trx->pdch[ts];
@@ -111,10 +115,75 @@
"not enabled\n", ts);
continue;
}
- return ts;
+
+ if (((1 << ts) & mask) == 0) {
+ if (mask_reason)
+ LOGP(DRLCMAC, LOGL_DEBUG,
+ "- Skipping TS %d, because %s\n",
+ ts, mask_reason);
+ continue;
+ }
+
+ valid_ts_set |= 1 << ts;
}
- return 8;
+ return valid_ts_set;
+}
+
+static int find_least_busy_pdch(struct gprs_rlcmac_trx *trx,
+ enum gprs_rlcmac_tbf_direction dir,
+ uint8_t mask,
+ int *free_usf = 0)
+{
+ unsigned ts;
+ int min_used = INT_MAX;
+ int min_ts = -1;
+ int min_usf = -1;
+
+ for (ts = 0; ts < ARRAY_SIZE(trx->pdch); ts++) {
+ struct gprs_rlcmac_pdch *pdch = &trx->pdch[ts];
+ int num_tbfs;
+ int usf = -1; /* must be signed */
+
+ if (((1 << ts) & mask) == 0)
+ continue;
+
+ num_tbfs = pdch->num_tbfs(dir);
+ if (num_tbfs < min_used) {
+ /* We have found a candidate */
+ /* Make sure that an USF is available */
+ if (dir == GPRS_RLCMAC_UL_TBF) {
+ usf = find_free_usf(pdch);
+ if (usf < 0) {
+ LOGP(DRLCMAC, LOGL_DEBUG,
+ "- Skipping TS %d, because "
+ "no USF available\n", ts);
+ continue;
+ }
+ }
+ if (min_ts >= 0)
+ LOGP(DRLCMAC, LOGL_DEBUG,
+ "- Skipping TS %d, because "
+ "num TBFs %d > %d\n",
+ min_ts, min_used, num_tbfs);
+ min_used = num_tbfs;
+ min_ts = ts;
+ min_usf = usf;
+ } else {
+ LOGP(DRLCMAC, LOGL_DEBUG,
+ "- Skipping TS %d, because "
+ "num TBFs %d >= %d\n",
+ ts, num_tbfs, min_used);
+ }
+ }
+
+ if (min_ts < 0)
+ return -1;
+
+ if (free_usf)
+ *free_usf = min_usf;
+
+ return min_ts;
}
static void attach_tbf_to_pdch(struct gprs_rlcmac_pdch *pdch,
@@ -154,29 +223,54 @@
struct gprs_rlcmac_tbf *tbf, uint32_t cust, uint8_t single)
{
struct gprs_rlcmac_pdch *pdch;
- uint8_t ts;
+ int ts = -1;
+ int usf = -1;
+ int mask = 0xff;
+ const char *mask_reason = NULL;
+ struct gprs_rlcmac_tbf *ref_tbf;
LOGP(DRLCMAC, LOGL_DEBUG, "Slot Allocation (Algorithm A) for class "
"%d\n", tbf->ms_class());
- ts = find_enabled_pdch(tbf->trx, 0);
- if (ts == 8)
+ if ((ref_tbf = ms->tbf(tbf->direction)))
+ mask_reason = "need to reuse TS";
+ else if ((ref_tbf = ms->tbf(reverse(tbf->direction))))
+ mask_reason = ref_tbf->direction == GPRS_RLCMAC_UL_TBF ?
+ "not an uplink TBF" : "not a downlink TBF";
+
+ if (ref_tbf)
+ ts = ref_tbf->first_common_ts;
+
+ if (ts >= 0)
+ mask = 1 << ts;
+
+ mask = find_possible_pdchs(tbf->trx, mask, mask_reason);
+ if (!mask)
return -EINVAL;
+ ts = find_least_busy_pdch(tbf->trx, tbf->direction, mask, &usf);
+
+ if (ts < 0) {
+ LOGP(DRLCMAC, LOGL_NOTICE, "- Failed "
+ "to allocate a TS, no USF available\n");
+ return -EBUSY;
+ }
+
pdch = &tbf->trx->pdch[ts];
if (tbf->direction == GPRS_RLCMAC_UL_TBF) {
- int8_t usf; /* must be signed */
struct gprs_rlcmac_ul_tbf *ul_tbf = static_cast<gprs_rlcmac_ul_tbf *>(tbf);
- /* if USF available */
- usf = find_free_usf(pdch);
+ if (usf < 0)
+ usf = find_free_usf(pdch);
+
if (usf < 0) {
LOGP(DRLCMAC, LOGL_NOTICE, "- Failed "
"allocating TS=%d, no USF available\n", ts);
return -EBUSY;
}
- LOGP(DRLCMAC, LOGL_DEBUG, "- Assign uplink "
- "TS=%d USF=%d\n", ts, usf);
+
+ LOGP(DRLCMAC, LOGL_DEBUG, "- Assign uplink TS=%d USF=%d\n",
+ ts, usf);
assign_uplink_tbf_usf(pdch, ul_tbf, usf);
} else {
struct gprs_rlcmac_dl_tbf *dl_tbf = static_cast<gprs_rlcmac_dl_tbf *>(tbf);
diff --git a/tests/alloc/AllocTest.cpp b/tests/alloc/AllocTest.cpp
index 5a91f6a..b918132 100644
--- a/tests/alloc/AllocTest.cpp
+++ b/tests/alloc/AllocTest.cpp
@@ -110,11 +110,11 @@
{
/* slots 2 - 3 */
test_alloc_a(GPRS_RLCMAC_DL_TBF, 0x0c, 32);
- test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x0c, 7);
+ test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x0c, 14);
/* slots 1 - 5 */
test_alloc_a(GPRS_RLCMAC_DL_TBF, 0x1e, 32);
- test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x1e, 7);
+ test_alloc_a(GPRS_RLCMAC_UL_TBF, 0x1e, 28);
}
static void dump_assignment(struct gprs_rlcmac_tbf *tbf, const char *dir)
@@ -557,13 +557,13 @@
}
printf(" Successfully allocated %d UL TBFs\n", counter);
- OSMO_ASSERT(counter >= expect_num);
+ OSMO_ASSERT(counter == expect_num);
}
static void test_successive_allocation()
{
test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_UL_AND_DL,
- 7, "algorithm A (UL and DL)");
+ 32, "algorithm A (UL and DL)");
test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_UL_AND_DL,
7, "algorithm B class 10 (UL and DL)");
test_successive_allocation(alloc_algorithm_b, 12, 12, TEST_MODE_UL_AND_DL,
@@ -574,29 +574,29 @@
18, "algorithm B class 1-29 (UL and DL)");
test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_DL_AND_UL,
- 7, "algorithm A (DL and UL)");
+ 32, "algorithm A (DL and UL)");
test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_DL_AND_UL,
7, "algorithm B class 10 (DL and UL)");
test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_DL_AFTER_UL,
- 7, "algorithm A (DL after UL)");
+ 32, "algorithm A (DL after UL)");
test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_DL_AFTER_UL,
- 7, "algorithm B class 10 (DL after UL)");
+ 32, "algorithm B class 10 (DL after UL)");
test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_UL_AFTER_DL,
- 7, "algorithm A (UL after DL)");
+ 32, "algorithm A (UL after DL)");
test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_UL_AFTER_DL,
7, "algorithm B class 10 (UL after DL)");
test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_UL_ONLY,
- 7, "algorithm A (UL only)");
+ 32, "algorithm A (UL only)");
test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_UL_ONLY,
7, "algorithm B class 10 (UL only)");
test_successive_allocation(alloc_algorithm_a, 1, 1, TEST_MODE_DL_ONLY,
- 7, "algorithm A (DL ONLY)");
+ 32, "algorithm A (DL ONLY)");
test_successive_allocation(alloc_algorithm_b, 10, 10, TEST_MODE_DL_ONLY,
- 7, "algorithm B class 10 (DL ONLY)");
+ 32, "algorithm B class 10 (DL ONLY)");
}
int main(int argc, char **argv)
diff --git a/tests/alloc/AllocTest.err b/tests/alloc/AllocTest.err
index db95601..3f9fc83 100644
--- a/tests/alloc/AllocTest.err
+++ b/tests/alloc/AllocTest.err
@@ -1,19 +1,19 @@
No TFI available.
-- Failed allocating TS=2, no USF available
+- Failed to allocate a TS, no USF available
No TFI available.
-- Failed allocating TS=1, no USF available
-- Failed allocating TS=3, no USF available
+- Failed to allocate a TS, no USF available
+No TFI available.
No suitable uplink slots available
No suitable uplink slots available
No suitable uplink slots available
No suitable uplink slots available
-- Failed allocating TS=3, no USF available
+No TFI available.
No suitable uplink slots available
No TFI available.
No TFI available.
-- Failed allocating TS=3, no USF available
+No TFI available.
No suitable uplink slots available
-- Failed allocating TS=3, no USF available
+No TFI available.
No suitable uplink slots available
No TFI available.
No TFI available.
diff --git a/tests/alloc/AllocTest.ok b/tests/alloc/AllocTest.ok
index 89393fc..3602d8c 100644
--- a/tests/alloc/AllocTest.ok
+++ b/tests/alloc/AllocTest.ok
@@ -8619,13 +8619,38 @@
Mass test: TS0(OOOOOOOO)TS7 MS_Class=29
Going to test assignment with many TBF, algorithm A (UL and DL)
TBF[0] class 1 reserves ...C....
- TBF[1] class 1 reserves ...C....
- TBF[2] class 1 reserves ...C....
- TBF[3] class 1 reserves ...C....
- TBF[4] class 1 reserves ...C....
+ TBF[1] class 1 reserves ....C...
+ TBF[2] class 1 reserves .....C..
+ TBF[3] class 1 reserves ......C.
+ TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
- TBF[6] class 1 reserves ...C....
- Successfully allocated 7 UL TBFs
+ TBF[6] class 1 reserves ....C...
+ TBF[7] class 1 reserves .....C..
+ TBF[8] class 1 reserves ......C.
+ TBF[9] class 1 reserves .......C
+ TBF[10] class 1 reserves ...C....
+ TBF[11] class 1 reserves ....C...
+ TBF[12] class 1 reserves .....C..
+ TBF[13] class 1 reserves ......C.
+ TBF[14] class 1 reserves .......C
+ TBF[15] class 1 reserves ...C....
+ TBF[16] class 1 reserves ....C...
+ TBF[17] class 1 reserves .....C..
+ TBF[18] class 1 reserves ......C.
+ TBF[19] class 1 reserves .......C
+ TBF[20] class 1 reserves ...C....
+ TBF[21] class 1 reserves ....C...
+ TBF[22] class 1 reserves .....C..
+ TBF[23] class 1 reserves ......C.
+ TBF[24] class 1 reserves .......C
+ TBF[25] class 1 reserves ...C....
+ TBF[26] class 1 reserves ....C...
+ TBF[27] class 1 reserves .....C..
+ TBF[28] class 1 reserves ......C.
+ TBF[29] class 1 reserves .......C
+ TBF[30] class 1 reserves ...C....
+ TBF[31] class 1 reserves ....C...
+ Successfully allocated 32 UL TBFs
Going to test assignment with many TBF, algorithm B class 10 (UL and DL)
TBF[0] class 10 reserves ...DDCD.
TBF[1] class 10 reserves ...DDCD.
@@ -8682,13 +8707,38 @@
Successfully allocated 18 UL TBFs
Going to test assignment with many TBF, algorithm A (DL and UL)
TBF[0] class 1 reserves ...C....
- TBF[1] class 1 reserves ...C....
- TBF[2] class 1 reserves ...C....
- TBF[3] class 1 reserves ...C....
- TBF[4] class 1 reserves ...C....
+ TBF[1] class 1 reserves ....C...
+ TBF[2] class 1 reserves .....C..
+ TBF[3] class 1 reserves ......C.
+ TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
- TBF[6] class 1 reserves ...C....
- Successfully allocated 7 UL TBFs
+ TBF[6] class 1 reserves ....C...
+ TBF[7] class 1 reserves .....C..
+ TBF[8] class 1 reserves ......C.
+ TBF[9] class 1 reserves .......C
+ TBF[10] class 1 reserves ...C....
+ TBF[11] class 1 reserves ....C...
+ TBF[12] class 1 reserves .....C..
+ TBF[13] class 1 reserves ......C.
+ TBF[14] class 1 reserves .......C
+ TBF[15] class 1 reserves ...C....
+ TBF[16] class 1 reserves ....C...
+ TBF[17] class 1 reserves .....C..
+ TBF[18] class 1 reserves ......C.
+ TBF[19] class 1 reserves .......C
+ TBF[20] class 1 reserves ...C....
+ TBF[21] class 1 reserves ....C...
+ TBF[22] class 1 reserves .....C..
+ TBF[23] class 1 reserves ......C.
+ TBF[24] class 1 reserves .......C
+ TBF[25] class 1 reserves ...C....
+ TBF[26] class 1 reserves ....C...
+ TBF[27] class 1 reserves .....C..
+ TBF[28] class 1 reserves ......C.
+ TBF[29] class 1 reserves .......C
+ TBF[30] class 1 reserves ...C....
+ TBF[31] class 1 reserves ....C...
+ Successfully allocated 32 UL TBFs
Going to test assignment with many TBF, algorithm B class 10 (DL and UL)
TBF[0] class 10 reserves ...DDCD.
TBF[1] class 10 reserves ...DDCD.
@@ -8700,37 +8750,37 @@
Successfully allocated 7 UL TBFs
Going to test assignment with many TBF, algorithm A (DL after UL)
TBF[0] class 1 reserves ...C....
- TBF[1] class 1 reserves ...C....
- TBF[2] class 1 reserves ...C....
- TBF[3] class 1 reserves ...C....
- TBF[4] class 1 reserves ...C....
+ TBF[1] class 1 reserves ....C...
+ TBF[2] class 1 reserves .....C..
+ TBF[3] class 1 reserves ......C.
+ TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
- TBF[6] class 1 reserves ...C....
- TBF[7] class 1 reserves ...C....
- TBF[8] class 1 reserves ...C....
- TBF[9] class 1 reserves ...C....
+ TBF[6] class 1 reserves ....C...
+ TBF[7] class 1 reserves .....C..
+ TBF[8] class 1 reserves ......C.
+ TBF[9] class 1 reserves .......C
TBF[10] class 1 reserves ...C....
- TBF[11] class 1 reserves ...C....
- TBF[12] class 1 reserves ...C....
- TBF[13] class 1 reserves ...C....
- TBF[14] class 1 reserves ...C....
+ TBF[11] class 1 reserves ....C...
+ TBF[12] class 1 reserves .....C..
+ TBF[13] class 1 reserves ......C.
+ TBF[14] class 1 reserves .......C
TBF[15] class 1 reserves ...C....
- TBF[16] class 1 reserves ...C....
- TBF[17] class 1 reserves ...C....
- TBF[18] class 1 reserves ...C....
- TBF[19] class 1 reserves ...C....
+ TBF[16] class 1 reserves ....C...
+ TBF[17] class 1 reserves .....C..
+ TBF[18] class 1 reserves ......C.
+ TBF[19] class 1 reserves .......C
TBF[20] class 1 reserves ...C....
- TBF[21] class 1 reserves ...C....
- TBF[22] class 1 reserves ...C....
- TBF[23] class 1 reserves ...C....
- TBF[24] class 1 reserves ...C....
+ TBF[21] class 1 reserves ....C...
+ TBF[22] class 1 reserves .....C..
+ TBF[23] class 1 reserves ......C.
+ TBF[24] class 1 reserves .......C
TBF[25] class 1 reserves ...C....
- TBF[26] class 1 reserves ...C....
- TBF[27] class 1 reserves ...C....
- TBF[28] class 1 reserves ...C....
- TBF[29] class 1 reserves ...C....
+ TBF[26] class 1 reserves ....C...
+ TBF[27] class 1 reserves .....C..
+ TBF[28] class 1 reserves ......C.
+ TBF[29] class 1 reserves .......C
TBF[30] class 1 reserves ...C....
- TBF[31] class 1 reserves ...C....
+ TBF[31] class 1 reserves ....C...
Successfully allocated 32 UL TBFs
Going to test assignment with many TBF, algorithm B class 10 (DL after UL)
TBF[0] class 10 reserves ...DDCD.
@@ -8768,13 +8818,38 @@
Successfully allocated 32 UL TBFs
Going to test assignment with many TBF, algorithm A (UL after DL)
TBF[0] class 1 reserves ...U....
- TBF[1] class 1 reserves ...U....
- TBF[2] class 1 reserves ...U....
- TBF[3] class 1 reserves ...U....
- TBF[4] class 1 reserves ...U....
+ TBF[1] class 1 reserves ....U...
+ TBF[2] class 1 reserves .....U..
+ TBF[3] class 1 reserves ......U.
+ TBF[4] class 1 reserves .......U
TBF[5] class 1 reserves ...U....
- TBF[6] class 1 reserves ...U....
- Successfully allocated 7 UL TBFs
+ TBF[6] class 1 reserves ....U...
+ TBF[7] class 1 reserves .....U..
+ TBF[8] class 1 reserves ......U.
+ TBF[9] class 1 reserves .......U
+ TBF[10] class 1 reserves ...U....
+ TBF[11] class 1 reserves ....U...
+ TBF[12] class 1 reserves .....U..
+ TBF[13] class 1 reserves ......U.
+ TBF[14] class 1 reserves .......U
+ TBF[15] class 1 reserves ...U....
+ TBF[16] class 1 reserves ....U...
+ TBF[17] class 1 reserves .....U..
+ TBF[18] class 1 reserves ......U.
+ TBF[19] class 1 reserves .......U
+ TBF[20] class 1 reserves ...U....
+ TBF[21] class 1 reserves ....U...
+ TBF[22] class 1 reserves .....U..
+ TBF[23] class 1 reserves ......U.
+ TBF[24] class 1 reserves .......U
+ TBF[25] class 1 reserves ...U....
+ TBF[26] class 1 reserves ....U...
+ TBF[27] class 1 reserves .....U..
+ TBF[28] class 1 reserves ......U.
+ TBF[29] class 1 reserves .......U
+ TBF[30] class 1 reserves ...U....
+ TBF[31] class 1 reserves ....U...
+ Successfully allocated 32 UL TBFs
Going to test assignment with many TBF, algorithm B class 10 (UL after DL)
TBF[0] class 10 reserves .....U..
TBF[1] class 10 reserves .....U..
@@ -8786,13 +8861,38 @@
Successfully allocated 7 UL TBFs
Going to test assignment with many TBF, algorithm A (UL only)
TBF[0] class 1 reserves ...U....
- TBF[1] class 1 reserves ...U....
- TBF[2] class 1 reserves ...U....
- TBF[3] class 1 reserves ...U....
- TBF[4] class 1 reserves ...U....
+ TBF[1] class 1 reserves ....U...
+ TBF[2] class 1 reserves .....U..
+ TBF[3] class 1 reserves ......U.
+ TBF[4] class 1 reserves .......U
TBF[5] class 1 reserves ...U....
- TBF[6] class 1 reserves ...U....
- Successfully allocated 7 UL TBFs
+ TBF[6] class 1 reserves ....U...
+ TBF[7] class 1 reserves .....U..
+ TBF[8] class 1 reserves ......U.
+ TBF[9] class 1 reserves .......U
+ TBF[10] class 1 reserves ...U....
+ TBF[11] class 1 reserves ....U...
+ TBF[12] class 1 reserves .....U..
+ TBF[13] class 1 reserves ......U.
+ TBF[14] class 1 reserves .......U
+ TBF[15] class 1 reserves ...U....
+ TBF[16] class 1 reserves ....U...
+ TBF[17] class 1 reserves .....U..
+ TBF[18] class 1 reserves ......U.
+ TBF[19] class 1 reserves .......U
+ TBF[20] class 1 reserves ...U....
+ TBF[21] class 1 reserves ....U...
+ TBF[22] class 1 reserves .....U..
+ TBF[23] class 1 reserves ......U.
+ TBF[24] class 1 reserves .......U
+ TBF[25] class 1 reserves ...U....
+ TBF[26] class 1 reserves ....U...
+ TBF[27] class 1 reserves .....U..
+ TBF[28] class 1 reserves ......U.
+ TBF[29] class 1 reserves .......U
+ TBF[30] class 1 reserves ...U....
+ TBF[31] class 1 reserves ....U...
+ Successfully allocated 32 UL TBFs
Going to test assignment with many TBF, algorithm B class 10 (UL only)
TBF[0] class 10 reserves .....U..
TBF[1] class 10 reserves .....U..
@@ -8804,37 +8904,37 @@
Successfully allocated 7 UL TBFs
Going to test assignment with many TBF, algorithm A (DL ONLY)
TBF[0] class 1 reserves ...C....
- TBF[1] class 1 reserves ...C....
- TBF[2] class 1 reserves ...C....
- TBF[3] class 1 reserves ...C....
- TBF[4] class 1 reserves ...C....
+ TBF[1] class 1 reserves ....C...
+ TBF[2] class 1 reserves .....C..
+ TBF[3] class 1 reserves ......C.
+ TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
- TBF[6] class 1 reserves ...C....
- TBF[7] class 1 reserves ...C....
- TBF[8] class 1 reserves ...C....
- TBF[9] class 1 reserves ...C....
+ TBF[6] class 1 reserves ....C...
+ TBF[7] class 1 reserves .....C..
+ TBF[8] class 1 reserves ......C.
+ TBF[9] class 1 reserves .......C
TBF[10] class 1 reserves ...C....
- TBF[11] class 1 reserves ...C....
- TBF[12] class 1 reserves ...C....
- TBF[13] class 1 reserves ...C....
- TBF[14] class 1 reserves ...C....
+ TBF[11] class 1 reserves ....C...
+ TBF[12] class 1 reserves .....C..
+ TBF[13] class 1 reserves ......C.
+ TBF[14] class 1 reserves .......C
TBF[15] class 1 reserves ...C....
- TBF[16] class 1 reserves ...C....
- TBF[17] class 1 reserves ...C....
- TBF[18] class 1 reserves ...C....
- TBF[19] class 1 reserves ...C....
+ TBF[16] class 1 reserves ....C...
+ TBF[17] class 1 reserves .....C..
+ TBF[18] class 1 reserves ......C.
+ TBF[19] class 1 reserves .......C
TBF[20] class 1 reserves ...C....
- TBF[21] class 1 reserves ...C....
- TBF[22] class 1 reserves ...C....
- TBF[23] class 1 reserves ...C....
- TBF[24] class 1 reserves ...C....
+ TBF[21] class 1 reserves ....C...
+ TBF[22] class 1 reserves .....C..
+ TBF[23] class 1 reserves ......C.
+ TBF[24] class 1 reserves .......C
TBF[25] class 1 reserves ...C....
- TBF[26] class 1 reserves ...C....
- TBF[27] class 1 reserves ...C....
- TBF[28] class 1 reserves ...C....
- TBF[29] class 1 reserves ...C....
+ TBF[26] class 1 reserves ....C...
+ TBF[27] class 1 reserves .....C..
+ TBF[28] class 1 reserves ......C.
+ TBF[29] class 1 reserves .......C
TBF[30] class 1 reserves ...C....
- TBF[31] class 1 reserves ...C....
+ TBF[31] class 1 reserves ....C...
Successfully allocated 32 UL TBFs
Going to test assignment with many TBF, algorithm B class 10 (DL ONLY)
TBF[0] class 10 reserves ...DDCD.
diff --git a/tests/tbf/TbfTest.err b/tests/tbf/TbfTest.err
index 7976870..317196c 100644
--- a/tests/tbf/TbfTest.err
+++ b/tests/tbf/TbfTest.err
@@ -4,6 +4,11 @@
Slot Allocation (Algorithm A) for class 0
- Skipping TS 0, because not enabled
- Skipping TS 1, because not enabled
+- Skipping TS 4, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
+- Skipping TS 3, because num TBFs 0 >= 0
- Assign downlink TS=2
PDCH(TS 2, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 2
@@ -15,6 +20,11 @@
Slot Allocation (Algorithm A) for class 0
- Skipping TS 0, because not enabled
- Skipping TS 1, because not enabled
+- Skipping TS 3, because not a downlink TBF
+- Skipping TS 4, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign uplink TS=2 USF=0
PDCH(TS 2, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=UL STATE=NULL), 1 TBFs.
- Setting Control TS 2
@@ -34,6 +44,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 4
@@ -75,6 +88,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
- Setting Control TS 4
@@ -90,6 +106,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE), 2 TBFs.
TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE) Trigger dowlink assignment on PACCH, because another LLC PDU has arrived in between
@@ -117,6 +136,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 4
@@ -158,6 +180,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
- Setting Control TS 4
@@ -173,6 +198,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE), 2 TBFs.
TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=WAIT RELEASE) Trigger dowlink assignment on PACCH, because another LLC PDU has arrived in between
@@ -200,6 +228,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 4
@@ -425,6 +456,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 4
@@ -441,6 +475,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
- Setting Control TS 4
@@ -476,6 +513,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 4
@@ -499,6 +539,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=1 TLLI=0x00000000 DIR=DL STATE=NULL), 2 TBFs.
- Setting Control TS 4
@@ -522,6 +565,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=2 TLLI=0x00000000 DIR=DL STATE=NULL), 3 TBFs.
- Setting Control TS 4
@@ -545,6 +591,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=3 TLLI=0x00000000 DIR=DL STATE=NULL), 4 TBFs.
- Setting Control TS 4
@@ -568,6 +617,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=4 TLLI=0x00000000 DIR=DL STATE=NULL), 5 TBFs.
- Setting Control TS 4
@@ -591,6 +643,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=5 TLLI=0x00000000 DIR=DL STATE=NULL), 6 TBFs.
- Setting Control TS 4
@@ -614,6 +669,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=6 TLLI=0x00000000 DIR=DL STATE=NULL), 7 TBFs.
- Setting Control TS 4
@@ -637,6 +695,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=7 TLLI=0x00000000 DIR=DL STATE=NULL), 8 TBFs.
- Setting Control TS 4
@@ -660,6 +721,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=8 TLLI=0x00000000 DIR=DL STATE=NULL), 9 TBFs.
- Setting Control TS 4
@@ -683,6 +747,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=9 TLLI=0x00000000 DIR=DL STATE=NULL), 10 TBFs.
- Setting Control TS 4
@@ -706,6 +773,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=10 TLLI=0x00000000 DIR=DL STATE=NULL), 11 TBFs.
- Setting Control TS 4
@@ -729,6 +799,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=11 TLLI=0x00000000 DIR=DL STATE=NULL), 12 TBFs.
- Setting Control TS 4
@@ -752,6 +825,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=12 TLLI=0x00000000 DIR=DL STATE=NULL), 13 TBFs.
- Setting Control TS 4
@@ -775,6 +851,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=13 TLLI=0x00000000 DIR=DL STATE=NULL), 14 TBFs.
- Setting Control TS 4
@@ -798,6 +877,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=14 TLLI=0x00000000 DIR=DL STATE=NULL), 15 TBFs.
- Setting Control TS 4
@@ -821,6 +903,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=15 TLLI=0x00000000 DIR=DL STATE=NULL), 16 TBFs.
- Setting Control TS 4
@@ -844,6 +929,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=16 TLLI=0x00000000 DIR=DL STATE=NULL), 17 TBFs.
- Setting Control TS 4
@@ -867,6 +955,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=17 TLLI=0x00000000 DIR=DL STATE=NULL), 18 TBFs.
- Setting Control TS 4
@@ -890,6 +981,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=18 TLLI=0x00000000 DIR=DL STATE=NULL), 19 TBFs.
- Setting Control TS 4
@@ -913,6 +1007,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=19 TLLI=0x00000000 DIR=DL STATE=NULL), 20 TBFs.
- Setting Control TS 4
@@ -936,6 +1033,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=20 TLLI=0x00000000 DIR=DL STATE=NULL), 21 TBFs.
- Setting Control TS 4
@@ -959,6 +1059,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=21 TLLI=0x00000000 DIR=DL STATE=NULL), 22 TBFs.
- Setting Control TS 4
@@ -982,6 +1085,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=22 TLLI=0x00000000 DIR=DL STATE=NULL), 23 TBFs.
- Setting Control TS 4
@@ -1005,6 +1111,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=23 TLLI=0x00000000 DIR=DL STATE=NULL), 24 TBFs.
- Setting Control TS 4
@@ -1028,6 +1137,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=24 TLLI=0x00000000 DIR=DL STATE=NULL), 25 TBFs.
- Setting Control TS 4
@@ -1051,6 +1163,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=25 TLLI=0x00000000 DIR=DL STATE=NULL), 26 TBFs.
- Setting Control TS 4
@@ -1074,6 +1189,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=26 TLLI=0x00000000 DIR=DL STATE=NULL), 27 TBFs.
- Setting Control TS 4
@@ -1097,6 +1215,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=27 TLLI=0x00000000 DIR=DL STATE=NULL), 28 TBFs.
- Setting Control TS 4
@@ -1120,6 +1241,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=28 TLLI=0x00000000 DIR=DL STATE=NULL), 29 TBFs.
- Setting Control TS 4
@@ -1143,6 +1267,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=29 TLLI=0x00000000 DIR=DL STATE=NULL), 30 TBFs.
- Setting Control TS 4
@@ -1166,6 +1293,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=30 TLLI=0x00000000 DIR=DL STATE=NULL), 31 TBFs.
- Setting Control TS 4
@@ -1189,6 +1319,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=31 TLLI=0x00000000 DIR=DL STATE=NULL), 32 TBFs.
- Setting Control TS 4
@@ -1215,6 +1348,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 4
@@ -1241,6 +1377,9 @@
- Skipping TS 1, because not enabled
- Skipping TS 2, because not enabled
- Skipping TS 3, because not enabled
+- Skipping TS 5, because not enabled
+- Skipping TS 6, because not enabled
+- Skipping TS 7, because not enabled
- Assign downlink TS=4
PDCH(TS 4, TRX 0): Attaching TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL), 1 TBFs.
- Setting Control TS 4