commit 16705a4db14f290cfee6afe23fbf6184ef8041e0
author Pau Espin Pedrol <pespin@sysmocom.de> Tue Oct 27 10:24:57 2020 +0100
committer pespin <pespin@sysmocom.de> Thu Oct 29 11:34:17 2020 +0000
tree 2a0cee93b342c3cbe75b3261b68081dff4882736
parent 4d1663594b442e3f6b6e9c89ab3e26948b8f786a

cosmetic: Fix ws between if keyword and parenthesis

Change-Id: I5932f21c58e76552f7187a175b8e281c5846536c

src/gsm_rlcmac.c

diff --git a/src/gsm_rlcmac.c b/src/gsm_rlcmac.c
index 06c721e..abb1e59 100644
--- a/src/gsm_rlcmac.c
+++ b/src/gsm_rlcmac.c
@@ -6056,7 +6056,7 @@
     LOGPC(DRLCMACDATA, LOGL_NOTICE, "E_1 = %u ", (unsigned)(data->E_1));
 
 
-    if(data->E_1 == 0) // Extension octet follows immediately
+    if (data->E_1 == 0) // Extension octet follows immediately
     {
       // Octet 3 (optional)
       i = 0;
@@ -6071,7 +6071,7 @@
         i++;
       } while((data->M[i-1] == 1)&&(data->E[i-1] == 0));
     }
-    if(data->TI == 1) // TLLI field is present
+    if (data->TI == 1) // TLLI field is present
     {
       data->TLLI = bitvec_read_field(vector, &readIndex, 32);
       LOGPC(DRLCMACDATA, LOGL_NOTICE, "TLLI = %08x ", data->TLLI);
@@ -6132,7 +6132,7 @@
     LOGPC(DRLCMACDATA, LOGL_NOTICE, "E_1 = %u ", (unsigned)(data->E_1));
 
     // Octet 3 (optional)
-    if(data->E_1 == 0)
+    if (data->E_1 == 0)
     {
       i = 0;
       do