fix bsc_vty out: timeslot indented too deeply.
In 'show running-config', timeslot appears as a sub-element of rsl, but it is a
direct child of trx. Fix the timeslot section in vty_out by removing one space
of idention.
Adjust various config examples.
Rationale: it's not relevant for function, but confuses human operators. Fixing
it will save the next hacker some time.
diff --git a/openbsc/doc/examples/osmo-nitb/bs11/openbsc-1bts-2trx.cfg b/openbsc/doc/examples/osmo-nitb/bs11/openbsc-1bts-2trx.cfg
index ebe6cc6..ca5689f 100644
--- a/openbsc/doc/examples/osmo-nitb/bs11/openbsc-1bts-2trx.cfg
+++ b/openbsc/doc/examples/osmo-nitb/bs11/openbsc-1bts-2trx.cfg
@@ -29,56 +29,56 @@
max_power_red 0
rsl e1 line 0 timeslot 1 sub-slot full
rsl e1 tei 1
- timeslot 0
- phys_chan_config CCCH+SDCCH4
- e1 line 0 timeslot 1 sub-slot full
- timeslot 1
- phys_chan_config SDCCH8
- e1 line 0 timeslot 2 sub-slot 1
- timeslot 2
- phys_chan_config TCH/F
- e1 line 0 timeslot 2 sub-slot 2
- timeslot 3
- phys_chan_config TCH/F
- e1 line 0 timeslot 2 sub-slot 3
- timeslot 4
- phys_chan_config TCH/F
- e1 line 0 timeslot 3 sub-slot 0
- timeslot 5
- phys_chan_config TCH/F
- e1 line 0 timeslot 3 sub-slot 1
- timeslot 6
- phys_chan_config TCH/F
- e1 line 0 timeslot 3 sub-slot 2
- timeslot 7
- phys_chan_config TCH/F
- e1 line 0 timeslot 3 sub-slot 3
+ timeslot 0
+ phys_chan_config CCCH+SDCCH4
+ e1 line 0 timeslot 1 sub-slot full
+ timeslot 1
+ phys_chan_config SDCCH8
+ e1 line 0 timeslot 2 sub-slot 1
+ timeslot 2
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 2 sub-slot 2
+ timeslot 3
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 2 sub-slot 3
+ timeslot 4
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 3 sub-slot 0
+ timeslot 5
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 3 sub-slot 1
+ timeslot 6
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 3 sub-slot 2
+ timeslot 7
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 3 sub-slot 3
trx 1
arfcn 123
max_power_red 0
rsl e1 line 0 timeslot 1 sub-slot full
rsl e1 tei 2
- timeslot 0
- phys_chan_config TCH/F
- e1 line 0 timeslot 4 sub-slot 0
- timeslot 1
- phys_chan_config TCH/F
- e1 line 0 timeslot 4 sub-slot 1
- timeslot 2
- phys_chan_config TCH/F
- e1 line 0 timeslot 4 sub-slot 2
- timeslot 3
- phys_chan_config TCH/F
- e1 line 0 timeslot 4 sub-slot 3
- timeslot 4
- phys_chan_config TCH/F
- e1 line 0 timeslot 5 sub-slot 0
- timeslot 5
- phys_chan_config TCH/F
- e1 line 0 timeslot 5 sub-slot 1
- timeslot 6
- phys_chan_config TCH/F
- e1 line 0 timeslot 5 sub-slot 2
- timeslot 7
- phys_chan_config TCH/F
- e1 line 0 timeslot 5 sub-slot 3
+ timeslot 0
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 4 sub-slot 0
+ timeslot 1
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 4 sub-slot 1
+ timeslot 2
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 4 sub-slot 2
+ timeslot 3
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 4 sub-slot 3
+ timeslot 4
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 5 sub-slot 0
+ timeslot 5
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 5 sub-slot 1
+ timeslot 6
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 5 sub-slot 2
+ timeslot 7
+ phys_chan_config TCH/F
+ e1 line 0 timeslot 5 sub-slot 3