diff --git a/hardware/icE1usb-proto/LICENSE b/hardware/icE1usb-proto/LICENSE
new file mode 100644
index 0000000..a39811e
--- /dev/null
+++ b/hardware/icE1usb-proto/LICENSE
@@ -0,0 +1,289 @@
+CERN Open Hardware Licence Version 2 - Strongly Reciprocal
+
+
+Preamble
+
+CERN has developed this licence to promote collaboration among
+hardware designers and to provide a legal tool which supports the
+freedom to use, study, modify, share and distribute hardware designs
+and products based on those designs. Version 2 of the CERN Open
+Hardware Licence comes in three variants: CERN-OHL-P (permissive); and
+two reciprocal licences: CERN-OHL-W (weakly reciprocal) and this
+licence, CERN-OHL-S (strongly reciprocal).
+
+The CERN-OHL-S is copyright CERN 2020. Anyone is welcome to use it, in
+unmodified form only.
+
+Use of this Licence does not imply any endorsement by CERN of any
+Licensor or their designs nor does it imply any involvement by CERN in
+their development.
+
+
+1 Definitions
+
+  1.1 'Licence' means this CERN-OHL-S.
+
+  1.2 'Compatible Licence' means
+
+       a) any earlier version of the CERN Open Hardware licence, or
+
+       b) any version of the CERN-OHL-S, or
+
+       c) any licence which permits You to treat the Source to which
+          it applies as licensed under CERN-OHL-S provided that on
+          Conveyance of any such Source, or any associated Product You
+          treat the Source in question as being licensed under
+          CERN-OHL-S.
+
+  1.3 'Source' means information such as design materials or digital
+      code which can be applied to Make or test a Product or to
+      prepare a Product for use, Conveyance or sale, regardless of its
+      medium or how it is expressed. It may include Notices.
+
+  1.4 'Covered Source' means Source that is explicitly made available
+      under this Licence.
+
+  1.5 'Product' means any device, component, work or physical object,
+      whether in finished or intermediate form, arising from the use,
+      application or processing of Covered Source.
+
+  1.6 'Make' means to create or configure something, whether by
+      manufacture, assembly, compiling, loading or applying Covered
+      Source or another Product or otherwise.
+
+  1.7 'Available Component' means any part, sub-assembly, library or
+      code which:
+
+       a) is licensed to You as Complete Source under a Compatible
+          Licence; or
+
+       b) is available, at the time a Product or the Source containing
+          it is first Conveyed, to You and any other prospective
+          licensees
+
+            i) as a physical part with sufficient rights and
+               information (including any configuration and
+               programming files and information about its
+               characteristics and interfaces) to enable it either to
+               be Made itself, or to be sourced and used to Make the
+               Product; or
+           ii) as part of the normal distribution of a tool used to
+               design or Make the Product.
+
+  1.8 'Complete Source' means the set of all Source necessary to Make
+      a Product, in the preferred form for making modifications,
+      including necessary installation and interfacing information
+      both for the Product, and for any included Available Components.
+      If the format is proprietary, it must also be made available in
+      a format (if the proprietary tool can create it) which is
+      viewable with a tool available to potential licensees and
+      licensed under a licence approved by the Free Software
+      Foundation or the Open Source Initiative. Complete Source need
+      not include the Source of any Available Component, provided that
+      You include in the Complete Source sufficient information to
+      enable a recipient to Make or source and use the Available
+      Component to Make the Product.
+
+  1.9 'Source Location' means a location where a Licensor has placed
+      Covered Source, and which that Licensor reasonably believes will
+      remain easily accessible for at least three years for anyone to
+      obtain a digital copy.
+
+ 1.10 'Notice' means copyright, acknowledgement and trademark notices,
+      Source Location references, modification notices (subsection
+      3.3(b)) and all notices that refer to this Licence and to the
+      disclaimer of warranties that are included in the Covered
+      Source.
+
+ 1.11 'Licensee' or 'You' means any person exercising rights under
+      this Licence.
+
+ 1.12 'Licensor' means a natural or legal person who creates or
+      modifies Covered Source. A person may be a Licensee and a
+      Licensor at the same time.
+
+ 1.13 'Convey' means to communicate to the public or distribute.
+
+
+2 Applicability
+
+  2.1 This Licence governs the use, copying, modification, Conveying
+      of Covered Source and Products, and the Making of Products. By
+      exercising any right granted under this Licence, You irrevocably
+      accept these terms and conditions.
+
+  2.2 This Licence is granted by the Licensor directly to You, and
+      shall apply worldwide and without limitation in time.
+
+  2.3 You shall not attempt to restrict by contract or otherwise the
+      rights granted under this Licence to other Licensees.
+
+  2.4 This Licence is not intended to restrict fair use, fair dealing,
+      or any other similar right.
+
+
+3 Copying, Modifying and Conveying Covered Source
+
+  3.1 You may copy and Convey verbatim copies of Covered Source, in
+      any medium, provided You retain all Notices.
+
+  3.2 You may modify Covered Source, other than Notices, provided that
+      You irrevocably undertake to make that modified Covered Source
+      available from a Source Location should You Convey a Product in
+      circumstances where the recipient does not otherwise receive a
+      copy of the modified Covered Source. In each case subsection 3.3
+      shall apply.
+
+      You may only delete Notices if they are no longer applicable to
+      the corresponding Covered Source as modified by You and You may
+      add additional Notices applicable to Your modifications.
+      Including Covered Source in a larger work is modifying the
+      Covered Source, and the larger work becomes modified Covered
+      Source.
+
+  3.3 You may Convey modified Covered Source (with the effect that You
+      shall also become a Licensor) provided that You:
+
+       a) retain Notices as required in subsection 3.2;
+
+       b) add a Notice to the modified Covered Source stating that You
+          have modified it, with the date and brief description of how
+          You have modified it;
+
+       c) add a Source Location Notice for the modified Covered Source
+          if You Convey in circumstances where the recipient does not
+          otherwise receive a copy of the modified Covered Source; and
+
+       d) license the modified Covered Source under the terms and
+          conditions of this Licence (or, as set out in subsection
+          8.3, a later version, if permitted by the licence of the
+          original Covered Source). Such modified Covered Source must
+          be licensed as a whole, but excluding Available Components
+          contained in it, which remain licensed under their own
+          applicable licences.
+
+
+4 Making and Conveying Products
+
+You may Make Products, and/or Convey them, provided that You either
+provide each recipient with a copy of the Complete Source or ensure
+that each recipient is notified of the Source Location of the Complete
+Source. That Complete Source is Covered Source, and You must
+accordingly satisfy Your obligations set out in subsection 3.3. If
+specified in a Notice, the Product must visibly and securely display
+the Source Location on it or its packaging or documentation in the
+manner specified in that Notice.
+
+
+5 Research and Development
+
+You may Convey Covered Source, modified Covered Source or Products to
+a legal entity carrying out development, testing or quality assurance
+work on Your behalf provided that the work is performed on terms which
+prevent the entity from both using the Source or Products for its own
+internal purposes and Conveying the Source or Products or any
+modifications to them to any person other than You. Any modifications
+made by the entity shall be deemed to be made by You pursuant to
+subsection 3.2.
+
+
+6 DISCLAIMER AND LIABILITY
+
+  6.1 DISCLAIMER OF WARRANTY -- The Covered Source and any Products
+      are provided 'as is' and any express or implied warranties,
+      including, but not limited to, implied warranties of
+      merchantability, of satisfactory quality, non-infringement of
+      third party rights, and fitness for a particular purpose or use
+      are disclaimed in respect of any Source or Product to the
+      maximum extent permitted by law. The Licensor makes no
+      representation that any Source or Product does not or will not
+      infringe any patent, copyright, trade secret or other
+      proprietary right. The entire risk as to the use, quality, and
+      performance of any Source or Product shall be with You and not
+      the Licensor. This disclaimer of warranty is an essential part
+      of this Licence and a condition for the grant of any rights
+      granted under this Licence.
+
+  6.2 EXCLUSION AND LIMITATION OF LIABILITY -- The Licensor shall, to
+      the maximum extent permitted by law, have no liability for
+      direct, indirect, special, incidental, consequential, exemplary,
+      punitive or other damages of any character including, without
+      limitation, procurement of substitute goods or services, loss of
+      use, data or profits, or business interruption, however caused
+      and on any theory of contract, warranty, tort (including
+      negligence), product liability or otherwise, arising in any way
+      in relation to the Covered Source, modified Covered Source
+      and/or the Making or Conveyance of a Product, even if advised of
+      the possibility of such damages, and You shall hold the
+      Licensor(s) free and harmless from any liability, costs,
+      damages, fees and expenses, including claims by third parties,
+      in relation to such use.
+
+
+7 Patents
+
+  7.1 Subject to the terms and conditions of this Licence, each
+      Licensor hereby grants to You a perpetual, worldwide,
+      non-exclusive, no-charge, royalty-free, irrevocable (except as
+      stated in subsections 7.2 and 8.4) patent license to Make, have
+      Made, use, offer to sell, sell, import, and otherwise transfer
+      the Covered Source and Products, where such licence applies only
+      to those patent claims licensable by such Licensor that are
+      necessarily infringed by exercising rights under the Covered
+      Source as Conveyed by that Licensor.
+
+  7.2 If You institute patent litigation against any entity (including
+      a cross-claim or counterclaim in a lawsuit) alleging that the
+      Covered Source or a Product constitutes direct or contributory
+      patent infringement, or You seek any declaration that a patent
+      licensed to You under this Licence is invalid or unenforceable
+      then any rights granted to You under this Licence shall
+      terminate as of the date such process is initiated.
+
+
+8 General
+
+  8.1 If any provisions of this Licence are or subsequently become
+      invalid or unenforceable for any reason, the remaining
+      provisions shall remain effective.
+
+  8.2 You shall not use any of the name (including acronyms and
+      abbreviations), image, or logo by which the Licensor or CERN is
+      known, except where needed to comply with section 3, or where
+      the use is otherwise allowed by law. Any such permitted use
+      shall be factual and shall not be made so as to suggest any kind
+      of endorsement or implication of involvement by the Licensor or
+      its personnel.
+
+  8.3 CERN may publish updated versions and variants of this Licence
+      which it considers to be in the spirit of this version, but may
+      differ in detail to address new problems or concerns. New
+      versions will be published with a unique version number and a
+      variant identifier specifying the variant. If the Licensor has
+      specified that a given variant applies to the Covered Source
+      without specifying a version, You may treat that Covered Source
+      as being released under any version of the CERN-OHL with that
+      variant. If no variant is specified, the Covered Source shall be
+      treated as being released under CERN-OHL-S. The Licensor may
+      also specify that the Covered Source is subject to a specific
+      version of the CERN-OHL or any later version in which case You
+      may apply this or any later version of CERN-OHL with the same
+      variant identifier published by CERN.
+
+  8.4 This Licence shall terminate with immediate effect if You fail
+      to comply with any of its terms and conditions.
+
+  8.5 However, if You cease all breaches of this Licence, then Your
+      Licence from any Licensor is reinstated unless such Licensor has
+      terminated this Licence by giving You, while You remain in
+      breach, a notice specifying the breach and requiring You to cure
+      it within 30 days, and You have failed to come into compliance
+      in all material respects by the end of the 30 day period. Should
+      You repeat the breach after receipt of a cure notice and
+      subsequent reinstatement, this Licence will terminate
+      immediately and permanently. Section 6 shall continue to apply
+      after any termination.
+
+  8.6 This Licence shall not be enforceable except by a Licensor
+      acting as such, and third party beneficiary rights are
+      specifically excluded.
diff --git a/hardware/icE1usb-proto/README b/hardware/icE1usb-proto/README
new file mode 100644
index 0000000..0238e71
--- /dev/null
+++ b/hardware/icE1usb-proto/README
@@ -0,0 +1,4 @@
+icE1usb-proto: Early prototype (PMOD based)
+===========================================
+
+Files are hosted here for archival purposes only.
diff --git a/hardware/icE1usb-proto/icE1usb-proto.brd b/hardware/icE1usb-proto/icE1usb-proto.brd
new file mode 100644
index 0000000..3521316
--- /dev/null
+++ b/hardware/icE1usb-proto/icE1usb-proto.brd
@@ -0,0 +1,1593 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.5.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="yes"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="12.5" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
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+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
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+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
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+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
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+<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
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+Naming:&lt;p&gt;
+MA = male&lt;p&gt;
+# contacts - # rows&lt;p&gt;
+W = angled&lt;p&gt;
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+die meisten Anwendungen passen. Sollte ihre Platine 
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+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="6mil"/>
+<param name="mdSmdVia" value="6mil"/>
+<param name="mdSmdSmd" value="6mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="15mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="6mil"/>
+<param name="msDrill" value="12mil"/>
+<param name="msMicroVia" value="12mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="4mil"/>
+<param name="mlMaxStopFrame" value="4mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="15mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
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+<signal name="USB_VSENSE">
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+<signal name="CLK_30M72_RAW">
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+</signal>
+<signal name="CLK_TUNE_PDM_LO">
+<contactref element="R22" pad="1"/>
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+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>
diff --git a/hardware/icE1usb-proto/icE1usb-proto.sch b/hardware/icE1usb-proto/icE1usb-proto.sch
new file mode 100644
index 0000000..5bc5078
--- /dev/null
+++ b/hardware/icE1usb-proto/icE1usb-proto.sch
@@ -0,0 +1,4282 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.5.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="yes"/>
+<setting verticaltext="up"/>
+</settings>
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+<layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/>
+<layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/>
+<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="frames">
+<description>&lt;b&gt;Frames for Sheet and Layout&lt;/b&gt;</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="DINA4_L">
+<frame x1="0" y1="0" x2="264.16" y2="180.34" columns="4" rows="4" layer="94" border-left="no" border-top="no" border-right="no" border-bottom="no"/>
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+<text x="72.39" y="1.27" size="2.54" layer="94">Sheet:</text>
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+<text x="1.27" y="11.43" size="2.54" layer="94">Document Number:</text>
+<text x="17.78" y="19.05" size="2.54" layer="94">&gt;DRAWING_NAME</text>
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+</symbols>
+<devicesets>
+<deviceset name="DINA4_L" prefix="FRAME" uservalue="yes">
+<description>&lt;b&gt;FRAME&lt;/b&gt;&lt;p&gt;
+DIN A4, landscape with extra doc field</description>
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+<gate name="G$2" symbol="DOCFIELD" x="162.56" y="0" addlevel="must"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="con-tycoelectronics">
+<description>&lt;b&gt;Tyco Electronics Connector&lt;/b&gt;&lt;p&gt;
+http://catalog.tycoelectronics.com&lt;br&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="RJ45-NO-SHIELD">
+<description>&lt;b&gt;RJ45 Low Profile&lt;/b&gt; No Shield&lt;p&gt;
+For all RJ45 N and Z Series Models&lt;br&gt;
+Source: www.tycoelectronics.com .. ENG_DS_1654001_1099_RJ_L_0507.pdf</description>
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+</packages>
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+<symbol name="JACK8">
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+<text x="-2.54" y="10.16" size="1.778" layer="95">&gt;NAME</text>
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+<pin name="1" x="-2.54" y="7.62" visible="pad" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="-2.54" y="5.08" visible="pad" length="short" direction="pas" swaplevel="1"/>
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+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="RJ45" prefix="X">
+<description>&lt;b&gt;CORCOM Modular RJ Jacks&lt;/b&gt; No Shield&lt;p&gt;
+Source: www.tycoelectronics.com .. ENG_DS_1654001_1099_RJ_L_0507.pdf</description>
+<gates>
+<gate name="G$1" symbol="JACK8" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="RJ45-NO-SHIELD">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+</connects>
+<technologies>
+<technology name="-6L-B">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="RJ45-6L-B" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="16R6090" constant="no"/>
+</technology>
+<technology name="-6L-S">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="RJ45-6L-S" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="16R6091" constant="no"/>
+</technology>
+<technology name="-6X">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="RJ45-6X" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="01P1604" constant="no"/>
+</technology>
+<technology name="-8L-B">
+<attribute name="MF" value="TYCO ELECTRONICS" constant="no"/>
+<attribute name="MPN" value="RJ45-8L-B" constant="no"/>
+<attribute name="OC_FARNELL" value="1279843" constant="no"/>
+<attribute name="OC_NEWARK" value="52K4445" constant="no"/>
+</technology>
+<technology name="-8L-S">
+<attribute name="MF" value="TYCO ELECTRONICS" constant="no"/>
+<attribute name="MPN" value="RJ45-8L-S" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="80K9067" constant="no"/>
+</technology>
+<technology name="-8X">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="RJ45-8X" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="16R6101" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="we_passive">
+<packages>
+<package name="PULSE_BH">
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+<description>Crystal Oscillator with Enable (E) &amp; Tune (T)</description>
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+<deviceset name="PULSE_T1094NL" prefix="TR">
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+<gate name="-1:2" symbol="E1_MAGNETICS" x="0" y="-10.16" addlevel="always"/>
+</gates>
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+<device name="" package="PULSE_BH">
+<connects>
+<connect gate="-1:1" pin="P$1" pad="16"/>
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+<connect gate="-1:1" pin="P$3" pad="14"/>
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+<connect gate="-1:2" pin="P$5" pad="7"/>
+<connect gate="-1:2" pin="P$6" pad="8"/>
+</connects>
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+</device>
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+<description>Resistor</description>
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+</gates>
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+<device name="_0402" package="0402">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
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+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="_0805" package="0805">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="_1206" package="1206">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_1210" package="1210">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0603_A" package="0603_A">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="C-EU" prefix="C" uservalue="yes">
+<description>Capacitor</description>
+<gates>
+<gate name="SYM" symbol="C-EU" x="0" y="0"/>
+</gates>
+<devices>
+<device name="_0402" package="0402">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="_0603" package="0603">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0805" package="0805">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="_1206" package="1206">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_1210" package="1210">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="XTAL_OSC_ET" prefix="X" uservalue="yes">
+<description>Crystal Oscillator with Enable (E) &amp; Tune (T)</description>
+<gates>
+<gate name="SYM" symbol="XTAL_OSC_ET" x="0" y="0"/>
+</gates>
+<devices>
+<device name="_CFPV-45/46" package="CFPV-45/46">
+<connects>
+<connect gate="SYM" pin="EN" pad="2"/>
+<connect gate="SYM" pin="GND" pad="3"/>
+<connect gate="SYM" pin="OUT" pad="4"/>
+<connect gate="SYM" pin="TUNE" pad="1"/>
+<connect gate="SYM" pin="VDD" pad="6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_TXC-6U" package="TXC-6U">
+<connects>
+<connect gate="SYM" pin="EN" pad="2"/>
+<connect gate="SYM" pin="GND" pad="3"/>
+<connect gate="SYM" pin="OUT" pad="4"/>
+<connect gate="SYM" pin="TUNE" pad="1"/>
+<connect gate="SYM" pin="VDD" pad="6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_CW_T" package="CW_OSC_T">
+<connects>
+<connect gate="SYM" pin="EN" pad="8"/>
+<connect gate="SYM" pin="GND" pad="4"/>
+<connect gate="SYM" pin="OUT" pad="5"/>
+<connect gate="SYM" pin="TUNE" pad="10"/>
+<connect gate="SYM" pin="VDD" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="FBEAD" prefix="FB" uservalue="yes">
+<description>&lt;b&gt;INDUCTOR&lt;/b&gt;&lt;p&gt;
+SMD Bead inductor</description>
+<gates>
+<gate name="SYM" symbol="FBEAD" x="0" y="0"/>
+</gates>
+<devices>
+<device name="_0805" package="0805">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0603" package="0603">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_1206" package="1206">
+<connects>
+<connect gate="SYM" pin="1" pad="1"/>
+<connect gate="SYM" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="we_supply">
+<packages>
+</packages>
+<symbols>
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+<wire x1="-2.54" y1="0" x2="2.54" y2="0" width="0.254" layer="94"/>
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+</symbol>
+<symbol name="GND">
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+<text x="-2.286" y="-3.302" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="5V">
+<wire x1="-2.54" y1="0" x2="2.54" y2="0" width="0.254" layer="94"/>
+<text x="-2.54" y="0.635" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="5V" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
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+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
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+</device>
+</devices>
+</deviceset>
+<deviceset name="GND">
+<gates>
+<gate name="G$1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="5V">
+<gates>
+<gate name="G$1" symbol="5V" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="con-lstb">
+<description>&lt;b&gt;Pin Headers&lt;/b&gt;&lt;p&gt;
+Naming:&lt;p&gt;
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+# contacts - # rows&lt;p&gt;
+W = angled&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
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+<gates>
+<gate name="G$1" symbol="MA04-2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="MA04-2">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
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+<technology name="">
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+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="con-cypressindustries">
+<description>&lt;b&gt;Connectors from Cypress Industries&lt;/b&gt;&lt;p&gt;
+www.cypressindustries.com&lt;br&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="32005-201">
+<description>&lt;b&gt;MINI USB-B R/A SMT W/ REAR&lt;/b&gt;&lt;p&gt;
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+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<gates>
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+</gates>
+<devices>
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+<connect gate="A" pin="6" pad="6"/>
+<connect gate="A" pin="7" pad="7"/>
+<connect gate="A" pin="8" pad="8"/>
+<connect gate="A" pin="9" pad="9"/>
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+<technologies>
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+<description>&lt;b&gt;LEDs&lt;/b&gt;&lt;p&gt;
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+<description>&lt;B&gt;LED&lt;/B&gt;&lt;p&gt;
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+Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf</description>
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+</package>
+<package name="SML1206">
+<description>&lt;b&gt;SML10XXKH-TR (HIGH INTENSITY) LED&lt;/b&gt;&lt;p&gt;
+&lt;table&gt;
+&lt;tr&gt;&lt;td&gt;SML10R3KH-TR&lt;/td&gt;&lt;td&gt;ULTRA RED&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10E3KH-TR&lt;/td&gt;&lt;td&gt;SUPER REDSUPER BLUE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10O3KH-TR&lt;/td&gt;&lt;td&gt;SUPER ORANGE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10PY3KH-TR&lt;/td&gt;&lt;td&gt;PURE YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10OY3KH-TR&lt;/td&gt;&lt;td&gt;ULTRA YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10AG3KH-TR&lt;/td&gt;&lt;td&gt;AQUA GREEN&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10BG3KH-TR&lt;/td&gt;&lt;td&gt;BLUE GREEN&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10PB1KH-TR&lt;/td&gt;&lt;td&gt;SUPER BLUE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10CW1KH-TR&lt;/td&gt;&lt;td&gt;WHITE&lt;/td&gt;&lt;/tr&gt;
+&lt;/table&gt;
+
+Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF</description>
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+<package name="SML0603">
+<description>&lt;b&gt;SML0603-XXX (HIGH INTENSITY) LED&lt;/b&gt;&lt;p&gt;
+&lt;table&gt;
+&lt;tr&gt;&lt;td&gt;AG3K&lt;/td&gt;&lt;td&gt;AQUA GREEN&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;B1K&lt;/td&gt;&lt;td&gt;SUPER BLUE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;R1K&lt;/td&gt;&lt;td&gt;SUPER RED&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;R3K&lt;/td&gt;&lt;td&gt;ULTRA RED&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;O3K&lt;/td&gt;&lt;td&gt;SUPER ORANGE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;O3KH&lt;/td&gt;&lt;td&gt;SOFT ORANGE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;Y3KH&lt;/td&gt;&lt;td&gt;SUPER YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;Y3K&lt;/td&gt;&lt;td&gt;SUPER YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;2CW&lt;/td&gt;&lt;td&gt;WHITE&lt;/td&gt;&lt;/tr&gt;
+&lt;/table&gt;
+Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf</description>
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+<text x="-1" y="-2" size="1.27" layer="27">&gt;VALUE</text>
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+<rectangle x1="-0.25" y1="0.175" x2="0" y2="0.4" layer="21"/>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
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+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
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+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-4.572" size="1.778" layer="95" rot="R90">&gt;NAME</text>
+<text x="5.715" y="-4.572" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
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+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED" prefix="LED" uservalue="yes">
+<description>&lt;b&gt;LED&lt;/b&gt;&lt;p&gt;
+&lt;u&gt;OSRAM&lt;/u&gt;:&lt;br&gt;
+
+- &lt;u&gt;CHIPLED&lt;/u&gt;&lt;br&gt;
+LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971
+LH N974, LH R974&lt;br&gt;
+LS Q976, LO Q976, LY Q976&lt;br&gt;
+LO Q996&lt;br&gt;
+
+- &lt;u&gt;Hyper CHIPLED&lt;/u&gt;&lt;br&gt;
+LW Q18S&lt;br&gt;
+LB Q993, LB Q99A, LB R99A&lt;br&gt;
+
+- &lt;u&gt;SideLED&lt;/u&gt;&lt;br&gt;
+LS A670, LO A670, LY A670, LG A670, LP A670&lt;br&gt;
+LB A673, LV A673, LT A673, LW A673&lt;br&gt;
+LH A674&lt;br&gt;
+LY A675&lt;br&gt;
+LS A676, LA A676, LO A676, LY A676, LW A676&lt;br&gt;
+LS A679, LY A679, LG A679&lt;br&gt;
+
+-  &lt;u&gt;Hyper Micro SIDELED®&lt;/u&gt;&lt;br&gt;
+LS Y876, LA Y876, LO Y876, LY Y876&lt;br&gt;
+LT Y87S&lt;br&gt;
+
+- &lt;u&gt;SmartLED&lt;/u&gt;&lt;br&gt;
+LW L88C, LW L88S&lt;br&gt;
+LB L89C, LB L89S, LG L890&lt;br&gt;
+LS L89K, LO L89K, LY L89K&lt;br&gt;
+LS L896, LA L896, LO L896, LY L896&lt;br&gt;
+
+- &lt;u&gt;TOPLED&lt;/u&gt;&lt;br&gt;
+LS T670, LO T670, LY T670, LG T670, LP T670&lt;br&gt;
+LSG T670, LSP T670, LSY T670, LOP T670, LYG T670&lt;br&gt;
+LG T671, LOG T671, LSG T671&lt;br&gt;
+LB T673, LV T673, LT T673, LW T673&lt;br&gt;
+LH T674&lt;br&gt;
+LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676&lt;br&gt;
+LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C&lt;br&gt;
+LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C&lt;br&gt;
+LW T67C&lt;br&gt;
+LS T679, LY T679, LG T679&lt;br&gt;
+LS T770, LO T770, LY T770, LG T770, LP T770&lt;br&gt;
+LB T773, LV T773, LT T773, LW T773&lt;br&gt;
+LH T774&lt;br&gt;
+LS E675, LA E675, LY E675, LS T675&lt;br&gt;
+LS T776, LA T776, LO T776, LY T776, LB T776&lt;br&gt;
+LHGB T686&lt;br&gt;
+LT T68C, LB T68C&lt;br&gt;
+
+- &lt;u&gt;Hyper Mini TOPLED®&lt;/u&gt;&lt;br&gt;
+LB M676&lt;br&gt;
+
+- &lt;u&gt;Mini TOPLED Santana®&lt;/u&gt;&lt;br&gt;
+LG M470&lt;br&gt;
+LS M47K, LO M47K, LY M47K
+&lt;p&gt;
+Source: http://www.osram.convergy.de&lt;p&gt;
+
+&lt;u&gt;LUXEON:&lt;/u&gt;&lt;br&gt;
+- &lt;u&gt;LUMILED®&lt;/u&gt;&lt;br&gt;
+LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00&lt;br&gt;
+LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00&lt;br&gt;
+LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00&lt;br&gt;
+LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00&lt;br&gt;
+LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00&lt;br&gt;
+LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00&lt;br&gt;
+LXK2-PH12-R00, LXK2-PH12-S00&lt;br&gt;
+LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00
+&lt;p&gt;
+Source: www.luxeon.com&lt;p&gt;
+
+&lt;u&gt;KINGBRIGHT:&lt;/U&gt;&lt;p&gt;
+KA-3528ASYC&lt;br&gt;
+Source: www.kingbright.com</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="SMT1206" package="1206">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LD260" package="LD260">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SQR2X5" package="LED2X5">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="3MM" package="LED3MM">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="5MM" package="LED5MM">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LSU260" package="LSU260">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LZR181" package="LZR181">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B152" package="Q62902-B152">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B153" package="Q62902-B153">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B155" package="Q62902-B155">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B156" package="Q62902-B156">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SFH480" package="SFH480">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SFH482" package="SFH482">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SQR5.7X3.2" package="U57X32">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="IRL80A" package="IRL80A">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P-LCC-2" package="P-LCC-2">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MINI-TOP" package="OSRAM-MINI-TOP-LED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SIDELED" package="OSRAM-SIDELED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMART-LED" package="SMART-LED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="B"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P-LCC-2-BACK" package="P-LCC-2-TOPLED-RG">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MICRO-SIDELED" package="MICRO-SIDELED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P-LCC-4" package="P-LCC-4">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C@4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIP-LED0603" package="CHIP-LED0603">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIP-LED0805" package="CHIP-LED0805">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="TOPLED-SANTANA" package="MINI-TOPLED-SANTANA">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED_0805" package="CHIPLED_0805">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED_1206" package="CHIPLED_1206">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED_0603" package="CHIPLED_0603">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED-0603-TTW" package="CHIPLED-0603-TTW">
+<connects>
+<connect gate="G$1" pin="A" pad="A@1"/>
+<connect gate="G$1" pin="C" pad="C@1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="" package="SMARTLED-TTW">
+<connects>
+<connect gate="G$1" pin="A" pad="A@1"/>
+<connect gate="G$1" pin="C" pad="C@1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-LUMILED+" package="LUMILED+">
+<connects>
+<connect gate="G$1" pin="A" pad="2+"/>
+<connect gate="G$1" pin="C" pad="4-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-LUMILED" package="LUMILED">
+<connects>
+<connect gate="G$1" pin="A" pad="2+"/>
+<connect gate="G$1" pin="C" pad="4-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="10MM" package="LED10MM">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="KA-3528ASYC" package="KA-3528ASYC">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SML0805" package="SML0805">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SML1206" package="SML1206">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SML0603" package="SML0603">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="FRAME1" library="frames" deviceset="DINA4_L" device=""/>
+<part name="X1" library="con-tycoelectronics" deviceset="RJ45" device="" technology="-8X"/>
+<part name="TR1" library="we_passive" deviceset="PULSE_T1094NL" device=""/>
+<part name="R1" library="we_passive" deviceset="R-EU" device="_0603_A" value="120R"/>
+<part name="C5" library="we_passive" deviceset="C-EU" device="_0603" value="1u"/>
+<part name="C6" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="R9" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k"/>
+<part name="R8" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="R10" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="U$1" library="we_supply" deviceset="3V3" device=""/>
+<part name="U$2" library="we_supply" deviceset="GND" device=""/>
+<part name="U$3" library="we_supply" deviceset="GND" device=""/>
+<part name="U$4" library="we_supply" deviceset="GND" device=""/>
+<part name="C9" library="we_passive" deviceset="C-EU" device="_0603" value="1u"/>
+<part name="C10" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="R16" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k"/>
+<part name="R15" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="R17" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="U$5" library="we_supply" deviceset="3V3" device=""/>
+<part name="U$6" library="we_supply" deviceset="GND" device=""/>
+<part name="U$7" library="we_supply" deviceset="GND" device=""/>
+<part name="U$8" library="we_supply" deviceset="GND" device=""/>
+<part name="C7" library="we_passive" deviceset="C-EU" device="_0603" value="1u"/>
+<part name="C8" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="R12" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k"/>
+<part name="R11" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="R13" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="U$9" library="we_supply" deviceset="3V3" device=""/>
+<part name="U$10" library="we_supply" deviceset="GND" device=""/>
+<part name="U$11" library="we_supply" deviceset="GND" device=""/>
+<part name="U$12" library="we_supply" deviceset="GND" device=""/>
+<part name="SV1" library="con-lstb" deviceset="MA04-2" device="" value="NT/TE"/>
+<part name="R2" library="we_passive" deviceset="R-EU" device="_0603_A" value="47R"/>
+<part name="R3" library="we_passive" deviceset="R-EU" device="_0603_A" value="47R"/>
+<part name="R4" library="we_passive" deviceset="R-EU" device="_0603_A" value="10k"/>
+<part name="R5" library="we_passive" deviceset="R-EU" device="_0603_A" value="10k"/>
+<part name="R6" library="we_passive" deviceset="R-EU" device="_0603_A" value="10k"/>
+<part name="R7" library="we_passive" deviceset="R-EU" device="_0603_A" value="10k"/>
+<part name="C1" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="C2" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="C3" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="C4" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="FRAME3" library="frames" deviceset="DINA4_L" device=""/>
+<part name="X3" library="con-cypressindustries" deviceset="MINI-USB-SCHIELD-" device="32005-201" value="USB"/>
+<part name="U$35" library="we_supply" deviceset="GND" device=""/>
+<part name="U$36" library="we_supply" deviceset="5V" device=""/>
+<part name="U$37" library="we_supply" deviceset="GND" device=""/>
+<part name="C14" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="X2" library="we_passive" deviceset="XTAL_OSC_ET" device="_CFPV-45/46"/>
+<part name="U$13" library="we_supply" deviceset="GND" device=""/>
+<part name="C11" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="U$14" library="we_supply" deviceset="3V3" device=""/>
+<part name="FB1" library="we_passive" deviceset="FBEAD" device="_0603"/>
+<part name="U$15" library="we_supply" deviceset="GND" device=""/>
+<part name="JP1" library="pinhead" deviceset="PINHD-2X6" device="/90" value="PMOD1A"/>
+<part name="JP2" library="pinhead" deviceset="PINHD-2X6" device="/90" value="PMOD1B"/>
+<part name="R29" library="we_passive" deviceset="R-EU" device="_0603_A" value="33R"/>
+<part name="R30" library="we_passive" deviceset="R-EU" device="_0603_A" value="33R"/>
+<part name="R25" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k5"/>
+<part name="R14" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="U$16" library="we_supply" deviceset="GND" device=""/>
+<part name="U$17" library="we_supply" deviceset="GND" device=""/>
+<part name="U$18" library="we_supply" deviceset="3V3" device=""/>
+<part name="U$19" library="we_supply" deviceset="3V3" device=""/>
+<part name="U$20" library="we_supply" deviceset="3V3" device=""/>
+<part name="U$21" library="we_supply" deviceset="GND" device=""/>
+<part name="R18" library="we_passive" deviceset="R-EU" device="_0603_A" value="10k"/>
+<part name="R19" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="C12" library="we_passive" deviceset="C-EU" device="_0603" value="1u"/>
+<part name="C13" library="we_passive" deviceset="C-EU" device="_0603" value="100n"/>
+<part name="R22" library="we_passive" deviceset="R-EU" device="_0603_A" value="120k"/>
+<part name="R21" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="R24" library="we_passive" deviceset="R-EU" device="_0603_A" value="DNP"/>
+<part name="U$22" library="we_supply" deviceset="3V3" device=""/>
+<part name="U$23" library="we_supply" deviceset="GND" device=""/>
+<part name="U$24" library="we_supply" deviceset="GND" device=""/>
+<part name="U$25" library="we_supply" deviceset="GND" device=""/>
+<part name="R23" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k"/>
+<part name="R27" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k5"/>
+<part name="LED1" library="led" deviceset="LED" device="CHIPLED_0603"/>
+<part name="U$26" library="we_supply" deviceset="5V" device=""/>
+<part name="U$27" library="we_supply" deviceset="GND" device=""/>
+<part name="LED2" library="led" deviceset="LED" device="CHIPLED_0603"/>
+<part name="R28" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k5"/>
+<part name="U$28" library="we_supply" deviceset="GND" device=""/>
+<part name="U$29" library="we_supply" deviceset="3V3" device=""/>
+<part name="R26" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k5"/>
+<part name="R31" library="we_passive" deviceset="R-EU" device="_0603_A" value="1k5"/>
+<part name="U$30" library="we_supply" deviceset="GND" device=""/>
+<part name="U$31" library="we_supply" deviceset="5V" device=""/>
+<part name="R20" library="we_passive" deviceset="R-EU" device="_0603_A" value="50R"/>
+</parts>
+<sheets>
+<sheet>
+<description>&lt;b&gt;E1 Line interface&lt;/b&gt;</description>
+<plain>
+<wire x1="165.1" y1="180.34" x2="165.1" y2="99.06" width="0.254" layer="94"/>
+<wire x1="165.1" y1="99.06" x2="165.1" y2="35.56" width="0.254" layer="94"/>
+<wire x1="165.1" y1="35.56" x2="264.16" y2="35.56" width="0.254" layer="94"/>
+<wire x1="162.56" y1="0" x2="162.56" y2="35.56" width="0.254" layer="94"/>
+<wire x1="162.56" y1="35.56" x2="165.1" y2="35.56" width="0.254" layer="94"/>
+<text x="170.18" y="172.72" size="3.81" layer="94">BIAS</text>
+<text x="139.7" y="172.72" size="3.81" layer="94">LINE IF</text>
+<wire x1="124.46" y1="81.28" x2="124.46" y2="78.74" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="78.74" x2="124.46" y2="73.66" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="73.66" x2="124.46" y2="71.12" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="71.12" x2="137.16" y2="76.2" width="0.1524" layer="94"/>
+<wire x1="137.16" y1="76.2" x2="124.46" y2="81.28" width="0.1524" layer="94"/>
+<wire x1="137.16" y1="76.2" x2="142.24" y2="76.2" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="53.34" x2="124.46" y2="50.8" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="50.8" x2="124.46" y2="45.72" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="45.72" x2="124.46" y2="43.18" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="43.18" x2="137.16" y2="48.26" width="0.1524" layer="94"/>
+<wire x1="137.16" y1="48.26" x2="124.46" y2="53.34" width="0.1524" layer="94"/>
+<wire x1="137.16" y1="48.26" x2="142.24" y2="48.26" width="0.1524" layer="94"/>
+<wire x1="125.73" y1="79.375" x2="125.73" y2="78.105" width="0.1524" layer="94"/>
+<wire x1="125.095" y1="78.74" x2="126.365" y2="78.74" width="0.1524" layer="94"/>
+<wire x1="125.095" y1="73.66" x2="126.365" y2="73.66" width="0.1524" layer="94"/>
+<wire x1="125.095" y1="50.8" x2="126.365" y2="50.8" width="0.1524" layer="94"/>
+<wire x1="125.73" y1="51.435" x2="125.73" y2="50.165" width="0.1524" layer="94"/>
+<wire x1="125.095" y1="45.72" x2="126.365" y2="45.72" width="0.1524" layer="94"/>
+<wire x1="124.46" y1="50.8" x2="121.92" y2="50.8" width="0.1524" layer="94"/>
+<wire x1="121.92" y1="45.72" x2="124.46" y2="45.72" width="0.1524" layer="94"/>
+<wire x1="121.92" y1="78.74" x2="124.46" y2="78.74" width="0.1524" layer="94"/>
+<wire x1="121.92" y1="73.66" x2="124.46" y2="73.66" width="0.1524" layer="94"/>
+<wire x1="165.1" y1="99.06" x2="0" y2="99.06" width="0.254" layer="94"/>
+<text x="137.16" y="5.08" size="3.81" layer="94">RX PHY</text>
+<text x="165.1" y="25.4" size="6.35" layer="94">E1 Line interface</text>
+<text x="167.64" y="40.64" size="1.27" layer="97">Place 100n close to FPGA input pins</text>
+<text x="167.64" y="38.1" size="1.27" layer="97">Place resistors close to FPGA output pins</text>
+<text x="203.2" y="7.62" size="1.778" layer="94">(c) Munaut.S &lt;tnt@246tnt.com&gt;
+CERN-OHL-S-2.0</text>
+</plain>
+<instances>
+<instance part="FRAME1" gate="G$1" x="0" y="0"/>
+<instance part="FRAME1" gate="G$2" x="162.56" y="0"/>
+<instance part="X1" gate="G$1" x="149.86" y="144.78"/>
+<instance part="TR1" gate="-1:1" x="66.04" y="154.94"/>
+<instance part="TR1" gate="-1:2" x="66.04" y="127"/>
+<instance part="R1" gate="SYM" x="22.86" y="154.94" rot="R90"/>
+<instance part="C5" gate="SYM" x="210.82" y="147.32"/>
+<instance part="C6" gate="SYM" x="218.44" y="147.32"/>
+<instance part="R9" gate="SYM" x="203.2" y="154.94"/>
+<instance part="R8" gate="SYM" x="231.14" y="162.56" rot="R90"/>
+<instance part="R10" gate="SYM" x="231.14" y="147.32" rot="R90"/>
+<instance part="U$1" gate="G$1" x="231.14" y="172.72"/>
+<instance part="U$2" gate="G$1" x="210.82" y="137.16"/>
+<instance part="U$3" gate="G$1" x="218.44" y="137.16"/>
+<instance part="U$4" gate="G$1" x="231.14" y="137.16"/>
+<instance part="C9" gate="SYM" x="210.82" y="55.88"/>
+<instance part="C10" gate="SYM" x="218.44" y="55.88"/>
+<instance part="R16" gate="SYM" x="203.2" y="63.5"/>
+<instance part="R15" gate="SYM" x="231.14" y="71.12" rot="R90"/>
+<instance part="R17" gate="SYM" x="231.14" y="55.88" rot="R90"/>
+<instance part="U$5" gate="G$1" x="231.14" y="81.28"/>
+<instance part="U$6" gate="G$1" x="210.82" y="45.72"/>
+<instance part="U$7" gate="G$1" x="218.44" y="45.72"/>
+<instance part="U$8" gate="G$1" x="231.14" y="45.72"/>
+<instance part="C7" gate="SYM" x="210.82" y="101.6"/>
+<instance part="C8" gate="SYM" x="218.44" y="101.6"/>
+<instance part="R12" gate="SYM" x="203.2" y="109.22"/>
+<instance part="R11" gate="SYM" x="231.14" y="116.84" rot="R90"/>
+<instance part="R13" gate="SYM" x="231.14" y="101.6" rot="R90"/>
+<instance part="U$9" gate="G$1" x="231.14" y="127"/>
+<instance part="U$10" gate="G$1" x="210.82" y="91.44"/>
+<instance part="U$11" gate="G$1" x="218.44" y="91.44"/>
+<instance part="U$12" gate="G$1" x="231.14" y="91.44"/>
+<instance part="SV1" gate="G$1" x="124.46" y="144.78" smashed="yes">
+<attribute name="VALUE" x="121.92" y="132.08" size="1.778" layer="96"/>
+<attribute name="NAME" x="121.92" y="134.62" size="1.778" layer="95"/>
+</instance>
+<instance part="R2" gate="SYM" x="35.56" y="134.62"/>
+<instance part="R3" gate="SYM" x="35.56" y="119.38"/>
+<instance part="R4" gate="SYM" x="88.9" y="78.74" smashed="yes">
+<attribute name="NAME" x="81.28" y="76.454" size="1.778" layer="95"/>
+<attribute name="VALUE" x="91.44" y="76.454" size="1.778" layer="96"/>
+</instance>
+<instance part="R5" gate="SYM" x="88.9" y="73.66" smashed="yes">
+<attribute name="NAME" x="81.28" y="75.946" size="1.778" layer="95" rot="MR180"/>
+<attribute name="VALUE" x="91.44" y="75.946" size="1.778" layer="96" rot="MR180"/>
+</instance>
+<instance part="R6" gate="SYM" x="88.9" y="50.8" smashed="yes">
+<attribute name="NAME" x="81.28" y="48.514" size="1.778" layer="95"/>
+<attribute name="VALUE" x="91.44" y="48.514" size="1.778" layer="96"/>
+</instance>
+<instance part="R7" gate="SYM" x="88.9" y="45.72" smashed="yes">
+<attribute name="NAME" x="81.28" y="48.006" size="1.778" layer="95" rot="MR180"/>
+<attribute name="VALUE" x="91.44" y="48.006" size="1.778" layer="96" rot="MR180"/>
+</instance>
+<instance part="C1" gate="SYM" x="58.42" y="78.74" smashed="yes" rot="R90">
+<attribute name="NAME" x="58.42" y="81.28" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="68.58" y="81.28" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="C2" gate="SYM" x="58.42" y="73.66" smashed="yes" rot="R90">
+<attribute name="NAME" x="58.42" y="76.2" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="68.58" y="76.2" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="C3" gate="SYM" x="58.42" y="50.8" smashed="yes" rot="R90">
+<attribute name="NAME" x="58.42" y="53.34" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="68.58" y="53.34" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="C4" gate="SYM" x="58.42" y="45.72" smashed="yes" rot="R90">
+<attribute name="NAME" x="58.42" y="48.26" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="68.58" y="48.26" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="R14" gate="SYM" x="246.38" y="86.36" rot="R90"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="E1_RX_CT_BIAS" class="0">
+<segment>
+<pinref part="TR1" gate="-1:1" pin="P$5"/>
+<wire x1="53.34" y1="154.94" x2="48.26" y2="154.94" width="0.1524" layer="91"/>
+<label x="48.26" y="154.94" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="R9" gate="SYM" pin="2"/>
+<wire x1="208.28" y1="154.94" x2="210.82" y2="154.94" width="0.1524" layer="91"/>
+<pinref part="R8" gate="SYM" pin="1"/>
+<wire x1="210.82" y1="154.94" x2="218.44" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="154.94" x2="231.14" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="154.94" x2="238.76" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="157.48" x2="231.14" y2="154.94" width="0.1524" layer="91"/>
+<junction x="231.14" y="154.94"/>
+<pinref part="R10" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="152.4" x2="231.14" y2="154.94" width="0.1524" layer="91"/>
+<pinref part="C6" gate="SYM" pin="1"/>
+<wire x1="218.44" y1="149.86" x2="218.44" y2="154.94" width="0.1524" layer="91"/>
+<junction x="218.44" y="154.94"/>
+<pinref part="C5" gate="SYM" pin="1"/>
+<wire x1="210.82" y1="149.86" x2="210.82" y2="154.94" width="0.1524" layer="91"/>
+<junction x="210.82" y="154.94"/>
+<label x="238.76" y="154.94" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_RING" class="0">
+<segment>
+<pinref part="TR1" gate="-1:1" pin="P$6"/>
+<wire x1="53.34" y1="147.32" x2="22.86" y2="147.32" width="0.1524" layer="91"/>
+<pinref part="R1" gate="SYM" pin="1"/>
+<wire x1="22.86" y1="147.32" x2="22.86" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="147.32" x2="17.78" y2="147.32" width="0.1524" layer="91"/>
+<junction x="22.86" y="147.32"/>
+<label x="17.78" y="147.32" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="C3" gate="SYM" pin="1"/>
+<wire x1="35.56" y1="50.8" x2="50.8" y2="50.8" width="0.1524" layer="91"/>
+<label x="35.56" y="50.8" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="50.8" y1="50.8" x2="55.88" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="50.8" x2="50.8" y2="73.66" width="0.1524" layer="91"/>
+<junction x="50.8" y="50.8"/>
+<pinref part="C2" gate="SYM" pin="1"/>
+<wire x1="50.8" y1="73.66" x2="55.88" y2="73.66" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_RX_CT_BIAS_PDM" class="0">
+<segment>
+<wire x1="193.04" y1="154.94" x2="198.12" y2="154.94" width="0.1524" layer="91"/>
+<pinref part="R9" gate="SYM" pin="1"/>
+<label x="193.04" y="154.94" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="C5" gate="SYM" pin="2"/>
+<pinref part="U$2" gate="G$1" pin="GND"/>
+<wire x1="210.82" y1="142.24" x2="210.82" y2="139.7" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C6" gate="SYM" pin="2"/>
+<pinref part="U$3" gate="G$1" pin="GND"/>
+<wire x1="218.44" y1="142.24" x2="218.44" y2="139.7" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R10" gate="SYM" pin="1"/>
+<pinref part="U$4" gate="G$1" pin="GND"/>
+<wire x1="231.14" y1="142.24" x2="231.14" y2="139.7" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C9" gate="SYM" pin="2"/>
+<pinref part="U$6" gate="G$1" pin="GND"/>
+<wire x1="210.82" y1="50.8" x2="210.82" y2="48.26" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C10" gate="SYM" pin="2"/>
+<pinref part="U$7" gate="G$1" pin="GND"/>
+<wire x1="218.44" y1="50.8" x2="218.44" y2="48.26" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R17" gate="SYM" pin="1"/>
+<pinref part="U$8" gate="G$1" pin="GND"/>
+<wire x1="231.14" y1="50.8" x2="231.14" y2="48.26" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C7" gate="SYM" pin="2"/>
+<pinref part="U$10" gate="G$1" pin="GND"/>
+<wire x1="210.82" y1="96.52" x2="210.82" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C8" gate="SYM" pin="2"/>
+<pinref part="U$11" gate="G$1" pin="GND"/>
+<wire x1="218.44" y1="96.52" x2="218.44" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R13" gate="SYM" pin="1"/>
+<pinref part="U$12" gate="G$1" pin="GND"/>
+<wire x1="231.14" y1="96.52" x2="231.14" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="3V3" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="3V3"/>
+<pinref part="R8" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="170.18" x2="231.14" y2="167.64" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$5" gate="G$1" pin="3V3"/>
+<pinref part="R15" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="78.74" x2="231.14" y2="76.2" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$9" gate="G$1" pin="3V3"/>
+<pinref part="R11" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="124.46" x2="231.14" y2="121.92" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_RX_VREF_N" class="0">
+<segment>
+<pinref part="R16" gate="SYM" pin="2"/>
+<wire x1="208.28" y1="63.5" x2="210.82" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="R15" gate="SYM" pin="1"/>
+<wire x1="210.82" y1="63.5" x2="218.44" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="63.5" x2="231.14" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="63.5" x2="236.22" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="236.22" y1="63.5" x2="238.76" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="66.04" x2="231.14" y2="63.5" width="0.1524" layer="91"/>
+<junction x="231.14" y="63.5"/>
+<pinref part="R17" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="60.96" x2="231.14" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="C10" gate="SYM" pin="1"/>
+<wire x1="218.44" y1="58.42" x2="218.44" y2="63.5" width="0.1524" layer="91"/>
+<junction x="218.44" y="63.5"/>
+<pinref part="C9" gate="SYM" pin="1"/>
+<wire x1="210.82" y1="58.42" x2="210.82" y2="63.5" width="0.1524" layer="91"/>
+<junction x="210.82" y="63.5"/>
+<label x="238.76" y="63.5" size="1.27" layer="95" xref="yes"/>
+<wire x1="236.22" y1="63.5" x2="236.22" y2="78.74" width="0.1524" layer="91"/>
+<junction x="236.22" y="63.5"/>
+<pinref part="R14" gate="SYM" pin="1"/>
+<wire x1="236.22" y1="78.74" x2="246.38" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="246.38" y1="78.74" x2="246.38" y2="81.28" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<label x="35.56" y="22.86" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="35.56" y1="22.86" x2="81.28" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="22.86" x2="81.28" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="R5" gate="SYM" pin="1"/>
+<wire x1="81.28" y1="45.72" x2="81.28" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="73.66" x2="83.82" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="45.72" x2="81.28" y2="45.72" width="0.1524" layer="91"/>
+<junction x="81.28" y="45.72"/>
+<pinref part="R7" gate="SYM" pin="1"/>
+</segment>
+</net>
+<net name="E1_RX_VREF_P" class="0">
+<segment>
+<pinref part="R12" gate="SYM" pin="2"/>
+<wire x1="208.28" y1="109.22" x2="210.82" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="R11" gate="SYM" pin="1"/>
+<wire x1="210.82" y1="109.22" x2="218.44" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="109.22" x2="231.14" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="109.22" x2="236.22" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="236.22" y1="109.22" x2="238.76" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="111.76" x2="231.14" y2="109.22" width="0.1524" layer="91"/>
+<junction x="231.14" y="109.22"/>
+<pinref part="R13" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="106.68" x2="231.14" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="C8" gate="SYM" pin="1"/>
+<wire x1="218.44" y1="104.14" x2="218.44" y2="109.22" width="0.1524" layer="91"/>
+<junction x="218.44" y="109.22"/>
+<pinref part="C7" gate="SYM" pin="1"/>
+<wire x1="210.82" y1="104.14" x2="210.82" y2="109.22" width="0.1524" layer="91"/>
+<junction x="210.82" y="109.22"/>
+<label x="238.76" y="109.22" size="1.27" layer="95" xref="yes"/>
+<wire x1="236.22" y1="109.22" x2="236.22" y2="93.98" width="0.1524" layer="91"/>
+<junction x="236.22" y="109.22"/>
+<pinref part="R14" gate="SYM" pin="2"/>
+<wire x1="236.22" y1="93.98" x2="246.38" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="246.38" y1="93.98" x2="246.38" y2="91.44" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<label x="35.56" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="35.56" y1="27.94" x2="76.2" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="27.94" x2="76.2" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="R4" gate="SYM" pin="1"/>
+<wire x1="76.2" y1="50.8" x2="76.2" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="78.74" x2="83.82" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="50.8" x2="76.2" y2="50.8" width="0.1524" layer="91"/>
+<junction x="76.2" y="50.8"/>
+<pinref part="R6" gate="SYM" pin="1"/>
+</segment>
+</net>
+<net name="E1_RX_VREF_N_PDM" class="0">
+<segment>
+<wire x1="193.04" y1="63.5" x2="198.12" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="R16" gate="SYM" pin="1"/>
+<label x="193.04" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="E1_LINE_P4" class="0">
+<segment>
+<pinref part="X1" gate="G$1" pin="4"/>
+<pinref part="SV1" gate="G$1" pin="5"/>
+<wire x1="147.32" y1="144.78" x2="132.08" y2="144.78" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_LINE_P5" class="0">
+<segment>
+<pinref part="X1" gate="G$1" pin="5"/>
+<wire x1="147.32" y1="142.24" x2="142.24" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="142.24" x2="142.24" y2="139.7" width="0.1524" layer="91"/>
+<pinref part="SV1" gate="G$1" pin="1"/>
+<wire x1="142.24" y1="139.7" x2="132.08" y2="139.7" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_LINE_P1" class="0">
+<segment>
+<pinref part="X1" gate="G$1" pin="1"/>
+<wire x1="147.32" y1="152.4" x2="114.3" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="114.3" y1="152.4" x2="114.3" y2="147.32" width="0.1524" layer="91"/>
+<pinref part="SV1" gate="G$1" pin="8"/>
+<wire x1="114.3" y1="147.32" x2="116.84" y2="147.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_LINE_P2" class="0">
+<segment>
+<pinref part="SV1" gate="G$1" pin="4"/>
+<wire x1="116.84" y1="142.24" x2="111.76" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="142.24" x2="111.76" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="154.94" x2="142.24" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="154.94" x2="142.24" y2="149.86" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="2"/>
+<wire x1="142.24" y1="149.86" x2="147.32" y2="149.86" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_LINE_RX_TIP" class="0">
+<segment>
+<pinref part="SV1" gate="G$1" pin="6"/>
+<wire x1="116.84" y1="144.78" x2="106.68" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="106.68" y1="144.78" x2="106.68" y2="157.48" width="0.1524" layer="91"/>
+<pinref part="TR1" gate="-1:1" pin="P$1"/>
+<wire x1="106.68" y1="157.48" x2="81.28" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="157.48" x2="81.28" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="162.56" x2="78.74" y2="162.56" width="0.1524" layer="91"/>
+<label x="83.82" y="160.02" size="1.27" layer="95" rot="MR180"/>
+</segment>
+</net>
+<net name="E1_LINE_RX_RING" class="0">
+<segment>
+<pinref part="SV1" gate="G$1" pin="2"/>
+<wire x1="116.84" y1="139.7" x2="104.14" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="139.7" x2="104.14" y2="152.4" width="0.1524" layer="91"/>
+<pinref part="TR1" gate="-1:1" pin="P$3"/>
+<wire x1="104.14" y1="152.4" x2="81.28" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="152.4" x2="81.28" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="147.32" x2="78.74" y2="147.32" width="0.1524" layer="91"/>
+<label x="83.82" y="149.86" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="E1_LINE_TX_RING" class="0">
+<segment>
+<pinref part="SV1" gate="G$1" pin="3"/>
+<wire x1="132.08" y1="142.24" x2="137.16" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="142.24" x2="137.16" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="124.46" x2="81.28" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="124.46" x2="81.28" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="119.38" x2="78.74" y2="119.38" width="0.1524" layer="91"/>
+<label x="83.82" y="121.92" size="1.27" layer="95"/>
+<pinref part="TR1" gate="-1:2" pin="P$3"/>
+</segment>
+</net>
+<net name="E1_LINE_TX_TIP" class="0">
+<segment>
+<pinref part="SV1" gate="G$1" pin="7"/>
+<wire x1="132.08" y1="147.32" x2="134.62" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="147.32" x2="134.62" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="129.54" x2="81.28" y2="129.54" width="0.1524" layer="91"/>
+<pinref part="TR1" gate="-1:2" pin="P$1"/>
+<wire x1="78.74" y1="134.62" x2="81.28" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="134.62" x2="81.28" y2="129.54" width="0.1524" layer="91"/>
+<label x="83.82" y="132.08" size="1.27" layer="95" rot="MR180"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="R2" gate="SYM" pin="2"/>
+<pinref part="TR1" gate="-1:2" pin="P$4"/>
+<wire x1="40.64" y1="134.62" x2="53.34" y2="134.62" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="TR1" gate="-1:2" pin="P$6"/>
+<pinref part="R3" gate="SYM" pin="2"/>
+<wire x1="53.34" y1="119.38" x2="40.64" y2="119.38" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_TX_TIP" class="0">
+<segment>
+<pinref part="R2" gate="SYM" pin="1"/>
+<wire x1="30.48" y1="134.62" x2="17.78" y2="134.62" width="0.1524" layer="91"/>
+<label x="17.78" y="134.62" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="E1_TX_RING" class="0">
+<segment>
+<pinref part="R3" gate="SYM" pin="1"/>
+<wire x1="30.48" y1="119.38" x2="17.78" y2="119.38" width="0.1524" layer="91"/>
+<label x="17.78" y="119.38" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_HI_P" class="0">
+<segment>
+<wire x1="93.98" y1="78.74" x2="96.52" y2="78.74" width="0.1524" layer="91"/>
+<label x="106.68" y="78.74" size="1.27" layer="95" xref="yes"/>
+<pinref part="R4" gate="SYM" pin="2"/>
+<wire x1="96.52" y1="78.74" x2="106.68" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="78.74" x2="96.52" y2="81.28" width="0.1524" layer="91"/>
+<junction x="96.52" y="78.74"/>
+<wire x1="96.52" y1="81.28" x2="71.12" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="81.28" x2="71.12" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="78.74" x2="63.5" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="C1" gate="SYM" pin="2"/>
+</segment>
+</net>
+<net name="E1_RX_HI_N" class="0">
+<segment>
+<wire x1="93.98" y1="73.66" x2="96.52" y2="73.66" width="0.1524" layer="91"/>
+<label x="106.68" y="73.66" size="1.27" layer="95" xref="yes"/>
+<pinref part="R5" gate="SYM" pin="2"/>
+<wire x1="96.52" y1="73.66" x2="106.68" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="73.66" x2="96.52" y2="71.12" width="0.1524" layer="91"/>
+<junction x="96.52" y="73.66"/>
+<wire x1="96.52" y1="71.12" x2="71.12" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="71.12" x2="71.12" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="73.66" x2="63.5" y2="73.66" width="0.1524" layer="91"/>
+<pinref part="C2" gate="SYM" pin="2"/>
+</segment>
+</net>
+<net name="E1_RX_LO_P" class="0">
+<segment>
+<wire x1="93.98" y1="50.8" x2="96.52" y2="50.8" width="0.1524" layer="91"/>
+<label x="106.68" y="50.8" size="1.27" layer="95" xref="yes"/>
+<pinref part="R6" gate="SYM" pin="2"/>
+<wire x1="96.52" y1="50.8" x2="106.68" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="50.8" x2="96.52" y2="53.34" width="0.1524" layer="91"/>
+<junction x="96.52" y="50.8"/>
+<wire x1="96.52" y1="53.34" x2="71.12" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="53.34" x2="71.12" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="50.8" x2="63.5" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="C3" gate="SYM" pin="2"/>
+</segment>
+</net>
+<net name="E1_RX_LO_N" class="0">
+<segment>
+<wire x1="93.98" y1="45.72" x2="96.52" y2="45.72" width="0.1524" layer="91"/>
+<label x="106.68" y="45.72" size="1.27" layer="95" xref="yes"/>
+<pinref part="R7" gate="SYM" pin="2"/>
+<wire x1="96.52" y1="45.72" x2="106.68" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="45.72" x2="96.52" y2="43.18" width="0.1524" layer="91"/>
+<junction x="96.52" y="45.72"/>
+<wire x1="96.52" y1="43.18" x2="71.12" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="45.72" x2="71.12" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="45.72" x2="71.12" y2="43.18" width="0.1524" layer="91"/>
+<pinref part="C4" gate="SYM" pin="2"/>
+</segment>
+</net>
+<net name="E1_RX_VREF_P_PDM" class="0">
+<segment>
+<wire x1="193.04" y1="109.22" x2="198.12" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="R12" gate="SYM" pin="1"/>
+<label x="193.04" y="109.22" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_TIP" class="0">
+<segment>
+<pinref part="TR1" gate="-1:1" pin="P$4"/>
+<wire x1="53.34" y1="162.56" x2="22.86" y2="162.56" width="0.1524" layer="91"/>
+<pinref part="R1" gate="SYM" pin="2"/>
+<wire x1="22.86" y1="162.56" x2="22.86" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="162.56" x2="17.78" y2="162.56" width="0.1524" layer="91"/>
+<junction x="22.86" y="162.56"/>
+<label x="17.78" y="162.56" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="C1" gate="SYM" pin="1"/>
+<wire x1="55.88" y1="78.74" x2="45.72" y2="78.74" width="0.1524" layer="91"/>
+<label x="35.56" y="78.74" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="45.72" y1="78.74" x2="35.56" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="78.74" x2="45.72" y2="45.72" width="0.1524" layer="91"/>
+<junction x="45.72" y="78.74"/>
+<pinref part="C4" gate="SYM" pin="1"/>
+<wire x1="45.72" y1="45.72" x2="55.88" y2="45.72" width="0.1524" layer="91"/>
+</segment>
+</net>
+</nets>
+</sheet>
+<sheet>
+<description>&lt;b&gt;PMOD, USB &amp; Clock&lt;/b&gt;</description>
+<plain>
+<text x="165.1" y="25.4" size="6.35" layer="94">PMOD, USB &amp; Clock</text>
+<text x="78.74" y="127" size="1.27" layer="97">1</text>
+<text x="78.74" y="152.4" size="1.27" layer="97">1</text>
+<text x="60.96" y="152.4" size="1.27" layer="97" rot="MR0">7</text>
+<text x="60.96" y="127" size="1.27" layer="97" rot="MR0">7</text>
+<text x="203.2" y="7.62" size="1.778" layer="94">(c) Munaut.S &lt;tnt@246tnt.com&gt;
+CERN-OHL-S-2.0</text>
+</plain>
+<instances>
+<instance part="FRAME3" gate="G$1" x="0" y="0"/>
+<instance part="FRAME3" gate="G$2" x="162.56" y="0"/>
+<instance part="X3" gate="G$1" x="33.02" y="45.72" smashed="yes" rot="R180">
+<attribute name="NAME" x="22.86" y="58.42" size="1.778" layer="95"/>
+<attribute name="VALUE" x="22.86" y="60.96" size="1.778" layer="96"/>
+</instance>
+<instance part="X3" gate="S" x="33.02" y="35.56" smashed="yes" rot="MR0"/>
+<instance part="U$35" gate="G$1" x="27.94" y="15.24"/>
+<instance part="U$36" gate="G$1" x="43.18" y="55.88"/>
+<instance part="U$37" gate="G$1" x="40.64" y="33.02"/>
+<instance part="C14" gate="SYM" x="27.94" y="25.4"/>
+<instance part="X2" gate="SYM" x="205.74" y="121.92"/>
+<instance part="U$13" gate="G$1" x="190.5" y="111.76"/>
+<instance part="C11" gate="SYM" x="182.88" y="121.92"/>
+<instance part="U$14" gate="G$1" x="167.64" y="132.08"/>
+<instance part="FB1" gate="SYM" x="175.26" y="127"/>
+<instance part="U$15" gate="G$1" x="182.88" y="111.76"/>
+<instance part="JP1" gate="A" x="71.12" y="142.24" rot="R180"/>
+<instance part="JP2" gate="A" x="71.12" y="116.84" rot="R180"/>
+<instance part="R29" gate="SYM" x="60.96" y="48.26"/>
+<instance part="R30" gate="SYM" x="60.96" y="40.64"/>
+<instance part="R25" gate="SYM" x="50.8" y="55.88" rot="R90"/>
+<instance part="U$16" gate="G$1" x="58.42" y="104.14"/>
+<instance part="U$17" gate="G$1" x="81.28" y="104.14"/>
+<instance part="U$18" gate="G$1" x="55.88" y="157.48"/>
+<instance part="U$19" gate="G$1" x="83.82" y="157.48"/>
+<instance part="U$20" gate="G$1" x="241.3" y="142.24"/>
+<instance part="U$21" gate="G$1" x="241.3" y="129.54"/>
+<instance part="R18" gate="SYM" x="231.14" y="137.16" smashed="yes">
+<attribute name="NAME" x="228.6" y="139.7" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="238.76" y="139.7" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="R19" gate="SYM" x="231.14" y="134.62" smashed="yes">
+<attribute name="NAME" x="223.52" y="132.08" size="1.778" layer="95"/>
+<attribute name="VALUE" x="233.68" y="132.08" size="1.778" layer="96"/>
+</instance>
+<instance part="C12" gate="SYM" x="210.82" y="78.74"/>
+<instance part="C13" gate="SYM" x="218.44" y="78.74"/>
+<instance part="R22" gate="SYM" x="195.58" y="86.36"/>
+<instance part="R21" gate="SYM" x="231.14" y="93.98" rot="R90"/>
+<instance part="R24" gate="SYM" x="231.14" y="78.74" rot="R90"/>
+<instance part="U$22" gate="G$1" x="231.14" y="104.14"/>
+<instance part="U$23" gate="G$1" x="210.82" y="68.58"/>
+<instance part="U$24" gate="G$1" x="218.44" y="68.58"/>
+<instance part="U$25" gate="G$1" x="231.14" y="68.58"/>
+<instance part="R23" gate="SYM" x="195.58" y="78.74"/>
+<instance part="R27" gate="SYM" x="121.92" y="50.8" rot="R90"/>
+<instance part="LED1" gate="G$1" x="121.92" y="38.1"/>
+<instance part="U$26" gate="G$1" x="121.92" y="60.96"/>
+<instance part="U$27" gate="G$1" x="121.92" y="25.4"/>
+<instance part="LED2" gate="G$1" x="134.62" y="38.1"/>
+<instance part="R28" gate="SYM" x="134.62" y="50.8" rot="R90"/>
+<instance part="U$28" gate="G$1" x="134.62" y="25.4"/>
+<instance part="U$29" gate="G$1" x="134.62" y="60.96"/>
+<instance part="R26" gate="SYM" x="109.22" y="50.8" rot="R90"/>
+<instance part="R31" gate="SYM" x="109.22" y="35.56" rot="R90"/>
+<instance part="U$30" gate="G$1" x="109.22" y="25.4"/>
+<instance part="U$31" gate="G$1" x="109.22" y="60.96"/>
+<instance part="R20" gate="SYM" x="228.6" y="121.92"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$7" class="0">
+<segment>
+<pinref part="X3" gate="S" pin="S4"/>
+<pinref part="C14" gate="SYM" pin="1"/>
+<wire x1="27.94" y1="33.02" x2="27.94" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="X3" gate="S" pin="S1"/>
+<wire x1="27.94" y1="30.48" x2="27.94" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="35.56" y1="33.02" x2="35.56" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="35.56" y1="30.48" x2="33.02" y2="30.48" width="0.1524" layer="91"/>
+<junction x="27.94" y="30.48"/>
+<pinref part="X3" gate="S" pin="S2"/>
+<wire x1="33.02" y1="30.48" x2="30.48" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="30.48" x2="27.94" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="33.02" x2="33.02" y2="30.48" width="0.1524" layer="91"/>
+<junction x="33.02" y="30.48"/>
+<pinref part="X3" gate="S" pin="S3"/>
+<wire x1="30.48" y1="33.02" x2="30.48" y2="30.48" width="0.1524" layer="91"/>
+<junction x="30.48" y="30.48"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="C14" gate="SYM" pin="2"/>
+<pinref part="U$35" gate="G$1" pin="GND"/>
+<wire x1="27.94" y1="20.32" x2="27.94" y2="17.78" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C11" gate="SYM" pin="2"/>
+<pinref part="U$15" gate="G$1" pin="GND"/>
+<wire x1="182.88" y1="116.84" x2="182.88" y2="114.3" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="X2" gate="SYM" pin="GND"/>
+<wire x1="193.04" y1="116.84" x2="190.5" y2="116.84" width="0.1524" layer="91"/>
+<pinref part="U$13" gate="G$1" pin="GND"/>
+<wire x1="190.5" y1="116.84" x2="190.5" y2="114.3" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="X3" gate="G$1" pin="5"/>
+<pinref part="U$37" gate="G$1" pin="GND"/>
+<wire x1="38.1" y1="50.8" x2="40.64" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="50.8" x2="40.64" y2="35.56" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$16" gate="G$1" pin="GND"/>
+<wire x1="58.42" y1="106.68" x2="58.42" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="JP2" gate="A" pin="4"/>
+<wire x1="58.42" y1="114.3" x2="66.04" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="JP1" gate="A" pin="4"/>
+<wire x1="66.04" y1="139.7" x2="58.42" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="139.7" x2="58.42" y2="114.3" width="0.1524" layer="91"/>
+<junction x="58.42" y="114.3"/>
+</segment>
+<segment>
+<pinref part="JP2" gate="A" pin="3"/>
+<wire x1="73.66" y1="114.3" x2="81.28" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="U$17" gate="G$1" pin="GND"/>
+<wire x1="81.28" y1="114.3" x2="81.28" y2="106.68" width="0.1524" layer="91"/>
+<pinref part="JP1" gate="A" pin="3"/>
+<wire x1="73.66" y1="139.7" x2="81.28" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="139.7" x2="81.28" y2="114.3" width="0.1524" layer="91"/>
+<junction x="81.28" y="114.3"/>
+</segment>
+<segment>
+<pinref part="R19" gate="SYM" pin="2"/>
+<pinref part="U$21" gate="G$1" pin="GND"/>
+<wire x1="236.22" y1="134.62" x2="241.3" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="241.3" y1="134.62" x2="241.3" y2="132.08" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C12" gate="SYM" pin="2"/>
+<pinref part="U$23" gate="G$1" pin="GND"/>
+<wire x1="210.82" y1="73.66" x2="210.82" y2="71.12" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C13" gate="SYM" pin="2"/>
+<pinref part="U$24" gate="G$1" pin="GND"/>
+<wire x1="218.44" y1="73.66" x2="218.44" y2="71.12" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R24" gate="SYM" pin="1"/>
+<pinref part="U$25" gate="G$1" pin="GND"/>
+<wire x1="231.14" y1="73.66" x2="231.14" y2="71.12" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="LED1" gate="G$1" pin="C"/>
+<pinref part="U$27" gate="G$1" pin="GND"/>
+<wire x1="121.92" y1="33.02" x2="121.92" y2="27.94" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="LED2" gate="G$1" pin="C"/>
+<pinref part="U$28" gate="G$1" pin="GND"/>
+<wire x1="134.62" y1="33.02" x2="134.62" y2="27.94" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R31" gate="SYM" pin="1"/>
+<pinref part="U$30" gate="G$1" pin="GND"/>
+<wire x1="109.22" y1="30.48" x2="109.22" y2="27.94" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="3V3" class="0">
+<segment>
+<pinref part="U$14" gate="G$1" pin="3V3"/>
+<wire x1="167.64" y1="129.54" x2="167.64" y2="127" width="0.1524" layer="91"/>
+<pinref part="FB1" gate="SYM" pin="1"/>
+<wire x1="167.64" y1="127" x2="170.18" y2="127" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$18" gate="G$1" pin="3V3"/>
+<wire x1="55.88" y1="154.94" x2="55.88" y2="137.16" width="0.1524" layer="91"/>
+<pinref part="JP2" gate="A" pin="2"/>
+<wire x1="55.88" y1="137.16" x2="55.88" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="55.88" y1="111.76" x2="66.04" y2="111.76" width="0.1524" layer="91"/>
+<pinref part="JP1" gate="A" pin="2"/>
+<wire x1="66.04" y1="137.16" x2="55.88" y2="137.16" width="0.1524" layer="91"/>
+<junction x="55.88" y="137.16"/>
+</segment>
+<segment>
+<pinref part="JP2" gate="A" pin="1"/>
+<pinref part="U$19" gate="G$1" pin="3V3"/>
+<wire x1="73.66" y1="111.76" x2="83.82" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="111.76" x2="83.82" y2="137.16" width="0.1524" layer="91"/>
+<pinref part="JP1" gate="A" pin="1"/>
+<wire x1="83.82" y1="137.16" x2="83.82" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="73.66" y1="137.16" x2="83.82" y2="137.16" width="0.1524" layer="91"/>
+<junction x="83.82" y="137.16"/>
+</segment>
+<segment>
+<pinref part="R18" gate="SYM" pin="2"/>
+<pinref part="U$20" gate="G$1" pin="3V3"/>
+<wire x1="236.22" y1="137.16" x2="241.3" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="241.3" y1="137.16" x2="241.3" y2="139.7" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$22" gate="G$1" pin="3V3"/>
+<pinref part="R21" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="101.6" x2="231.14" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$29" gate="G$1" pin="3V3"/>
+<pinref part="R28" gate="SYM" pin="2"/>
+<wire x1="134.62" y1="58.42" x2="134.62" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$1" class="0">
+<segment>
+<pinref part="FB1" gate="SYM" pin="2"/>
+<pinref part="X2" gate="SYM" pin="VDD"/>
+<wire x1="180.34" y1="127" x2="182.88" y2="127" width="0.1524" layer="91"/>
+<pinref part="C11" gate="SYM" pin="1"/>
+<wire x1="182.88" y1="127" x2="193.04" y2="127" width="0.1524" layer="91"/>
+<wire x1="182.88" y1="127" x2="182.88" y2="124.46" width="0.1524" layer="91"/>
+<junction x="182.88" y="127"/>
+</segment>
+</net>
+<net name="5V" class="0">
+<segment>
+<pinref part="X3" gate="G$1" pin="1"/>
+<pinref part="U$36" gate="G$1" pin="5V"/>
+<wire x1="38.1" y1="40.64" x2="43.18" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="43.18" y1="40.64" x2="43.18" y2="53.34" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$26" gate="G$1" pin="5V"/>
+<pinref part="R27" gate="SYM" pin="2"/>
+<wire x1="121.92" y1="58.42" x2="121.92" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$31" gate="G$1" pin="5V"/>
+<pinref part="R26" gate="SYM" pin="2"/>
+<wire x1="109.22" y1="58.42" x2="109.22" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="USB_DN_PIN" class="0">
+<segment>
+<pinref part="X3" gate="G$1" pin="2"/>
+<wire x1="38.1" y1="43.18" x2="45.72" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="43.18" x2="45.72" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="40.64" x2="55.88" y2="40.64" width="0.1524" layer="91"/>
+<pinref part="R30" gate="SYM" pin="1"/>
+</segment>
+</net>
+<net name="USB_DP_PIN" class="0">
+<segment>
+<pinref part="X3" gate="G$1" pin="3"/>
+<wire x1="38.1" y1="45.72" x2="45.72" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="45.72" x2="45.72" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="48.26" x2="50.8" y2="48.26" width="0.1524" layer="91"/>
+<pinref part="R29" gate="SYM" pin="1"/>
+<pinref part="R25" gate="SYM" pin="1"/>
+<wire x1="50.8" y1="48.26" x2="55.88" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="50.8" x2="50.8" y2="48.26" width="0.1524" layer="91"/>
+<junction x="50.8" y="48.26"/>
+</segment>
+</net>
+<net name="USB_DP" class="0">
+<segment>
+<pinref part="R29" gate="SYM" pin="2"/>
+<wire x1="66.04" y1="48.26" x2="71.12" y2="48.26" width="0.1524" layer="91"/>
+<label x="71.12" y="48.26" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="JP1" gate="A" pin="11"/>
+<wire x1="73.66" y1="149.86" x2="88.9" y2="149.86" width="0.1524" layer="91"/>
+<label x="88.9" y="149.86" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="USB_DN" class="0">
+<segment>
+<pinref part="R30" gate="SYM" pin="2"/>
+<wire x1="66.04" y1="40.64" x2="71.12" y2="40.64" width="0.1524" layer="91"/>
+<label x="71.12" y="40.64" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="JP1" gate="A" pin="12"/>
+<wire x1="66.04" y1="149.86" x2="50.8" y2="149.86" width="0.1524" layer="91"/>
+<label x="50.8" y="149.86" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="USB_DET" class="0">
+<segment>
+<pinref part="R25" gate="SYM" pin="2"/>
+<wire x1="50.8" y1="60.96" x2="50.8" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="63.5" x2="71.12" y2="63.5" width="0.1524" layer="91"/>
+<label x="71.12" y="63.5" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="JP1" gate="A" pin="9"/>
+<wire x1="73.66" y1="147.32" x2="88.9" y2="147.32" width="0.1524" layer="91"/>
+<label x="88.9" y="147.32" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_HI_P" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="11"/>
+<wire x1="73.66" y1="124.46" x2="88.9" y2="124.46" width="0.1524" layer="91"/>
+<label x="88.9" y="124.46" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_LO_N" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="9"/>
+<wire x1="73.66" y1="121.92" x2="88.9" y2="121.92" width="0.1524" layer="91"/>
+<label x="88.9" y="121.92" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_VREF_P_PDM" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="7"/>
+<wire x1="73.66" y1="119.38" x2="88.9" y2="119.38" width="0.1524" layer="91"/>
+<label x="88.9" y="119.38" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="E1_TX_RING" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="5"/>
+<wire x1="73.66" y1="116.84" x2="88.9" y2="116.84" width="0.1524" layer="91"/>
+<label x="88.9" y="116.84" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_LO_P" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="12"/>
+<wire x1="66.04" y1="124.46" x2="50.8" y2="124.46" width="0.1524" layer="91"/>
+<label x="50.8" y="124.46" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_HI_N" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="10"/>
+<wire x1="66.04" y1="121.92" x2="50.8" y2="121.92" width="0.1524" layer="91"/>
+<label x="50.8" y="121.92" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="E1_TX_TIP" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="8"/>
+<wire x1="66.04" y1="119.38" x2="50.8" y2="119.38" width="0.1524" layer="91"/>
+<label x="50.8" y="119.38" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="E1_RX_VREF_N_PDM" class="0">
+<segment>
+<pinref part="JP2" gate="A" pin="6"/>
+<wire x1="66.04" y1="116.84" x2="50.8" y2="116.84" width="0.1524" layer="91"/>
+<label x="50.8" y="116.84" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="CLK_30M72" class="0">
+<segment>
+<pinref part="JP1" gate="A" pin="6"/>
+<wire x1="66.04" y1="142.24" x2="50.8" y2="142.24" width="0.1524" layer="91"/>
+<label x="50.8" y="142.24" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<wire x1="233.68" y1="121.92" x2="243.84" y2="121.92" width="0.1524" layer="91"/>
+<label x="243.84" y="121.92" size="1.27" layer="95" xref="yes"/>
+<pinref part="R20" gate="SYM" pin="2"/>
+</segment>
+</net>
+<net name="N$4" class="0">
+<segment>
+<pinref part="X2" gate="SYM" pin="EN"/>
+<wire x1="218.44" y1="127" x2="220.98" y2="127" width="0.1524" layer="91"/>
+<wire x1="220.98" y1="127" x2="220.98" y2="134.62" width="0.1524" layer="91"/>
+<pinref part="R18" gate="SYM" pin="1"/>
+<wire x1="220.98" y1="134.62" x2="220.98" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="220.98" y1="137.16" x2="226.06" y2="137.16" width="0.1524" layer="91"/>
+<pinref part="R19" gate="SYM" pin="1"/>
+<wire x1="226.06" y1="134.62" x2="220.98" y2="134.62" width="0.1524" layer="91"/>
+<junction x="220.98" y="134.62"/>
+</segment>
+</net>
+<net name="CLK_TUNE" class="0">
+<segment>
+<pinref part="R22" gate="SYM" pin="2"/>
+<wire x1="200.66" y1="86.36" x2="203.2" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="R21" gate="SYM" pin="1"/>
+<wire x1="203.2" y1="86.36" x2="210.82" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="210.82" y1="86.36" x2="218.44" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="86.36" x2="231.14" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="86.36" x2="238.76" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="88.9" x2="231.14" y2="86.36" width="0.1524" layer="91"/>
+<junction x="231.14" y="86.36"/>
+<pinref part="R24" gate="SYM" pin="2"/>
+<wire x1="231.14" y1="83.82" x2="231.14" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="C13" gate="SYM" pin="1"/>
+<wire x1="218.44" y1="81.28" x2="218.44" y2="86.36" width="0.1524" layer="91"/>
+<junction x="218.44" y="86.36"/>
+<pinref part="C12" gate="SYM" pin="1"/>
+<wire x1="210.82" y1="81.28" x2="210.82" y2="86.36" width="0.1524" layer="91"/>
+<junction x="210.82" y="86.36"/>
+<pinref part="R23" gate="SYM" pin="2"/>
+<wire x1="200.66" y1="78.74" x2="203.2" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="78.74" x2="203.2" y2="86.36" width="0.1524" layer="91"/>
+<junction x="203.2" y="86.36"/>
+<wire x1="238.76" y1="86.36" x2="238.76" y2="116.84" width="0.1524" layer="91"/>
+<pinref part="X2" gate="SYM" pin="TUNE"/>
+<wire x1="238.76" y1="116.84" x2="218.44" y2="116.84" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="CLK_TUNE_PDM_HI" class="0">
+<segment>
+<pinref part="R23" gate="SYM" pin="1"/>
+<wire x1="190.5" y1="78.74" x2="185.42" y2="78.74" width="0.1524" layer="91"/>
+<label x="185.42" y="78.74" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="JP1" gate="A" pin="7"/>
+<wire x1="73.66" y1="144.78" x2="88.9" y2="144.78" width="0.1524" layer="91"/>
+<label x="88.9" y="144.78" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="N$13" class="0">
+<segment>
+<pinref part="R27" gate="SYM" pin="1"/>
+<pinref part="LED1" gate="G$1" pin="A"/>
+<wire x1="121.92" y1="45.72" x2="121.92" y2="40.64" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$14" class="0">
+<segment>
+<pinref part="R28" gate="SYM" pin="1"/>
+<pinref part="LED2" gate="G$1" pin="A"/>
+<wire x1="134.62" y1="45.72" x2="134.62" y2="40.64" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="E1_RX_CT_BIAS_PDM" class="0">
+<segment>
+<pinref part="JP1" gate="A" pin="8"/>
+<wire x1="66.04" y1="144.78" x2="50.8" y2="144.78" width="0.1524" layer="91"/>
+<label x="50.8" y="144.78" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="USB_VSENSE" class="0">
+<segment>
+<pinref part="R26" gate="SYM" pin="1"/>
+<pinref part="R31" gate="SYM" pin="2"/>
+<wire x1="109.22" y1="45.72" x2="109.22" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="43.18" x2="109.22" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="43.18" x2="101.6" y2="43.18" width="0.1524" layer="91"/>
+<junction x="109.22" y="43.18"/>
+<label x="101.6" y="43.18" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="JP1" gate="A" pin="10"/>
+<wire x1="66.04" y1="147.32" x2="50.8" y2="147.32" width="0.1524" layer="91"/>
+<label x="50.8" y="147.32" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="CLK_30M72_RAW" class="0">
+<segment>
+<pinref part="X2" gate="SYM" pin="OUT"/>
+<wire x1="218.44" y1="121.92" x2="223.52" y2="121.92" width="0.1524" layer="91"/>
+<pinref part="R20" gate="SYM" pin="1"/>
+</segment>
+</net>
+<net name="CLK_TUNE_PDM_LO" class="0">
+<segment>
+<wire x1="185.42" y1="86.36" x2="190.5" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="R22" gate="SYM" pin="1"/>
+<label x="185.42" y="86.36" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="JP1" gate="A" pin="5"/>
+<wire x1="73.66" y1="142.24" x2="88.9" y2="142.24" width="0.1524" layer="91"/>
+<label x="88.9" y="142.24" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/hardware/icE1usb-proto/plot/icE1usb-proto.pdf b/hardware/icE1usb-proto/plot/icE1usb-proto.pdf
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index 0000000..5c4e47c
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+++ b/hardware/icE1usb-proto/plot/icE1usb-proto.pdf
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