| commit | 488bf8a29f97f9d660f19433472a870918248f07 | [log] [tgz] |
|---|---|---|
| author | Sylvain Munaut <tnt@246tNt.com> | Fri Oct 09 13:05:53 2020 +0200 |
| committer | Sylvain Munaut <tnt@246tNt.com> | Fri Oct 09 13:05:53 2020 +0200 |
| tree | e2140938539a5789632e9d795ad127237bc82af9 | |
| parent | 5853197f848e3fdc900189b5a8fdc89a47470e0a [diff] |
gateware/common: Add register stage for the 'ack' and 'rdata' This greatly improves timing at the expense of one cycle delay for all wishbone access to peripherals. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>