First revision
Boards ordered from Aisler on August 12th 2020. Gerbers used are in the repo.
This revision is mostly just to keep a record of the changes that were applied directly on the r0.0 prototypes and how they were assembled.
E1 TX side resistors changed to 27R (from 82R)
Consequently all other uses of 82R were updated
Connection from GND to USB shield changed to 91k (from 1k5)
All 47R networks were swapped for 33R.
Some silkscreen label was added on the PCB
Rev 0.0 PCBs were used and assembled / reworked to match this revision. Two boards in total: one for @LaF0rge and one for @tnt.
Flash footprint is wrong. The selected flash is not using the "wide" variant of SO8.
The NT/TE selection pin-header is completely wrong
The lightpipe is a bit loose. Turns out the holes came out 10% oversized out of Aisler :/ Dimensions left as the manufacturer ones and hope that the prod are closer to nominal.
The E1 bias configuration should probably have been reversed with the bias_fixed
assigned to the _n
side. This way the variable bias would have been lower and the common mode voltage closer to what the comparator expect for LVDS.
This however would break compatibility with the proto which is a waste and has no real-world impact. The common-mode voltage change is minimal and comparator work fine where it is. And even if it was an issue we could put the variable bias lower and flip the input polarity in the bitstream.
Production version, sent to manufacturer for production.
Silkscreen updated
Flash footprint updated to narrow SO8 (150mil)
Rewired the NT/TE header properly
Changed RF trackwidth to 0.175 mm to account for production stackup
Changed board outline to cater to connectors being more outward
Adjust positions of connectors / ...
As a result of those moves some minor adjustments were made
Rerouted 1v2 on the bottom to add more distance from GND vias. Also widened the T junction to one of the via to 0.6 mm
Adding series resistor for gps_reset_n
and gps_pps
was considered, but deemed not necessary.
gps_pps
is generated by the module itself, so any fast edge is coming from the module.gps_reset_n
is static.Adding a capacitor between tx_hi
and tx_lo
(after the series resistor) was also an option. Testing showed it didn't really change / improve the pulse shape and simulation showed increased peak current (and thus stress on the UP5k drivers). I considered adding a DNP footprint but area was a bit cramped and some more work would have been needed for something that would most likely stay unpopulated.
A thought that occured to me to improve pulse shape is to use an external buffered gate (those sot-23/sc-67 single/double gate buffer ICs) and possibly putting it in parallel :
From -----,----------,--\/\/\/---> To TX FPGA \ / R Magnetics \__|\__/ |/
This would take strain off the FPGA driver, provide more current and the delay of the gate might actually help make the pulse shape more correct.