output 50 MHz for RMII
in hardware revision 2 the Ethernet PHY RMII_CLOCK input clock is
connected to the MCU pin PA10.
GCLK4 of the MCU now outputs the required 50 MHz clock on this pin.
the same clock is re-used for UART debug to generate the 921600
bps baud rate.
Change-Id: Id3a3dee15c3986536b0623d0f39ca62e94acd1fd
diff --git a/sysmoOCTSIM/atmel_start_pins.h b/sysmoOCTSIM/atmel_start_pins.h
index 0264736..7cbaed5 100644
--- a/sysmoOCTSIM/atmel_start_pins.h
+++ b/sysmoOCTSIM/atmel_start_pins.h
@@ -31,6 +31,7 @@
#define SIM5_INT GPIO(GPIO_PORTA, 3)
#define SIM0_IO GPIO(GPIO_PORTA, 4)
#define SIM2_IO GPIO(GPIO_PORTA, 9)
+#define RMII_CLOCK GPIO(GPIO_PORTA, 10)
#define SIMCLK_20MHZ GPIO(GPIO_PORTA, 11)
#define SIM1_IO GPIO(GPIO_PORTA, 16)
#define VB0 GPIO(GPIO_PORTA, 20)